davinci: add basic dm355/dm350/dm335 support

Add some basic declarations for DaVinci DM355/DM350/DM335 support,
keyed on CONFIG_SOC_DM355.  (DM35X isn't quite right because the
DM357 is very different; while the DM355 is like a DM355 without
the MPEG/JPEG coprocessor).

These have different peripherals than the DM6446, and some of
the peripherals are at different addresses.  Notably for U-Boot,
there's no EMAC, and the NAND controller address is different

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

3 files changed, 84 insertions, 17 deletions

diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index 6052e02330..480f19f557 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).a
 
 COBJS-y				+= timer.o psc.o
+COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= ether.o lxt972.o dp83848.o
 
diff --git a/cpu/arm926ejs/davinci/dm355.c b/cpu/arm926ejs/davinci/dm355.c
new file mode 100644
index 0000000000..bc45b67fbe
--- /dev/null
+++ b/cpu/arm926ejs/davinci/dm355.c
@@ -0,0 +1,45 @@
+/*
+ * SoC-specific code for tms320dm355 and similar chips
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
+
+#ifdef CONFIG_DRIVER_DAVINCI_I2C
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX3) |= (1 << 20) | (1 << 19);
+}
+#endif
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index 3f6d4834b0..a28cfb4ae0 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -44,13 +44,16 @@ typedef volatile unsigned int *	dv_reg_p;
 
 /*
  * Base register addresses
+ *
+ * NOTE:  some of these DM6446-specific addresses DO NOT WORK
+ * on other DaVinci chips.  Double check them before you try
+ * using the addresses ... or PSC module identifiers, etc.
  */
 #define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
 #define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
 #define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
 #define DAVINCI_UART0_BASE			(0x01c20000)
 #define DAVINCI_UART1_BASE			(0x01c20400)
-#define DAVINCI_UART2_BASE			(0x01c20800)
 #define DAVINCI_I2C_BASE			(0x01c21000)
 #define DAVINCI_TIMER0_BASE			(0x01c21400)
 #define DAVINCI_TIMER1_BASE			(0x01c21800)
@@ -62,30 +65,41 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_PLL_CNTRL0_BASE			(0x01c40800)
 #define DAVINCI_PLL_CNTRL1_BASE			(0x01c40c00)
 #define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01c41000)
-#define DAVINCI_SYSTEM_DFT_BASE			(0x01c42000)
 #define DAVINCI_ARM_INTC_BASE			(0x01c48000)
-#define DAVINCI_IEEE1394_BASE			(0x01c60000)
 #define DAVINCI_USB_OTG_BASE			(0x01c64000)
 #define DAVINCI_CFC_ATA_BASE			(0x01c66000)
 #define DAVINCI_SPI_BASE			(0x01c66800)
 #define DAVINCI_GPIO_BASE			(0x01c67000)
-#define DAVINCI_UHPI_BASE			(0x01c67800)
 #define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		(0x01c80000)
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	(0x01c81000)
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		(0x01c82000)
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		(0x01c84000)
-#define DAVINCI_IMCOP_BASE			(0x01cc0000)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		(0x01e00000)
-#define DAVINCI_VLYNQ_BASE			(0x01e01000)
-#define DAVINCI_MCBSP_BASE			(0x01e02000)
-#define DAVINCI_MMC_SD_BASE			(0x01e10000)
-#define DAVINCI_MS_BASE				(0x01e20000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
-#define DAVINCI_VLYNQ_REMOTE_BASE		(0x0c000000)
+
+#ifdef CONFIG_SOC_DM644X
+#define DAVINCI_UART2_BASE			0x01c20800
+#define DAVINCI_UHPI_BASE			0x01c67800
+#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01c80000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01c81000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01c82000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01c84000
+#define DAVINCI_IMCOP_BASE			0x01cc0000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e00000
+#define DAVINCI_VLYNQ_BASE			0x01e01000
+#define DAVINCI_ASP_BASE			0x01e02000
+#define DAVINCI_MMC_SD_BASE			0x01e10000
+#define DAVINCI_MS_BASE				0x01e20000
+#define DAVINCI_VLYNQ_REMOTE_BASE		0x0c000000
+
+#elif defined(CONFIG_SOC_DM355)
+#define DAVINCI_MMC_SD1_BASE			0x01e00000
+#define DAVINCI_ASP0_BASE			0x01e02000
+#define DAVINCI_ASP1_BASE			0x01e04000
+#define DAVINCI_UART2_BASE			0x01e06000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
+#define DAVINCI_MMC_SD0_BASE			0x01e11000
+
+#endif
 
 /* Power and Sleep Controller (PSC) Domains */
 #define DAVINCI_GPSC_ARMDOMAIN		0
@@ -168,7 +182,14 @@ void davinci_errata_workarounds(void);
 
 /* Miscellania... */
 #define VBPR				(0x20000020)
-#define PINMUX0				(0x01c40000)
-#define PINMUX1				(0x01c40004)
+
+/* NOTE:  system control modules are *highly* chip-specific, both
+ * as to register content (e.g. for muxing) and which registers exist.
+ */
+#define PINMUX0				0x01c40000
+#define PINMUX1				0x01c40004
+#define PINMUX2				0x01c40008
+#define PINMUX3				0x01c4000c
+#define PINMUX4				0x01c40010
 
 #endif /* __ASM_ARCH_HARDWARE_H */