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| author | Bo Shen <voice.shen@atmel.com> | 2012-11-08 17:49:14 +0000 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2012-11-10 14:04:08 +0100 |
| commit | cfcd1c03e44fc22f2146948dc9f341b28e6ec583 (patch) | |
| tree | 52c5d4d4c53e1c5ff6d8ac9e59163326512e7063 | |
| parent | d484b52e6fcb28dc011ce45718294496c6ea83d0 (diff) | |
| download | blackbird-obmc-uboot-cfcd1c03e44fc22f2146948dc9f341b28e6ec583.tar.gz blackbird-obmc-uboot-cfcd1c03e44fc22f2146948dc9f341b28e6ec583.zip | |
video: atmel: implement lcd_setcolreg function
implement the common api lcd_setcolreg in include/lcd.h
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[agust: fixed commit log and gcc 4.6 -Wparentheses warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
| -rw-r--r-- | drivers/video/atmel_hlcdfb.c | 12 | ||||
| -rw-r--r-- | include/atmel_hlcdc.h | 7 |
2 files changed, 19 insertions, 0 deletions
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index beb7fa396e..b10ca4b677 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -51,6 +51,18 @@ short console_row; #define lcdc_readl(reg) __raw_readl((reg)) #define lcdc_writel(reg, val) __raw_writel((val), (reg)) +/* + * the CLUT register map as following + * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0) + */ +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ + lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) + | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) + | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk), + panel_info.mmio + ATMEL_LCDC_LUT(regno)); +} + void lcd_ctrl_init(void *lcdbase) { unsigned long value; diff --git a/include/atmel_hlcdc.h b/include/atmel_hlcdc.h index 945b30acb0..fbd2f92457 100644 --- a/include/atmel_hlcdc.h +++ b/include/atmel_hlcdc.h @@ -217,6 +217,13 @@ struct atmel_hlcd_regs { #define LCDC_BASECFG3_RDEF(value) \ ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos))) +#define LCDC_BASECLUT_BCLUT_Pos 0 +#define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos) +#define LCDC_BASECLUT_GCLUT_Pos 8 +#define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos) +#define LCDC_BASECLUT_RCLUT_Pos 16 +#define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos) + #define LCDC_BASECFG4_DMA (0x1 << 8) #define LCDC_BASECFG4_REP (0x1 << 9) |
