Merge branch 'master' of git://git.denx.de/u-boot-arm

17 files changed, 82 insertions, 2243 deletions

diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile
deleted file mode 100644
index 0d082c5696..0000000000
--- a/board/ns9750dev/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ns9750dev.o flash.o led.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/ns9750dev/config.mk b/board/ns9750dev/config.mk
deleted file mode 100644
index e5d87029d3..0000000000
--- a/board/ns9750dev/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#######################################################################
-#
-# Copyright (C) 2004 by FS Forth-Systeme GmbH.
-# Markus Pietrek <mpietrek@fsforth.de>
-#
-# @TODO
-# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000
-# optionally with a ramdisk at 0080'0000
-#
-# we load ourself to 0078'0000
-#
-# download area is 0060'0000
-#
-
-
-CONFIG_SYS_TEXT_BASE = 0x00780000
diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c
deleted file mode 100644
index 185bc2d73a..0000000000
--- a/board/ns9750dev/flash.c
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)			__swab16(x)
-#else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)			__swab32(x)
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
-	unsigned int sector_number;
-	unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
-	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
-	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-			break;
-		default:
-			panic ("configured too many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-	flash_protect (FLAG_PROTECT_SET,
-			CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR,
-			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-	OrgDef *pOrgDef;
-
-	pOrgDef = OrgIntel_28F256L18T;
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			if (i > 255) {
-				info->start[i] = base + (i * 0x8000);
-				info->protect[i] = 0;
-			} else {
-				info->start[i] = base +
-						(i * PHYS_FLASH_SECT_SIZE);
-				info->protect[i] = 0;
-			}
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F256L18T:
-		printf ("FLASH 28F256L18T\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	volatile FPW value;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW) 0x00AA00AA;
-	addr[0x2AAA] = (FPW) 0x00550055;
-	addr[0x5555] = (FPW) 0x00900090;
-
-	mb ();
-	value = addr[0];
-
-	switch (value) {
-
-	case (FPW) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);		/* no or unknown flash  */
-	}
-
-	mb ();
-	value = addr[1];	/* device ID        */
-	switch (value) {
-
-	case (FPW) (INTEL_ID_28F256L18T):
-		info->flash_id += FLASH_28F256L18T;
-		info->sector_count = 259;
-		info->size = 0x02000000;
-		break;			/* => 32 MB     */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK    0x0080
-
-	*addr = (FPW) 0x00500050;	/* clear status register */
-
-	/* this sends the clear lock bit command */
-	*addr = (FPW) 0x00600060;
-	*addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-				info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			flash_unprotect_sectors (addr);
-
-			/* arm simple, non interrupt dependent timer */
-			start = get_timer(0);
-
-			*addr = (FPW) 0x00500050;/* clear status register */
-			*addr = (FPW) 0x00200020;/* erase setup */
-			*addr = (FPW) 0x00D000D0;/* erase confirm */
-
-			while (((status =
-				*addr) & (FPW) 0x00800080) !=
-				(FPW) 0x00800080) {
-					if (get_timer(start) >
-					CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					/* suspend erase     */
-					*addr = (FPW) 0x00B000B0;
-					/* reset to read mode */
-					*addr = (FPW) 0x00FF00FF;
-					rcode = 1;
-					break;
-				}
-			}
-
-			/* clear status register cmd.   */
-			*addr = (FPW) 0x00500050;
-			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
-			printf (" done\n");
-		}
-	}
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int count, i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < port_width && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	count = 0;
-	while (cnt >= port_width) {
-		data = 0;
-		for (i = 0; i < port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-		cnt -= port_width;
-		if (count++ > 0x800) {
-			spin_wheel ();
-			count = 0;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong status;
-	int flag;
-	ulong start;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
-		return (2);
-	}
-	flash_unprotect_sectors (addr);
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-			return (1);
-		}
-	}
-	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-	return (0);
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c
deleted file mode 100644
index b85c869d85..0000000000
--- a/board/ns9750dev/led.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Defines helper functions for toggeling LEDs
- * @Usage:
- * @References: [1]
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifdef CONFIG_STATUS_LED
-
-#include <ns9750_bbus.h>
-
-static inline void __led_init( led_id_t mask, int state )
-{
-	XXXX;
-}
-
-static inline void __led_toggle( led_id_t mask )
-{
-}
-
-static inline void __led_set( led_id_t mask, int state )
-{
-}
-
-#endif /* CONFIG_STATUS_LED */
diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S
deleted file mode 100644
index ba5ff8124e..0000000000
--- a/board/ns9750dev/lowlevel_init.S
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for the NS9750 DevBoard by
- * (C) Copyright 2004 by FS Forth-Systeme GmbH.
- * Markus Pietrek <mpietrek@fsforth.de>
- * @References: [1] NS9750 Hardware Reference/December 2003
- *	        [2] ns9750_a.cmd from MAJIC configuration
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_NS9750DEV)
-# ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#  include <./ns9750_sys.h>
-#  include <./ns9750_mem.h>
-# endif
-#endif
-
-/***********************************************************************
- * @Function: write_register_block
- * @Return: nothing
- * @Descr: Copies the register block of register_offset:register value to
- *         the registers at base r0. The block is assumed to start in RAM at r1
- *         and end at r2. The linked RAM base address of U-Boot is assumed to be
- *	   in r5 while the ROM base address we are running from is r6
- *         Uses r3 and r4 as tempory registers
- ***********************************************************************/
-
-.macro	write_register_block
-	@@ map the addresses to high memory
-	sub	r1, r1, r5
-	add	r1, r1, r6
-	sub	r2, r2, r5
-	add	r2, r2, r6
-
-	@@ copy all
-1:
-	@@ Write register/value pair starting at [r1] to register base r0
-	ldr	r3, [r1], #4
-	ldr	r4, [r1], #4
-	str	r4, [r0,r3]
-	cmp	r1, r2
-	blt	1b
-.endm
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	@ sdram load addr from config.mk
-_PHYS_FLASH:
-	.word	PHYS_FLASH_1    @ real flash address (without mirroring)
-_CAS_LATENCY:
-	.word	0x00022000	@ for CAS2 latency
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-.globl lowlevel_init
-lowlevel_init:
-
-	/* U-Boot may be linked to RAM at 0x780000. But this code will run in
-	   flash from 0x0. But in order to enable RAM we have to disable the
-	   mirror bit, therefore we have to jump to our real flash address
-	   beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
-	   _run_at_real_flash_address may be 0x500003b0 while be linked to
-	   0x7803b0. So we must modify our linked addresses */
-
-	@@ branch to high memory address, away from 0x0
-	ldr	r5, _TEXT_BASE
-	ldr	r6, _PHYS_FLASH
-	ldr	r0, =_run_at_real_flash_address
-	sub	r0, r0, r5
-	add	r0, r0, r6
-	mov	pc, r0
-	nop			@ for pipelining
-
-_run_at_real_flash_address:
-	@@ now we are running > PHYS_FLASH_1, safe to enable memory controller
-
-	@@ Write Memory Configuration Registers
-
-	ldr	r0, _NS9750_MEM_MODULE_BASE
-	ldr	r1, =_MEM_CONFIG_START
-	ldr	r2, =_MEM_CONFIG_END
-
-	write_register_block
-
-	@@ Give SDRAM some time to settle
-	@@ @TODO. According to [2] it should be 2 AHB cycles. Check
-
-	ldr	r1, =0x50
-_sdram_settle:
-	subs	r1, r1, #1
-	bne	_sdram_settle
-
-_enable_mappings:
-	@@ Enable SDRAM Mode
-
-	ldr	r1, =_MEM_MODE_START
-	ldr	r2, =_MEM_MODE_END
-
-	write_register_block
-
-	ldr	r3, _CAS_LATENCY @ perform one read from SDRAM
-	ldr	r3, [r3]
-
-	@@ Enable SDRAM and memory mappings
-
-	ldr	r1, =_MEM_ENABLE_START
-	ldr	r2, =_MEM_ENABLE_END
-
-	write_register_block
-
-	@@ Activate AHB monitor
-
-	ldr	r0, =NS9750_SYS_MODULE_BASE
-	ldr	r1, =_AHB_MONITOR_START
-	ldr	r2, =_AHB_MONITOR_END
-
-	write_register_block
-_relocate_lr:
-	/* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
-	   PHYS_FLASH. */
-	mov	r1, ip
-	add	r1, r1, r6
-	mov	ip, r1
-
-	mov	r1, lr
-	add	r1, r1, r6
-	mov	lr, r1
-
-	@@ back to arch calling code
-	mov	pc,	lr
-
-	.ltorg
-
-_NS9750_MEM_MODULE_BASE:
-	.word	NS9750_MEM_MODULE_BASE
-
-_MEM_CONFIG_START:
-	/* Table of 2 32bit entries. First word is register address offset
-	   relative to NS9750_MEM_MODULE_BASE, second one is value. They are
-	   written in order of appearance */
-
-	@@ Register values taken from [2]
-	.word	NS9750_MEM_CTRL
-	.word	NS9750_MEM_CTRL_E
-
-	.word	NS9750_MEM_DYN_REFRESH
-	.word	(0x6 & NS9750_MEM_DYN_REFRESH_MA)
-
-	.word	NS9750_MEM_DYN_READ_CFG
-	.word	(0x1 & NS9750_MEM_DYN_READ_CFG_MA)
-
-	.word	NS9750_MEM_DYN_TRP
-	.word	(0x1 & NS9750_MEM_DYN_TRP_MA)
-
-	.word	NS9750_MEM_DYN_TRAS
-	.word	(0x4 & NS9750_MEM_DYN_TRAS_MA)
-
-	.word	NS9750_MEM_DYN_TAPR
-	.word	(0x1 & NS9750_MEM_DYN_TRAS_MA)
-
-	.word	NS9750_MEM_DYN_TDAL
-	.word	(0x5 & NS9750_MEM_DYN_TDAL_MA)
-
-	.word	NS9750_MEM_DYN_TWR
-	.word	(0x1 & NS9750_MEM_DYN_TWR_MA)
-
-	.word	NS9750_MEM_DYN_TRC
-	.word	(0x6 & NS9750_MEM_DYN_TRC_MA)
-
-	.word	NS9750_MEM_DYN_TRFC
-	.word	(0x6 & NS9750_MEM_DYN_TRFC_MA)
-
-	.word	NS9750_MEM_DYN_TRRD
-	.word	(0x1 & NS9750_MEM_DYN_TRRD_MA)
-
-	.word	NS9750_MEM_DYN_TMRD
-	.word	(0x1 & NS9750_MEM_DYN_TMRD_MA)
-
-	@@ CS 4
-	.word	NS9750_MEM_DYN_CFG(0)
-	.word	(NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-	.word	NS9750_MEM_DYN_RAS_CAS(0)
-	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-	@@ CS 5
-	.word	NS9750_MEM_DYN_CFG(1)
-	.word	(NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-	.word	NS9750_MEM_DYN_RAS_CAS(1)
-	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-	@@ CS 6
-	.word	NS9750_MEM_DYN_CFG(2)
-	.word	(NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-	.word	NS9750_MEM_DYN_RAS_CAS(2)
-	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-	@@ CS 7
-	.word	NS9750_MEM_DYN_CFG(3)
-	.word	(NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-	.word	NS9750_MEM_DYN_RAS_CAS(3)
-	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-	.word	NS9750_MEM_DYN_CTRL
-	.word	(NS9750_MEM_DYN_CTRL_I_PALL | \
-		 NS9750_MEM_DYN_CTRL_SR | \
-		 NS9750_MEM_DYN_CTRL_CE )
-
-	.word	NS9750_MEM_DYN_REFRESH
-	.word	(0x1 & NS9750_MEM_DYN_REFRESH_MA)
-	@@ No further register settings after refresh
-_MEM_CONFIG_END:
-
-_MEM_MODE_START:
-	.word	NS9750_MEM_DYN_REFRESH
-	.word	(0x30 & NS9750_MEM_DYN_REFRESH_MA)
-
-	.word	NS9750_MEM_DYN_CTRL
-	.word	(NS9750_MEM_DYN_CTRL_I_MODE | \
-		 NS9750_MEM_DYN_CTRL_SR | \
-		 NS9750_MEM_DYN_CTRL_CE )
-_MEM_MODE_END:
-
-_MEM_ENABLE_START:
-	.word	NS9750_MEM_DYN_CTRL
-	.word	(NS9750_MEM_DYN_CTRL_I_NORMAL | \
-		 NS9750_MEM_DYN_CTRL_SR | \
-		 NS9750_MEM_DYN_CTRL_CE )
-
-	@@ CS 4
-	.word	NS9750_MEM_DYN_CFG(0)
-	.word	(NS9750_MEM_DYN_CFG_BDMC | \
-		 NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-	@@ CS 5
-	.word	NS9750_MEM_DYN_CFG(1)
-	.word	(NS9750_MEM_DYN_CFG_BDMC | \
-		 NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-	@@ CS 6
-	.word	NS9750_MEM_DYN_CFG(2)
-	.word	(NS9750_MEM_DYN_CFG_BDMC | \
-		 NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-	@@ CS 7
-	.word	NS9750_MEM_DYN_CFG(3)
-	.word	(NS9750_MEM_DYN_CFG_BDMC | \
-		 NS9750_MEM_DYN_CFG_AM | \
-		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-_MEM_ENABLE_END:
-
-_AHB_MONITOR_START:
-	.word	NS9750_SYS_AHB_TIMEOUT
-	.word	0x01000100	@ @TODO not calculated yet
-
-	.word	NS9750_SYS_AHB_MON
-	.word	(NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
-		 NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
-_AHB_MONITOR_END:
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c
deleted file mode 100644
index fc46244c74..0000000000
--- a/board/ns9750dev/ns9750dev.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- * Markus Pietrek <mpietrek@fsforth.de>
- * derived from omap1610innovator.c
- * @References: [1] NS9750 Hardware Reference/December 2003
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if defined(CONFIG_NS9750DEV)
-# include <./configs/ns9750dev.h>
-# include <./ns9750_bbus.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init( void );
-void ether__init( void );
-
-static inline void delay( unsigned long loops )
-{
-	__asm__ volatile ("1:\n"
-		"subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0" (loops));
-}
-
-
-/***********************************************************************
- * @Function: board_init
- * @Return: 0
- * @Descr: Enables BBUS modules and other devices
- ***********************************************************************/
-
-int board_init( void )
-{
-	/* Active BBUS modules */
-	*get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0;
-
-#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new
-	/* arch number of OMAP 1510-Board */
-	/* to be changed for OMAP 1610 Board */
-	gd->bd->bi_arch_number = 234;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x10000100;
-
-
-/* this speeds up your boot a quite a bit.  However to make it
- *  work, you need make sure your kernel startup flush bug is fixed.
- *  ... rkw ...
- */
-	icache_enable();
-
-	flash__init();
-	ether__init();
-	return 0;
-}
-
-
-int misc_init_r (void)
-{
-	/* currently empty */
-	return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
-			   for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-#if CONFIG_NR_DRAM_BANKS > 1
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
-	return 0;
-}
diff --git a/doc/README.ns9750dev b/doc/README.ns9750dev
deleted file mode 100644
index 29914406ba..0000000000
--- a/doc/README.ns9750dev
+++ /dev/null
@@ -1,36 +0,0 @@
-U-Boot Port to the NS9750 DevKit from NetSilicon
-
-1 Overview
-2 Board Configuration
-3 Installation
-
-
-1 Overview
-----------
-
-This port supports these NS9750 features.
-
-o one UART
-
-2 Board Configuration
----------------------
-
-Switches:
-SW10: 4
-SW11: 6,7
-SW16: 6,7,8
-SW17-SW20: 1
-SW4: 3, 6
-SW 1: 1
-SW2: 4
-SW3: 3
-SW8: 3 (rotated by 180 degree!!!!)
-
-Serial Console is Port B (bottom right port)
-
-3 Installation
---------------
-
-Have fun,
---
-Markus Pietrek <mpietrek@fsforth.de>
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 2b868e6515..e9ca96cba7 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -9,83 +9,84 @@ maintain a list of such former fellows, so archeologists can check
 easily if here is something they might want to dig for...
 
 
-Board	Arch	CPU	removed	    Commit	last known maintainer/contact
-=============================================================================
-AMX860	powerpc	mpc860	-	  -		Wolfgang Denk <wd@denx.de>
-c2mon	powerpc	mpc855	-	  -		Wolfgang Denk <wd@denx.de>
-ETX094	powerpc	mpc850	-	  -		Wolfgang Denk <wd@denx.de>
-IAD210	powerpc	mpc860	-	  -		-
-LANTEC	powerpc	mpc850	-	  -		Wolfgang Denk <wd@denx.de>
-SCM	powerpc	mpc8260	-	  -		Wolfgang Grandegger <wg@denx.de>
-SX1	arm	arm925t	-         -
-TQM85xx	powerpc	MPC85xx	d923a5d5  2012-10-04	Stefan Roese <sr@denx.de>
-apollon arm     omap24xx 535c74f  2012-09-18    Kyungmin Park <kyungmin.park@samsung.com>
-tb0229	mips	mips32	3f3110d	  2011-12-12
-rmu	powerpc	MPC850	fb82fd7   2011-12-07	Wolfgang Denk <wd@denx.de>
-OXC	powerpc	MPC8240	309a292   2011-12-07
-BAB7xx	powerpc	MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling <fgottschling@eltec.de>
-xm250   arm     pxa     c746cdd   2011-25-11
-pleb2   arm     pxa     b185a1c   2011-25-11
-cradle  arm     pxa     4e24f8a   2011-25-11    Kyle Harris <kharris@nexus-tech.net>
-cerf250 arm     pxa     a3f1241   2011-25-11    Prakash Kumar <prakash@embedx.com>
-mpq101	powerpc	mpc85xx	e877fab	  2011-10-23	Alex Dubov <oakad@yahoo.com>
-ixdpg425 arm	ixp	0ca8eb7	  2011-09-22	Stefan Roese <sr@denx.de>
-ixdp425 arm	ixp	0ca8eb7	  2011-09-22	Kyle Harris <kharris@nexus-tech.net>
-zylonite arm	pxa	b66521a	  2011-09-05
-shannon arm	sa1100	5df092d	  2011-09-05	Rolf Offermanns <rof@sysgo.de>
-modnet50 arm	arm720t	9c62815	  2011-09-05	Thomas Elste <info@elste.org>
-lpc2292sodimm arm arm720t d1a067a  2011-09-05
-lart	arm	sa1100	3d57573	  2011-09-05	Alex Züpke <azu@sysgo.de>
-impa7	arm	arm720t	c1f8750	  2011-09-05	Marius Gröger <mag@sysgo.de>
-gcplus	arm	sa1100	2c650e2	  2011-09-05	George G. Davis <gdavis@mvista.com>
-evb4510	arm	arm720t	26e670e	  2011-09-05	Curt Brune <curt@cucy.com>
-ep7312	arm	arm720t	c8f63b4	  2011-09-05	Marius Gröger <mag@sysgo.de>
-dnp1110	arm	sa1100	fc5e5ce	  2011-09-05	Alex Züpke <azu@sysgo.de>
-SMN42	arm	arm720t	6aac646	  2011-09-05
-at91rm9200dk arm arm920t 1c85752  2011-07-17
-m501sk	arm	arm920t	b1a2bd4	  2011-07-17
-kb9202	arm	arm920t	5bd3814	  2011-07-17
-csb637	arm	arm920t	d14af08	  2011-07-17
-cmc_pu2	arm	arm920t	37a9b4d	  2011-07-17
-at91cap9adk arm	arm926ejs b550834 2011-07-17	Stelian Pop <stelian@popies.net>
-voiceblue arm	arm925t	1b793a4	  2011-07-17
-smdk2400 arm	arm920t	ad218a8	  2011-07-17	Gary Jennejohn <garyj@denx.de>
-sbc2410x arm	arm920t	1f7f0ed	  2011-07-17
-netstar	arm	arm925t	6ea2405	  2011-07-17
-mx1fs2	arm	arm920t	6962419	  2011-07-17
-lpd7a404 arm	lh7a40x	957731e	  2011-07-17
-edb9301	arm	arm920t	716f7ad	  2011-07-17
-edb9302	arm	arm920t	716f7ad	  2011-07-17
-edb9302a arm	arm920t	716f7ad	  2011-07-17
-edb9307	 arm	arm920t	716f7ad	  2011-07-17
-edb9307a arm	arm920t	716f7ad	  2011-07-17
-edb9312	arm	arm920t	716f7ad	  2011-07-17
-edb9315	arm	arm920t	716f7ad	  2011-07-17
-edb9315a arm	arm920t	716f7ad	  2011-07-17
-B2	arm	s3c44b0 5dcf536	  2011-07-16	Andrea Scian <andrea.scian@dave-tech.it>
-armadillo arm	arm720t	be28857	  2011-07-16	Rowel Atienza <rowel@diwalabs.com>
-assabet	arm	sa1100	c91e90d	  2011-07-16	George G. Davis <gdavis@mvista.com>
-trab	arm	S3C2400	566e5cf	  2011-05-01	Gary Jennejohn <garyj@denx.de>
-xsengine ARM	PXA2xx	4262a7c   2010-10-20
-wepep250 ARM	PXA2xx	7369478   2010-10-20	Peter Figuli <peposh@etc.sk>
-delta	ARM	PXA2xx	75e2035   2010-10-20
-mp2usb	ARM	AT91RM2900  ee986e2 2011-01-25	Eric Bénard <eric@eukrea.com>
-barco	powerpc	MPC8245	afaa27b	  2010-11-23	Marc Leeman <marc.leeman@barco.com>
-ERIC	powerpc	405GP	d9ba451	  2010-11-21	Swen Anderson <sand@peppercon.de>
-VoVPN-GW_100MHz	powerpc	MPC8260 26fe3d2 2010-10-24	Juergen Selent <j.selent@elmeg.de>
-NC650	powerpc	MPC852	333d86d   2010-10-19	Wolfgang Denk <wd@denx.de>
-CP850	powerpc	MPC852	333d86d   2010-10-19	Wolfgang Denk <wd@denx.de>
-logodl	ARM	PXA2xx	059e778   2010-10-18	August Hoeraendl <august.hoerandl@gmx.at>
-CCM	powerpc	MPC860	dff07e1   2010-10-06	Wolfgang Grandegger <wg@denx.de>
-PCU_E	powerpc	MPC860T	544d97e   2010-10-06	Wolfgang Denk <wd@denx.de>
-spieval	powerpc	MPC5200	69434e4   2010-09-19
-smmaco4	powerpc	MPC5200	9ddc3af   2010-09-19
-HMI10	powerpc	MPC823	77efe35   2010-09-19	Wolfgang Denk <wd@denx.de>
-GTH	powerpc	MPC860	0fe247b   2010-07-17	Thomas Lange <thomas@corelatus.se>
-AmigaOneG3SE		953b7e6   2010-06-23
-suzaku	microblaze	4f18060   2009-10-03	Yasushi Shoji <yashi@atmark-techno.com>
-XUPV2P	microblaze	8fab49e   2008-12-10	Michal Simek <monstr@monstr.eu>
-MVS1	powerpc	MPC823	306620b   2008-08-26	Andre Schwarz <andre.schwarz@matrix-vision.de>
-adsvix	ARM	PXA27x	7610db1   2008-07-30	Adrian Filipi <adrian.filipi@eurotech.com>
-R5200	ColdFire	48ead7a   2008-03-31	Zachary P. Landau <zachary.landau@labxtechnologies.com>
-CPCI440	powerpc	440GP	b568fd2   2007-12-27	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
+=================================================================================================
+ns9750dev        arm         arm926ejs      -           -           Markus Pietrek <mpietrek@fsforth.de>
+AMX860           powerpc     mpc860         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
+c2mon            powerpc     mpc855         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
+ETX094           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
+IAD210           powerpc     mpc860         1b0757e     2012-10-28  -
+LANTEC           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
+SCM              powerpc     mpc8260        1b0757e     2012-10-28  Wolfgang Grandegger <wg@denx.de>
+SX1              arm         arm925t        53c4154     2012-10-26
+TQM85xx          powerpc     MPC85xx        d923a5d     2012-10-04  Stefan Roese <sr@denx.de>
+apollon          arm         omap24xx       535c74f     2012-09-18  Kyungmin Park <kyungmin.park@samsung.com>
+tb0229           mips        mips32         3f3110d     2011-12-12
+rmu              powerpc     MPC850         fb82fd7     2011-12-07  Wolfgang Denk <wd@denx.de>
+OXC              powerpc     MPC8240        309a292     2011-12-07
+BAB7xx           powerpc     MPC740/MPC750  c53043b     2011-12-07  Frank Gottschling <fgottschling@eltec.de>
+xm250            arm         pxa            c746cdd     2011-25-11
+pleb2            arm         pxa            b185a1c     2011-25-11
+cradle           arm         pxa            4e24f8a     2011-25-11  Kyle Harris <kharris@nexus-tech.net>
+cerf250          arm         pxa            a3f1241     2011-25-11  Prakash Kumar <prakash@embedx.com>
+mpq101           powerpc     mpc85xx        e877fab     2011-10-23  Alex Dubov <oakad@yahoo.com>
+ixdpg425         arm         ixp            0ca8eb7     2011-09-22  Stefan Roese <sr@denx.de>
+ixdp425          arm         ixp            0ca8eb7     2011-09-22  Kyle Harris <kharris@nexus-tech.net>
+zylonite         arm         pxa            b66521a     2011-09-05
+shannon          arm         sa1100         5df092d     2011-09-05  Rolf Offermanns <rof@sysgo.de>
+modnet50         arm         arm720t        9c62815     2011-09-05  Thomas Elste <info@elste.org>
+lpc2292sodimm    arm         arm720t        d1a067a     2011-09-05
+lart             arm         sa1100         3d57573     2011-09-05  Alex Züpke <azu@sysgo.de>
+impa7            arm         arm720t        c1f8750     2011-09-05  Marius Gröger <mag@sysgo.de>
+gcplus           arm         sa1100         2c650e2     2011-09-05  George G. Davis <gdavis@mvista.com>
+evb4510          arm         arm720t        26e670e     2011-09-05  Curt Brune <curt@cucy.com>
+ep7312           arm         arm720t        c8f63b4     2011-09-05  Marius Gröger <mag@sysgo.de>
+dnp1110          arm         sa1100         fc5e5ce     2011-09-05  Alex Züpke <azu@sysgo.de>
+SMN42            arm         arm720t        6aac646     2011-09-05
+at91rm9200dk     arm         arm920t        1c85752     2011-07-17
+m501sk           arm         arm920t        b1a2bd4     2011-07-17
+kb9202           arm         arm920t        5bd3814     2011-07-17
+csb637           arm         arm920t        d14af08     2011-07-17
+cmc_pu2          arm         arm920t        37a9b4d     2011-07-17
+at91cap9adk      arm         arm926ejs      b550834     2011-07-17  Stelian Pop <stelian@popies.net>
+voiceblue        arm         arm925t        1b793a4     2011-07-17
+smdk2400         arm         arm920t        ad218a8     2011-07-17  Gary Jennejohn <garyj@denx.de>
+sbc2410x         arm         arm920t        1f7f0ed     2011-07-17
+netstar          arm         arm925t        6ea2405     2011-07-17
+mx1fs2           arm         arm920t        6962419     2011-07-17
+lpd7a404         arm         lh7a40x        957731e     2011-07-17
+edb9301          arm         arm920t        716f7ad     2011-07-17
+edb9302          arm         arm920t        716f7ad     2011-07-17
+edb9302a         arm         arm920t        716f7ad     2011-07-17
+edb9307          arm         arm920t        716f7ad     2011-07-17
+edb9307a         arm         arm920t        716f7ad     2011-07-17
+edb9312          arm         arm920t        716f7ad     2011-07-17
+edb9315          arm         arm920t        716f7ad     2011-07-17
+edb9315a         arm         arm920t        716f7ad     2011-07-17
+B2               arm         s3c44b0        5dcf536     2011-07-16  Andrea Scian <andrea.scian@dave-tech.it>
+armadillo        arm         arm720t        be28857     2011-07-16  Rowel Atienza <rowel@diwalabs.com>
+assabet          arm         sa1100         c91e90d     2011-07-16  George G. Davis <gdavis@mvista.com>
+trab             arm         S3C2400        566e5cf     2011-05-01  Gary Jennejohn <garyj@denx.de>
+xsengine         ARM         PXA2xx         4262a7c     2010-10-20
+wepep250         ARM         PXA2xx         7369478     2010-10-20  Peter Figuli <peposh@etc.sk>
+delta            ARM         PXA2xx         75e2035     2010-10-20
+mp2usb           ARM         AT91RM2900     ee986e2     2011-01-25  Eric Bénard <eric@eukrea.com>
+barco            powerpc     MPC8245        afaa27b     2010-11-23  Marc Leeman <marc.leeman@barco.com>
+ERIC             powerpc     405GP          d9ba451     2010-11-21  Swen Anderson <sand@peppercon.de>
+VoVPN-GW_100MHz  powerpc     MPC8260        26fe3d2     2010-10-24  Juergen Selent <j.selent@elmeg.de>
+NC650            powerpc     MPC852         333d86d     2010-10-19  Wolfgang Denk <wd@denx.de>
+CP850            powerpc     MPC852         333d86d     2010-10-19  Wolfgang Denk <wd@denx.de>
+logodl           ARM         PXA2xx         059e778     2010-10-18  August Hoeraendl <august.hoerandl@gmx.at>
+CCM              powerpc     MPC860         dff07e1     2010-10-06  Wolfgang Grandegger <wg@denx.de>
+PCU_E            powerpc     MPC860T        544d97e     2010-10-06  Wolfgang Denk <wd@denx.de>
+spieval          powerpc     MPC5200        69434e4     2010-09-19
+smmaco4          powerpc     MPC5200        9ddc3af     2010-09-19
+HMI10            powerpc     MPC823         77efe35     2010-09-19  Wolfgang Denk <wd@denx.de>
+GTH              powerpc     MPC860         0fe247b     2010-07-17  Thomas Lange <thomas@corelatus.se>
+AmigaOneG3SE     powerpc     74xx_7xx       953b7e6     2010-06-23
+suzaku           microblaze  -              4f18060     2009-10-03  Yasushi Shoji <yashi@atmark-techno.com>
+XUPV2P           microblaze  -              8fab49e     2008-12-10  Michal Simek <monstr@monstr.eu>
+MVS1             powerpc     MPC823         306620b     2008-08-26  Andre Schwarz <andre.schwarz@matrix-vision.de>
+adsvix           ARM         PXA27x         7610db1     2008-07-30  Adrian Filipi <adrian.filipi@eurotech.com>
+R5200            ColdFire    -              48ead7a     2008-03-31  Zachary P. Landau <zachary.landau@labxtechnologies.com>
+CPCI440          powerpc     440GP          b568fd2     2007-12-27  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt
index c6a8ab0521..ef71fea2b8 100644
--- a/doc/driver-model/UDM-serial.txt
+++ b/doc/driver-model/UDM-serial.txt
@@ -86,7 +86,7 @@ III) Analysis of in-tree drivers
 
   7) ns9750_serial.c
   ------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+  Unmaintained port. Code got removed.
 
   8) opencores_yanu.c
   -------------------
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 5e8b64873d..de3f471996 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -33,7 +33,6 @@ COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
 COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
 COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 COBJS-$(CONFIG_MCFUART) += mcfuart.o
-COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
 COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
 COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
 COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
diff --git a/drivers/serial/ns9750_serial.c b/drivers/serial/ns9750_serial.c
deleted file mode 100644
index 85fc68a076..0000000000
--- a/drivers/serial/ns9750_serial.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Serial driver for the NS9750. Only one UART is supported yet.
- * @References: [1] NS9750 Hardware Reference/December 2003
- * @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#include <common.h>
-
-#include "ns9750_bbus.h"	/* for GPIOs */
-#include "ns9750_ser.h"		/* for serial configuration */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_CONS_INDEX)
-#error "No console index specified."
-#endif
-
-#define CONSOLE CONFIG_CONS_INDEX
-
-static unsigned int calcBitrateRegister( void );
-static unsigned int calcRxCharGapRegister( void );
-
-static char cCharsAvailable; /* Numbers of chars in unCharCache */
-static unsigned int unCharCache; /* unCharCache is only valid if
-				  * cCharsAvailable > 0 */
-
-/***********************************************************************
- * @Function: serial_init
- * @Return: 0
- * @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off
- ***********************************************************************/
-
-static int ns9750_serial_init(void)
-{
-	unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 };
-	unsigned int aunGPIORxD[] = { 1, 9, 41, 45 };
-
-	cCharsAvailable = 0;
-
-	/* configure TxD and RxD pins for their special function */
-	set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ],
-			      NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT );
-	set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ],
-			      NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT );
-
-	/* configure serial engine */
-	*get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) =
-		NS9750_SER_CTRL_A_CE |
-		NS9750_SER_CTRL_A_STOP |
-		NS9750_SER_CTRL_A_WLS_8;
-
-	serial_setbrg();
-
-	*get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) =
-		NS9750_SER_CTRL_B_RCGT;
-
-	return 0;
-}
-
-/***********************************************************************
- * @Function: serial_putc
- * @Return: n/a
- * @Descr: writes one character to the FIFO. Blocks until FIFO is not full
- ***********************************************************************/
-
-static void ns9750_serial_putc(const char c)
-{
-	if (c == '\n')
-		serial_putc( '\r' );
-
-	while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) &
-		 NS9750_SER_STAT_A_TRDY ) ) {
-		/* do nothing, wait for characters in FIFO sent */
-	}
-
-	*(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO,
-						    CONSOLE) = c;
-}
-
-/***********************************************************************
- * @Function: serial_getc
- * @Return: the character read
- * @Descr: performs only 8bit accesses to the FIFO. No error handling
- ***********************************************************************/
-
-static int ns9750_serial_getc(void)
-{
-	int i;
-
-	while (!serial_tstc() ) {
-		/* do nothing, wait for incoming characters */
-	}
-
-	/*  at least one character in unCharCache */
-	i = (int) (unCharCache & 0xff);
-
-	unCharCache >>= 8;
-	cCharsAvailable--;
-
-	return i;
-}
-
-/***********************************************************************
- * @Function: serial_tstc
- * @Return: 0 if no input available, otherwise != 0
- * @Descr: checks for incoming FIFO not empty. Stores the incoming chars in
- *	   unCharCache and the numbers of characters in cCharsAvailable
- ***********************************************************************/
-
-static int ns9750_serial_tstc(void)
-{
-	unsigned int unRegCache;
-
-	if ( cCharsAvailable )
-		return 1;
-
-	unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE );
-	if( unRegCache & NS9750_SER_STAT_A_RBC ) {
-		*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) =
-			NS9750_SER_STAT_A_RBC;
-		unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,
-							CONSOLE );
-	}
-
-	if ( unRegCache & NS9750_SER_STAT_A_RRDY ) {
-		cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20;
-		if ( !cCharsAvailable )
-			cCharsAvailable = 4;
-
-		unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO,
-							 CONSOLE );
-		return 1;
-	}
-
-	/* no chars available */
-	return 0;
-}
-
-static void ns9750_serial_setbrg(void)
-{
-	*get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) =
-		calcBitrateRegister();
-	*get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) =
-		calcRxCharGapRegister();
-}
-
-/***********************************************************************
- * @Function: calcBitrateRegister
- * @Return: value for the serial bitrate register
- * @Descr: register value depends on clock frequency and baudrate
- ***********************************************************************/
-
-static unsigned int calcBitrateRegister( void )
-{
-	return ( NS9750_SER_BITRATE_EBIT |
-		 NS9750_SER_BITRATE_CLKMUX_BCLK |
-		 NS9750_SER_BITRATE_TMODE |
-		 NS9750_SER_BITRATE_TCDR_16 |
-		 NS9750_SER_BITRATE_RCDR_16 |
-		 ( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */
-		       ( gd->baudrate * 16 ) ) - 1 ) &
-		   NS9750_SER_BITRATE_N_MA ) );
-}
-
-/***********************************************************************
- * @Function: calcRxCharGapRegister
- * @Return: value for the character gap timer register
- * @Descr: register value depends on clock frequency and baudrate. Currently 0
- *	   is used as there is a bug with the gap timer in PLL bypass mode.
- ***********************************************************************/
-
-static unsigned int calcRxCharGapRegister( void )
-{
-	return NS9750_SER_RX_CHAR_TIMER_TRUN;
-}
-
-static struct serial_device ns9750_serial_drv = {
-	.name	= "ns9750_serial",
-	.start	= ns9750_serial_init,
-	.stop	= NULL,
-	.setbrg	= ns9750_serial_setbrg,
-	.putc	= ns9750_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= ns9750_serial_getc,
-	.tstc	= ns9750_serial_tstc,
-};
-
-void ns9750_serial_initialize(void)
-{
-	serial_register(&ns9750_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &ns9750_serial_drv;
-}
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 1f8955a0fd..7922bf0669 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -164,7 +164,6 @@ serial_initfunc(altera_serial_initialize);
 serial_initfunc(atmel_serial_initialize);
 serial_initfunc(lpc32xx_serial_initialize);
 serial_initfunc(mcf_serial_initialize);
-serial_initfunc(ns9750_serial_initialize);
 serial_initfunc(oc_serial_initialize);
 serial_initfunc(s3c64xx_serial_initialize);
 serial_initfunc(sandbox_serial_initialize);
@@ -259,7 +258,6 @@ void serial_initialize(void)
 	atmel_serial_initialize();
 	lpc32xx_serial_initialize();
 	mcf_serial_initialize();
-	ns9750_serial_initialize();
 	oc_serial_initialize();
 	s3c64xx_serial_initialize();
 	sandbox_serial_initialize();
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
deleted file mode 100644
index 3f49c6f0b1..0000000000
--- a/include/configs/ns9750dev.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- * Markus Pietrek <mpietrek@fsforth.de>
- *
- * Configuation settings for the NetSilicon NS9750 DevBoard
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
-#define	CONFIG_NS9750		1	/* in an NetSilicon NS9750 SoC     */
-#define CONFIG_NS9750DEV	1	/* on an NetSilicon NS9750 DevBoard  */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	324403200 /* Don't use PLL. SW11-4 off */
-
-#define CPU_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/2)
-#define AHB_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/4)
-#define BBUS_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/8)
-
-/*@TODO #define CONFIG_STATUS_LED*/
-#define CONFIG_USE_IRQ
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_NS9750_UART		1	/* use on-chip UART */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX          1		/* Port B */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY	3
-/*#define CONFIG_BOOTARGS	"root=ramfs devfs=mount console=ttySA0,9600" */
-
-#define CONFIG_ETHADDR		00:04:f3:ff:ff:fb /*@TODO unset */
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		192.168.42.30
-#define CONFIG_SERVERIP		192.168.42.1
-
-/*#define CONFIG_BOOTFILE	"elinos-lart" */
-/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */
-
-#define	CONFIG_SYS_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */
-
-#define	CONFIG_SYS_HZ			(CPU_CLK_FREQ/64)
-
-#define NS9750_ETH_PHY_ADDRESS	(0x0000)
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-/* TODO */
-#define CONFIG_NR_DRAM_BANKS	2	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
-#define PHYS_SDRAM_2		0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
-
-#define PHYS_FLASH_1		0x50000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* @TODO*/
-#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
-#if 0
-#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* @TODO */
-/*#define	CONFIG_ENV_IS_IN_FLASH	1*/
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
-
-#ifdef CONFIG_STATUS_LED
-
-extern void __led_init(led_id_t mask, int state);
-extern void __led_toggle(led_id_t mask);
-extern void __led_set(led_id_t mask, int state);
-
-#endif /* CONFIG_STATUS_LED */
-
-#endif	/* __CONFIG_H */
diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h
deleted file mode 100644
index 9485338f73..0000000000
--- a/include/ns9750_bbus.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for BBus usage
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_BBUS_H
-#define FS_NS9750_BBUS_H
-
-#define NS9750_BBUS_MODULE_BASE		(0x90600000)
-
-#define get_bbus_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
-
-/* We have support for 50 GPIO pins */
-
-#define get_gpio_cfg_reg_addr(pin) \
-	get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
-
-/* To Read/Modify/Write a pin configuration register, use it like
-   set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
-   They should be wrapped by cli()/sti() */
-#define set_gpio_cfg_reg_val(pin,cfg) \
-	*get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
-					~NS9750_GPIO_CFG_MASK((pin))) |\
-				NS9750_GPIO_CFG_VAL((pin),(cfg));
-
-#define NS9750_GPIO_CFG_MASK(pin)	(NS9750_GPIO_CFG_VAL(pin, \
-					 NS9750_GPIO_CFG_MA))
-#define NS9750_GPIO_CFG_VAL(pin,cfg)	((cfg) << (((pin) % 8) * 4))
-
-#define NS9750_GPIO_CFG_MA		(0x0F)
-#define NS9750_GPIO_CFG_INPUT		(0x00)
-#define NS9750_GPIO_CFG_OUTPUT		(0x08)
-#define NS9750_GPIO_CFG_FUNC_GPIO	(0x03)
-#define NS9750_GPIO_CFG_FUNC_2		(0x02)
-#define NS9750_GPIO_CFG_FUNC_1		(0x01)
-#define NS9750_GPIO_CFG_FUNC_0		(0x00)
-
-/* the register addresses */
-
-#define NS9750_BBUS_MASTER_RESET	(0x00)
-#define NS9750_BBUS_GPIO_CFG_BASE	(0x10)
-#define NS9750_BBUS_GPIO_CTRL_BASE	(0x30)
-#define NS9750_BBUS_GPIO_STAT_BASE	(0x40)
-#define NS9750_BBUS_MONITOR		(0x50)
-#define NS9750_BBUS_DMA_INT_STAT	(0x60)
-#define NS9750_BBUS_DMA_INT_ENABLE	(0x64)
-#define NS9750_BBUS_USB_CFG		(0x70)
-#define NS9750_BBUS_ENDIAN_CFG		(0x80)
-#define NS9750_BBUS_ARM_WAKE_UP		(0x90)
-
-/* register bit fields */
-
-#define NS9750_BBUS_MASTER_RESET_UTIL	(0x00000100)
-#define NS9750_BBUS_MASTER_RESET_I2C	(0x00000080)
-#define NS9750_BBUS_MASTER_RESET_1284	(0x00000040)
-#define NS9750_BBUS_MASTER_RESET_SER4	(0x00000020)
-#define NS9750_BBUS_MASTER_RESET_SER3	(0x00000010)
-#define NS9750_BBUS_MASTER_RESET_SER2	(0x00000008)
-#define NS9750_BBUS_MASTER_RESET_SER1	(0x00000004)
-#define NS9750_BBUS_MASTER_RESET_USB	(0x00000002)
-#define NS9750_BBUS_MASTER_RESET_DMA	(0x00000001)
-
-/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
-
-#define NS9750_BBUS_DMA_INT_BINT16	(0x00010000)
-#define NS9750_BBUS_DMA_INT_BINT15	(0x00008000)
-#define NS9750_BBUS_DMA_INT_BINT14	(0x00004000)
-#define NS9750_BBUS_DMA_INT_BINT13	(0x00002000)
-#define NS9750_BBUS_DMA_INT_BINT12	(0x00001000)
-#define NS9750_BBUS_DMA_INT_BINT11	(0x00000800)
-#define NS9750_BBUS_DMA_INT_BINT10	(0x00000400)
-#define NS9750_BBUS_DMA_INT_BINT9	(0x00000200)
-#define NS9750_BBUS_DMA_INT_BINT8	(0x00000100)
-#define NS9750_BBUS_DMA_INT_BINT7	(0x00000080)
-#define NS9750_BBUS_DMA_INT_BINT6	(0x00000040)
-#define NS9750_BBUS_DMA_INT_BINT5	(0x00000020)
-#define NS9750_BBUS_DMA_INT_BINT4	(0x00000010)
-#define NS9750_BBUS_DMA_INT_BINT3	(0x00000008)
-#define NS9750_BBUS_DMA_INT_BINT2	(0x00000004)
-#define NS9750_BBUS_DMA_INT_BINT1	(0x00000002)
-#define NS9750_BBUS_DMA_INT_BINT0	(0x00000001)
-
-#define NS9750_BBUS_USB_CFG_OUTEN	(0x00000008)
-#define NS9750_BBUS_USB_CFG_SPEED	(0x00000004)
-#define NS9750_BBUS_USB_CFG_CFG_MA	(0x00000003)
-#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
-#define NS9750_BBUS_USB_CFG_CFG_DEVICE	(0x00000002)
-#define NS9750_BBUS_USB_CFG_CFG_HOST	(0x00000001)
-#define NS9750_BBUS_USB_CFG_CFG_DIS	(0x00000000)
-
-#define NS9750_BBUS_ENDIAN_CFG_AHBM	(0x00001000)
-#define NS9750_BBUS_ENDIAN_CFG_I2C	(0x00000080)
-#define NS9750_BBUS_ENDIAN_CFG_IEEE1284	(0x00000040)
-#define NS9750_BBUS_ENDIAN_CFG_SER4	(0x00000020)
-#define NS9750_BBUS_ENDIAN_CFG_SER3	(0x00000010)
-#define NS9750_BBUS_ENDIAN_CFG_SER2	(0x00000008)
-#define NS9750_BBUS_ENDIAN_CFG_SER1	(0x00000004)
-#define NS9750_BBUS_ENDIAN_CFG_USB	(0x00000002)
-#define NS9750_BBUS_ENDIAN_CFG_DMA	(0x00000001)
-
-#endif /* FS_NS9750_BBUS_H */
diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h
deleted file mode 100644
index 666e4127c8..0000000000
--- a/include/ns9750_mem.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for Memory Control Module
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_MEM_H
-#define FS_NS9750_SYS_H
-
-#define NS9750_MEM_MODULE_BASE		(0xA0700000)
-
-#define get_mem_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
-
-/* the register addresses */
-
-#define NS9750_MEM_CTRL			(0x0000)
-#define NS9750_MEM_STATUS		(0x0004)
-#define NS9750_MEM_CFG			(0x0008)
-#define NS9750_MEM_DYN_CTRL		(0x0020)
-#define NS9750_MEM_DYN_REFRESH		(0x0024)
-#define NS9750_MEM_DYN_READ_CFG		(0x0028)
-#define NS9750_MEM_DYN_TRP		(0x0030)
-#define NS9750_MEM_DYN_TRAS		(0x0034)
-#define NS9750_MEM_DYN_TSREX		(0x0038)
-#define NS9750_MEM_DYN_TAPR		(0x003C)
-#define NS9750_MEM_DYN_TDAL		(0x0040)
-#define NS9750_MEM_DYN_TWR		(0x0044)
-#define NS9750_MEM_DYN_TRC		(0x0048)
-#define NS9750_MEM_DYN_TRFC		(0x004C)
-#define NS9750_MEM_DYN_TXSR		(0x0050)
-#define NS9750_MEM_DYN_TRRD		(0x0054)
-#define NS9750_MEM_DYN_TMRD		(0x0058)
-#define NS9750_MEM_STAT_EXT_WAIT	(0x0080)
-#define NS9750_MEM_DYN_CFG_BASE		(0x0100)
-#define NS9750_MEM_DYN_RAS_CAS_BASE	(0x0104)
-#define NS9750_MEM_STAT_CFG_BASE	(0x0200)
-#define NS9750_MEM_STAT_WAIT_WEN_BASE	(0x0204)
-#define NS9750_MEM_STAT_WAIT_OEN_BASE	(0x0208)
-#define NS9750_MEM_STAT_WAIT_RD_BASE	(0x020C)
-#define NS9750_MEM_STAT_WAIT_PAGE_BASE	(0x0210)
-#define NS9750_MEM_STAT_WAIR_WR_BASE	(0x0214)
-#define NS9750_MEM_STAT_WAIT_TURN_BASE	(0x0218)
-
-/* the vectored register addresses */
-
-#define NS9750_MEM_DYN_CFG(c)		(NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
-#define NS9750_MEM_DYN_RAS_CAS(c)	(NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
-#define NS9750_MEM_STAT_CFG(c)		(NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
-#define NS9750_MEM_STAT_WAIT_WEN(c)	(NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_WAIT_OEN(c)	(NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_RD(c)		(NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_PAGE(c)		(NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_WR(c)		(NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_TURN(c)		(NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
-
-/* register bit fields */
-
-#define NS9750_MEM_CTRL_L		(0x00000004)
-#define NS9750_MEM_CTRL_M		(0x00000002)
-#define NS9750_MEM_CTRL_E		(0x00000001)
-
-#define NS9750_MEM_STAT_SA		(0x00000004)
-#define NS9750_MEM_STAT_S		(0x00000002)
-#define NS9750_MEM_STAT_B		(0x00000001)
-
-#define NS9750_MEM_CFG_CLK		(0x00000010)
-#define NS9750_MEM_CFG_N		(0x00000001)
-
-#define NS9750_MEM_DYN_CTRL_NRP		(0x00004000)
-#define NS9750_MEM_DYN_CTRL_DP		(0x00002000)
-#define NS9750_MEM_DYN_CTRL_I_MA	(0x00000180)
-#define NS9750_MEM_DYN_CTRL_I_NORMAL	(0x00000000)
-#define NS9750_MEM_DYN_CTRL_I_MODE	(0x00000080)
-#define NS9750_MEM_DYN_CTRL_I_PALL	(0x00000100)
-#define NS9750_MEM_DYN_CTRL_I_NOP	(0x00000180)
-#define NS9750_MEM_DYN_CTRL_SR		(0x00000002)
-#define NS9750_MEM_DYN_CTRL_CE		(0x00000001)
-
-
-#define NS9750_MEM_DYN_REFRESH_MA	(0x000007FF)
-
-#define NS9750_MEM_DYN_READ_CFG_MA	(0x00000003)
-#define NS9750_MEM_DYN_READ_CFG_DELAY0	(0x00000001)
-#define NS9750_MEM_DYN_READ_CFG_DELAY1  (0x00000002)
-#define NS9750_MEM_DYN_READ_CFG_DELAY2	(0x00000003)
-
-#define NS9750_MEM_DYN_TRP_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TRAS_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TSREX_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TAPR_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TDAL_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TWR_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TRC_MA		(0x0000001F)
-
-#define NS9750_MEM_DYN_TRFC_MA		(0x0000001F)
-
-#define NS9750_MEM_DYN_TXSR_MA		(0x0000001F)
-
-#define NS9750_MEM_DYN_TRRD_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TMRD_MA		(0x0000000F)
-
-#define NS9750_MEM_STAT_EXTW_WAIT_MA	(0x0000003F)
-
-#define NS9750_MEM_DYN_CFG_P		(0x00100000)
-#define NS9750_MEM_DYN_CFG_BDMC		(0x00080000)
-#define NS9750_MEM_DYN_CFG_AM		(0x00004000)
-#define NS9750_MEM_DYN_CFG_AM_MA	(0x00001F80)
-#define NS9750_MEM_DYN_CFG_MD		(0x00000018)
-
-#define NS9750_MEM_DYN_RAS_CAS_CAS_MA	(0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_1	(0x00000100)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_2	(0x00000200)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_3	(0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_MA	(0x00000003)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_1	(0x00000001)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_2	(0x00000002)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_3	(0x00000003)
-
-#define NS9750_MEM_STAT_CFG_PSMC	(0x00100000)
-#define NS9750_MEM_STAT_CFG_BSMC	(0x00080000)
-#define NS9750_MEM_STAT_CFG_EW		(0x00000100)
-#define NS9750_MEM_STAT_CFG_PB		(0x00000080)
-#define NS9750_MEM_STAT_CFG_PC		(0x00000040)
-#define NS9750_MEM_STAT_CFG_PM		(0x00000008)
-#define NS9750_MEM_STAT_CFG_MW_MA	(0x00000003)
-#define NS9750_MEM_STAT_CFG_MW_8	(0x00000000)
-#define NS9750_MEM_STAT_CFG_MW_16	(0x00000001)
-#define NS9750_MEM_STAT_CFG_MW_32	(0x00000002)
-
-#define NS9750_MEM_STAT_WAIT_WEN_MA	(0x0000000F)
-
-#define NS9750_MEM_STAT_WAIT_OEN_MA	(0x0000000F)
-
-#define NS9750_MEM_STAT_WAIT_RD_MA	(0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_PAGE_MA	(0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_WR_MA	(0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_TURN_MA	(0x0000000F)
-
-
-#endif /* FS_NS9750_MEM_H */
diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h
deleted file mode 100644
index b5c297e436..0000000000
--- a/include/ns9750_ser.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @References: [1] NS9750 Hardware Reference, December 2003
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_SER_H
-#define FS_NS9750_SER_H
-
-#define NS9750_SER_MODULE_BASE		(0x90200000)
-
-#define get_ser_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
-
-#define get_ser_reg_addr_channel(reg,chan) \
-	get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
-
-/* the register addresses */
-
-#define NS9750_SER_CTRL_A		(0x00)
-#define NS9750_SER_CTRL_B		(0x04)
-#define NS9750_SER_STAT_A		(0x08)
-#define NS9750_SER_BITRATE		(0x0C)
-#define NS9750_SER_FIFO			(0x10)
-#define NS9750_SER_RX_BUF_TIMER		(0x14)
-#define NS9750_SER_RX_CHAR_TIMER	(0x18)
-#define NS9750_SER_RX_MATCH		(0x1C)
-#define NS9750_SER_RX_MATCH_MASK	(0x20)
-#define NS9750_SER_FLOW_CTRL		(0x34)
-#define NS9750_SER_FLOW_CTRL_FORCE	(0x38)
-
-/* register bit fields */
-
-/* control A register */
-
-#define NS9750_SER_CTRL_A_CE		(0x80000000)
-#define NS9750_SER_CTRL_A_BRK		(0x40000000)
-#define NS9750_SER_CTRL_A_STICKP	(0x20000000)
-#define NS9750_SER_CTRL_A_EPS		(0x10000000)
-#define NS9750_SER_CTRL_A_PE		(0x08000000)
-#define NS9750_SER_CTRL_A_STOP		(0x04000000)
-#define NS9750_SER_CTRL_A_WLS_MA	(0x03000000)
-#define NS9750_SER_CTRL_A_WLS_5		(0x00000000)
-#define NS9750_SER_CTRL_A_WLS_6		(0x01000000)
-#define NS9750_SER_CTRL_A_WLS_7		(0x02000000)
-#define NS9750_SER_CTRL_A_WLS_8		(0x03000000)
-#define NS9750_SER_CTRL_A_CTSTX		(0x00800000)
-#define NS9750_SER_CTRL_A_RTSRX		(0x00400000)
-#define NS9750_SER_CTRL_A_RL		(0x00200000)
-#define NS9750_SER_CTRL_A_LL		(0x00100000)
-#define NS9750_SER_CTRL_A_RES		(0x000CF000)
-#define NS9750_SER_CTRL_A_DTR		(0x00020000)
-#define NS9750_SER_CTRL_A_RTS		(0x00010000)
-#define NS9750_SER_CTRL_A_RIE_MA	(0x00000E00)
-#define NS9750_SER_CTRL_A_ERXDMA	(0x00000100)
-#define NS9750_SER_CTRL_A_RIC_MA	(0x000000E0)
-#define NS9750_SER_CTRL_A_TIC_MA	(0x0000001E)
-#define NS9750_SER_CTRL_A_ETXDMA	(0x00000001)
-
-/* control B register */
-
-#define NS9750_SER_CTRL_B_RDM1		(0x80000000)
-#define NS9750_SER_CTRL_B_RDM2		(0x40000000)
-#define NS9750_SER_CTRL_B_RDM3		(0x20000000)
-#define NS9750_SER_CTRL_B_RDM4		(0x10000000)
-#define NS9750_SER_CTRL_B_RBGT		(0x08000000)
-#define NS9750_SER_CTRL_B_RCGT		(0x04000000)
-#define NS9750_SER_CTRL_B_MODE_MA	(0x00300000)
-#define NS9750_SER_CTRL_B_MODE_UART	(0x00000000)
-#define NS9750_SER_CTRL_B_MODE_HDLC	(0x00100000)
-#define NS9750_SER_CTRL_B_MODE_SPI_M	(0x00200000)
-#define NS9750_SER_CTRL_B_MODE_SPI_S	(0x00300000)
-#define NS9750_SER_CTRL_B_BITORDR	(0x00080000)
-#define NS9750_SER_CTRL_B_RES		(0x0007703F)
-#define NS9750_SER_CTRL_B_RTSTX		(0x00008000)
-#define NS9750_SER_CTRL_B_ENDEC_MA	(0x00000FC0)
-
-/* status A register */
-
-#define NS9750_SER_STAT_A_MATCH1	(0x80000000)
-#define NS9750_SER_STAT_A_MATCH2	(0x40000000)
-#define NS9750_SER_STAT_A_MATCH3	(0x20000000)
-#define NS9750_SER_STAT_A_MATCH4	(0x10000000)
-#define NS9750_SER_STAT_A_BGAP		(0x08000000)
-#define NS9750_SER_STAT_A_CGAP		(0x04000000)
-#define NS9750_SER_STAT_A_RXFDB_MA	(0x00300000)
-#define NS9750_SER_STAT_A_RXFDB_FULL	(0x00000000)
-#define NS9750_SER_STAT_A_RXFDB_1	(0x00100000)
-#define NS9750_SER_STAT_A_RXFDB_2	(0x00200000)
-#define NS9750_SER_STAT_A_RXFDB_3	(0x00300000)
-#define NS9750_SER_STAT_A_DCD		(0x00080000)
-#define NS9750_SER_STAT_A_RI		(0x00040000)
-#define NS9750_SER_STAT_A_DSR		(0x00020000)
-#define NS9750_SER_STAT_A_CTS		(0x00010000)
-#define NS9750_SER_STAT_A_RBRK		(0x00008000)
-#define NS9750_SER_STAT_A_RFE		(0x00004000)
-#define NS9750_SER_STAT_A_RPE		(0x00002000)
-#define NS9750_SER_STAT_A_ROVER		(0x00001000)
-#define NS9750_SER_STAT_A_RRDY		(0x00000800)
-#define NS9750_SER_STAT_A_RHALF		(0x00000400)
-#define NS9750_SER_STAT_A_RBC		(0x00000200)
-#define NS9750_SER_STAT_A_RFULL		(0x00000100)
-#define NS9750_SER_STAT_A_DCDI		(0x00000080)
-#define NS9750_SER_STAT_A_RII		(0x00000040)
-#define NS9750_SER_STAT_A_DSRI		(0x00000020)
-#define NS9750_SER_STAT_A_CTSI		(0x00000010)
-#define NS9750_SER_STAT_A_TRDY		(0x00000008)
-#define NS9750_SER_STAT_A_THALF		(0x00000004)
-#define NS9750_SER_STAT_A_TBC		(0x00000002)
-#define NS9750_SER_STAT_A_TEMPTY	(0x00000001)
-
-#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
-				        NS9750_SER_STAT_A_ROVER | \
-				        NS9750_SER_STAT_A_RPE )
-#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
-				        NS9750_SER_STAT_A_RBRK | \
-				        NS9750_SER_STAT_A_RRDY | \
-					NS9750_SER_STAT_A_RHALF | \
-					NS9750_SER_STAT_A_RBC | \
-					NS9750_SER_STAT_A_DCDI | \
-					NS9750_SER_STAT_A_RII | \
-					NS9750_SER_STAT_A_DSRI | \
-					NS9750_SER_STAT_A_CTSI )
-#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
-				        NS9750_SER_STAT_A_THALF | \
-				        NS9750_SER_STAT_A_TBC | \
-					NS9750_SER_STAT_A_TEMPTY )
-/* bit rate register */
-
-#define NS9750_SER_BITRATE_EBIT		 (0x80000000)
-#define NS9750_SER_BITRATE_TMODE	 (0x40000000)
-#define NS9750_SER_BITRATE_RXSRC	 (0x20000000)
-#define NS9750_SER_BITRATE_TXSRC	 (0x10000000)
-#define NS9750_SER_BITRATE_RXEXT	 (0x08000000)
-#define NS9750_SER_BITRATE_TXEXT	 (0x04000000)
-#define NS9750_SER_BITRATE_CLKMUX_MA	 (0x03000000)
-#define NS9750_SER_BITRATE_CLKMUX_XTAL	 (0x00000000)
-#define NS9750_SER_BITRATE_CLKMUX_BCLK	 (0x01000000)
-#define NS9750_SER_BITRATE_CLKMUX_OUT1	 (0x02000000)
-#define NS9750_SER_BITRATE_CLKMUX_OUT2	 (0x03000000)
-#define NS9750_SER_BITRATE_TXCINV	 (0x00800000)
-#define NS9750_SER_BITRATE_RXCINV	 (0x00400000)
-#define NS9750_SER_BITRATE_TCDR_MA	 (0x00180000)
-#define NS9750_SER_BITRATE_TCDR_1	 (0x00000000)
-#define NS9750_SER_BITRATE_TCDR_8	 (0x00080000)
-#define NS9750_SER_BITRATE_TCDR_16	 (0x00100000)
-#define NS9750_SER_BITRATE_TCDR_32	 (0x00180000)
-#define NS9750_SER_BITRATE_RCDR_MA	 (0x00070000)
-#define NS9750_SER_BITRATE_RCDR_1	 (0x00000000)
-#define NS9750_SER_BITRATE_RCDR_8	 (0x00020000)
-#define NS9750_SER_BITRATE_RCDR_16	 (0x00040000)
-#define NS9750_SER_BITRATE_RCDR_32	 (0x00060000)
-#define NS9750_SER_BITRATE_TICS		 (0x00010000)
-#define NS9750_SER_BITRATE_RICS		 (0x00008000)
-#define NS9750_SER_BITRATE_N_MA		 (0x00007FFF)
-
-/* receive buffer gap timer */
-
-#define NS9750_SER_RX_BUF_TIMER_TRUN	 (0x80000000) /* UART and SPI */
-#define NS9750_SER_RX_BUF_TIMER_BT_MA	 (0x0000FFFF) /* UART and SPI */
-#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
-
-/* receive character gap timer */
-
-#define NS9750_SER_RX_CHAR_TIMER_TRUN	 (0x80000000)
-#define NS9750_SER_RX_CHAR_TIMER_CT_MA	 (0x000FFFFF)
-
-/* receive match */
-
-#define NS9750_SER_RX_MATCH_RDMB1_MA	 (0xFF000000)
-#define NS9750_SER_RX_MATCH_RDMB2_MA	 (0x00FF0000)
-#define NS9750_SER_RX_MATCH_RDMB3_MA	 (0x0000FF00)
-#define NS9750_SER_RX_MATCH_RDMB4_MA	 (0x000000FF)
-
-/* receive match mask */
-
-#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
-#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
-#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
-#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
-
-#endif /* FS_NS9750_SER_H */
diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h
deleted file mode 100644
index f1dc2b2382..0000000000
--- a/include/ns9750_sys.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for SYS Control Module
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_SYS_H
-#define FS_NS9750_SYS_H
-
-#define NS9750_SYS_MODULE_BASE		(0xA0900000)
-
-#define get_sys_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
-
-/* the register addresses */
-
-#define NS9750_SYS_AHB_GEN		(0x0000)
-#define NS9750_SYS_BRC_BASE		(0x0004)
-#define NS9750_SYS_AHB_TIMEOUT		(0x0014)
-#define NS9750_SYS_AHB_ERROR1		(0x0018)
-#define NS9750_SYS_AHB_ERROR2		(0x001C)
-#define NS9750_SYS_AHB_MON		(0x0020)
-#define NS9750_SYS_TIMER_COUNT_BASE	(0x0044)
-#define NS9750_SYS_TIMER_READ_BASE	(0x0084)
-#define NS9750_SYS_INT_VEC_ADR_BASE	(0x00C4)
-#define NS9750_SYS_INT_CFG_BASE		(0x0144)
-#define NS9750_SYS_ISRADDR		(0x0164)
-#define NS9750_SYS_INT_STAT_ACTIVE	(0x0168)
-#define NS9750_SYS_INT_STAT_RAW		(0x016C)
-#define NS9750_SYS_TIMER_INT_STAT	(0x0170)
-#define NS9750_SYS_SW_WDOG_CFG		(0x0174)
-#define NS9750_SYS_SW_WDOG_TIMER	(0x0178)
-#define NS9750_SYS_CLOCK		(0x017C)
-#define NS9750_SYS_RESET		(0x0180)
-#define NS9750_SYS_MISC			(0x0184)
-#define NS9750_SYS_PLL			(0x0188)
-#define NS9750_SYS_ACT_INT_STAT		(0x018C)
-#define NS9750_SYS_TIMER_CTRL_BASE	(0x0190)
-#define NS9750_SYS_CS_DYN_BASE_BASE	(0x01D0)
-#define NS9750_SYS_CS_DYN_MASK_BASE	(0x01D4)
-#define NS9750_SYS_CS_STATIC_BASE_BASE	(0x01F0)
-#define NS9750_SYS_CS_STATIC_MASK_BASE	(0x01F4)
-#define NS9750_SYS_GEN_ID		(0x0210)
-#define NS9750_SYS_EXT_INT_CTRL_BASE	(0x0214)
-
-/* the vectored register addresses */
-
-#define NS9750_SYS_TIMER_COUNT(c)	(NS9750_SYS_TIMER_COUNT_BASE + (c))
-#define NS9750_SYS_TIMER_READ(c)	(NS9750_SYS_TIMER_READ_BASE + (c))
-#define NS9750_SYS_INT_VEC_ADR(c)	(NS9750_SYS_INT_VEC_ADR_BASE + (c))
-#define NS9750_SYS_TIMER_CTRL(c)	(NS9750_SYS_TIMER_CTRL_BASE + (c))
-/* CS_DYN start with 4 */
-#define NS9750_SYS_CS_DYN_BASE(c)	(NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2)
-#define NS9750_SYS_CS_DYN_MASK(c)	(NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2)
-/* CS_STATIC start with 0 */
-#define NS9750_SYS_CS_STATIC_BASE(c)	(NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2)
-#define NS9750_SYS_CS_STATIC_MASK(c)	(NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2)
-#define NS9750_SYS_EXT_INT_CTRL(c)	(NS9750_SYS_EXT_INT_CTRL + (c))
-
-/* register bit fields */
-
-#define NS9750_SYS_AHB_GEN_EXMAM	(0x00000001)
-
-/* need to be n*8bit to BRC channel */
-#define NS9750_SYS_BRC_CEB		(0x00000080)
-#define NS9750_SYS_BRC_BRF_MA		(0x00000030)
-#define NS9750_SYS_BRC_BRF_100		(0x00000000)
-#define NS9750_SYS_BRC_BRF_75		(0x00000010)
-#define NS9750_SYS_BRC_BRF_50		(0x00000020)
-#define NS9750_SYS_BRC_BRF_25		(0x00000030)
-
-#define NS9750_SYS_AHB_TIMEOUT_BAT_MA	(0xFFFF0000)
-#define NS9750_SYS_AHB_TIMEOUT_BMT_MA	(0x0000FFFF)
-
-#define NS9750_SYS_AHB_ERROR2_ABL	(0x00040000)
-#define NS9750_SYS_AHB_ERROR2_AER	(0x00020000)
-#define NS9750_SYS_AHB_ERROR2_ABM	(0x00010000)
-#define NS9750_SYS_AHB_ERROR2_ABA	(0x00008000)
-#define NS9750_SYS_AHB_ERROR2_HWRT	(0x00004000)
-#define NS9750_SYS_AHB_ERROR2_HMID_MA	(0x00003C00)
-#define NS9750_SYS_AHB_ERROR2_HTPC_MA	(0x000003C0)
-#define NS9750_SYS_AHB_ERROR2_HSZ_MA	(0x00000038)
-#define NS9750_SYS_AHB_ERROR2_RR_MA	(0x00000007)
-
-#define NS9750_SYS_AHB_MON_EIC		(0x00800000)
-#define NS9750_SYS_AHB_MON_MBII		(0x00400000)
-#define NS9750_SYS_AHB_MON_MBL_MA	(0x003FFFC0)
-#define NS9750_SYS_AHB_MON_MBLDC	(0x00000020)
-#define NS9750_SYS_AHB_MON_SERDC	(0x00000010)
-#define NS9750_SYS_AHB_MON_BMTC_MA	(0x0000000C)
-#define NS9750_SYS_AHB_MON_BMTC_RECORD	(0x00000000)
-#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ	(0x00000004)
-#define NS9750_SYS_AHB_MON_BMTC_GEN_RES	(0x00000008)
-#define NS9750_SYS_AHB_MON_BATC_MA	(0x00000003)
-#define NS9750_SYS_AHB_MON_BATC_RECORD	(0x00000000)
-#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ	(0x00000001)
-#define NS9750_SYS_AHB_MON_BATC_GEN_RES	(0x00000002)
-
-/* need to be n*8bit to Int Level */
-
-#define NS9750_SYS_INT_CFG_IE		(0x00000080)
-#define NS9750_SYS_INT_CFG_IT		(0x00000020)
-#define NS9750_SYS_INT_CFG_IAD_MA	(0x0000001F)
-
-#define NS9750_SYS_TIMER_INT_STAT_MA	(0x0000FFFF)
-
-#define NS9750_SYS_SW_WDOG_CFG_SWWE	(0x00000080)
-#define NS9750_SYS_SW_WDOG_CFG_SWWI	(0x00000020)
-#define NS9750_SYS_SW_WDOG_CFG_SWWIC	(0x00000010)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA	(0x00000007)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2	(0x00000000)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4	(0x00000001)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8	(0x00000002)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16	(0x00000003)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32	(0x00000004)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64	(0x00000005)
-
-#define NS9750_SYS_CLOCK_LPCS_MA	(0x00000380)
-#define NS9750_SYS_CLOCK_LPCS_1		(0x00000000)
-#define NS9750_SYS_CLOCK_LPCS_2		(0x00000080)
-#define NS9750_SYS_CLOCK_LPCS_4		(0x00000100)
-#define NS9750_SYS_CLOCK_LPCS_8		(0x00000180)
-#define NS9750_SYS_CLOCK_LPCS_EXT	(0x00000200)
-#define NS9750_SYS_CLOCK_BBC		(0x00000040)
-#define NS9750_SYS_CLOCK_LCC		(0x00000020)
-#define NS9750_SYS_CLOCK_MCC		(0x00000010)
-#define NS9750_SYS_CLOCK_PARBC		(0x00000008)
-#define NS9750_SYS_CLOCK_PC		(0x00000004)
-#define NS9750_SYS_CLOCK_MACC		(0x00000001)
-
-#define NS9750_SYS_RESET_SR		(0x80000000)
-#define NS9750_SYS_RESET_I2CW		(0x00100000)
-#define NS9750_SYS_RESET_CSE		(0x00080000)
-#define NS9750_SYS_RESET_SMWE		(0x00040000)
-#define NS9750_SYS_RESET_EWE		(0x00020000)
-#define NS9750_SYS_RESET_PI3WE		(0x00010000)
-#define NS9750_SYS_RESET_BBT		(0x00000040)
-#define NS9750_SYS_RESET_LCDC		(0x00000020)
-#define NS9750_SYS_RESET_MEMC		(0x00000010)
-#define NS9750_SYS_RESET_PCIAR		(0x00000008)
-#define NS9750_SYS_RESET_PCIM		(0x00000004)
-#define NS9750_SYS_RESET_MACM		(0x00000001)
-
-#define NS9750_SYS_MISC_REV_MA		(0xFF000000)
-#define NS9750_SYS_MISC_PCIA		(0x00002000)
-#define NS9750_SYS_MISC_VDIS		(0x00001000)
-#define NS9750_SYS_MISC_BMM		(0x00000800)
-#define NS9750_SYS_MISC_CS1DB		(0x00000400)
-#define NS9750_SYS_MISC_CS1DW_MA	(0x00000300)
-#define NS9750_SYS_MISC_MCCM		(0x00000080)
-#define NS9750_SYS_MISC_PMSS		(0x00000040)
-#define NS9750_SYS_MISC_CS1P		(0x00000020)
-#define NS9750_SYS_MISC_ENDM		(0x00000008)
-#define NS9750_SYS_MISC_MBAR		(0x00000004)
-#define NS9750_SYS_MISC_IRAM0		(0x00000001)
-
-#define NS9750_SYS_PLL_PLLBS		(0x02000000)
-#define NS9750_SYS_PLL_PLLFS_MA		(0x01800000)
-#define NS9750_SYS_PLL_PLLIS_MA		(0x00600000)
-#define NS9750_SYS_PLL_PLLND_MA		(0x001F0000)
-#define NS9750_SYS_PLL_PLLSW		(0x00008000)
-#define NS9750_SYS_PLL_PLLBSSW		(0x00000200)
-#define NS9750_SYS_PLL_FSEL_MA		(0x00000180)
-#define NS9750_SYS_PLL_CPCC_MA		(0x00000060)
-#define NS9750_SYS_PLL_NDSW_MA		(0x0000001F)
-
-#define NS9750_SYS_ACT_INT_STAT_MA	(0x0000FFFF)
-
-#define NS9750_SYS_TIMER_CTRL_TEN	(0x00008000)
-#define NS9750_SYS_TIMER_CTRL_INTC	(0x00000200)
-#define NS9750_SYS_TIMER_CTRL_TLCS_MA	(0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_1	(0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TLCS_2	(0x00000040)
-#define NS9750_SYS_TIMER_CTRL_TLCS_4	(0x00000080)
-#define NS9750_SYS_TIMER_CTRL_TLCS_8	(0x000000C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_16	(0x00000100)
-#define NS9750_SYS_TIMER_CTRL_TLCS_32	(0x00000140)
-#define NS9750_SYS_TIMER_CTRL_TLCS_64	(0x00000180)
-#define NS9750_SYS_TIMER_CTRL_TLCS_EXT	(0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TM_MA	(0x00000030)
-#define NS9750_SYS_TIMER_CTRL_TM_INT	(0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TM_LOW	(0x00000010)
-#define NS9750_SYS_TIMER_CTRL_TM_HIGH	(0x00000020)
-#define NS9750_SYS_TIMER_CTRL_INTS	(0x00000008)
-#define NS9750_SYS_TIMER_CTRL_UDS	(0x00000004)
-#define NS9750_SYS_TIMER_CTRL_TSZ	(0x00000002)
-#define NS9750_SYS_TIMER_CTRL_REN	(0x00000001)
-
-#define NS9750_SYS_EXT_INT_CTRL_STS	(0x00000008)
-#define NS9750_SYS_EXT_INT_CTRL_CLR	(0x00000004)
-#define NS9750_SYS_EXT_INT_CTRL_PLTY	(0x00000002)
-#define NS9750_SYS_EXT_INT_CTRL_LVEDG	(0x00000001)
-
-#endif /* FS_NS9750_SYS_H */