armv8: ls2085a: Add workaround of errata A009635

If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

5 files changed, 81 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
index db9359dd33..f9323c1d28 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@@ -303,3 +303,23 @@ How to use commands :-
 	=> fsl_mc start aiop 0x580900000
 	=> setenv ethact DPMAC1@xgmii
 	=> fsl_mc apply dpl 580700000
+
+Errata A009635
+---------------
+If the core runs at higher than x3 speed of the platform, there is
+possiblity about sev instruction to getting missed by other cores.
+This is because of SoC Run Control block may not able to sample
+the EVENTI(Sev) signals.
+
+Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
+wake up A57 cores
+
+Errata workaround uses Env variable "a009635_interval_val". It uses decimal
+value.
+- Default value of env variable is platform clock (MHz)
+
+- User can modify default value by updating the env variable
+  setenv a009635_interval_val 600; saveenv;
+  It configure platform clock as 600 MHz
+
+- Env variable as 0 signifies no workaround
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 571ee7b70d..8847fc0287 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -484,7 +484,13 @@ int arch_early_init_r(void)
 {
 #ifdef CONFIG_MP
 	int rv = 1;
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+	erratum_a009635();
+#endif
 
+#ifdef CONFIG_MP
 	rv = fsl_layerscape_wake_seconday_cores();
 	if (rv)
 		printf("Did not wake secondary cores\n");
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f427ac2bb2..8896b70e78 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -9,10 +9,53 @@
 #include <asm/arch/soc.h>
 #include <asm/io.h>
 #include <asm/global_data.h>
+#include <asm/arch-fsl-layerscape/config.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+#define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"
+
+static unsigned long get_internval_val_mhz(void)
+{
+	char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
+	/*
+	 *  interval is the number of platform cycles(MHz) between
+	 *  wake up events generated by EPU.
+	 */
+	ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
+
+	if (interval)
+		interval_mhz = simple_strtoul(interval, NULL, 10);
+
+	return interval_mhz;
+}
+
+void erratum_a009635(void)
+{
+	u32 val;
+	unsigned long interval_mhz = get_internval_val_mhz();
+
+	if (!interval_mhz)
+		return;
+
+	val = in_le32(DCSR_CGACRE5);
+	writel(val | 0x00000200, DCSR_CGACRE5);
+
+	val = in_le32(EPU_EPCMPR5);
+	writel(interval_mhz, EPU_EPCMPR5);
+	val = in_le32(EPU_EPCCR5);
+	writel(val | 0x82820000, EPU_EPCCR5);
+	val = in_le32(EPU_EPSMCR5);
+	writel(val | 0x002f0000, EPU_EPSMCR5);
+	val = in_le32(EPU_EPECR5);
+	writel(val | 0x20000000, EPU_EPECR5);
+	val = in_le32(EPU_EPGCR);
+	writel(val | 0x80000000, EPU_EPGCR);
+}
+#endif	/* CONFIG_SYS_FSL_ERRATUM_A009635 */
+
 static void erratum_a008751(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index afc329ad6b..b5a2d28c08 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -98,11 +98,20 @@
 #define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
 #define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
 
+#define DCSR_CGACRE5		0x700070914ULL
+#define EPU_EPCMPR5		0x700060914ULL
+#define EPU_EPCCR5		0x700060814ULL
+#define EPU_EPSMCR5		0x700060228ULL
+#define EPU_EPECR5		0x700060314ULL
+#define EPU_EPCTR5		0x700060a14ULL
+#define EPU_EPGCR		0x700060000ULL
+
 #define CONFIG_SYS_FSL_ERRATUM_A008336
 #define CONFIG_SYS_FSL_ERRATUM_A008511
 #define CONFIG_SYS_FSL_ERRATUM_A008514
 #define CONFIG_SYS_FSL_ERRATUM_A008585
 #define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009635
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 86919065f3..504c1f9197 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -58,4 +58,7 @@ void fsl_lsch2_early_init_f(void);
 #endif
 
 void cpu_name(char *name);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+void erratum_a009635(void);
+#endif
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */