diff options
| author | Markus Klotzbuecher <mk@denx.de> | 2008-07-10 10:26:07 +0200 |
|---|---|---|
| committer | Markus Klotzbuecher <mk@denx.de> | 2008-07-10 10:26:07 +0200 |
| commit | 794a5924972fc8073616e98a2668da4a5f9aea90 (patch) | |
| tree | dd0db39b3e183b5bcb0300d5377d7a0d5ac5fd0c | |
| parent | f2aeecc320f5b181b30effcaa67683aec8d5a843 (diff) | |
| parent | 4188f0491886b3b486164e819c0a83fdb97efd7d (diff) | |
| download | blackbird-obmc-uboot-794a5924972fc8073616e98a2668da4a5f9aea90.tar.gz blackbird-obmc-uboot-794a5924972fc8073616e98a2668da4a5f9aea90.zip | |
Merge branch 'master' of git://www.denx.de/git/u-boot
1087 files changed, 26863 insertions, 11587 deletions
@@ -1,3 +1,3716 @@ +commit 8915f1189c1d29d8be7f4de325702d90a8988219 +Author: Paul Gortmaker <paul.gortmaker@windriver.com> +Date: Wed Jul 9 17:50:45 2008 -0400 + + e1000: add support for 82545GM 64bit PCI-X copper variant + + This PCI-X e1000 variant works by just adding in the correct + PCI IDs in the appropriate places. + + Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> + +commit 21ae6ca0315afdbc65dc3e95ffd5763e6773d030 +Author: Daniel Hellstrom <daniel@gaisler.com> +Date: Wed Jul 9 12:34:11 2008 +0000 + + SPARC: Build error fix + + (introduced by commit 391fd93ab23e15ab3dd58a54f5b609024009c378) + + This patch makes SPARC targets build again. It is caused by + phys_addr_t and phys_size_t being defined in the wrong header + file. include/lmb.h need those typedefs to build. + + Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> + +commit 11ccc33fa21acce108f6b4a6936e3271af904c64 +Author: Marcel Ziswiler <marcel@ziswiler.com> +Date: Wed Jul 9 08:17:15 2008 +0200 + + Many spelling fixes in README. + + Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> + +commit dbab0691d2533560f7e91b92ae844046a9ad1df3 +Author: Marcel Ziswiler <marcel@ziswiler.com> +Date: Wed Jul 9 08:17:06 2008 +0200 + + Minor spelling fix in comment. + + Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> + +commit 89134ea1f67208fd3160bdbb0b9eaab4eab98484 +Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> +Date: Tue Jul 8 14:54:58 2008 -0400 + + Round the serial port clock divisor value returned by calc_divisor() + + Round the serial port clock divisor value returned by + calc_divisor(). + + Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> + Signed-off-by: John Roberts <john.roberts@pwav.com> + +commit 9d2e3947b2944e5bb85b4335533f8c93c58445fe +Author: Scott Wood <scottwood@freescale.com> +Date: Wed Jul 9 17:47:52 2008 -0500 + + NAND: ifdef-protect most of nand.h when using legacy NAND. + + Some macros such as NAND_CTL_SETALE conflict between current and legacy + NAND, being defined by the subsystem in the former case and the board + config file in the latter. + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 2b1fa9d383cbbb7d347c1583bd6ca4e181ba8e9e +Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> +Date: Tue Jul 8 11:02:05 2008 -0400 + + ARM: Fix for wrong patch version applied for Lyrtech SFF-SDR board (ARM926EJS) + + ARM: Fix for incorrect version of patch applied when + adding support for the Lyrtech SFF-SDR board. + + Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> + Signed-off-by: Philip Balister, OpenSDR <philip@opensdr.com> + +commit 47042b363ee5022b8180c65d3f4558e7972c79cd +Author: Kyungmin Park <kmpark@infradead.org> +Date: Tue Jul 8 09:08:40 2008 +0900 + + Remove useless print message at apollon + + Remove useless print message at apollon + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit 98874ff329d4a5b32c467b43f6e966e1aa68479f +Author: Andy Fleming <afleming@freescale.com> +Date: Mon Jul 7 14:24:39 2008 -0500 + + Fix LMB type issues + + The LMB code now uses phys_addr_t and phys_size_t. Also, there were a couple + of casting problems in the bootm code that called the LMB functions. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit da8693a91b8eef75ade8de50a1b2ce035bc5fb54 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Jul 7 09:39:06 2008 -0500 + + Fix compiler warnings + + gcc-4.3.x generates the following: + + bootm.c: In function 'do_bootm_linux': + bootm.c:208: warning: cast from pointer to integer of different size + bootm.c:215: warning: cast from pointer to integer of different size + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 5bb12dbd7ae03189b6c13d8737b5a1b37c3df698 +Author: Harald Welte <laforge@gnumonks.org> +Date: Mon Jul 7 15:40:39 2008 +0800 + + Remove code duplication for setting the default environment + + common/env_common.c (default_env): new function that resets the environment to + the default value + common/env_common.c (env_relocate): use default_env instead of own copy + common/env_nand.c (env_relocate_spec): use default_env instead of own copy + include/environment.h: added default_env prototype + + Signed-off-by: Werner Almesberger <werner@openmoko.org> + Signed-off-by: Harald Welte <laforge@openmoko.org> + +commit 99c2b434d37863df5dda5207a53760c6506fc2be +Author: Marcel Ziswiler <marcel@ziswiler.com> +Date: Sun Jun 22 16:13:46 2008 +0200 + + NAND: Fix warning due to missing env_ptr casts to u_char * in env_nand.c. + + The writeenv() and readenv() calls introduced by the recently added bad block + management for environment variables were missing casts therefore producing + compile time warnings. + While at it fixing some typo in a comment and indentation. + + Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 3167c5386ea1c98b638be5d8763ef6d5938ef1bd +Author: Scott Wood <scottwood@freescale.com> +Date: Fri Jun 20 12:38:57 2008 -0500 + + NAND: Rename DEBUG to MTDDEBUG to avoid namespace pollution. + + This is particularly problematic now that non-NAND-specific code is + including <nand.h>, and thus all debugging code is being compiled + regardless of whether it was requested, as reported by Scott McNutt + <smcnutt@psyent.com>. + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit c3bf1ad7baa1b0dd989dedc260b7098b6089ae05 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Thu Jun 12 19:27:58 2008 +0200 + + mmc: Move atmel_mci driver into drivers/mmc + + This makes it easier to use the driver on other platforms. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + Acked-by: Jean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit d2d54ea449639f3d1a6007e333ab9fcc609a18f0 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Thu Jun 12 19:27:57 2008 +0200 + + avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver + + After we move the atmel_mci driver into drivers/mmc, we can't select + it with CONFIG_MMC anymore. Introduce a new symbol specifically for + this driver so that there's no ambiguity. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + Acked-by: Jean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 5ce13051a48c62bda9723df3b4778c492fb47f36 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Thu Jun 12 19:27:56 2008 +0200 + + Create drivers/mmc subdirectory + + In order to consolidate more of the various MMC drivers around the + tree, we must first have a common place to put them. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + Acked-by: Jean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit b502611b51f02718c2d1117d4981dabceb5af6de +Author: Joakim Tjernlund <joakim.tjernlund@transmode.se> +Date: Sun Jul 6 12:30:09 2008 +0200 + + Change env_get_char from a global function ptr to a function + + This avoids an early global data reference. + + Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> + +commit 27269417ade432189b234d9fbac98b54e37b978c +Author: Matvejchikov Ilya <matvejchikov@gmail.com> +Date: Sun Jul 6 13:57:58 2008 +0400 + + Some copy-n-paste fixes in printf usage + + Signed-off-by: Matvejchikov Ilya <matvejchikov@gmail.com> + +commit 0e6989b9faf1588e8723535539e88a0df3c71356 +Author: Matvejchikov Ilya <matvejchikov@gmail.com> +Date: Sun Jul 6 13:57:00 2008 +0400 + + FDT memory and pci node fixes for MPC8260ADS + + Signed-off-by: Matvejchikov Ilya <matvejchikov@gmail.com> + +commit dc4b0b38d4aadf08826f6c31270f1eecd27964fd +Author: Andrew Klossner <andrew@cesa.opbu.xerox.com> +Date: Mon Jul 7 06:41:14 2008 -0700 + + Fix printf errors. + + The compiler will help find mismatches between printf formats and + arguments if you let it. This patch adds the necessary attributes to + declarations in include/common.h, then begins to correct the resulting + compiler warnings. Some of these were bugs, e.g., "$d" instead of + "%d" and incorrect arguments. Others were just annoying, like + int-long mismatches on a system where both are 32 bits. It's worth + fixing the annoying errors to catch the real ones. + + Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com> + +commit 417faf285b2527acb2de24c5cd3e2621d385408c +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Wed Jul 9 11:09:41 2008 -0500 + + Allow print_size to print in GB + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit e7c374529c87525c9aa463e0557c287887ae4e9e +Author: Jason McMullan <mcmullan@netapp.com> +Date: Sun Jun 8 23:56:00 2008 -0400 + + mips: When booting Linux images, add 'ethaddr' and 'eth1addr' to the environment + + Add 'ethaddr' and 'eth1addr' to the Linux kernel environment if + they are set in the U-Boot environment. + + Signed-off-by: Jason McMullan <mcmullan@netapp.com> + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 0192d7d56e9320819dea262f49789ae18fdd2c72 +Author: Stefan Roese <sr@denx.de> +Date: Tue Jul 8 12:57:14 2008 +0200 + + jedec_flash: Fix AM29DL800BB device ID + + As pointed out by Jerry Hicks, this patch corrects the device ID of + the Spansion AM29DL800BB NOR device. Verified against latest Spansion + datasheet (rev C4 from Dezember 2006). + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 689c1b30caacba3fbca0b1813facb3ab70b6cd63 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Mon Jul 7 11:22:37 2008 +0900 + + sh: Fix compile error sh7763rdp board + + Disable SH ether driver. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 9e23fe0560b84e324dc5f0ff8813dab2aa34f074 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Tue Jul 8 12:03:24 2008 +0900 + + sh: Fix SH-boards compile error + + By Cleanup out-or-tree building for some boards (.depend) + (commit:c8a3b109f07f02342d097b30908965f7261d9f15) + because filse ware changed, some SH-boards have compile error. + I revised this problem. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 63676841ca2d603b13765f3f7b72ff1a61c23f90 +Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> +Date: Wed Jun 18 12:10:33 2008 -0400 + + Remove duplicate code in cpu/arm926ejs/davinci/lxt972.c. + + Remove duplicate code in cpu/arm926ejs/davinci/lxt972.c. + + Remove duplicate code in a if/else block in + cpu/arm926ejs/davinci/lxt972.c. + Fixed style issues. + + Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit fec61431a003f5778bafa2624073a571af8bec9f +Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> +Date: Wed Jun 18 12:10:31 2008 -0400 + + Remove duplicate definitions in include/lxt971a.h. + + Remove duplicate definitions in include/lxt971a.h. + + Remove duplicate registers and bits definitions in + include/lxt971a.h for standard MII registers, and + use values in include/miiphy.h instead. + + Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 9751ee0990f467941da0b095a4e995f863672d7a +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Wed Jun 11 21:05:00 2008 +0900 + + net: sh: Renesas SH7763 Ethernet device support + + Renesas SH7763 has 2 channel Ethernet device. + This is 10/100/1000 Base support. + But this patch check 10/100 Base only. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 873d97aabc0b1c8822ed1d87e8c5c8ae0a7e4ae9 +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:28:05 2008 +0900 + + sh: Update Renesas R2DPlus board + + New NOR Flash board support and remove old type flash board config. + And Remove network setting from config file. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit ec39d479d2003f15e86e23ebc4e02a1c9a3a181c +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:28:01 2008 +0900 + + sh: Update Renesas R7780MP board + + New NOR Flash board support and remove network setting from config file. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit c001cd604e9f133743effbddb1c215b48e761c5a +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:27:56 2008 +0900 + + sh: Update Renesas Migo-R board + + Remove network setting from config file. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit f9599eca7cb5ebe40e5305c8006dced6ecc5cd9e +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:27:52 2008 +0900 + + sh: Update Hitachi MS7722SE board + + Remove network setting from config file. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 26209e48e8791670c93108029a5c31a30016c6df +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:27:48 2008 +0900 + + sh: Cleanup source code of SH7763RDP + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 5cd5b2c96ef0025762931349d350287aec03ab47 +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:27:44 2008 +0900 + + sh: Cleanup source code of R2DPlus + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 4ec7e915cfaa31b392755dd2c8231e64736d2ea8 +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:27:41 2008 +0900 + + sh: Cleanup source code of R7780MP + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 0955ef34c0454ae2ee59a78657a0f01fb3ef16d6 +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:27:38 2008 +0900 + + sh: Cleanup source code of MS7722SE + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 1d7b31d97b34ccb6f9b20a2465864998b0bf2691 +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Tue Jun 17 16:27:34 2008 +0900 + + sh: Cleanup source code of MS7720SE + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 3ab4827cbe409488ebea1a2ee5094783f2672214 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Jul 7 00:45:03 2008 +0200 + + SH: fix out of tree building + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 9047bfa1e737d787be460387dd6f45737eeceb10 +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Thu Jul 3 23:16:06 2008 +0900 + + net: smc911x: Fix typo + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + +commit 5ed546fdd0ca46a165661c2009fa743d9c9fceca +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Wed Jul 2 18:54:08 2008 +0200 + + update mvBL-M7 board config + + update mvBL-M7 config file to use UBOOT_VERSION and define + CONFIG_HIGH_BATS. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + +commit 5cacc5d0ec52678a5eb83ecda5c3bcb22eb47f30 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Mon Jun 30 17:45:01 2008 +0900 + + net: fix compile problem in smc911x driver. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + Acked-by: Ben Warren <biggerbadderben@gmail.com> + +commit 9fea65a6c469b1b474b27446feb58738baba2d31 +Author: Michal Simek <monstr@monstr.eu> +Date: Tue Jun 24 09:54:09 2008 +0200 + + ppc4xx: Rename CONFIG_XILINX_ML300 to CONFIG_XILINX_405 + + This change helps with better handling with others + Xilinx based platform. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + Acked-by: Stefan Roese <sr@denx.de> + +commit cbb6289569ae4fc6e2d676528e46ffcc72d743d0 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Tue Jun 17 13:07:11 2008 +0900 + + net: ne2000: Move dev_addr variable from grobal to local. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit dd7e5fa5f847188f78f62f2c52de6cb3def3ecdb +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Tue Jun 17 13:07:15 2008 +0900 + + net: ne2000: Fix compile error of NE2000 + + If enable DEBUG, can not compile ne2000 driver. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit dd35479a50f6c7c31ea491c07c5200c6dfd06a24 +Author: Ben Warren <biggerbadderben@gmail.com> +Date: Mon Jun 23 22:57:27 2008 -0700 + + Add mechanisms for CPU and board-specific Ethernet initialization + + This patch is the first step in cleaning up net/eth.c, by moving Ethernet + initialization to CPU or board-specific code. Initial implementation is + only on the Freescale TSEC controller, but others will be added soon. + + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 7754f2be5d1835d263aad21b5a629526f3e680b0 +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Jul 6 01:21:46 2008 +0200 + + include/sha256.h: fix file permissions. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit d3bcdf838e2991d58571308fa6e04ca335bc06e8 +Author: Patrice Vilchez <patrice.vilchez@atmel.com> +Date: Tue May 27 11:15:29 2008 +0200 + + [AT91SAM9] Fix NAND FLASH timings + + Fix NAND FLASH timings for at91sam9x evaluation kits. + + New timings are based on application note + "NAND Flash Support on AT91SAM9 Microcontrollers" available at + http://atmel.com/dyn/resources/prod_documents/doc6255.pdf + + Signed-off-by: Patrice Vilchez <patice.vilchez@atmel.com> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + Acked-by: Stelian Pop <stelian@popies.net> + +commit 19bd688484322fe62d1a66c8299da6ff9e967ff9 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 22 00:15:40 2008 +0200 + + Fix boot from NOR due to incorrect reset delay. + + AT91 RSTC registers are battery-backuped, so their values + are not reset across power cycles. One of those registers, + the AT91_RSTC_MR register, is being modified by U-Boot, in + the ethernet initialisation routine, to generate a 500ms + user reset. + + Unfortunately, this value is not being restored afterwards, + causing subsequent resets to also last for 500ms. + + This long reset sequence causes problems (at least) in the + boot sequence from NOR: by the time the CPU tries to load + a program from the NOR flash, the latter is still in reset + and not yet available. + + Additionaly, this patch fixes a bug in the original code which + caused the reset delay to last for 2s instead of 500ms. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit f492dd636fbbae529e17533995bc6e5813c007f6 +Author: Wolfgang Denk <wd@denx.de> +Date: Fri Jul 4 20:11:49 2008 +0200 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 5e6e350fc489aa19402f1e79037dd8c0a4bbd73d +Author: Wolfgang Denk <wd@denx.de> +Date: Fri Jul 4 20:07:35 2008 +0200 + + CCM/SCM boards: fix out of tree building + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit ab4c3a490df9a964711556d2a05b0c787db45fde +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Jul 3 23:22:27 2008 +0200 + + SCM board: fix build errors. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit a566466f17ba0e2d2b6c250e77da678fb932470d +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Jul 3 23:06:36 2008 +0200 + + IAD210 board: fix ``"ALIGN" redefined'' warning. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit ad756314797c16fa5dca23e115aab881011f164f +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Jul 3 23:00:24 2008 +0200 + + CCM board: fix build errors. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit f16ed51702cb9fb6fa2e019bbc0fcd1466b57c3b +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Wed Jul 2 18:54:08 2008 +0200 + + update mvBL-M7 board config + + update mvBL-M7 config file to use UBOOT_VERSION. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit ced209c50e80c25f13c083099b05044048d21f4f +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Jul 3 22:39:21 2008 +0200 + + sacsng board: fix warnings "suggest explicit braces to avoid ambiguous 'else'" + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 4ff170a8180a79da4cdaab1b30d58cd7b6be565e +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Jul 3 22:34:08 2008 +0200 + + Cleanup: fix "expected specifier-qualifier-list before 'phys_size_t'" errors + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 730f298485984b011b6ee8f4acb511cb45a843dd +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Jul 3 22:04:17 2008 +0200 + + lmb: fix "implicit declaration of function 'lmb_free'" warning + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 322ef5e28d2dc62571afc699b00add22a8e006e4 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Jul 2 23:53:23 2008 +0200 + + Cleanup: remove redundant deleting on *~ files + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit c8a3b109f07f02342d097b30908965f7261d9f15 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Jul 2 23:49:18 2008 +0200 + + Cleanup out-or-tree building for some boards (.depend) + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit a30cc5a340e7f8f5f85a0e08e7f6c4106ce117c4 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Jul 2 23:38:50 2008 +0200 + + Cleanup: fix out-of-tree building for some boards + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 461fa68d20861811487944d22291db5a13410e20 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Jul 2 23:00:14 2008 +0200 + + Cleanup: replace hard-wired $(AR) 'crv' settings by $(ARFLAGS) + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 5981ebd32017e062b08aa6747cf591276f2db779 +Author: Detlev Zundel <dzu@denx.de> +Date: Fri Jun 20 22:26:24 2008 +0200 + + fdt: Fix typo in variable name. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit a7a5982cd0f3482f88225af4da7795bc4f6cb9bc +Author: Gary Jennejohn <garyj@denx.de> +Date: Thu Jun 19 11:11:19 2008 +0200 + + Add logos for RRvision board + + Signed-off-by: Gary Jennejohn <garyj@denx.de> + +commit ee4ae38342142237ca85913f88ee570c1eb5ca7c +Author: Esben Haabendal <EsbenHaabendal@gmail.com> +Date: Wed Jun 18 11:03:57 2008 +0200 + + mpc8260: add fdt_fixup_ethernet support + + Add support for updating mac-address and local-mac-address in fdt for + all MPC8260 targets. + + Signed-off-by: Esben Haabendal <eha@doredevelopment.dk> + +commit f6a69559d64498a04e1e0b087a9b920e5775f866 +Author: Steven A. Falco <sfalco@harris.com> +Date: Thu Jun 12 13:24:42 2008 -0400 + + cmd_nvedit.c: clean up syntax highlighting + + My text-editor (vim) has a bit of trouble syntax-highlighting the + cmd_nvedit.c file, because it apparently does not parse C + ifdef/else/endif. The following patch does not change the behavior of + the code at all, but does allow the editor to properly + syntax-highlight the file. + + Signed-off-by: Steve Falco <sfalco@harris.com> + +commit 75678c807a6272ecc5541eb32898c93887f08400 +Author: Steven A. Falco <sfalco@harris.com> +Date: Thu Jun 12 13:22:12 2008 -0400 + + Make setenv() return status + + Currently, the setenv function does not return an error code. + This patch allows to test for errors. + + Signed-off-by: Steve Falco <sfalco@harris.com> + +commit 4928e97c8531283ca9b368b7c29a8a12e726562a +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Jun 11 10:14:06 2008 -0500 + + PPC: Added fls, fls64, __ilog2_u64, and ffs64 to bitops + + fls64, __ilog2_u64, ffs64 are variants that work on an u64, + and fls is used to implement them. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 83002a77cbdf383015ca384eff5fa31722d8e571 +Author: Magnus Lilja <lilja.magnus@gmail.com> +Date: Mon Jun 9 22:58:48 2008 +0200 + + i.MX31: Cleanup comments in lowlevel_init.S. + + Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> + +commit f8cc312bbee69257d741dc9f4062f4a0f5adf609 +Author: Ben Warren <biggerbadderben@gmail.com> +Date: Sun Jun 8 23:28:33 2008 -0700 + + Move conditional compilation of MPC8XXX SPI driver to Makefile + + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit d92ea21bafb674ee2bf27447970b047845e7b0a2 +Author: Juergen Kilb <J.Kilb@gmx.de> +Date: Sun Jun 8 17:59:53 2008 +0200 + + i.MX31: fixed CTRL-C detection + + The Register URXD contains status information in bits [15..8]. + With status bit 15 set, CTRL-C was reported as 0x8003 instead + of 0x03. Therefore CTRL-C was not detected. + To solve this, bits [15..8] were masked out now. + + Signed-off-by: Juergen Kilb <J.Kilb@gmx.de> + Acked-by: Felix Radensky <felix@embedded-sol.com> + +commit b571afde0295b007a45055ee49f8822c753a5651 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Sat Jun 7 12:29:52 2008 +0200 + + add SHA256 support + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + Signed-off-by: Francesco Albanese <Francesco.Albanese@swisscom.com> + +commit 3bab76a26e03df4ff81342fcc16393ce37d9766b +Author: Marian Balakowicz <m8@semihalf.com> +Date: Fri Jun 6 23:07:40 2008 +0200 + + Delay FIT format check on sector based devices + + Global FIT image operations like format check cannot be performed on + a first sector data, defer them to the point when whole FIT image was + uploaded to a system RAM. + + Signed-off-by: Marian Balakowicz <m8@semihalf.com> + Partial ('cmd_nand' case) Acked-by: Grant Erickson <gerickson@nuovations.com> + NAND and DOC bits Acked-by: Scott Wood <scottwood@freescale.com> + +commit 9810263afec5ac5f38f92963bb3b6d799e4331d0 +Author: Dave Liu <r63238@freescale.com> +Date: Tue Jun 3 17:38:19 2008 +0800 + + sata: wait for device updating signature to host + + The driver need wait for the device updating signature to host. + If we don't wait for it, the driver can not detect the device(disk) + when the system powers up. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit 745d8a0d3cea82e6d1753e14afb4588c34761b15 +Author: Stefan Roese <sr@denx.de> +Date: Sat Jun 28 14:56:17 2008 +0200 + + ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic + + This patch implements a fix provided by AMCC so that the lockup upon + simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur + anymore: + + Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] + (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, + USB 2.0 host and SATA. + + This errata is not officially available yet. I'll update the comment + to add the errata number later. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 8b616edb118e37d05f6401389eaee1c636b22828 +Author: Stuart Wood <stuart.wood@labxtechnologies.com> +Date: Mon Jun 2 16:42:19 2008 -0400 + + serial_pl010.c: add watchdog support + + Signed-off-by: Stuart Wood <stuart.wood@labxtechnologies.com> + +commit 86d3273e2b7be3fffb45e20c08535d6ad3aded6b +Author: Stuart Wood <stuart.wood@labxtechnologies.com> +Date: Mon Jun 2 16:40:08 2008 -0400 + + jffs2_1pass.c: add watchdog support + + Signed-off-by: Stuart Wood <stuart.wood@labxtechnologies.com> + +commit 5744ddc6637fea4f7b911a54a5fa860cb81a5d89 +Author: Sascha Laue <sascha.laue@liebherr.com> +Date: Fri May 30 09:48:14 2008 +0200 + + Configure DSP POST; add watchdog reset to diag command + + Signed-off-by: Sascha Laue <sascha.laue@liebherr.com> + +commit f13526517859bf6b573e23ff47199e107d1009b5 +Author: Tor Krill <tor@excito.com> +Date: Thu May 29 10:40:17 2008 +0200 + + Add sata sil3114 support + + Signed-off-by: Tor Krill <tor@excito.com> + +commit e093a247628228100f405b6d7f6b1bfc16141938 +Author: Wolfgang Denk <wd@denx.de> +Date: Sat Jun 28 23:34:37 2008 +0200 + + Coding Style Cleanup + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 01db232dd7a0ceb81208a9f2545720c80e5bfd83 +Author: Wolfgang Denk <wd@denx.de> +Date: Sat Jun 28 23:16:01 2008 +0200 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit c7f879ec2b389c4f2bf726b293bd516f4c692e03 +Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> +Date: Wed May 21 13:58:41 2008 -0400 + + ARM: Add support for Lyrtech SFF-SDR board (ARM926EJS) + + This patch adds support for the Lyrtech SFF-SDR board, + based on the TI DaVinci architecture (ARM926EJS). + + Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> + Signed-off-by: Philip Balister <philip@balister.org> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 341188b9ccaa8d4462d772cc067aca8d7618633a +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Thu May 22 11:09:59 2008 +0200 + + MMC: Consolidate MMC/SD command definitions + + This moves the MMC and SD Card command definitions from + include/asm/arch/mmc.h into include/mmc.h. These definitions are + given by the MMC and SD Card standards, not by any particular + architecture. + + There's a lot more room for consolidation in the MMC drivers which + I'm hoping to get done eventually, but this patch is a start. + + Compile-tested for all avr32 boards as well as lpc2292sodimm and + lubbock. This should cover all three mmc drivers in the tree. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit fa60edfc4c952626e048c0e065f654b3c1822fa5 +Author: Kyungmin Park <kmpark@infradead.org> +Date: Wed May 21 14:38:08 2008 +0900 + + Use better Ethernet timings for apollon board + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit 41c5eaa7253ed82bbae1eda5667755872c615164 +Author: Andy Fleming <afleming@freescale.com> +Date: Mon Jun 16 13:58:56 2008 -0500 + + Resize device tree to allow space for board changes and the chosen node + + Current code requires that a compiled device tree have space added to the end to + leave room for extra nodes added by board code (and the chosen node). This + requires that device tree creators anticipate how much space U-Boot will add to + the tree, which is absurd. Ideally, the code would resize and/or relocate the + tree when it needed more space, but this would require a systemic change to the + fdt code, which is non-trivial. Instead, we resize the tree inside + boot_relocate_fdt, reserving either the remainder of the bootmap (in the case + where the fdt is inside the bootmap), or adding CFG_FDT_PAD bytes to the size. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 7570a9941fc565922078679a72d246fe208d696d +Author: Andy Fleming <afleming@freescale.com> +Date: Mon Jun 16 13:58:55 2008 -0500 + + Fix an underflow bug in __lmb_alloc_base + + __lmb_alloc_base can underflow if it fails to find free space. This was fixed + in linux with commit d9024df02ffe74d723d97d552f86de3b34beb8cc. This patch + merely updates __lmb_alloc_base to resemble the current version in Linux. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 63796c4e61b207d2e635729d41b7a7f7d188b03c +Author: Andy Fleming <afleming@freescale.com> +Date: Mon Jun 16 13:58:54 2008 -0500 + + Add lmb_free + + lmb_free allows us to unreserve some memory so we can use lmb_alloc_base or + lmb_reserve to temporarily reserve some memory. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 4b03ac8b5102ad95f9fede7d13fa236977593e7d +Author: Andy Fleming <afleming@freescale.com> +Date: Mon Jun 16 13:58:53 2008 -0500 + + Add ALIGN() macro + + ALIGN() returns the smallest aligned value greater than the passed + in address or size. Taken from Linux. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 93262af85e3e9d9974c6c08fbd37a9a72e090ca2 +Author: Stefan Roese <sr@denx.de> +Date: Tue Jun 24 17:15:22 2008 +0200 + + ppc4xx: Fix compilation problems with phys_size_t + + This patch includes <asm/types.h> before <asm/u-boot.h> in some 4xx + board specific files where it has been missing. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 28eab0d77352b84885f938759bf2612b7bf0bc44 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Mon May 19 12:26:38 2008 +0200 + + Conditionally add -fno-stack-protector to CFLAGS + + When compile-testing on powerpc, I get errors like this: + + net/nfs.c:422: undefined reference to `__stack_chk_fail_local' + + This seems to be because -fstack-protector is on by default, so + let's explicitly disable it on all architectures that support the + option. + + The Ubuntu toolchain is affected by this problem, and according to + Mike Frysinger, Gentoo has been running with SSP enabled for years. + More and more distros are turning SSP on by default, so this problem + is likely to get worse in the future. + + Also, powerpc just happens to be one of the arches I do + compile-testing on. There may be other arches affected by this too. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit dfd3be881c03a26e31f0dea4a42e76061fa610ac +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Sun May 18 19:09:52 2008 +0200 + + pcmcia/ti_pci1410a: Move compile condition to the Makefile + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 72d5d5f7b5c74a188df238ec6dd824d80c74857a +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Sun May 18 19:09:51 2008 +0200 + + pxa_pcmcia: Move compile condition to the Makefile + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit c9eff32881fb429101c937cf8c268f1d42e5c2a9 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Sun May 18 19:09:50 2008 +0200 + + marabun_pcmcia: Move compile condition to the Makefile + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 6a19c46cae43c16c528eddefae3db97134f1915d +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Mon Jun 23 13:25:34 2008 +0200 + + fix non-working mvBL-M7 + + Add missing #define CONFIG_HIGH_BATS in mvBL-M7 board config file. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 846f1574ddddeda2bc227655e687308695f41cdc +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Mon Jun 23 11:40:56 2008 +0200 + + fix system config overwrite @ MPC834x and MPC8313 + + During 83xx setup the "System I/O configuration register high" gets + overwritten with user defined value if CFG_SICRH is defined. + + Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH + must keep their reset value regardless of configuration. + + On my board (using RGMII) those bits are set after reset - yet it's + unclear where they come from. + + The patch keeps both bits on MPC834x and MPC8313. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 4890246a2c5df90a74e2941e3673a49bbd36aee9 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jun 17 17:45:27 2008 -0500 + + mpc83xx: move CPU_TYPE_ENTRY over to processor.h + + to avoid this: + + cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined + In file included from cpu.c:33: + /home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit aac7a5095b968d6c9a3e6422f31b4ad203cac9c8 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 23 11:15:09 2008 +0200 + + ppc4xx: Fix problem in gpio_config() + + As pointed out by Guennadi Liakhovetski (thanks), pin2 is already shifted + left by one. So the additional shift is bogus. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 40777812316fc252c941665c0f60c148fd79d50f +Author: Detlev Zundel <dzu@denx.de> +Date: Fri Jun 20 22:24:05 2008 +0200 + + fdt: Fix typo in variable name. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit 5f723a3b98c630bde33de74351f2121691fdef14 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri Jun 20 10:41:05 2008 +0200 + + avr32: Enable SPI flash support on ATNGW100 + + The ATNGW100 has 8MB DataFlash on board. Give users access to it through + the new SPI flash framework. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 5605ef6b5802921cbefe6a933a9dea3497396b5c +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri Jun 20 12:44:28 2008 +0200 + + avr32: Fix SPI portmux initialization + + Use the new GPIO manipulation functions to set up the chip select lines, + and make sure both busses use GPIO for chip select control. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 4688f9e34a87e825aed34d07c9ca7a273e6fc8ab +Author: Peter Ma <pma@mediamatech.com> +Date: Sun Jun 1 22:59:24 2008 -0700 + + avr32: Add GPIO manipulation functions + + Adds GPIO manipulation functions for AVR32 AP7 platform. + + Signed-off-by: Peter Ma <pma@mediamatech.com> + [haavard.skinnemoen@atmel.com: coding style fixup, slight simplification] + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit b4fe1a71090c73efc6e4188eed188b2ff67fc02a +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:02:30 2008 +0200 + + MPC8360ERDK: adapt NAND interface for the re-written FSL NAND UPM driver + + This patch is based on the following patch sent a few minutes ago: + "NAND FSL UPM: driver re-write using the hwcontrol callback" + It is untested, of course. Anton, could you please give it a try. + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> + +commit 96026d42fa4e646d28318c0a1438aac4b2017909 +Author: Anatolij Gustschin <agust@denx.de> +Date: Thu Jun 12 12:40:11 2008 +0200 + + Fix 4xx build issue + + Building for 4xx doesn't work since commit 4dbdb768: + + In file included from 4xx_pcie.c:28: + include/asm/processor.h:971: error: expected ')' before 'ver' + make[1]: *** [4xx_pcie.o] Error 1 + + This patch fixes the problem. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + Acked-by: Stefan Roese <sr@denx.de> + Acked-by: Kumar Gala <galak@kernel.crashing.org> + +commit fb8c061ea05fc68d37e2a8b9f8c949d76c8d71a8 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 16 10:40:02 2008 +0200 + + cfi-flash: Fix problem in flash_toggle(), busy was not detected reliably + + This patch simplifies flash_toggle() (AMD commandset), which is used to + detect if a FLASH device is still busy with erase/program operations. On + 800MHz Canyonlands/Glacier boards (460EX/GT) the current implementation + did not detect the busy state reliably, resulting in non erased sectors + etc. This patch now simplifies this function by "just" comparing the + complete data-word instead of ANDing it with the command-word (0x40) + before the compatison. It is done the same way in the Linux implementation + chip_ready() in cfi_cmdset_0002.c. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 9e4006bca3d9fb4a2d061996771036cb01e539d3 +Author: Philip Balister <philip@balister.org> +Date: Mon Jun 16 08:58:07 2008 -0400 + + NAND: Add missing declaration to non-redundant saveenv(). + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 2cdb7f50ac59594540fffdf8dbd7b12beac79c52 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Mon Jun 2 15:09:55 2008 +0200 + + MPC8360ERDK: adapt NAND interface for the re-written FSL NAND UPM driver + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 212ed90615c3d20fa6bd73d70d5153bd0d124e5f +Author: Stefan Roese <sr@denx.de> +Date: Tue Jun 10 15:34:11 2008 +0200 + + ppc4xx: Canyonlands: Disable the RTC M41T62 square wave output + + This patch disables the square wave output of the M41T62 RTC used on + Canyonlands & Glacier. Here the explanation: + + The serial real-time clock part used in the design is an + STMicro M41T62. This part has a full-time 32KHz square wave + output that is connected to the TmrClk input to the + processor. The default state for this square wave output is + enabled so the output runs continuously when the board is + powered normally and also from the battery. The TmrClk input + to the processor goes to ground when the power is removed + from the board/processor, and therefore the running square + wave output is driving ground which drains the battery quickly. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a94f22f08f280905926219e568568964cb9eeb9d +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Jun 11 18:10:20 2008 -0500 + + Fix build issue with string.h and linux/string.h + + This commit: + commit 338cc038461a6c7709c5b86fd9a240209338a1ae + Author: Wolfgang Denk <wd@denx.de> + Date: Fri Jun 6 14:28:14 2008 +0200 + + tools/mkimage: fix compiler warnings on some systems. + + Broke building on some systems, because the host's string.h was interfering + with u-boot's linux/string.h. It doesn't look like we need the u-boot one if + we're building for the host, so now we only include when building inside + u-boot. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit 9973e3c614721bbf169882ffc3be266a6611cd60 +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Mon Jun 9 16:03:40 2008 -0500 + + Change initdram() return type to phys_size_t + + This patch changes the return type of initdram() from long int to phys_size_t. + This is required for a couple of reasons: long int limits the amount of dram + to 2GB, and u-boot in general is moving over to phys_size_t to represent the + size of physical memory. phys_size_t is defined as an unsigned long on almost + all current platforms. + + This patch *only* changes the return type of the initdram function (in + include/common.h, as well as in each board's implementation of initdram). It + does not actually modify the code inside the function on any of the platforms; + platforms which wish to support more than 2GB of DRAM will need to modify + their initdram() function code. + + Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc + MPC8641HPCN. + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit 391fd93ab23e15ab3dd58a54f5b609024009c378 +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Mon Jun 9 20:37:18 2008 -0500 + + Change lmb to use phys_size_t/phys_addr_t + + This updates the lmb code to use phys_size_t + and phys_addr_t instead of unsigned long. Other code + which interacts with this code, like getenv_bootm_size() + is also updated. + + Booted on MPC8641HPCN, build-tested ppc, arm, mips. + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit 61b09fc2952dc636017df4e7970e3de132276ba1 +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Mon Jun 9 20:37:17 2008 -0500 + + Change print_size to take phys_size_t + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit b57ca3e128cc10a133ba79bc7ec3e7b50e7c8fbe +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Mon Jun 9 20:37:16 2008 -0500 + + Change bd/gd memsize/ram_size to be phys_size_t. + + Currently, both are defined as an unsigned long, but + should be phys_size_t. This should result in no real change, + since phys_size_t is currently an unsigned long for all the + default configs. Also add print_lnum to cmd_bdinfo to deal + with the potentially wider memsize. + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit ba04f7010958e88a8910f2a123fee53fdc72e013 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Jun 10 16:16:02 2008 -0500 + + FSL LAW: Add new interface to use the last free LAW + + LAWs have the concept of priority so its useful to be able to allocate + the lowest (highest number) priority. We will end up using this with the + new DDR code. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 859a86a25c569d3665ff413d1d923394b8a961f3 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Jun 11 00:51:45 2008 -0500 + + 85xx/86xx: Move to dynamic mgmt of LAWs + + With the new LAW interface (set_next_law) we can move to letting the + system allocate which LAWs are used for what purpose. This makes life + a bit easier going forward with the new DDR code. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Signed-off-by: Andy Fleming <afleming@freescale.com> + Acked-by: Jon Loeliger <jdl@freescale.com> + Acked-by: Becky Bruce <becky.bruce@freescale.com> + +commit f060054dadbbe7027ca088eed806a3ef1f82fdb7 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Jun 11 00:44:10 2008 -0500 + + FSL LAW: Keep track of LAW allocations + + Make it so we keep track of which LAWs have allocated and provide + a function (set_next_law) which can allocate a LAW for us if one is + free. + + In the future we will move to doing more "dynamic" LAW allocation + since the majority of users dont really care about what LAW number + they are at. + + Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit ddde74a159caa6e18b481fec01d40b885aebb566 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Jun 9 22:31:57 2008 -0500 + + 85xx: remove dummy board_early_init_f + + A number of board ports have empty version of board_early_init_f + for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 81e56e9af0d43712db8efb843606a8d62eab454f +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Jun 9 18:55:38 2008 -0500 + + MPC8544DS: Update config.h + + * Enable flash progress + * remove CLEAR_LAW0 since we dont really use it + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 978e81604c1b28526ed580df0fbe64eb8384e94f +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Jun 9 13:37:24 2008 -0500 + + 85xx: Remove unused and unconfigured memory test code. + + Remove unused and unconfigured DDR test code from FSL 85xx boards. + Besides, other common code exists. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit a23cddde1a95f987e3fe2a720a7ec9375b7264d7 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Fri Jun 6 15:42:45 2008 +0200 + + Socrates: Added FPGA base address update in FDT. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit fd51b0e0e620b8bc9fd4f6daa3a4fa6f5e1316f4 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Fri Jun 6 15:42:44 2008 +0200 + + Socrates: NAND support added. Changed the U-Boot base address and + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 248ae5cfc8bf69074d1da099dc495d8e06070547 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Fri Jun 6 15:42:43 2008 +0200 + + NAND: Added support for 128-bit OOB, adapted + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 31ca0208612f2eb57690110d7c2815953650e47b +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Fri Jun 6 15:42:42 2008 +0200 + + Socrates: added missed file with UPMA configuration data. + + Signed-of-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 59abd15b43cab7a4d19de4ba0943837d9555f7ba +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Fri Jun 6 15:42:41 2008 +0200 + + Socrates: Added FPGA mapping. LAWs and TLBs cleanup. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 740280e68ccc0b971e613face7eaaa8bd1382b8c +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Fri Jun 6 15:42:40 2008 +0200 + + Added the upmconfig() function for 85xx. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit d39e68514ff943930ee692cff3fde03532eb7fec +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Fri Jun 6 15:42:39 2008 +0200 + + Socrates: config file cleanup. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit e8cc3f04b124f757af4528206e60d8eb715ae083 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:10 2008 +0200 + + TQM85xx: Change memory map to support Flash memory > 128 MiB + + Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash + memory. The current memory map only supports up to 128 MiB Flash. + This patch adds the configuration option CONFIG_TQM_BIGFLASH. If + set, up to 1 GiB flash is supported. To achieve this, the memory + map has to be adjusted in great parts (for example the CCSRBAR is + moved from 0xE0000000 to 0xA0000000). + + If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new + memory map also has to be considered in the kernel (changed + CCSRBAR address, changed PCI IO base address, ...). Please use + an appropriate Flat Device Tree blob (tqm8548.dtb). + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 1c2deff22cd6e2bf0e618fd6e09ca3eec5a8d051 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:09 2008 +0200 + + TQM85xx: NAND support via local bus UPMB + + This patch adds support for NAND FLASH on the TQM8548. It is disabled by + default and can be enabled for the TQM8548 modules. It is now based on + the re-written FSL NAND UPM driver. A patch has been posted earlier today + with the subject: + + "NAND FSL UPM: driver re-write using the hwcontrol callback" + + Note that the R/B pin is not supported by that module requiring to use + the specified maximum delay time. + + Note: With NAND support enabled the size of the U-Boot image exceeds + 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, + doubling the image size :-(. + + Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit b9e8078bb3f3c48111a7081e27279938c3a445e1 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:08 2008 +0200 + + TQM8548: PCI express support + + This patch adds support for PCI express cards. The board support + now uses common FSL PCI init code, for both, PCI and PCIe on all + TQM85xx modules. + + Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 1287e0c55a2ee2c575ac9ce8e4302cd4085be876 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:07 2008 +0200 + + TQM8548: Basic support for the TQM8548 modules + + This patch adds basic support for the TQM8548 module from TQ-Components + (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for + eTSEC 3 and 4 + + Furthermore Flash buffer write has been enabled to speed up output to + the Flash by approx. a factor of 10. + + Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 25991353204c78b094c3c1fec90182dcd607ab8f +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:06 2008 +0200 + + TQM85xx: Support for Flat Device Tree + + This patch adds support for Linux kernels using the Flat Device Tree. + It also re-defines the default environment settings for booting Linux + with the FDT blob. + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit d9ee843d54c54776e1fdb86336ce554906a87331 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:05 2008 +0200 + + TQM85xx: Support for Intel 82527 compatible CAN controller + + This patch adds initialization of the UPMC RAM to support up to two + Intel 82527 compatible CAN controller on the TQM85xx modules. + + Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 518d5cfe72916323c746af1647764459914f555f +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:04 2008 +0200 + + TQM85xx: Bugfix in the SDRAM initialisation + + The CS0_BNDS register is now set according to the detected + memory size. + + Signed-off-by Martin Krause <martin.krause@tqs.de> + +commit 45dee2e620ccec6ac7b3548fe8979a34fd030e5d +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:03 2008 +0200 + + TQM85xx: Fix chip select configuration for second FLASH bank + + This patch fixes the re-calculation of the automatic chip select + configuration for boards with two populated FLASH banks. + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + +commit 46346f27cda6fd025a496bde8f2d4aeee04aca5f +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:02 2008 +0200 + + TQM85xx: Support for Spansion 'N' type flashes added + + The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors, + than the formerly used 'M' types (S29GLxxxM series), so the flash layout + needs to be changed -> new start address of the environment. The macro + definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be + defined for boards with 'N' type flashes. + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 5d5bd838f76eade22c0ea40a500389f924d0da36 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:01 2008 +0200 + + TQM85xx: Fix CPM port pin configuration + + Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 + board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used + as serial interface anyway. Worse, on some board variants configuring the + pins for SCC1 leads to short circuits (for example on the TQM8541-BG). + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + +commit b99ba1679e8cd51b023e67098c89e606e47137d2 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:12:00 2008 +0200 + + TQM85xx: Various coding style fixes + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit ae9e97fa96f643c8ba2b666b06a026cc8717eb00 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Tue Jun 10 22:15:58 2008 -0400 + + libfdt: Move the working_fdt pointer to cmd_fdt.c + + The working_fdt pointer was declared in common/fdt_support.c but was + not used there. Move it to common/cmd_fdt.c where it is used (it is + also used in lib_ppc/bootm.c). + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit e489b9c078e22b0d9e75f002cd2a1bd967e88f5e +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jun 10 11:06:17 2008 -0500 + + fdt: unshadow global working fdt variable + + differentiate with local variables of the same name by renaming the + global 'fdt' variable 'working_fdt'. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit e1eb0e25d9d8fd8efdfb93f670a417663f386022 +Author: Andy Fleming <afleming@freescale.com> +Date: Tue Jun 10 18:49:34 2008 -0500 + + socrates: Fix PCI clk fix patch + + The submitted patch seems to have been more up-to-date, but an older patch was + already in the repository. This patch encompasses the differences + + Taken entirely from Sergei Poselenov <sposelenov@emcraft.com> + + Signed-off-by: Andy Fleming <afleming@freescale.com> + +commit a75a57ef6e4b613c81434971e96ed70cf9ec9ba0 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:02:29 2008 +0200 + + NAND FSL UPM: driver re-write using the hwcontrol callback + + This is a re-write of the NAND FSL UPM driver using the more universal + hwcontrol callback (instead of the cmdfunc callback). Here is a brief + list of furher modifications: + + - For the time being, the UPM setup writing the UPM array has been + removed from the driver and must now be done by the board specific + code. + + - The bus width definition in "struct fsl_upm_nand" is now in bits to + comply with the corresponding Linux driver and 8, 16 and 32 bit + accesses are supported. + + - chip->dev_read is only set if fun->dev_ready != NULL, which is + required for boards not connecting the R/B pin. + + - A few issue have been fixed with MxMR bit manipulation like in the + corresponding Linux driver. + + Note: I think the "io_addr" field of "struct fsl_upm" could be removed + as well, because the address is already determined by + "nand->IO_ADDR_[RW]", but I'm not 100% sure. + + This patch has been tested on a TQM8548 modules with the NAND chip + Micron MT29F8G08FABWP. + + This patch is based on the following patches posted to this list a few + minutes ago: + + PPC: add accessor macros to clear and set bits in one shot + 83xx/85xx/86xx: add more MxMR local bus definitions + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> + +commit 6beecfbb542992eede5831240cd58678274683a9 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Thu Jun 5 13:11:59 2008 +0200 + + MPC85xx: Beautify boot output of L2 cache configuration + + The boot output is now aligned poperly with other boot output + lines, e.g.: + + FLASH: 128 MB + L2: 512 KB enabled + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 398415114f0a705163a14543e9fef03f734b1ffa +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Wed Jun 4 12:45:22 2008 +0200 + + PPC: add accessor macros to clear and set bits in one shot + + PPC: add accessor macros to clear and set bits in one shot + + This patch adds macros from linux/include/asm-powerpc/io.h to clear and + set bits in one shot using the in_be32, out_be32, etc. accessor functions. + They are very handy to manipulate bits it I/O registers. + + This patch is required for my forthcoming FSL NAND UPM driver re-write and + the support for the TQM8548 module. + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 4677988c7edc070c3786d3db7994abeca3ab82a0 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Wed Jun 4 13:52:17 2008 +0200 + + TQM: move TQM boards to board/tqc + + Move all TQM board directories to the vendor specific directory "tqc" + for modules from TQ-Components GmbH (http://www.tqc.de). + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit 6fab2fe72ca5bf95280cd52cdf378af3e506eb50 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Mon Jun 2 12:09:30 2008 +0200 + + 83xx/85xx/86xx: add more MxMR local bus definitions + + 83xx/85xx/86xx: add more MxMR local bus definitions + + This patch adds more macro definitions for the UPM Machine Mode Registers + They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx + common local bus definitions into include/asm-ppc/fsl_lbc.h. They are + required for my forthcoming FSL NAND UPM driver re-write and the support + for the TQM8548 module. + + This patch is based on the following two patches from Anton Vorontsov: + + http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06511.html + http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06587.html + + I leave coding style violation fixes, code beautification and name + corrections to somebody else ;-(. + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + +commit c8c5fc266e4499e283c293ccb972863156aa4134 +Author: Anton Vorontsov <avorontsov@ru.mvista.com> +Date: Thu May 29 18:14:56 2008 +0400 + + 83xx/85xx: further localbus cleanups + + Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names + from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2. + + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> + +commit 42dbd667c88d496882d53e22656e89b654205492 +Author: Anton Vorontsov <avorontsov@ru.mvista.com> +Date: Wed May 28 18:20:15 2008 +0400 + + 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h + + This patch moves Freescale Localbus defines out of mpc83xx.h, so we could + use it on MPC85xx and MPC86xx processors. + + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> + +commit 730b2fcf6fcd9eec3ea86fbb087c3f98aa23a769 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu May 29 11:22:06 2008 -0500 + + 85xx: Add setting of cache props in the device tree. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 4dbdb7681e243431530df0725627192a0c4aefda +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Jun 10 16:53:46 2008 -0500 + + 85xx: expose cpu identification + + The current cpu identification code is used just to return the name + of the processor at boot. There are some other locations that the name + is useful (device tree setup). Expose the functionality to other bits + of code. + + Also, drop the 'E' suffix and add it on by looking at the SVR version + when we print this out. This is mainly to allow the most flexible use + of the name. The device tree code tends to not care about the 'E' suffix. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 2329fe113d847e43cca8e4a0e4edd613b50b8492 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jun 10 13:25:24 2008 -0500 + + mpc83xx: MVBLM7: minor build fixups + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit a1293e549b56da135ef32ffca5b9d35a16aa6802 +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Tue Jun 10 09:14:05 2008 +0200 + + add MPC8343 based board mvBlueLYNX-M7 (board+make files) + + Add MPC8343 based board mvBlueLYNX-M7. + It's a single board stereo camera system. + Please read doc/README.mvblm7 for details. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit c005b93925ba49f07da2aa748527996d927e172f +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Tue Jun 10 09:13:16 2008 +0200 + + add MPC8343 based board mvBlueLYNX-M7 (doc+config) + + Add MPC8343 based board mvBlueLYNX-M7. + It's a single board stereo camera system. + Please read doc/README.mvblm7 for details. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit f9023afbdfd9f27e7c38f3cce965746e56d62dd3 +Author: Anton Vorontsov <avorontsov@ru.mvista.com> +Date: Thu May 29 18:14:56 2008 +0400 + + 83xx/85xx: further localbus cleanups + + move the BRx_* and ORx_* left behind in mpc85xx.h + + The same is needed for mpc8xx.h and mpc8260.h (defines are almost + the same, just few differences which needs some attention though). + + But the bad news for mpc8xx and mpc8260 is that there are a lot of users + of these defines. So this cleanup I'll leave for the "better times". + + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit bf30bb1f7c954d7855d9b23624b33b00c50b4697 +Author: Anton Vorontsov <avorontsov@ru.mvista.com> +Date: Wed May 28 18:20:15 2008 +0400 + + 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h + + This patch moves Freescale Localbus defines out of mpc83xx.h, so we could + use it on MPC85xx and MPC86xx processors. + + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> + Acked-by: Andy Fleming <afleming@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit d82b4fc0ce8cca95e857fc51022e841cb2dbee6a +Author: Tor Krill <tor@excito.com> +Date: Mon Jun 2 15:09:30 2008 +0200 + + Add missing CSCONFIG_BANK_BIT_3 define to mpc83xx.h + + Signed-off-by: Tor Krill <tor@excito.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 3b904ccb93c3196727e2e9870cb1df903cab19ad +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Mon Jun 9 23:37:44 2008 +0900 + + net: Conditional COBJS inclusion of network drivers + + Replace COBJS-y with appropriate driver config names. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 2fb698bf50f4aff2485581a12fa634a07c040e4a +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Mon Jun 9 21:02:17 2008 -0400 + + Use strncmp() for the fdt command + + Cleaner than doing multiple conditionals on characters. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 47abe8ab290d2721a8eeadff65b939e6af8c01b0 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Sat Jun 7 12:25:05 2008 -0400 + + The fdt boardsetup command criteria was not unique + + It was checking just for "b", which is not unique with respect to the + "boot" command. Change to check for "boa"[rdsetup]. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 2f08bfa9526bae4f461e043530cfb903fec0d273 +Author: David Gibson <david@gibson.dropbear.id.au> +Date: Tue May 20 17:19:11 2008 +1000 + + libfdt: Several cleanups to parameter checking + + This patch makes a couple of small cleanups to parameter checking of + libfdt functions. + + - In several functions which take a node offset, we use an + idiom involving fdt_next_tag() first to check that we have indeed been + given a node offset. This patch adds a helper function + _fdt_check_node_offset() to encapsulate this usage of fdt_next_tag(). + + - In fdt_rw.c in several places we have the expanded version + of the RW_CHECK_HEADER() macro for no particular reason. This patch + replaces those instances with an invocation of the macro; that's what + it's for. + + - In fdt_sw.c we rename the check_header_sw() function to + sw_check_header() to match the analgous function in fdt_rw.c, and we + provide an SW_CHECK_HEADER() wrapper macro as RW_CHECK_HEADER() + functions in fdt_rw.c + + Signed-off-by: David Gibson <david@gibson.dropbear.id.au> + +commit fec6d9ee7c10443f65ce1788ef818919167bbf2e +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Tue Jun 3 20:34:45 2008 -0400 + + Remove the deprecated CONFIG_OF_FLAT_TREE + + Use CONFIG_OF_LIBFDT instead to support flattened device trees. It is + cleaner, has better functionality, and is better supported. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 62bcdda293efa752f8281fbd9da03822b27ce82f +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Tue Jun 3 20:26:29 2008 -0400 + + Change the stxxst to CONFIG_OF_LIBFDT + + This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change + to CONFIG_OF_LIBFDT. + + WARNING: It appears that this board lost its ability to boot via a + flattened device tree prior to this changeset. + + WARNING: This conversion was untested because I do not have a board to + test it on. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 589c04271d129729a8b01391453851ab9cc4069c +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Tue Jun 3 20:24:58 2008 -0400 + + Convert mpc7448hpc2 to CONFIG_OF_LIBFDT + + This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change + to CONFIG_OF_LIBFDT. + + WARNING: This conversion is untested because I do not have a board to + test it on. + + NOTE: The FDT blob (DTS) must have an /aliases/ethernet0 and (optionally) + /aliases/ethernet1 property for the ethernet to work. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit ee1e35bede91debc8bff9b02f75574486033b652 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu May 29 01:21:24 2008 -0500 + + 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 3b9519fc50802436e417c839e69df7b2016cade5 +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Wed May 14 13:10:04 2008 -0500 + + MPC85xx: Change traps.c to not reference non-addressable memory + + Currently, END_OF_RAM is used by the trap code to determine if + we should attempt to access the stack pointer or not. However, + on systems with a lot of RAM, only a subset of the RAM is + guaranteed to be mapped in and accessible. Change END_OF_RAM + to use get_effective_memsize() instead of using the raw ram + size out of the bd. + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit 7faddaecea52f585f538fdf9c2e61f85a789b19c +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Mon Jun 9 13:39:57 2008 +0900 + + sh: Renesas Solutions SH7763RDP board support + + SH7763RDP has SCIF, NOR Flash, Ethernet, USB host, LCDC and MMC. + In this patch, support SCIF, NOR Flash, and Ethernet. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 60179098a95eaa972007d7ec58e4c1588029720f +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Fri Jun 6 16:24:13 2008 +0900 + + sh: Add support Renesas SH7763 + + Renesas SH7763 has 3 SCIF, MMC, LCDC, Ethernet and other. + This patch supprts CPU register's header file. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 08c5fabe181d663eec0feba5ecd02c0b78934a52 +Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +Date: Fri Jun 6 16:16:08 2008 +0900 + + sh: SH7763 SCIF support + + SH7763 has 3 SCIF channels. SCIF0 and 1 are same register constitution, + but only SCIF2 is different. This patch work all SCIF channel. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 79b51ff8205f0354d5300570614c1d2db499679c +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Sat Jun 7 20:51:59 2008 +0900 + + [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines + + Also get rid of some #ifdefs in *.c files. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 8bde63eb3f79d68f693201528dafc8ae7aa087de +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Sat Jun 7 20:51:56 2008 +0900 + + [MIPS] Rename Alchemy processor configs into CONFIG_SOC_* + + CONFIG_SOC_AU1X00 + + Common Alchemy Au1x00 stuff. All Alchemy processor based machines + need to have this config as a system type specifier. + + CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200, + CONFIG_SOC_AU1500, CONFIG_SOC_AU1550 + + Machine type specifiers. Each port should have one of aboves. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit cc49cadeeb8bb2f0ae3fdc13af7051ae59f083bc +Author: Stuart Wood <stuart.wood@labxtechnologies.com> +Date: Fri May 30 16:05:28 2008 -0400 + + env_nand.c: Added bad block management for environment variables + + Modified to check for bad blocks and to skipping over them when + CFG_ENV_RANGE has been defined. + CFG_ENV_RANGE must be larger than CFG_ENV_SIZE and aligned to the NAND + flash block size. + + Signed-off-by: Stuart Wood <stuart.wood@labxtechnologies.com> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 279726bd00558e80263d44581c44167625b7fb9a +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Wed May 14 13:09:58 2008 -0500 + + MPC86xx: Change traps.c to not reference non-addressable memory + + Currently, END_OF_RAM is used by the trap code to determine if + we should attempt to access the stack pointer or not. However, + on systems with a lot of RAM, only a subset of the RAM is + guaranteed to be mapped in and accessible. Change END_OF_RAM + to use get_effective_memsize() instead of using the raw ram + size out of the bd to prevent us from trying to access + non-mapped memory. + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit 338cc038461a6c7709c5b86fd9a240209338a1ae +Author: Wolfgang Denk <wd@denx.de> +Date: Fri Jun 6 14:28:14 2008 +0200 + + tools/mkimage: fix compiler warnings on some systems. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit b2815f79288d4da7a3ba18bdbd05120ce09d5622 +Author: Stefan Roese <sr@denx.de> +Date: Fri Jun 6 16:10:41 2008 +0200 + + ppc4xx: Fix misspelled CONFIG_440SPE/440EPX/GRX config options + + We use upper case letters for the AMCC processor defines (like + CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and + not CONFIG_440SPe. This patch fixes the last misspelled config options. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 72675dc6c06a48846d180106161d49dd714383cc +Author: Stefan Roese <sr@denx.de> +Date: Fri Jun 6 15:55:21 2008 +0200 + + ppc4xx: Unify AMCC's board config files (part 3/3) + + This patch series unifies the AMCC eval board ports by introducing + a common include header for all AMCC eval boards: + + include/configs/amcc-common.h + + This header now includes all common configuration options/defines which + are removed from the board specific headers. + + The reason for this is ease of maintenance and unified look and feel + of all AMCC boards. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 490f204096d6e2c9940f67816f154a8125bab116 +Author: Stefan Roese <sr@denx.de> +Date: Fri Jun 6 15:55:03 2008 +0200 + + ppc4xx: Unify AMCC's board config files (part 2/3) + + This patch series unifies the AMCC eval board ports by introducing + a common include header for all AMCC eval boards: + + include/configs/amcc-common.h + + This header now includes all common configuration options/defines which + are removed from the board specific headers. + + The reason for this is ease of maintenance and unified look and feel + of all AMCC boards. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a8a11a9ed046b480a16e47a158f8f5300028dfa6 +Author: Stefan Roese <sr@denx.de> +Date: Fri Jun 6 15:54:31 2008 +0200 + + ppc4xx: Unify AMCC's board config files (part 1/3) + + This patch series unifies the AMCC eval board ports by introducing + a common include header for all AMCC eval boards: + + include/configs/amcc-common.h + + This header now includes all common configuration options/defines which + are removed from the board specific headers. + + The reason for this is ease of maintenance and unified look and feel + of all AMCC boards. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 0e38c938ed4bcadb4f4fc1419a541431e94fc202 +Author: Remy Bohmer <linux@bohmer.net> +Date: Thu Jun 5 13:03:36 2008 +0200 + + DM9000 fix status check fail 0x6d error for trizeps board + + According to the Application Notes of the DM9000, only the 2 bits 0:1 of + the status byte need to be checked to identify a valid packet in the fifo + + But, The several different Application Notes do not all speak the same + language on these bits. They do not disagree, but only 1 Application Note + noted explicitly that only these 2 bits need to be checked. + Even the datasheets do not mention anything about these 2 bits. + + Because the old code, and the kernel check the whole byte, I left this piece + untouched. + + However, I tested all board/DM9000[A|E|EP] devices with this 2 bit check, so + it should work. + + Notice, that the 2nd iteration through this receive loop (when a 2nd packet is + in the fifo) is much shorter now, compared to the older U-boot driver code, + so that we can maybe run into a hardware condition now that was never seen + before, or maybe was seen very unfrequently. + + Additionaly added a cleanup of a stack variable. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 7daf2ebe9196dd67131a06d85049c3a8a08ca413 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Thu Jun 5 22:29:00 2008 +0900 + + [MIPS] Update <asm/addrspace.h> header + + - Fix traditional KSEG names + - Replace PHYSADDR with CPHYSADDR + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit f0d5a6f060d00358b85c62a921a423ea8df71184 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Thu Jun 5 22:29:00 2008 +0900 + + [MIPS] mips_config.mk: Misc fixes + + - Kill redundant `-pipe' (this will be added by $(TOPDIR)/config.mk) + - Modify comments + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 5f64d21c9a2998794f255b469165b91f092dfc2d +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Thu Jun 5 22:29:00 2008 +0900 + + [MIPS] Kill unused <version.h> inclusions + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit a55d48174cfd1a5bc184159513f48dcbbe409c83 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Thu Jun 5 22:29:00 2008 +0900 + + [MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines + + MIPS port has two problems in timer routines. One is now we assume CFG_HZ + equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000 + in the U-Boot system. + + The other is we don't have a proper time management counter like timestamp + other ARCHs have. We need the 32-bit millisecond clock counter. + + This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a + 32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number + of calculated CP0 counter cycles in a CFG_HZ. + + STRATEGY: + + * Fix improper CFG_HZ value to have 1000 + + * Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead. + + * timer_init: initialize timestamp and set up the first timer expiration. + Note that we don't need to initialize CP0 count/compare registers here + as they have been already zeroed out on the system reset. Leave them as + they are. + + * get_timer: calculate how many timestamps have been passed, then return + base-relative timestamp. Make sure we can easily count missed timestamps + regardless of CP0 count/compare value. + + * get_ticks: return the current timestamp, that is get_timer(0). + + Most parts are from good old Linux v2.6.16 kernel. + + v2: + - Remove FIXME comments as they turned out to be trivial. + - Use CP0 compare register as a global variable for expirelo. + - Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY + instead. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 199e4f657c8af42efe3fb3ba1d1104eb6bb28c25 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Thu Jun 5 22:29:00 2008 +0900 + + [MIPS] lib_mips/time.c: Fix udelay + + What we have to do is just to wait for given micro-seconds. No need to + take into account current time, get_timer and CFG_HZ. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit c7e38e413ae69120d3e51f132c7cb1d6b3514d03 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Thu Jun 5 22:28:59 2008 +0900 + + [MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros + + We already have many pre-defined CP0 access macros in <asm/mipsregs.h>. + This patch replaces mips_{compare,count}_set and mips_count_get with + existing macros. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 6b52cfe16cd539935e32bd8cf19146522e462a4d +Author: Remy Bohmer <linux@bohmer.net> +Date: Tue Jun 3 15:48:17 2008 +0200 + + Get rid of annoying/superfluous bad-checksum warning message + + U-boot can complain a lot about 'checksum bad' when it is attached to the network. + It is annoying for ordinary users who start to doubt the network connection + in general when they see messages like this. + + This is caused by the routine NetCksumOk() which cannot handle IP-headers longer + than 20 bytes. Those packages can be ignored anyway by U-boot, so we trash them + now before checking the checksum. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit d6ee5fa40c26970d39990c6fc4a2f20a97822650 +Author: Remy Bohmer <linux@bohmer.net> +Date: Wed Jun 4 10:47:25 2008 +0200 + + Fix order for reading rx-status registers in 32bit mode of DM9000 + + A last minute cleanup before submitting the DM9000A patch series yesterday introduced + a bug in reading the rx-status registers in 32bit mode only. + This patch repairs this. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 98291e2e689096420465074cce926b226d2e71b4 +Author: Remy Bohmer <linux@bohmer.net> +Date: Tue Jun 3 15:26:26 2008 +0200 + + DM9000: Some minor code cleanups + + Some lines of the U-boot DM9000x driver are longer than 80 characters, or + need some other minor cleanup. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 850ba7555dbd4ca8d14fc475b864d534797adab3 +Author: Remy Bohmer <linux@bohmer.net> +Date: Tue Jun 3 15:26:25 2008 +0200 + + DM9000: Make driver work properly for DM9000A + + The DM9000A network controller does not work with the U-boot DM9000x driver. + Analysis showed that many incoming packets are lost. + + The DM9000A Application Notes V1.20 (section 5.6.1) recommend that the poll to + check for a valid rx packet be done on the interrupt status register, not + directly by performing the dummy read and the rx status check as is currently + the case in the u-boot driver. + + When the recommended poll is done as suggested the driver starts working + correctly on 10Mbit/HD, but on 100MBit/FD packets come in faster so that there + can be more than 1 package in the fifo at the same time. + + The driver must perform the rx-status check in a loop and read and handle all + packages until there is no more left _after_ the interrupt RX flag is set. + + This change has been tested with DM9000A, DM9000E, DM9000EP. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit fbcb7ece0ea1e364180f1cf963e0fa0ce7f6560d +Author: Remy Bohmer <linux@bohmer.net> +Date: Tue Jun 3 15:26:24 2008 +0200 + + DM9000: Improve eth_reset() routine + + According to the application notes of the DM9000 v1.22 chapter 5.2 bullet 2, the + reset procedure must be done twice to properly reset the DM9000 by means of software. + This errata is not needed anymore for the DM9000A, but it does not bother it. + + This change has been tested with DM9000A, DM9000E, DM9000EP. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit acba31847fad9ae40708cc2c9f3a634ec35f3416 +Author: Remy Bohmer <linux@bohmer.net> +Date: Tue Jun 3 15:26:23 2008 +0200 + + DM9000: improve eth_send() routine + + The eth_send routine of the U-boot DM9000x driver does not match the + DM9000 or DM9000A application notes/programming guides. + + This change improves the stability of the DM9000A network controller. + + This change has been tested with DM9000A, DM9000E, DM9000EP. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 134e266253c02a7832560da59d394989c4f64453 +Author: Remy Bohmer <linux@bohmer.net> +Date: Tue Jun 3 15:26:22 2008 +0200 + + DM9000: repair debug logging + + It seems that the debugging code of the DM9000x driver in U-boot has not been + compiled for a long time, because it cannot compile... + + Also rearranged some loglines to get more useful info while debugging. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit a101361bfe23c120321e45d114c0603b8e0763e9 +Author: Remy Bohmer <linux@bohmer.net> +Date: Tue Jun 3 15:26:21 2008 +0200 + + DM9000: Add data bus-width auto detection. + + The U-boot DM9000x driver contains a compile time bus-width definition for + the databus connected to the network controller. + + This compile check makes the code unclear, inflexible and is unneccessary. + It can be asked to the network controller what its bus-width is by reading bits + 6 and 7 of the interrupt status register. + + The linux kernel already uses a runtime mechanism to determine this bus-width, + so the implementation below looks somewhat like that implementation. + + This change has been tested with DM9000A, DM9000E, DM9000EP. + + Signed-off-by: Remy Bohmer <linux@bohmer.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 63a0afa0c32e5f4ea98a9439542870072437404d +Author: Stefan Roese <sr@denx.de> +Date: Wed Jun 4 19:19:20 2008 +0200 + + ppc4xx: Fix problem with SDRAM init in bamboo NAND booting port + + This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene) + introduced by the commit: + + ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S + + With this patch SDRAM will get initialized again and booting from NAND + is working again. + + Signed-off-by: Stefan Roese <sr@denx.de> + Acked-by: Eugene O'Brien <eugene.obrien@advantechamt.com> + +commit 9ef1cbef1a649e3779298b0e663be4865cbbbfbc +Author: Wolfgang Denk <wd@denx.de> +Date: Tue May 27 14:19:30 2008 +0200 + + Socrates: Fix PCI bus frequency report + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 8ec6e332eace0ee78c71ee5f645d12b06813b86f +Author: Tor Krill <tor@excito.com> +Date: Thu May 29 11:10:30 2008 +0200 + + Fix incorrect switch for IF_TYPE in part.c + + Use correct field in block_dev_desc_t when writing interface type in + dev_print. Error introduced in 574b3195. + + Also added fix from Martin Krause + + Signed-off-by: Tor Krill <tor@excito.com> + +commit b64b8a0bd310935b70af69ac970952f2b364ae56 +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Tue May 27 10:25:39 2008 +0200 + + Add size #defines for Altera Cyclone-II EP2C8 and EP2C20. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + +commit 35ef877f0a8f6232cdef748f442fed5accb2b641 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Thu May 22 18:56:52 2008 -0500 + + Additional fix to readline_into_buffer() with CONFIG_CMDLINE_EDITING before relocating + + Removed unneeded command line history initialization. Also, the original + code would access the 'initted' variable before relocation to SDRAM + which resulted in erratic behavior since the bss is not initialized when + executing from flash. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 22f371b63038a4ecab04068877c1089e51a01ba1 +Author: Grant Erickson <gerickson@nuovations.com> +Date: Wed May 21 13:28:30 2008 -0700 + + PPC4xx: Simplified post_word_{load, store} + + This patch simplifies post_word_{load,store} by using the preprocessor + to eliminate redundant, copy-and-pasted code. + + Signed-off-by: Grant Erickson <gerickson@nuovations.com> + +commit 9c048b523413ae5f3ff34e00cf57569c3368ab51 +Author: Vasiliy Leoenenko <vasiliy.leonenko@mail.ru> +Date: Wed May 7 21:25:33 2008 +0400 + + cfi_flash: enable M18 flash chips family support. + + Added new command set ID. Buffered write command processing is changed + in order to support M18 flash chips family. + + Signed-off-by: Alexey Korolev <akorolev@infradead.org> + Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko@mail.ru> + +commit 93c56f212ccdadc182018f0769cb284426b88f1d +Author: Vasiliy Leoenenko <vasiliy.leonenko@mail.ru> +Date: Wed May 7 21:24:44 2008 +0400 + + cfi_flash: support of long cmd in U-boot. + + Some NOR flash chips needs support of commands with length grether than max + value size of uchar. For example all M18 family chips use 0x1ff command in + buffered write mode as value of program loops count. + + Signed-off-by: Alexey Korolev <akorolev@infradead.org> + Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko@mail.ru> + +commit 4d91d1df2f16b511ab80dec50c80e050ba0d841e +Author: Stefan Roese <sr@denx.de> +Date: Fri May 16 11:06:06 2008 +0200 + + DTT: Issue one-shot command on AD7414 (LM75 code) to read temp + + On AD7414 the first value upon bootup is not read correctly. + This is most likely because of the 800ms update time of the + temp register in normal update mode. To get current values + each time we issue the "dtt" command including upon powerup + we switch into one-short mode. + + This patch fixes the problem on AD7414 equipped boards (Sequoia, + Canyonlands etc), that temp value printed in the bootup log was + incorrect. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit de5bfcf7b0425e032be12698252dbaa6b65a28c0 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Fri May 30 16:55:06 2008 +0200 + + ppc4xx: Cleanup CPCI405 variant's config file + + This patch removes some dead code from CPCI405 board's + config files. JFFS2 support is also removed. It's not used and + CPCI4052 does not build anymore without some size reduction. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit 2918eb9d42bc705fcbd18c9fcc39d15ff2843c65 +Author: Kenneth Johansson <kenneth@southpole.se> +Date: Thu May 29 16:32:33 2008 +0200 + + Remove shell variable UNDEF_SYM. + + UNDEF_SYM is a shell variable in the main Makefile used to force the + linker to add all u-boot commands to the final image. It has no use here. + + Signed-off-by: Kenneth Johansson <kenneth@southpole.se> + +commit 8c66497e06bf803489c589df58ee591d71033274 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 16 11:10:35 2008 +0200 + + Add support for environment in SPI flash + + This is pretty incomplete...it doesn't handle reading the environment + before relocation, it doesn't support redundant environment, and it + doesn't support embedded environment. But apart from that, it does + seem to work. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit b6368467e6a97f225e0a5fd7bfc5c7598ef5ddc4 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 16 11:10:34 2008 +0200 + + SPI Flash: Add "sf" command + + This adds a new command, "sf" which can be used to manipulate SPI + flash. Currently, initialization, reading, writing and erasing is + supported. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit d25ce7d24cc0f93881559f4009175ea305af65e8 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 16 11:10:33 2008 +0200 + + SPI Flash subsystem + + This adds a new SPI flash subsystem. + + Currently, only AT45 DataFlash in non-power-of-two mode is supported, + but some preliminary support for other flash types is in place as + well. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 60445cb5c3eb77ed1a07f2d908eef09174483698 +Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com> +Date: Fri May 16 11:10:32 2008 +0200 + + atmel_spi: Driver for the Atmel SPI controller + + This adds a driver for the SPI controller found on most AT91 and AVR32 + chips, implementing the new SPI API. + + Changed in v4: + - Update to new API + - Handle zero-length transfers appropriately. The user may send a + zero-length SPI transfer with SPI_XFER_END set in order to + deactivate the chip select after a series of transfers with chip + select active. This is useful e.g. when polling the status + register of DataFlash. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit d255bb0e78d1cac5b7c8c98cb77a095f5f16de0d +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri May 16 11:10:31 2008 +0200 + + SPI API improvements + + This patch gets rid of the spi_chipsel table and adds a handful of new + functions that makes the SPI layer cleaner and more flexible. + + Instead of the spi_chipsel table, each board that wants to use SPI + gets to implement three hooks: + * spi_cs_activate(): Activates the chipselect for a given slave + * spi_cs_deactivate(): Deactivates the chipselect for a given slave + * spi_cs_is_valid(): Determines if the given bus/chipselect + combination can be activated. + + Not all drivers may need those extra functions however. If that's the + case, the board code may just leave them out (assuming they know what + the driver needs) or rely on the linker to strip them out (assuming + --gc-sections is being used.) + + To set up communication parameters for a given slave, the driver needs + to call spi_setup_slave(). This returns a pointer to an opaque + spi_slave struct which must be passed as a parameter to subsequent SPI + calls. This struct can be freed by calling spi_free_slave(), but most + driver probably don't want to do this. + + Before starting one or more SPI transfers, the driver must call + spi_claim_bus() to gain exclusive access to the SPI bus and initialize + the hardware. When all transfers are done, the driver must call + spi_release_bus() to make the bus available to others, and possibly + shut down the SPI controller hardware. + + spi_xfer() behaves mostly the same as before, but it now takes a + spi_slave parameter instead of a spi_chipsel function pointer. It also + got a new parameter, flags, which is used to specify chip select + behaviour. This may be extended with other flags in the future. + + This patch has been build-tested on all powerpc and arm boards + involved. I have not tested NIOS since I don't have a toolchain for it + installed, so I expect some breakage there even though I've tried + fixing up everything I could find by visual inspection. + + I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and + DataFlash drivers posted as a follow-up. I'd like some help testing + other boards that use the existing SPI API. + + But most of all, I'd like some comments on the new API. Is this stuff + usable for everyone? If not, why? + + Changed in v4: + - Build fixes for various boards, drivers and commands + - Provide common struct spi_slave definition that can be extended by + drivers + - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate + - Make default bus and mode build-time configurable + - Override default SPI bus ID and mode on mx32ads and imx31_litekit. + + Changed in v3: + - Add opaque struct spi_slave for controller-specific data associated + with a slave. + - Add spi_claim_bus() and spi_release_bus() + - Add spi_free_slave() + - spi_setup() is now called spi_setup_slave() and returns a + struct spi_slave + - soft_spi now supports four SPI modes (CPOL|CPHA) + - Add bus parameter to spi_setup_slave() + - Convert the new i.MX32 SPI driver + - Convert the new MC13783 RTC driver + + Changed in v2: + - Convert the mpc8xxx_spi driver and the mpc8349emds board to the + new API. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + Tested-by: Guennadi Liakhovetski <lg@denx.de> + +commit 289011207d999b2e4085150d2aa30d547ad9b800 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 16 11:10:30 2008 +0200 + + Move definition of container_of() to common.h + + AVR32 and AT91SAM9 both have their own identical definitions of + container_of() taken from the Linux kernel. Move it to common.h so + that all architectures can use it. + + container_of() is already used by some drivers, and will be used + extensively by the new and improved SPI API. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 110e006fe67fb4a6e1719ae6956c79b7ffc0148b +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 16 11:08:11 2008 +0200 + + soft_i2c: Pull SDA high before reading + + Spotted by Dean Capindale. + + Systems that support open-drain GPIO properly are allowed provide an + empty I2C_TRISTATE define. However, this means that we need to be + careful not to drive SDA low when the slave is expected to respond. + + This patch adds a missing I2C_SDA(1) to read_byte() required to + tristate the SDA line on systems that support open-drain GPIO. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 3c1de1a6d36be9eee284a6c596a86e94f19cc5b2 +Author: Stefan Roese <sr@denx.de> +Date: Mon May 19 11:34:53 2008 +0200 + + ppc4xx: Remove implementations of testdram() + + This patch removes the used testdram() implementations of the board + that are maintained by myself. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit bbeff30cbd1c5d551eb0ad1c2239ec01844c0b0a +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 2 17:37:28 2008 +0200 + + ppc4xx: Remove superfluous dram_init() call or replace it by initdram() + + Historically the 405 U-Boot port had a dram_init() call in early init + stage. This function was still called from start.S and most of the time + coded in assembler. This is not needed anymore (since a long time) and + boards should implement the common initdram() function in C instead. + + This patch now removed the dram_init() call from start.S and removes the + empty implementations that are scattered through most of the 405 board + ports. Some older board ports really implement this dram_init() though. + These are: + + csb272 + csb472 + ERIC + EXBITGEN + W7OLMC + W7OLMG + + I changed those boards to call this assembler dram_init() function now + from their board specific initdram() instead. This *should* work, but please + test again on those platforms. And it is perhaps a good idea that those + boards use some common 405 SDRAM initialization code from cpu/ppc4xx at + some time. So further patches welcome here. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 192f90e272b3989ee7b4a666d1fdab831f20f8d2 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 2 17:22:11 2008 +0200 + + ppc4xx: Use new 4xx SDRAM controller enable defines in common ECC code + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 39b32be18cd33b53a84065edcd4e465165cc5564 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 2 17:20:03 2008 +0200 + + ppc4xx: Fix common ECC generation code for 440GP style platforms + + This patch makes the common 4xx ECC code really usable on 440GP style + platforms. + + Since the IBM DDR controller used on 440GP/GX/EP/GR is not register + compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT + we need to make some processor dependant defines used later on by the + driver. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit ec724f883ee3f3925e6c55027e8ffa70ada83303 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 2 17:13:55 2008 +0200 + + ppc4xx: Change Kilauea to use the common DDR2 init function + + This patch changes the kilauea and kilauea_nand (for NAND booting) + board port to not use a board specific DDR2 init routine anymore. Now + the common code from cpu/ppc4xx is used. + + Thanks to Grant Erickson for all his basic work on this 405EX early + bootup. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 17ceb069b85fbb9269c4dc09b2c237f88334c5ba +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 2 14:59:21 2008 +0200 + + ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part2 + + This patch now adds a new header file (asm-ppc/ppc4xx-sdram.h) for all + ppc4xx related SDRAM/DDR/DDR2 controller defines. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 36ea16f6a066ccb046e91ebce4f326b69f4c0569 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 2 14:57:41 2008 +0200 + + ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 + + This patch removes all SDRAM related defines from the PPC4xx headers + ppc405.h and ppc440.h. This is needed since now some 405 PPC's use + the same SDRAM controller as 440 systems do (like 405EX and 440SP). + + It also introduces new defines for the equipped SDRAM controller based on + which PPC variant is used. There new defines are: + + used on 405GR/CR/EP and some Xilinx Virtex boards. + + used on 440GP/GX/EP/GR. + + used on 440EPx/GRx. + + used on 405EX/r/440SP/SPe/460EX/GT. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 64852d09e06dd6db2b2db2a3c59bc2db176a54d6 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jun 2 14:35:44 2008 +0200 + + ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S + + This patch consolidates the 405 and 440 parts of the NAND booting code + selected via CONFIG_NAND_SPL. Now common code is used to initialize the + SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc. + Only *after* running from this location, nand_boot() is called. + + Please note that the initsdram() call is now moved from nand_boot.c + to start.S. I experienced problems with some boards like Kilauea + (405EX), which don't have internal SRAM (OCM) and relocation needs to + be done to SDRAM before the NAND controller can get accessed. When + initdram() is called later on in nand_boot(), this can lead to problems + with variables in the bss sections like nand_ecc_pos[]. + + Signed-off-by: Stefan Roese <sr@denx.de> + Acked-by: Scott Wood <scottwood@freescale.com> + +commit 8a24c07ba5da2c72ad1f05e3eb8a463750200c98 +Author: Grant Erickson <gerickson@nuovations.com> +Date: Thu May 22 14:44:24 2008 -0700 + + ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling + + This patch (Part 2 of 2): + + * Rolls up a suite of changes to enable correct primordial stack and + global data handling when the data cache is used for such a purpose + for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). + + * Related to the first, unifies DDR2 SDRAM and ECC initialization by + eliminating redundant ECC initialization implementations and moving + redundant SDRAM initialization out of board code into shared 4xx + code. + + * Enables MCSR visibility on the 405EX(r). + + * Enables the use of the data cache for initial RAM on + both AMCC's Kilauea and Makalu and removes a redundant + CFG_POST_MEMORY flag from each board's CONFIG_POST value. + + - Removed, per Stefan Roese's request, defunct memory.c file for + Makalu and rolled sdram_init from it into makalu.c. + + With respect to the 4xx DDR initialization and ECC unification, there + is certainly more work that can and should be done (file renaming, + etc.). However, that can be handled at a later date on a second or + third pass. As it stands, this patch moves things forward in an + incremental yet positive way for those platforms that utilize this + code and the features associated with it. + + Signed-off-by: Grant Erickson <gerickson@nuovations.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c821b5f120bedf73867513466412587c6912a8f8 +Author: Grant Erickson <gerickson@nuovations.com> +Date: Thu May 22 14:44:14 2008 -0700 + + ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling + + This patch (Part 1 of 2): + + * Rolls up a suite of changes to enable correct primordial stack and + global data handling when the data cache is used for such a purpose + for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). + + * Related to the first, unifies DDR2 SDRAM and ECC initialization by + eliminating redundant ECC initialization implementations and moving + redundant SDRAM initialization out of board code into shared 4xx + code. + + * Enables MCSR visibility on the 405EX(r). + + * Enables the use of the data cache for initial RAM on + both AMCC's Kilauea and Makalu and removes a redundant + CFG_POST_MEMORY flag from each board's CONFIG_POST value. + + - Removed, per Stefan Roese's request, defunct memory.c file for + Makalu and rolled sdram_init from it into makalu.c. + + With respect to the 4xx DDR initialization and ECC unification, there + is certainly more work that can and should be done (file renaming, + etc.). However, that can be handled at a later date on a second or + third pass. As it stands, this patch moves things forward in an + incremental yet positive way for those platforms that utilize this + code and the features associated with it. + + Signed-off-by: Grant Erickson <gerickson@nuovations.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a439680019e06171d4a5694b7992accce87f590e +Author: Grant Erickson <gerickson@nuovations.com> +Date: Wed May 21 13:28:30 2008 -0700 + + PPC4xx: Simplified post_word_{load, store} + + This patch simplifies post_word_{load,store} by using the preprocessor + to eliminate redundant, copy-and-pasted code. + + Signed-off-by: Grant Erickson <gerickson@nuovations.com> + +commit f979690ee337450b2030aba128f95b7a8d9881c0 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu May 15 15:13:08 2008 -0500 + + Fix warnings from gcc-4.3.0 build on a ppc host + + * The cfi_flash.c memset fix actual allows the board to boot so there is + a bit more going on here than just resolving warnings associated with + uninitialized variables. + + * include/asm/bitops.h:302: warning: '__swab32p' is static but used in + inline function 'ext2_find_next_zero_bit' which is not static + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 9b124a68346ce9605b6e1fcf79e1021541cdba9e +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Wed May 14 13:09:51 2008 -0500 + + MPC512x: Change traps.c to not reference non-addressable memory + + Currently, END_OF_RAM is used by the trap code to determine if + we should attempt to access the stack pointer or not. However, + on systems with a lot of RAM, only a subset of the RAM is + guaranteed to be mapped in and accessible. Change END_OF_RAM + to use get_effective_memsize() instead of using the raw ram + size out of the bd. + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit 81673e9ae14b771cd13faf19947192599cae3959 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue May 13 19:01:54 2008 -0500 + + Make sure common.h is the first include. + + If common.h isn't first we can get CONFIG_ options defined in the + board config file ignored. This can cause an issue if any of those + config options impact the size of types of data structures + (eg CONFIG_PHYS_64BIT). + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 95d449ad4de79dd32b1705b8a4d3550f1e9081e3 +Author: Marian Balakowicz <m8@semihalf.com> +Date: Tue May 13 15:53:29 2008 +0200 + + Avoid initrd and logbuffer area overlaps + + Add logbuffer to reserved LMB areas to prevent initrd allocation + from overlaping with it. + + Make sure to use correct logbuffer base address. + + Signed-off-by: Marian Balakowicz <m8@semihalf.com> + +commit 6956d53d9934862507f83f0e3255dfd4662e7482 +Author: Sascha Laue <sascha.laue@liebherr.com> +Date: Tue May 13 13:29:54 2008 +0200 + + lwmon5: add memory-pattern-test to FPGA POST. + +commit e34a0e911b6a1568d0ca864234fbd0ee060d9b35 +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Thu May 8 19:02:51 2008 -0500 + + PPC: 86xx Add bat registers to reginfo command + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit d5b9b8cdb8b6eb3a8b0f5d9909d69ccc9c703ed9 +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Fri May 9 15:41:35 2008 -0500 + + PPC: Add print_bats() to lib_ppc/bat_rw.c + + This function prints the values of all the BAT register + pairs - I needed this for debug earlier this week; adding it to + lib_ppc so others can use it (and add it to reginfo commands + if so desired). + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit c148f24c15743a02e855636e6bed013bd121f7f2 +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Thu May 15 21:29:04 2008 -0500 + + PPC: Change lib_ppc/bat_rw.c to use high bats + + Currently, this code only deals with BATs 0-3, which makes + it useless on systems that support BATs 4-7. Add the + support for these registers. + + Signed-off-by: Becky Bruce <Becky.bruce@freescale.com> + +commit 31d826722434931e1152a09d140187dcf72f8aac +Author: Becky Bruce <becky.bruce@freescale.com> +Date: Thu May 8 19:02:12 2008 -0500 + + PPC: Create and use CONFIG_HIGH_BATS + + Change all code that conditionally operates on high bat + registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS + instead of the myriad ways this is done now. Define the option + for every config for which high bats are supported (and + enabled by early boot, on parts where they're not always + enabled) + + Signed-off-by: Becky Bruce <becky.bruce@freescale.com> + +commit aa3b8bf9c30065bb2ea852799d32db5020598495 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Wed May 28 19:55:19 2008 +0200 + + E1000: Add support for the 82541GI LF Intel Pro 1000 GT Desktop Adapter + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit ff36fbb2e7583fb808eef773f511489c7a9c2df3 +Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com> +Date: Wed May 28 13:06:25 2008 -0500 + + ColdFire: Add 10 base ethernet support for mcf5445x + + Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 1a9fcc4b765599db24fa9c32293599f24c7a19ba +Author: Jason McMullan <mcmullan@netapp.com> +Date: Fri May 30 00:53:38 2008 +0900 + + mips: Add an 'include/asm/errno.h', like all other architectures + + All other u-boot architectures have an include/asm/errno.h, so + this change adds it to the mips include/asm-mips headers also. + + Stolen from Linux 2.6.25. + + Signed-off-by: Jason McMullan <mcmullan@netapp.com> + +commit e2ad8426624bac457acc6925b6ff408e9bf20466 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Fri May 30 00:53:38 2008 +0900 + + [MIPS] <asm/mipsregs.h>: Update coprocessor register access macros + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 1a3adac81c292f2ee76e43cdeb2fbe8f915fe194 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Fri May 30 00:53:38 2008 +0900 + + [MIPS] <asm/mipsregs.h>: Update register / bit field definitions + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit bf462ae450a7f2eeeddc699ed345b391e3263540 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Fri May 30 00:53:37 2008 +0900 + + [MIPS] <asm/mipsregs.h>: CodinygStyle cleanups + + No functional changes. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 89a1550ec6b74452274a7a23127936e2c7eec711 +Author: Jason McMullan <mcmullan@netapp.com> +Date: Fri May 30 00:53:37 2008 +0900 + + mips: If CONFIG_CMD_SPI is defined, call spi_init() + + The mips architecture currently does not call 'spi_init()' in the generic + board initialization routine is CONFIG_CMD_SPI is defined. + + This patch rectifies that problem. + + Signed-off-by: Jason McMullan <mcmullan@netapp.com> + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit e996bc339b0f39f6c0b29b1455ba7eb318b023d3 +Author: Jason McMullan <mcmullan@netapp.com> +Date: Fri May 30 00:53:37 2008 +0900 + + [MIPS] lib_mips/board.c: Add nand_init + + This patch adds the standard 'nand_init()' call to the mips generic + 'board_init_r()' call, bringing MIPS in line with the other architectures. + + Signed-off-by: Jason McMullan <mcmullan@netapp.com> + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit d6ac2ed893c2168738aee01579d6283af8d37045 +Author: Scott Wood <scottwood@freescale.com> +Date: Thu May 22 10:49:46 2008 -0500 + + Remove prototypes of nand_init() in favor of including nand.h. + + Likewise with onenand_init(). + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 229c56f07a82eacda8c8720cb146fc9be0f6db54 +Author: Scott Wood <scottwood@freescale.com> +Date: Thu May 22 10:49:00 2008 -0500 + + Make onenand_uboot.h self-sufficient. + + Don't assume types are provided by previously included headers. + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 9723bbb46abb7b2ca24eead5114a3faa58060c20 +Author: Dirk Behme <dirk.behme@gmail.com> +Date: Wed Jan 16 14:26:59 2008 +0100 + + nand: Correct NAND erase percentage output + + For NAND erase sizes smaller than one NAND erase block, erase + percentage output becomes grater than 100% e.g. + + -- cut -- + > nand info + Device 0: NAND 64MiB 1,8V 8-bit, sector size 16 KiB + > nand erase 0x100000 0x2000 + NAND erase: device 0 offset 0x100000, size 0x2000 + Erasing at 0x100000 -- 200% complete. + OK + > + -- cut -- + + Correct this and give user a warning that more is erased than specified: + + -- cut -- + > nand erase 0x100000 0x2000 + NAND erase: device 0 offset 0x100000, size 0x2000 + Warning: Erase size 0x00002000 smaller than one erase block 0x00004000 + Erasing 0x00004000 instead + Erasing at 0x100000 -- 100% complete. + OK + > + -- cut -- + + Signed-off-by: Dirk Behme <dirk.behme@gmail.com> + +commit 5922db6c0948506be91e0de44e7a6863a18a417f +Author: Stelian Pop <stelian@popies.net> +Date: Tue May 13 17:31:24 2008 +0200 + + Cleanup nand_info[] declaration. + + The nand_info array is declared as extern in several .c files. + Those days, nand.h contains a reference to the array, so there is + no need to declare it elsewhere. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 135f0a7488af2947adbe4b40b79280bdfe5e9886 +Author: Scott Wood <scottwood@freescale.com> +Date: Mon May 19 09:30:43 2008 -0500 + + NAND: Provide a sane default for NAND_MAX_CHIPS. + + This allows the header to be included regardless of whether a board's + config file provides NAND-related defininitions. + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit a8092c021d27f27f4b323b7d49979ca01b3fc19d +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Mon May 26 12:19:10 2008 +0200 + + avr32: Fix theoretical race in udelay() + + If the specified delay is very short, the cycle counter may go past the + "end" time we are waiting for before we get around to reading it. + + Fix it by checking the different between the cycle count "now" and the + cycle count at the beginning. This will work as long as the delay + measured in number of cycles is below 2^31. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 48ea623eae8674793372e3e7c95e72e5a44d7a95 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Wed May 21 13:01:09 2008 +0200 + + avr32: Compile atmel_mci.o conditionally + + Remove #ifdef CONFIG_MMC from the source file and use conditional + compilation in the Makefile instead. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit e92a5bf8330654e33ac13f6b3058634e58f5d1c0 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Thu May 22 12:28:25 2008 +0200 + + avr32: Fix wrong error flags in atmel_mci driver + + Make sure we check for CRC errors when sending commands that use CRC + checking. + + Reported-by: Gururaja Hebbar K R <gururajakr@sanyo.co.in> + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 7a96ddadd13e6ac9a829affce9b6f8823f580e49 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Wed May 21 11:10:59 2008 +0200 + + avr32: Fix two warnings in atmel_mci.c + + The warnings are harmless but annoying. Let's fix them. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit a23e277c4a3a2bbc42d237aae29da3a8971e757f +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Mon May 19 11:36:28 2008 +0200 + + avr32: Rework SDRAM initialization code + + This cleans up the SDRAM initialization and related code a bit, and + allows faster booting. + + * Add definitions for EBI and internal SRAM to asm/arch/memory-map.h + * Remove memory test from sdram_init() and make caller responsible + for verifying the SDRAM and determining its size. + * Remove base_address member from struct sdram_config (was sdram_info) + * Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT + * Add support for a common STK1000 hack: 16MB SDRAM instead of 8. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 95107b7c028806919630bf02c653aa8f4f867c94 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Mon May 19 11:27:37 2008 +0200 + + avr32: Do stricter stack checking in the exception handler + + Don't do a stack dump if the stack pointer is outside the memory area + reserved for stack. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit caf83ea888a0220f41747d0b7748fa43b4a4bd49 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 2 15:32:57 2008 +0200 + + avr32: Use the same entry point for reset and exception handling + + Since the reset vector is always aligned to a very large boundary, we + can save a couple of KB worth of alignment padding by placing the + exception vectors at the same address. + + Deciding which one it is is easy: If we're handling an exception, the + CPU is in Exception mode. If we're starting up after reset, the CPU is + in Supervisor mode. So this adds a very minimal overhead to the reset + path (only executed once) and the exception handling path (normally + never executed at all.) + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 0c16eed2189a190bd5655b33c029f809a9b31128 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 2 15:24:22 2008 +0200 + + avr32: Put memset in its own section + + All C code is compiled with -ffunction-sections -fdata-sections. + Assembly functions should get their own sections as well so that + everything looks consistent. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 3ace2527ba80bd2fe1bceaab50d0b3c4fb5dd020 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Fri May 2 15:21:40 2008 +0200 + + avr32: Rename pm_init() as clk_init() and make SoC-specific + + pm_init() was always more about clock initialization than anything + else. Dealing with PLLs, clock gating and such is also inherently + SoC-specific, so move it into a SoC-specific directory. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 4f5972c3b2454c22957f2842cfe64ec8118e015b +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Wed Apr 30 16:15:57 2008 +0200 + + avr32: Use new-style Makefile for the at32ap platform + + This makes it easier to avoid compiling certain files later. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit a9b2bb78a1bd8ebdb633509bdd1c8134d527b213 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Wed Apr 30 14:36:47 2008 +0200 + + avr32: Remove unused file cpu/at32ap/pm.c + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 44453b25b06426eef0b7b2fa7c026fdf19ce34f2 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Wed Apr 30 14:19:28 2008 +0200 + + avr32: Clean up the HMATRIX code + + Rework the HMATRIX configuration interface so that it becomes easier + to configure the HMATRIX for boards with special needs, and add new + parts. + + The HMATRIX header file has been split into a general, + chip-independent part with register definitions, etc. and a + chip-specific part with SFR bitfield definitions and master/slave + identifiers. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 0a2e48792dd372c90b80059f3235e67a567e16fc +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Thu Nov 22 12:14:11 2007 +0100 + + avr32: Add support for the ATSTK1006 board + + This is a replacement for ATSTK1002 with 64MB SDRAM and NAND flash on + board. It's currently in production and will be available soon. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 781eb9a1e4af4bd34c138e6126ec5cc6dd4b5440 +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Tue Apr 29 12:53:05 2008 +0200 + + avr32: Get rid of the .flashprog section + + The .flashprog section was only needed back when we were running + directly from flash, and it's even more useless on NGW100 since it + uses the CFI flash driver which never used this workaround in the + first place. + + Remove it on STK1000 as well, and get rid of all the associated code and + annotations. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit cdd42c0c7a5205fc380912d83229069a71ea3abf +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Wed Apr 30 13:09:56 2008 +0200 + + avr32: Use correct condition around macb clock accessors + + get_macb_pclk_rate() and get_macb_hclk_rate() should be available when + the chip has a MACB controller, not when it has a USART. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit f793a3581901ff39c2abb94012d9bbc8573ccf02 +Author: David Brownell <david-b@pacbell.net> +Date: Wed Apr 16 22:57:58 2008 -0700 + + avr32: Disable the AP7000 internal watchdog on startup + + This patch forces the watchdog off in all cases. That will at least + get rid of the constant reboot cycle, though it won't let the watchdog + actually run in the new kernels: its probe() comes up with a polite + warning. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 55ac7a7490b55da56659f95d82a0c83b9756df27 +Author: David Brownell <david-b@pacbell.net> +Date: Fri Feb 22 12:54:39 2008 -0800 + + avr32: stk1002 and ngw100 convergence + + Make STK1002 and NGW100 boards act more alike: + - STK boards can use as many arguments as NGW + - STK boards don't need to manage FPGAs either + - NGW commands should match STK ones + + Also spell U-Boot right in prompts for STK1002 and NGW100. + + Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> + [haavard.skinnemoen@atmel.com: update STK100[34] as well] + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit 5e1882df6a3efc7de5524d28cea4ecde7d163d54 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Tue May 27 13:47:00 2008 +0200 + + Socrates: Fix PCI bus frequency report + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 791e1dba8de76ad8e762a7badb869f224a1f8b82 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Tue May 27 11:49:13 2008 +0200 + + Socrates: Added USB support. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 5a904e5637cff1d708dc67098004f83ba9e84c54 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Tue May 27 11:35:02 2008 +0200 + + USB: add new configuration variable CONFIG_PCI_OHCI_DEVNO + + In case of several PCI USB controllers on a board this variable + specifys which controller to use. + See doc/README.generic_usb_ohci for details. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 2f7468aeba60e1288030a8d007c4e63bd3f13221 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Tue May 27 10:36:07 2008 +0200 + + Socrates: add support for DS75 Digital Thermo Sensor on I2C bus. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 83e9d7a2614d4006b92690afa3390c291734267e +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Mon May 26 18:16:04 2008 +0200 + + Socrates: Config file cleanup. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 602cac1389b755b223272f2328a47e6f8c240848 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Sat May 24 12:47:46 2008 +0200 + + MAKEALL: add at91 list + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 290ef6436838b1cc013bd67e0e0495c9eb3e23c0 +Author: Ron Madrid <ron_madrid@sbcglobal.net> +Date: Fri May 23 15:37:05 2008 -0700 + + Add Marvell 88E1118 support for TSEC + + Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 557b377d8bfc8b833b6e749457bcdfa298331a24 +Author: Jens Gehrlein <sew_s@tqs.de> +Date: Mon May 5 14:06:11 2008 +0200 + + smc911x: add 16 bit support + + Signed-off-by: Jens Gehrlein <sew_s@tqs.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit c918261c6d9f265f88baf70f8a73dfe6f0cb9596 +Author: Christian Eggers <ceggers@gmx.de> +Date: Wed May 21 22:12:00 2008 +0200 + + USB: replace old swap_ with proper endianess conversion macros + + Signed-off-by: Christian Eggers <ceggers@gmx.de> + Signed-off-by: Markus Klotzbuecher <mk@denx.de> + +commit fb63939b4fe140849cdba69f9e64a3e0e2f3ce1c +Author: Christian Eggers <ceggers@gmx.de> +Date: Wed May 21 21:29:10 2008 +0200 + + Fix endianess conversion in usb_ohci.c + + Signed-off-by: Christian Eggers <ceggers@gmx.de> + Signed-off-by: Markus Klotzbuecher <mk@denx.de> + +commit 477434c63c2ea5baa5c6c4e43500786f436511ff +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Thu May 22 01:15:53 2008 +0200 + + USB: add support for multiple PCI OHCI controllers + + Add new configuration variable CONFIG_PCI_OHCI_DEVNO. + In case of several PCI USB controllers on a board this variable + specifys which controller to use. + + Also add USB support for sokrates board. + + See doc/README.generic_usb_ohci for details. + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + Signed-off-by: Markus Klotzbuecher <mk@denx.de> + +commit ce6754df61cbe23b5b73d095a00ac9a8504b3d77 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed May 21 16:56:08 2008 +0200 + + Fix some whitespace issues + + introduced by 53677ef18 "Big white-space cleanup." + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 4416603aeb06861b468b06a981e52c3ff805db7b +Author: York Sun <yorksun@freescale.com> +Date: Mon May 12 14:36:39 2008 -0500 + + Make ads5121 out-of-tree compiling safe + + Reuse the existing DIU driver in board/freescale/common. + + Signed-off-by: York Sun <yorksun@freescale.com> + +commit 0e1bad47cd345c76c91a64caf41011e431b62599 +Author: York Sun <yorksun@freescale.com> +Date: Mon May 5 10:20:01 2008 -0500 + + Adding DIU support for Freescale 5121ADS + + Add DIU and cfb console support to FSL 5121ADS board. + + Use #define CONFIG_VIDEO in config file to enable fb console. + + Signed-off-by: York Sun <yorksun@freescale.com> + +commit a48ff68d235e671176f6b496c44246dbe5e0a93f +Author: York Sun <yorksun@freescale.com> +Date: Mon May 5 10:20:00 2008 -0500 + + Replace DPRINTF with debug + + Remove DPRINTF macro and replace it with generic debug macro. + + Signed-off-by: York Sun <yorksun@freescale.com> + +commit 3b80c5f574ad7f6e1c55a68f42752b427fdf778d +Author: York Sun <yorksun@freescale.com> +Date: Mon May 5 10:19:59 2008 -0500 + + Move pixel clock setting to board file + + The clock divider has different format in 5121 and 8610. This patch moves it to + board specific code. + + Signed-off-by: York Sun <yorksun@freescale.com> + +commit 53677ef18e25c97ac613349087c5cb33ae5a2741 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue May 20 16:00:29 2008 +0200 + + Big white-space cleanup. + + This commit gets rid of a huge amount of silly white-space issues. + Especially, all sequences of SPACEs followed by TAB characters get + removed (unless they appear in print statements). + + Also remove all embedded "vim:" and "vi:" statements which hide + indentation problems. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 2f845dc2bdf461bfee9fa25823f769f5db9eba0b +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Thu May 8 17:46:23 2008 +0200 + + socrates: fix second TSEC configuration (it is actually TSEC3) + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 793670c3c0f0f72caead62f0be9fc3d9fbc6060f +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Thu May 8 14:17:08 2008 +0200 + + Fixed reset for socrates + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit e18575d5f589a62e19c70d471d4b4e27cad3af56 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Wed May 7 15:10:49 2008 +0200 + + socrates: changes to support FDT + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 5d108ac8f435924c624cd6aaacd44f35f5cf94c0 +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Wed Apr 30 11:42:50 2008 +0200 + + Initial support for "Socrates" board + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 0e15ddd11f1a84c465e434eb051d2ef08ef02b9b +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu May 8 15:46:42 2008 +0200 + + POST: replace the LOGBUFF_INITIALIZED flag in gd->post_log_word (1 << 31) with the GD_FLG_LOGINIT flag in gd->flags. + + This way we become able to utilize the full post_log_word for POST + activities (overwise, POST ECC, which has 0x8000 ID, could be + erroneously treated as started in post_output_backlog() even if there + was actually no POST ECC run (because of OCM POST failure, for + example). + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit 7845d49094c81321021b50a4dbb8864d2f3777e4 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu May 8 15:46:02 2008 +0200 + + POST: mark OCM test as POST_STOP + + Signed-off-by: Ilya Yanok <yanok@emcraft.com> + +commit 28a385065882d6cb6ac5f443311ff87887ed7c13 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu May 8 15:45:26 2008 +0200 + + POST: add POST_STOP flag + + Don't run futher tests in case of a test fails that is marked as + POST_STOP. + + Signed-off-by: Ilya Yanok <yanok@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit a525145d8110d15b4389d23c3ea8a78f22509d3f +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu May 8 15:44:16 2008 +0200 + + POST: switch CFG_POST_OCM with CFG_POST_CODEC (workaround) + + Switch the OCM testid with the codec one. The reason is that current + implementation requires the POST_ROM testid to fit into lower 16 + bits, and the codec test will never run with POST_ROM hopefully. + + Signed-off-by: Ilya Yanok <yanok@emcraft.com> + +commit 8b96c788d58f7cb85a89ee3f19c9b335d22443cd +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu May 8 15:43:28 2008 +0200 + + lwmon5: enable OCM post test on lwmon5 board + + Signed-off-by: Ilya Yanok <yanok@emcraft.com> + +commit 6e8ec682268493b8d098f99e17b1ce71b4448977 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu May 8 15:42:47 2008 +0200 + + POST: OCM test added. + + Added OCM test to POST layer. This version runs before all other tests + but doesn't yet interrupt post sequence on failure. + + Signed-off-by: Ilya Yanok <yanok@emcraft.com> + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit 6891260bdd935a382c95d9fa333922b0dfded68a +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Thu May 8 15:40:39 2008 +0200 + + POST: typo fix + + Signed-off-by: Ilya Yanok <yanok@emcraft.com> + +commit 727f63334676e760877d43bfb8f0e9331ac8b101 +Author: Hebbar <gururajakr@sanyo.co.in> +Date: Tue May 20 02:16:36 2008 -0700 + + common/usb.c: fix incorrect escape sequence + + Signed off by: Gururaja Hebbar <gururajakr@sanyo.co.in> + +commit 4ce1e23b5e12283579828b3d23e8fd6e1328a7aa +Author: York Sun <yorksun@freescale.com> +Date: Thu May 15 15:26:27 2008 -0500 + + Fix 8313ERDB board configuration + + Change LCRR clock ratio from 2 to 4 to commodate VSC7385. + Correct TSEC1 vs TSEC2 assignment. + Define ETHADDR and ETH1ADDR always. + + Signed-off-by: York Sun <yorksun@freescale.com> + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit 2c289e320dcfb3760e99cf1d765cb067194a1202 +Author: Jon Loeliger <jdl@freescale.com> +Date: Mon May 19 09:47:25 2008 -0500 + + mpc86xx: Removed unused and unconfigured memory test code. + + Besides, other common code exists. + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 180a90abdae72587c0f679edf8991455e559440d +Author: Wolfgang Denk <wd@denx.de> +Date: Mon May 19 12:47:11 2008 +0200 + + Release v1.3.3 + + Update CHANGELOG for release. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 16bedc661de0dae767b1377d8413373a3fbcfa79 Author: Stefan Roese <sr@denx.de> Date: Mon May 19 07:14:38 2008 +0200 @@ -88,6 +3801,17 @@ Date: Wed May 14 23:34:53 2008 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit 0c11935cd62ca1f65eeb228ff4c848440d4553bf +Author: Gary Jennejohn <garyj@denx.de> +Date: Wed May 14 13:39:22 2008 +0200 + + ppc4xx: QUAD100HD: Allow the environment to be put into flash. + + After moving TEXT_BASE the value for CFG_ENV_ADDR was incorrect. Also + use a redundant environment. + + Signed-off-by: Gary Jennejohn <garyj@denx.de> + commit cda2a4a9961fd4341b7db305cb22fc05957e8b77 Author: Wolfgang Denk <wd@denx.de> Date: Wed May 14 13:55:30 2008 +0200 @@ -166,6 +3890,19 @@ Date: Tue May 13 23:15:52 2008 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit 54694a91428f6c3280fe1ee0923488a1e7e8dbc4 +Author: Stelian Pop <stelian@popies.net> +Date: Tue May 13 17:31:24 2008 +0200 + + Cleanup nand_info[] declaration. + + The nand_info array is declared as extern in several .c files. + Those days, nand.h contains a reference to the array, so there is + no need to declare it elsewhere. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + commit 70fab1908fc1734a403711eaabbef546bc4b77dc Author: Stefan Roese <sr@denx.de> Date: Tue May 13 20:22:01 2008 +0200 @@ -221,6 +3958,308 @@ Date: Sun May 11 23:13:57 2008 +0200 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +commit 67e3beb52c320b0a31cf030716c99392cde2d532 +Author: Stelian Pop <stelian@popies.net> +Date: Fri May 9 21:46:51 2008 +0200 + + AT91: Cleanup unused config header file definitions. + + CONFIG_ENV_OVERWRITE is commented out in the config header files, + so let's cleanup the files by removing the whole definition. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 19883aede2ac0a522493bfb2b35a7dbb200071b1 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 14:52:34 2008 +0200 + + Support AT91CAP9 revC CPUs + + The AT91CAP9 revC CPU has a few differences over the previous, + revB CPU which was distributed in small quantities only (revA was + an internal Atmel product only). + + The revC silicon needs a special initialisation sequence to + switch from the internal (imprecise) RC oscillator to the + external 32k clock. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 098b7b4b441b12c2a64dd517930f43c793542759 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 14:52:33 2008 +0200 + + Use custom logo for Atmel boards + + This patch adds a custom vendor logo for the Atmel AT91 boards. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 761c70b80cdd3bead40146b96a8e713d6ae01632 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 14:52:32 2008 +0200 + + AT91SAM9RLEK: hook up the ATMEL LCD driver + + This patch makes the necessary adaptations (PIO configurations and + defines in config header file) to hook up the Atmel LCD driver to the + AT91SAM9RLEK board. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 56a2479cd7fecabdd91348a775b2801dd2e65c7f +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 14:52:31 2008 +0200 + + AT91SAM9263EK: hook up the ATMEL LCD driver + + This patch makes the necessary adaptations (PIO configurations and + defines in config header file) to hook up the Atmel LCD driver to the + AT91SAM9263EK board. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 820f2a958325061a446115f3035e48e4726b3390 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 14:52:30 2008 +0200 + + AT91SAM9261EK: hook up the ATMEL LCD driver + + This patch makes the necessary adaptations (PIO configurations and + defines in config header file) to hook up the Atmel LCD driver to the + AT91SAM9261EK board. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit c139b17d20c8371c1e0a8d7fb27c11050cf86304 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 14:52:29 2008 +0200 + + AT91CAP9ADK: hook up the ATMEL LCD driver + + This patch makes the necessary adaptations (PIO configurations and + defines in config header file) to hook up the Atmel LCD driver to the + AT91CAP9ADK board. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 39cf480484fcce5c04a590ee1c30be0c17b02c34 +Author: Stelian Pop <stelian@popies.net> +Date: Fri May 9 21:57:18 2008 +0200 + + Add ATMEL LCD driver + + This patch adds support for the ATMEL LCDC driver which is used on some + AT91 and AVR platforms. + + Is has been tested with the AT91CAP9ADK, AT91SAM9261EK, AT91SAM9263EK and + AT91SAM9RLEK boards. Adaptation for AVR32 should probably be easy. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 2118ebb44dc40f8117c94950fd95799a9ef821b2 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 18:52:25 2008 +0200 + + AT91SAM9RLEK support + + This patch adds support for the AT91SAM9RL chip and the AT91SAM9RLEK + board. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 8e429b3eee23927c1222679f6b6f53667b21595c +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 18:52:23 2008 +0200 + + AT91SAM9263EK support + + This patch adds support for the AT91SAM9263 chip and the AT91SAM9263EK + board. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit d99a8ff66d8ae87e5c87590ed2e4ead629540607 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:22 2008 +0200 + + AT91SAM9261EK support + + This patch adds support for the AT91SAM9261 chip and the AT91SAM9261EK + board. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 86c8c8a414988c50104a3b02c29f50af2be738c0 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:21 2008 +0200 + + AT91SAM9260EK: Fix dataflash offsets in CONFIG_BOOTCOMMAND + + This patch fixes the dataflash offsets used in CONFIG_BOOTCOMMAND + in order to cope with the changes in DataFlash partitionning scheme + (cset c3a60cb3). + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 96996ac25d5222611a8888968db6e53a6d3726da +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:20 2008 +0200 + + AT91SAM9260EK: Normalize BOOTARGS + + This patch adapts CONFIG_BOOTARGS to the chosen boot method (boot from + DataFlash or from NAND), and gives to Linux a fully specified mtdparts + variable. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 79f0cb6e9c54d31a1d9e3f5e226a9bebc3c3a47a +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:19 2008 +0200 + + AT91SAM9260EK: Normalize SPI timings + + This patch changes the SPI timings to closely match the ones + used by the Linux kernel and the Atmel's own bootstrap project. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit c1212b2f5c5ed440bf8e9ebc8e4fd7488858b935 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:18 2008 +0200 + + AT91SAM9260EK: Handle 8 or 16 bit NAND + + The Atmel boards can handle 8 or 16 bit NAND memories. This patch + makes the support configurable in the board config header file + (CFG_NAND_DBW_8 or CFG_NAND_DBW_16). + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit ab52640fc01624e208424e527af0b7b3a5a65a12 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:17 2008 +0200 + + AT91CAP9ADK: Fix dataflash offsets in CONFIG_BOOTCOMMAND + + This patch fixes the dataflash offsets used in CONFIG_BOOTCOMMAND + in order to cope with the changes in DataFlash partitionning scheme + (cset c3a60cb3). + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 3267508ec4c9e74c39ee41c9ae6951ad185fe270 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:16 2008 +0200 + + AT91CAP9ADK: Normalize BOOTARGS + + This patch adapts CONFIG_BOOTARGS to the chosen boot method (boot from + DataFlash or from NAND), and gives to Linux a fully specified mtdparts + variable. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 93da48b910511911ce110656e17ed733c8ac4c45 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:15 2008 +0200 + + AT91CAP9ADK: Normalize SPI timings + + This patch changes the SPI timings to closely match the ones + used by the Linux kernel and the Atmel's own bootstrap project. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 1c90df3e148ce0a3e2c86c63b38b19d47772f2a0 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:14 2008 +0200 + + AT91CAP9ADK: Handle 8 or 16 bit NAND + + The Atmel boards can handle 8 or 16 bit NAND memories. This patch + makes the support configurable in the board config header file + (CFG_NAND_DBW_8 or CFG_NAND_DBW_16). + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 11b162bae058e96c7929e358d4adff2bee6c2cc4 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:13 2008 +0200 + + Use a common u-boot.lds file across all AT91CAP9/AT91SAM9 platforms + + All the AT91CAP9/AT91SAM9 boards have the same linker script. The patch + below avoids the duplication of u-boot.lds by putting the file in the + cpu directory instead of the board one. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit d48abea4b89adaf5e45ea75b5e38c0d8de179ece +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:12 2008 +0200 + + Add proper copyright notices in Atmel boards Makefiles + + The Makefiles for the AT91CAP9/AT91SAM9 boards have an incomplete + copyright notice. This patch adds the missing pieces. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit e817a042cef6164bf26fee86f90326f2ec9e6745 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:11 2008 +0200 + + Add copyright information in Atmel boards partition.c + + When Ulf did the dataflash.c cleanup, he didn't add his copyright on + the new created files. This patch fixes the problem. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 4f6c810106f4f76d83cfc57d98f4540cd45f9a19 +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 20:52:10 2008 +0200 + + Update origin and copyright information in arch-at91sam9 header files + + When doing the AT91CAP9/AT91SAM9 port, a number of header files were + copied from the Linux kernel sources. This patch explicitly specifies + this origin for all the copied headers, and for those missing copyright + information, adds it. + + Additionaly, the header file 'at91sam926x_mc.h' has been superceeded + in the latest kernel sources by 'at91sam9_smc.h'. + + The copyright information has been confirmed by the AT91 Linux kernel + maintainer, Andrew Victor <avictor.za@gmail.com>. + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + commit 79dd1712689d6a5031d7cbff54957049680751c7 Author: Markus Klotzbücher <mk@denx.de> Date: Thu May 8 16:00:55 2008 +0200 @@ -556,6 +4595,32 @@ Date: Fri May 9 10:16:13 2008 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit 567fb852178dbf59529d7301620a3f3732a4b02d +Author: Stelian Pop <stelian@popies.net> +Date: Thu May 8 22:52:09 2008 +0200 + + Fix @ -> <at> substitution + + When applying the AT91CAP9 patches upstream, something transformed + the '@' character into the ' <at> ' sequence. + + The patch below restores the original form in all the places where + it has been modified (the AT91CAP9 files, the AT91SAM9260 files which + were copied from AT91CAP9, and a couple of other files where the + ' <at> ' sequence was present). + + Signed-off-by: Stelian Pop <stelian@popies.net> + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 73ccb3410a0785593cda7aee455dfc51f790e281 +Author: Gary Jennejohn <gary.jennejohn@freenet.de> +Date: Mon Apr 28 14:04:32 2008 +0200 + + ppc4xx: Add the Harris QUAD100HD AMCC 405EP-based board + + Signed-off-by: Gary Jennejohn <garyj@denx.de> + Signed-off-by: Stefan Roese <sr@denx.de> + commit ef2642625cbfb1c3695e3478d08ae515052a4950 Author: Stefan Roese <sr@denx.de> Date: Thu May 8 11:10:46 2008 +0200 @@ -424,6 +424,10 @@ N: Paolo Scaffardi E: arsenio@tin.it D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more +N: Andre Schwarz +E: andre.schwarz@matrix-vision.de +D: Support for Matrix Vision boards (MVBLM7) + N: Robert Schwebel E: r.schwebel@pengutronix.de D: Support for csb226, logodl and innokom boards (PXA2xx) @@ -533,3 +537,8 @@ N: Timo Tuunainen E: timo.tuunainen@sysart.fi D: Support for Artila M-501 starter kit W: http://www.sysart.fi/ + +N: Philip Balister +E: philip@opensdr.com +D: Port to Lyrtech SFFSDR development board. +W: www.opensdr.com diff --git a/MAINTAINERS b/MAINTAINERS index ac7572cfc1..a3d70b1d31 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -204,6 +204,10 @@ Klaus Heydeck <heydeck@kieback-peter.de> KUP4K MPC855 KUP4X MPC859 +Gary Jennejohn <garyj@denx.de> + + quad100hd PPC405EP + Murray Jensen <Murray.Jensen@csiro.au> cogent_mpc8xx MPC8xx @@ -367,6 +371,10 @@ Peter De Schrijver <p2@mind.be> ML2 PPC4xx +Andre Schwarz <andre.schwarz@matrix-vision.de> + + mvblm7 MPC8343 + Timur Tabi <timur@freescale.com> MPC8349E-mITX MPC8349 @@ -538,6 +546,9 @@ Stelian Pop <stelian.pop@leadtechdesign.com> at91cap9adk ARM926EJS (AT91CAP9 SoC) at91sam9260ek ARM926EJS (AT91SAM9260 SoC) + at91sam9261ek ARM926EJS (AT91SAM9261 SoC) + at91sam9263ek ARM926EJS (AT91SAM9263 SoC) + at91sam9rlek ARM926EJS (AT91SAM9RL SoC) Stefan Roese <sr@denx.de> @@ -695,6 +706,7 @@ Haavard Skinnemoen <hskinnemoen@atmel.com> ATSTK1002 AT32AP7000 ATSTK1003 AT32AP7001 ATSTK1004 AT32AP7002 + ATSTK1006 AT32AP7000 ATNGW100 AT32AP7000 ######################################################################### @@ -710,6 +722,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org> MS7722SE SH7722 R7780MP SH7780 R2DPlus SH7751R + SH7763RDP SH7763 Mark Jonas <mark.jonas@de.bosch.com> @@ -219,6 +219,7 @@ LIST_4xx=" \ PMC405 \ PMC440 \ PPChameleonEVB \ + quad100hd \ rainier \ sbc405 \ sc3 \ @@ -330,6 +331,7 @@ LIST_83xx=" \ MPC8360ERDK_66 \ MPC837XEMDS \ MPC837XERDB \ + MVBLM7 \ sbc8349 \ TQM834x \ " @@ -359,6 +361,7 @@ LIST_85xx=" \ stxssa \ TQM8540 \ TQM8541 \ + TQM8548 \ TQM8555 \ TQM8560 \ " @@ -461,6 +464,9 @@ LIST_ARM9=" \ at91cap9adk \ at91rm9200dk \ at91sam9260ek \ + at91sam9261ek \ + at91sam9263ek \ + at91sam9rlek \ cmc_pu2 \ ap920t \ ap922_XA10 \ @@ -497,6 +503,7 @@ LIST_ARM9=" \ voiceblue \ davinci_dvevm \ davinci_schmoogie \ + davinci_sffsdr \ davinci_sonata \ " @@ -521,6 +528,24 @@ LIST_ARM11=" \ " ######################################################################### +## AT91 Systems +######################################################################### + +LIST_at91=" \ + at91cap9adk \ + at91rm9200dk \ + at91sam9260ek \ + at91sam9261ek \ + at91sam9263ek \ + at91sam9rlek \ + cmc_pu2 \ + csb637 \ + kb9202 \ + mp2usb \ + m501sk \ +" + +######################################################################### ## Xscale Systems ######################################################################### @@ -697,6 +722,7 @@ LIST_avr32=" \ atstk1002 \ atstk1003 \ atstk1004 \ + atstk1006 \ atngw100 \ " @@ -723,9 +749,10 @@ LIST_sh3=" \ LIST_sh4=" \ ms7750se \ ms7722se \ - Migo-R \ + MigoR \ r7780mp \ r2dplus \ + sh7763rdp \ " LIST_sh=" \ @@ -765,7 +792,7 @@ build_target() { for arg in $@ do case "$arg" in - arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa \ + arm|SA|ARM7|ARM9|ARM10|ARM11|at91|ixp|pxa \ |avr32 \ |blackfin \ |coldfire \ @@ -220,10 +220,12 @@ LIBS += drivers/hwmon/libhwmon.a LIBS += drivers/i2c/libi2c.a LIBS += drivers/input/libinput.a LIBS += drivers/misc/libmisc.a +LIBS += drivers/mmc/libmmc.a LIBS += drivers/mtd/libmtd.a LIBS += drivers/mtd/nand/libnand.a LIBS += drivers/mtd/nand_legacy/libnand_legacy.a LIBS += drivers/mtd/onenand/libonenand.a +LIBS += drivers/mtd/spi/libspi_flash.a LIBS += drivers/net/libnet.a LIBS += drivers/net/sk98lin/libsk98lin.a LIBS += drivers/pci/libpci.a @@ -386,10 +388,12 @@ TAG_SUBDIRS += drivers/hwmon TAG_SUBDIRS += drivers/i2c TAG_SUBDIRS += drivers/input TAG_SUBDIRS += drivers/misc +TAG_SUBDIRS += drivers/mmc TAG_SUBDIRS += drivers/mtd TAG_SUBDIRS += drivers/mtd/nand TAG_SUBDIRS += drivers/mtd/nand_legacy TAG_SUBDIRS += drivers/mtd/onenand +TAG_SUBDIRS += drivers/mtd/spi TAG_SUBDIRS += drivers/net TAG_SUBDIRS += drivers/net/sk98lin TAG_SUBDIRS += drivers/pci @@ -484,7 +488,7 @@ PATI_config: unconfig ######################################################################### aev_config: unconfig - @$(MKCONFIG) -a aev ppc mpc5xxx tqm5200 + @$(MKCONFIG) -a aev ppc mpc5xxx tqm5200 tqc BC3450_config: unconfig @$(MKCONFIG) -a BC3450 ppc mpc5xxx bc3450 @@ -638,13 +642,13 @@ PM520_ROMBOOT_DDR_config: unconfig @$(MKCONFIG) -a PM520 ppc mpc5xxx pm520 smmaco4_config: unconfig - @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 + @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 tqc cm5200_config: unconfig @$(MKCONFIG) -a cm5200 ppc mpc5xxx cm5200 spieval_config: unconfig - @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 + @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 tqc TB5200_B_config \ TB5200_config: unconfig @@ -653,7 +657,7 @@ TB5200_config: unconfig { echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \ $(XECHO) "... with MPC5200B processor" ; \ } - @$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200 + @$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200 tqc MINI5200_config \ EVAL5200_config \ @@ -702,7 +706,7 @@ TQM5200_B_HIGHBOOT_config \ TQM5200_config \ TQM5200_STK100_config: unconfig @mkdir -p $(obj)include - @mkdir -p $(obj)board/tqm5200 + @mkdir -p $(obj)board/tqc/tqm5200 @[ -z "$(findstring cam5200,$@)" ] || \ { echo "#define CONFIG_CAM5200" >>$(obj)include/config.h ; \ echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \ @@ -735,7 +739,7 @@ TQM5200_STK100_config: unconfig @[ -z "$(findstring HIGHBOOT,$@)" ] || \ { echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \ } - @$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 + @$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 tqc uc101_config: unconfig @$(MKCONFIG) uc101 ppc mpc5xxx uc101 motionpro_config: unconfig @@ -828,7 +832,7 @@ hermes_config : unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx hermes HMI10_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx + @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc IAD210_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx IAD210 siemens @@ -1057,7 +1061,7 @@ RRvision_LCD_config: unconfig @$(MKCONFIG) -a RRvision ppc mpc8xx RRvision SM850_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx + @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc spc1920_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920 @@ -1107,13 +1111,13 @@ virtlab2_config: unconfig echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \ $(XECHO) "... with LCD display" ; \ } - @$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx + @$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx tqc TTTech_config: unconfig @mkdir -p $(obj)include @echo "#define CONFIG_LCD" >$(obj)include/config.h @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h - @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx + @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc uc100_config : unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx uc100 @@ -1128,7 +1132,7 @@ wtk_config: unconfig @mkdir -p $(obj)include @echo "#define CONFIG_LCD" >$(obj)include/config.h @echo "#define CONFIG_SHARP_LQ065T9DR51U" >>$(obj)include/config.h - @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx + @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc ######################################################################### ## PPC4xx Systems @@ -1391,6 +1395,9 @@ PPChameleonEVB_HI_33_config: unconfig } @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave +quad100hd_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd + sbc405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405 @@ -1779,10 +1786,10 @@ TQM8265_AA_config: unconfig echo "#undef CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \ $(XECHO) "... without 60x Bus Mode" ; \ fi - @$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260 + @$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260 tqc TQM8272_config: unconfig - @$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272 + @$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272 tqc VoVPN-GW_66MHz_config \ VoVPN-GW_100MHz_config: unconfig @@ -2102,11 +2109,14 @@ MPC837XEMDS_HOST_config: unconfig MPC837XERDB_config: unconfig @$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale +MVBLM7_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 + sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 TQM834x_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x + @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc ######################################################################### @@ -2225,6 +2235,7 @@ stxssa_4M_config: unconfig TQM8540_config \ TQM8541_config \ +TQM8548_config \ TQM8555_config \ TQM8560_config: unconfig @mkdir -p $(obj)include @@ -2233,9 +2244,8 @@ TQM8560_config: unconfig echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \ - echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h - @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx + echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; + @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc ######################################################################### ## MPC86xx Systems @@ -2335,6 +2345,15 @@ shannon_config : unconfig at91rm9200dk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200 +at91sam9261ek_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9 + +at91sam9263ek_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9 + +at91sam9rlek_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9 + cmc_pu2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200 @@ -2411,6 +2430,9 @@ davinci_dvevm_config : unconfig davinci_schmoogie_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci +davinci_sffsdr_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs sffsdr davinci davinci + davinci_sonata_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci @@ -2879,6 +2901,9 @@ atstk1003_config : unconfig atstk1004_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x +atstk1006_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x + atngw100_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x @@ -2890,40 +2915,48 @@ atngw100_config : unconfig ## sh3 (Renesas SuperH) ######################################################################### mpr2_config: unconfig - @ >include/config.h - @echo "#define CONFIG_MPR2 1" >> include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_MPR2 1" > $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh3 mpr2 ms7720se_config: unconfig - @echo "#define CONFIG_MS7720SE 1" > include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se ######################################################################### ## sh4 (Renesas SuperH) ######################################################################### ms7750se_config: unconfig + @mkdir -p $(obj)include @echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh4 ms7750se ms7722se_config : unconfig + @mkdir -p $(obj)include @echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se MigoR_config : unconfig - @ >include/config.h - @echo "#define CONFIG_MIGO_R 1" >> include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h @./mkconfig -a $(@:_config=) sh sh4 MigoR r7780mp_config: unconfig - @ >include/config.h - @echo "#define CONFIG_R7780MP 1" >> include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h @./mkconfig -a $(@:_config=) sh sh4 r7780mp r2dplus_config : unconfig - @ >include/config.h - @echo "#define CONFIG_R2DPLUS 1" >> include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h @./mkconfig -a $(@:_config=) sh sh4 r2dplus +sh7763rdp_config : unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h + @./mkconfig -a $(@:_config=) sh sh4 sh7763rdp + #======================================================================== # SPARC #======================================================================== @@ -74,7 +74,7 @@ git://www.denx.de/git/u-boot.git ; you can browse it online at http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary The "snapshot" links on this page allow you to download tarballs of -any version you might be interested in. Ofifcial releases are also +any version you might be interested in. Official releases are also available for FTP download from the ftp://ftp.denx.de/pub/u-boot/ directory. @@ -94,7 +94,7 @@ Where we come from: * Provide extended interface to Linux boot loader * S-Record download * network boot - * PCMCIA / CompactFLash / ATA disk / SCSI ... boot + * PCMCIA / CompactFlash / ATA disk / SCSI ... boot - create ARMBoot project (http://sourceforge.net/projects/armboot) - add other CPU families (starting with ARM) - create U-Boot project (http://sourceforge.net/projects/u-boot) @@ -230,7 +230,7 @@ Example: For a TQM823L module type: cd u-boot make TQM823L_config -For the Cogent platform, you need to specify the cpu type as well; +For the Cogent platform, you need to specify the CPU type as well; e.g. "make cogent_mpc8xx_config". And also configure the cogent directory according to the instructions in cogent/README. @@ -278,7 +278,7 @@ The following options need to be configured: - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined) Define one or more of CONFIG_LCD_HEARTBEAT - update a character position on - the lcd display every second with + the LCD display every second with a "rotator" |\-/|\-/ - Board flavour: (if CONFIG_MPC8260ADS is defined) @@ -293,7 +293,7 @@ The following options need to be configured: Define exactly one of CONFIG_MPC8240, CONFIG_MPC8245 -- 8xx CPU Options: (if using an MPC8xx cpu) +- 8xx CPU Options: (if using an MPC8xx CPU) CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if get_gclk_freq() cannot work e.g. if there is no 32KHz @@ -346,11 +346,11 @@ The following options need to be configured: CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] - When transfering memsize parameter to linux, some versions + When transferring memsize parameter to linux, some versions expect it to be in bytes, others in MB. Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. - CONFIG_OF_LIBFDT / CONFIG_OF_FLAT_TREE + CONFIG_OF_LIBFDT New kernel versions are expecting firmware settings to be passed using flattened device trees (based on open firmware @@ -361,19 +361,13 @@ The following options need to be configured: * Adds the "fdt" command * The bootm command automatically updates the fdt - CONFIG_OF_FLAT_TREE - * Deprecated, see CONFIG_OF_LIBFDT - * Original ft_build.c-based support - * Automatically modifies the dft as part of the bootm command - * The environment variable "disable_of", when set, - disables this functionality. - OF_CPU - The proper name of the cpus node. OF_SOC - The proper name of the soc node. OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device - boards with QUICC Engines require OF_QE to set UCC mac addresses + boards with QUICC Engines require OF_QE to set UCC MAC + addresses CONFIG_OF_BOARD_SETUP @@ -382,7 +376,7 @@ The following options need to be configured: CONFIG_OF_BOOT_CPU - This define fills in the correct boot cpu in the boot + This define fills in the correct boot CPU in the boot param header, the default value is zero if undefined. - Serial Ports: @@ -452,7 +446,7 @@ The following options need to be configured: linux_logo.h for logo. Requires CONFIG_VIDEO_LOGO CONFIG_CONSOLE_EXTRA_INFO - addional board info beside + additional board info beside the logo When CONFIG_CFB_CONSOLE is defined, video console is @@ -522,7 +516,7 @@ The following options need to be configured: The value of these goes into the environment as "ramboot" and "nfsboot" respectively, and can be used as a convenience, when switching between booting from - ram and nfs. + RAM and NFS. - Pre-Boot Commands: CONFIG_PREBOOT @@ -742,11 +736,11 @@ The following options need to be configured: Support for Intel 8254x gigabit chips. CONFIG_E1000_FALLBACK_MAC - default MAC for empty eeprom after production. + default MAC for empty EEPROM after production. CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. - Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom + Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM write routine for first time initialisation. CONFIG_TULIP @@ -786,6 +780,21 @@ The following options need to be configured: Define this to use i/o functions instead of macros (some hardware wont work with macros) + CONFIG_DRIVER_SMC911X + Support for SMSC's LAN911x and LAN921x chips + + CONFIG_DRIVER_SMC911X_BASE + Define this to hold the physical address + of the device (I/O space) + + CONFIG_DRIVER_SMC911X_32_BIT + Define this if data bus is 32 bits + + CONFIG_DRIVER_SMC911X_16_BIT + Define this if data bus is 16 bits. If your processor + automatically converts one 32 bit word to two 16 bit + words you may also try CONFIG_DRIVER_SMC911X_32_BIT. + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define @@ -810,7 +819,7 @@ The following options need to be configured: Define the below if you wish to use the USB console. Once firmware is rebuilt from a serial console issue the command "setenv stdin usbtty; setenv stdout usbtty" and - attach your usb cable. The Unix command "dmesg" should print + attach your USB cable. The Unix command "dmesg" should print it has found a new device. The environment variable usbtty can be set to gserial or cdc_acm to enable your device to appear to a USB host as a Linux gserial device or a @@ -924,7 +933,7 @@ The following options need to be configured: assumed. For the CT69000 and SMI_LYNXEM drivers, videomode is - selected via environment 'videomode'. Two diferent ways + selected via environment 'videomode'. Two different ways are possible: - "videomode=num" 'num' is a standard LiLo mode numbers. Following standard modes are supported (* is default): @@ -961,6 +970,10 @@ The following options need to be configured: display); also select one of the supported displays by defining one of these: + CONFIG_ATMEL_LCD: + + HITACHI TX09D70VM1CCA, 3.5", 240x320. + CONFIG_NEC_NL6448AC33: NEC NL6448AC33-18. Active, color, single scan. @@ -1043,7 +1056,7 @@ The following options need to be configured: CONFIG_PHY_GIGE If this option is set, support for speed/duplex - detection of Gigabit PHY is included. + detection of gigabit PHY is included. CONFIG_PHY_RESET_DELAY @@ -1062,21 +1075,21 @@ The following options need to be configured: CONFIG_ETH2ADDR CONFIG_ETH3ADDR - Define a default value for ethernet address to use - for the respective ethernet interface, in case this + Define a default value for Ethernet address to use + for the respective Ethernet interface, in case this is not determined automatically. - IP address: CONFIG_IPADDR Define a default value for the IP address to use for - the default ethernet interface, in case this is not + the default Ethernet interface, in case this is not determined through e.g. bootp. - Server IP address: CONFIG_SERVERIP - Defines a default value for theIP address of a TFTP + Defines a default value for the IP address of a TFTP server to contact when using the "tftboot" command. - Multicast TFTP Mode: @@ -1084,7 +1097,7 @@ The following options need to be configured: Defines whether you want to support multicast TFTP as per rfc-2090; for example to work with atftp. Lets lots of targets - tftp down the same boot image concurrently. Note: the ethernet + tftp down the same boot image concurrently. Note: the Ethernet driver in use must provide a function: mcast() to join/leave a multicast group. @@ -1172,7 +1185,7 @@ The following options need to be configured: A printf format string which contains the ascii name of the port. Normally is set to "eth%d" which sets - eth0 for the first ethernet, eth1 for the second etc. + eth0 for the first Ethernet, eth1 for the second etc. CONFIG_CDP_CAPABILITIES @@ -1221,7 +1234,7 @@ The following options need to be configured: These enable I2C serial bus commands. Defining either of (but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will - include the appropriate I2C driver for the selected cpu. + include the appropriate I2C driver for the selected CPU. This will allow you to use i2c commands at the u-boot command line (as long as you set CONFIG_CMD_I2C in @@ -1246,10 +1259,10 @@ The following options need to be configured: In both cases you will need to define CFG_I2C_SPEED to be the frequency (in Hz) at which you wish your i2c bus to run and CFG_I2C_SLAVE to be the address of this node (ie - the cpu's i2c node address). + the CPU's i2c node address). Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c) - sets the cpu up as a master node and so its address should + sets the CPU up as a master node and so its address should therefore be cleared to 0 (See, eg, MPC823e User's Manual p.16-473). So, set CFG_I2C_SLAVE to 0. @@ -1468,17 +1481,17 @@ The following options need to be configured: Maximum time to wait for the INIT_B line to deassert after PROB_B has been deasserted during a Virtex II FPGA configuration sequence. The default time is 500 - mS. + ms. CFG_FPGA_WAIT_BUSY Maximum time to wait for BUSY to deassert during - Virtex II FPGA configuration. The default is 5 mS. + Virtex II FPGA configuration. The default is 5 ms. CFG_FPGA_WAIT_CONFIG Time to wait after FPGA configuration. The default is - 200 mS. + 200 ms. - Configuration Management: CONFIG_IDENT_STRING @@ -1495,7 +1508,7 @@ The following options need to be configured: protects these variables from casual modification by the user. Once set, these variables are read-only, and write or delete attempts are rejected. You can - change this behviour: + change this behaviour: If CONFIG_ENV_OVERWRITE is #defined in your config file, the write protection for vendor parameters is @@ -1504,7 +1517,7 @@ The following options need to be configured: Alternatively, if you #define _both_ CONFIG_ETHADDR _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default - ethernet address is installed in the environment, + Ethernet address is installed in the environment, which can be changed exactly ONCE by the user. [The serial# is unaffected by this, i. e. it remains read-only.] @@ -1548,7 +1561,7 @@ The following options need to be configured: Define this variable to stop the system in case of a fatal error, so that you have to reset it manually. This is probably NOT a good idea for an embedded - system where you want to system to reboot + system where you want the system to reboot automatically as fast as possible, but it may be useful during development since you can try to debug the conditions that lead to the situation. @@ -1615,7 +1628,7 @@ The following options need to be configured: - Commandline Editing and History: CONFIG_CMDLINE_EDITING - Enable editiong and History functions for interactive + Enable editing and History functions for interactive commandline input operations - Default Environment: @@ -1656,7 +1669,7 @@ The following options need to be configured: Adding this option adds support for Xilinx SystemACE chips attached via some sort of local bus. The address - of the chip must alsh be defined in the + of the chip must also be defined in the CFG_SYSTEMACE_BASE macro. For example: #define CONFIG_SYSTEMACE @@ -1722,7 +1735,7 @@ Legacy uImage format: -12 common/image.c Ramdisk data has bad checksum 11 common/image.c Ramdisk data has correct checksum 12 common/image.c Ramdisk verification complete, start loading - -13 common/image.c Wrong Image Type (not PPC Linux Ramdisk) + -13 common/image.c Wrong Image Type (not PPC Linux ramdisk) 13 common/image.c Start multifile image verification 14 common/image.c No initial ramdisk, no multifile, continue. @@ -1782,13 +1795,13 @@ Legacy uImage format: -60 common/env_common.c Environment has a bad CRC, using default - 64 net/eth.c starting with Ethernetconfiguration. + 64 net/eth.c starting with Ethernet configuration. -64 net/eth.c no Ethernet found. 65 net/eth.c Ethernet found. -80 common/cmd_net.c usage wrong 80 common/cmd_net.c before calling NetLoop() - -81 common/cmd_net.c some error in NetLoop() occured + -81 common/cmd_net.c some error in NetLoop() occurred 81 common/cmd_net.c NetLoop() back without error -82 common/cmd_net.c size == 0 (File with size 0 loaded) 82 common/cmd_net.c trying automatic boot @@ -1811,8 +1824,8 @@ FIT uImage format: 105 common/cmd_bootm.c Kernel subimage hash verification OK -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture 106 common/cmd_bootm.c Architecture check OK - -106 common/cmd_bootm.c Kernel subimage has wrong typea - 107 common/cmd_bootm.c Kernel subimge type OK + -106 common/cmd_bootm.c Kernel subimage has wrong type + 107 common/cmd_bootm.c Kernel subimage type OK -107 common/cmd_bootm.c Can't get kernel subimage data/size 108 common/cmd_bootm.c Got kernel subimage data/size -108 common/cmd_bootm.c Wrong image type (not legacy, FIT) @@ -1825,7 +1838,7 @@ FIT uImage format: 120 common/image.c Start initial ramdisk verification -120 common/image.c Ramdisk FIT image has incorrect format 121 common/image.c Ramdisk FIT image has correct format - 122 common/image.c No Ramdisk subimage unit name, using configuration + 122 common/image.c No ramdisk subimage unit name, using configuration -122 common/image.c Can't get configuration for ramdisk subimage 123 common/image.c Ramdisk unit name specified -124 common/image.c Can't get ramdisk subimage node offset @@ -1839,13 +1852,13 @@ FIT uImage format: 129 common/image.c Can't get ramdisk load address -129 common/image.c Got ramdisk load address - -130 common/cmd_doc.c Icorrect FIT image format + -130 common/cmd_doc.c Incorrect FIT image format 131 common/cmd_doc.c FIT image format OK - -140 common/cmd_ide.c Icorrect FIT image format + -140 common/cmd_ide.c Incorrect FIT image format 141 common/cmd_ide.c FIT image format OK - -150 common/cmd_nand.c Icorrect FIT image format + -150 common/cmd_nand.c Incorrect FIT image format 151 common/cmd_nand.c FIT image format OK @@ -1854,7 +1867,7 @@ Modem Support: [so far only for SMDK2400 and TRAB boards] -- Modem support endable: +- Modem support enable: CONFIG_MODEM_SUPPORT - RTS/CTS Flow control enable: @@ -1870,11 +1883,11 @@ Modem Support: There are common interrupt_init() and timer_interrupt() for all PPC archs. interrupt_init() calls interrupt_init_cpu() - for cpu specific initialization. interrupt_init_cpu() + for CPU specific initialization. interrupt_init_cpu() should set decrementer_count to appropriate value. If - cpu resets decrementer automatically after interrupt + CPU resets decrementer automatically after interrupt (ppc4xx) it should set decrementer_count to zero. - timer_interrupt() calls timer_interrupt_cpu() for cpu + timer_interrupt() calls timer_interrupt_cpu() for CPU specific handling. If board has watchdog / status_led / other_activity_monitor it works automatically from general timer_interrupt(). @@ -1884,7 +1897,7 @@ Modem Support: In the target system modem support is enabled when a specific key (key combination) is pressed during power-on. Otherwise U-Boot will boot normally - (autoboot). The key_pressed() fuction is called from + (autoboot). The key_pressed() function is called from board_init(). Currently key_pressed() is a dummy function, returning 1 and thus enabling modem initialization. @@ -1892,7 +1905,7 @@ Modem Support: If there are no modem init strings in the environment, U-Boot proceed to autoboot; the previous output (banner, info printfs) will be - supressed, though. + suppressed, though. See also: doc/README.Modem @@ -1948,7 +1961,7 @@ Configuration Settings: - CFG_MEM_TOP_HIDE (PPC only): If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top - (end) of ram and won't get "touched" at all by U-Boot. By + (end) of RAM and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux @@ -2043,8 +2056,8 @@ Configuration Settings: The two-step approach is usually more reliable, since you can check if the download worked before you erase - the flash, but in some situations (when sytem RAM is - too limited to allow for a tempory copy of the + the flash, but in some situations (when system RAM is + too limited to allow for a temporary copy of the downloaded image) this option may be very useful. - CFG_FLASH_CFI: @@ -2074,11 +2087,11 @@ Configuration Settings: column displays, 15 (3..1) for 40 column displays. - CFG_RX_ETH_BUFFER: - Defines the number of ethernet receive buffers. On some - ethernet controllers it is recommended to set this value + Defines the number of Ethernet receive buffers. On some + Ethernet controllers it is recommended to set this value to 8 or even higher (EEPRO100 or 405 EMAC), since all buffers can be full shortly after enabling the interface - on high ethernet traffic. + on high Ethernet traffic. Defaults to 4 if not defined. The following definitions that deal with the placement and management @@ -2146,7 +2159,7 @@ following configurations: CFG_ENV_SIZE_REDUND These settings describe a second storage area used to hold - a redundand copy of the environment data, so that there is + a redundant copy of the environment data, so that there is a valid backup copy in case there is a power failure during a "saveenv" operation. @@ -2164,14 +2177,14 @@ accordingly! - CFG_ENV_ADDR: - CFG_ENV_SIZE: - These two #defines are used to determin the memory area you + These two #defines are used to determine the memory area you want to use for environment. It is assumed that this memory can just be read and written to, without any special provision. BE CAREFUL! The first access to the environment happens quite early in U-Boot initalization (when we try to get the setting of for the -console baudrate). You *MUST* have mappend your NVRAM area then, or +console baudrate). You *MUST* have mapped your NVRAM area then, or U-Boot will hang. Please note that even with NVRAM we still use a copy of the @@ -2320,14 +2333,14 @@ Low Level (hardware related) configuration options: CFG_ISA_IO_STRIDE - defines the spacing between fdc chipset registers + defines the spacing between FDC chipset registers (default value 1) CFG_ISA_IO_OFFSET defines the offset of register from address. It depends on which part of the data bus is connected to - the fdc chipset. (default value 0) + the FDC chipset. (default value 0) If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and CFG_FDC_DRIVE_NUMBER are undefined, they take their @@ -2523,7 +2536,7 @@ Low Level (hardware related) configuration options: Normally these variables MUST NOT be defined. The only exception is when U-Boot is loaded (to RAM) by some other boot loader or by a debugger which - performs these intializations itself. + performs these initializations itself. Building the Software: @@ -2558,7 +2571,7 @@ Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for instance, the TQM823L systems are available without (standard) or with LCD support. You can select such additional "features" - when chosing the configuration, i. e. + when choosing the configuration, i. e. make TQM823L_config - will configure for a plain TQM823L, i. e. no LCD support @@ -2761,7 +2774,7 @@ Some configuration options can be set using Environment Variables: for use by the bootm command. See also "bootm_size" environment variable. Address defined by "bootm_low" is also the base of the initial memory mapping for the Linux - kernel -- see the descripton of CFG_BOOTMAPSZ. + kernel -- see the description of CFG_BOOTMAPSZ. bootm_size - Memory range available for image processing in the bootm command can be restricted. This variable is given as @@ -2868,7 +2881,7 @@ Some configuration options can be set using Environment Variables: themselves. npe_ucode - see CONFIG_IXP4XX_NPE_EXT_UCOD - if set load address for the npe microcode + if set load address for the NPE microcode tftpsrcport - If this is set, the value is used for TFTP's UDP source port. @@ -2877,7 +2890,7 @@ Some configuration options can be set using Environment Variables: destination port instead of the Well Know Port 69. vlan - When set to a value < 4095 the traffic over - ethernet is encapsulated/received over 802.1q + Ethernet is encapsulated/received over 802.1q VLAN tagged frames. The following environment variables may be used and automatically @@ -2955,14 +2968,14 @@ General rules: executed anyway. (2) If you execute several variables with one call to run (i. e. - calling run with a list af variables as arguments), any failing + calling run with a list of variables as arguments), any failing command will cause "run" to terminate, i. e. the remaining variables are not executed. Note for Redundant Ethernet Interfaces: ======================================= -Some boards come with redundant ethernet interfaces; U-Boot supports +Some boards come with redundant Ethernet interfaces; U-Boot supports such configurations and is capable of automatic selection of a "working" interface when needed. MAC assignment works as follows: @@ -3303,7 +3316,7 @@ parameters. You can check and modify this variable using the Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000] ... -If you want to boot a Linux kernel with initial ram disk, you pass +If you want to boot a Linux kernel with initial RAM disk, you pass the memory addresses of both the kernel and the initrd image (PPBCOOT format!) to the "bootm" command: @@ -3613,13 +3626,13 @@ locked as (mis-) used as memory, etc. require any physical RAM backing up the cache. The cleverness is that the cache is being used as a temporary supply of necessary storage before the SDRAM controller is setup. It's - beyond the scope of this list to expain the details, but you + beyond the scope of this list to explain the details, but you can see how this works by studying the cache architecture and operation in the architecture and processor-specific manuals. OCM is On Chip Memory, which I believe the 405GP has 4K. It is another option for the system designer to use as an - initial stack/ram area prior to SDRAM being available. Either + initial stack/RAM area prior to SDRAM being available. Either option should work for you. Using CS 4 should be fine if your board designers haven't used it for something that would cause you grief during the initial boot! It is frequently not @@ -3644,7 +3657,7 @@ code for the initialization procedures: * Initialized global data (data segment) is read-only. Do not attempt to write it. -* Do not use any unitialized global data (or implicitely initialized +* Do not use any uninitialized global data (or implicitely initialized as zero data - BSS segment) at all - this is undefined, initiali- zation is performed later (when relocating to RAM). @@ -3756,7 +3769,7 @@ System Initialization: ---------------------- In the reset configuration, U-Boot starts at the reset entry point -(on most PowerPC systens at address 0x00000100). Because of the reset +(on most PowerPC systems at address 0x00000100). Because of the reset configuration for CS0# this is a mirror of the onboard Flash memory. To be able to re-map memory U-Boot then jumps to its link address. To be able to implement the initialization code in C, a (small!) diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c index dcfd83ed27..fad9c406d9 100644 --- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c +++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c @@ -39,7 +39,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { int size,i; diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c index 775db738e6..5f506314c5 100644 --- a/board/LEOX/elpt860/elpt860.c +++ b/board/LEOX/elpt860/elpt860.c @@ -35,7 +35,7 @@ ** ------ ** int board_early_init_f(void) ** int checkboard(void) -** long int initdram(int board_type) +** phys_size_t initdram(int board_type) ** called from 'board_init_f()' into 'common/board.c' ** ** void reset_phy(void) @@ -179,7 +179,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c index 3bbc09dd9c..e118563fc4 100644 --- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c +++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c @@ -81,7 +81,7 @@ int checkboard (void) return 0; } -long initdram (int board_type) +phys_size_t initdram (int board_type) { return articiaS_ram_init (); } diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index f04aaf9a6e..ecadaf2710 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -1728,7 +1728,7 @@ long int dram_size (long int *base, long int maxsize) /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index 176220232e..f36f3484ab 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -1737,7 +1737,7 @@ long int dram_size (long int *base, long int maxsize) /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; diff --git a/board/MigoR/Makefile b/board/MigoR/Makefile index 5a9d651afb..661b59d005 100644 --- a/board/MigoR/Makefile +++ b/board/MigoR/Makefile @@ -24,25 +24,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := migo_r.o +COBJS := migo_r.o SOBJS := lowlevel_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c index 49cb8ad24f..804635a4ae 100644 --- a/board/RPXClassic/RPXClassic.c +++ b/board/RPXClassic/RPXClassic.c @@ -165,7 +165,7 @@ void rpxclassic_init (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c index f37e07b923..bca31e4c8e 100644 --- a/board/RPXlite/RPXlite.c +++ b/board/RPXlite/RPXlite.c @@ -102,7 +102,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c index d3dc081219..d6fabf04ea 100644 --- a/board/RPXlite_dw/RPXlite_dw.c +++ b/board/RPXlite_dw/RPXlite_dw.c @@ -104,7 +104,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c index f46bb9e8e4..c0b772d727 100644 --- a/board/RRvision/RRvision.c +++ b/board/RRvision/RRvision.c @@ -110,7 +110,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c index 737d35d76c..c1eceaa2f4 100644 --- a/board/a3000/a3000.c +++ b/board/a3000/a3000.c @@ -38,7 +38,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/actux1/Makefile b/board/actux1/Makefile index 83611e7c03..b7cc6e11d5 100644 --- a/board/actux1/Makefile +++ b/board/actux1/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/actux2/Makefile b/board/actux2/Makefile index 37fd2622ab..5ef3bdaeab 100644 --- a/board/actux2/Makefile +++ b/board/actux2/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/actux3/Makefile b/board/actux3/Makefile index f6168c3e7f..2cd6d84a17 100644 --- a/board/actux3/Makefile +++ b/board/actux3/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/actux4/Makefile b/board/actux4/Makefile index 845af93fe6..b82fc62e9e 100644 --- a/board/actux4/Makefile +++ b/board/actux4/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/adder/Makefile b/board/adder/Makefile index b2ffd28833..6b3706daae 100644 --- a/board/adder/Makefile +++ b/board/adder/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/adder/adder.c b/board/adder/adder.c index 817c8649aa..e8a5737f58 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -65,7 +65,7 @@ static uint sdram_table[] = { 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 }; -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long int msize; volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index f4dacce285..52d0d3c58c 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -45,7 +45,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 2892665295..ef66663330 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -112,7 +112,7 @@ int board_early_init_f (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { u32 msize = 0; diff --git a/board/adsvix/Makefile b/board/adsvix/Makefile index 214c7dbe45..05601b48d1 100644 --- a/board/adsvix/Makefile +++ b/board/adsvix/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/alaska/Makefile b/board/alaska/Makefile index 27475ea4d7..5297e81435 100644 --- a/board/alaska/Makefile +++ b/board/alaska/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c index 9531703fc9..49a8f712ba 100644 --- a/board/alaska/alaska.c +++ b/board/alaska/alaska.c @@ -131,7 +131,7 @@ void setupBat (ulong size) mtspr (DBAT7U, batu); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong size; diff --git a/board/altera/dk1c20/Makefile b/board/altera/dk1c20/Makefile index 6af83890a8..60ac6e6b70 100644 --- a/board/altera/dk1c20/Makefile +++ b/board/altera/dk1c20/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c index d0eb9eacb8..46695bea92 100644 --- a/board/altera/dk1c20/dk1c20.c +++ b/board/altera/dk1c20/dk1c20.c @@ -50,7 +50,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } diff --git a/board/altera/dk1s10/Makefile b/board/altera/dk1s10/Makefile index 6af83890a8..60ac6e6b70 100644 --- a/board/altera/dk1s10/Makefile +++ b/board/altera/dk1s10/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/altera/dk1s10/dk1s10.c b/board/altera/dk1s10/dk1s10.c index c45e7f15d7..64d591e714 100644 --- a/board/altera/dk1s10/dk1s10.c +++ b/board/altera/dk1s10/dk1s10.c @@ -54,7 +54,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } diff --git a/board/altera/ep1c20/Makefile b/board/altera/ep1c20/Makefile index 7a8caf7c11..acad2aad85 100644 --- a/board/altera/ep1c20/Makefile +++ b/board/altera/ep1c20/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c index 29491391ef..c5bfb85a71 100644 --- a/board/altera/ep1c20/ep1c20.c +++ b/board/altera/ep1c20/ep1c20.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile index 7a8caf7c11..acad2aad85 100644 --- a/board/altera/ep1s10/Makefile +++ b/board/altera/ep1s10/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c index 9c7e28e68c..de9bf42bdc 100644 --- a/board/altera/ep1s10/ep1s10.c +++ b/board/altera/ep1s10/ep1s10.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile index 7a8caf7c11..acad2aad85 100644 --- a/board/altera/ep1s40/Makefile +++ b/board/altera/ep1s40/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c index cb75550476..c0eca17b92 100644 --- a/board/altera/ep1s40/ep1s40.c +++ b/board/altera/ep1s40/ep1s40.c @@ -29,7 +29,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index c56b2733a9..9abb29d85f 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 709d41e41a..48a6725745 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -33,14 +33,6 @@ extern void board_pll_init_f(void); -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { @@ -67,7 +59,7 @@ static void cram_bcr_write(u32 wr_val) } #endif -long int initdram(int board_type) +phys_size_t initdram(int board_type) { #if defined(CONFIG_NAND_SPL) u32 reg; @@ -116,10 +108,3 @@ long int initdram(int board_type) return (CFG_MBYTES_RAM << 20); } - -#ifndef CONFIG_NAND_SPL -int testdram(void) -{ - return (0); -} -#endif diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile index d01cc49e2c..0649799889 100644 --- a/board/amcc/bamboo/Makefile +++ b/board/amcc/bamboo/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 50771879e1..f4157017f1 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -453,7 +453,7 @@ int checkboard(void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; @@ -466,73 +466,6 @@ long int initdram (int board_type) #endif } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n, *p32, ctr; - const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024; - - mtmsr(0); - - for (k = 0; k < CFG_MBYTES_SDRAM*1024; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - - /* - * Perform a sequence test to ensure that all - * memory locations are uniquely addressable - */ - ctr = 0; - p32 = 0; - while ((unsigned long)p32 != bend) { - if (0 == ((unsigned long)p32 & ((1<<20)-1))) - printf("Writing %3d MB\r", (unsigned long)p32 >> 20); - *p32++ = ctr++; - } - - ctr = 0; - p32 = 0; - while ((unsigned long)p32 != bend) { - if (0 == ((unsigned long)p32 & ((1<<20)-1))) - printf("Verifying %3d MB\r", (unsigned long)p32 >> 20); - - if (*p32 != ctr) { - printf("SDRAM test fails at: %08x\n", p32); - return 1; - } - - ctr++; - p32++; - } - - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile index 50fecc6d48..1939d51688 100644 --- a/board/amcc/bubinga/Makefile +++ b/board/amcc/bubinga/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index 66e7509da8..74a2a1c214 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -66,30 +66,14 @@ int checkboard(void) return (0); } -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - /* ------------------------------------------------------------------------- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of the necessary info for SDRAM controller configuration ------------------------------------------------------------------------- */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { long int ret; ret = spd_sdram(); return ret; } - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile index 7a2eaa5163..2aeead60f9 100644 --- a/board/amcc/canyonlands/Makefile +++ b/board/amcc/canyonlands/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 0f66061278..e9eba49c4b 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -22,6 +22,7 @@ #include <ppc440.h> #include <libfdt.h> #include <fdt_support.h> +#include <i2c.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/mmu.h> @@ -205,50 +206,12 @@ u32 ddr_clktr(u32 default_val) { * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot * code. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return CFG_MBYTES_SDRAM << 20; } #endif -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /* * pci_target_init * @@ -431,6 +394,7 @@ int misc_init_r(void) u32 sdr0_srst1 = 0; u32 eth_cfg; u32 pvr = get_pvr(); + u8 val; /* * Set EMAC mode/configuration (GMII, SGMII, RGMII...). @@ -458,6 +422,15 @@ int misc_init_r(void) sdr0_srst1 &= ~SDR0_SRST1_AHB; mtsdr(SDR0_SRST1, sdr0_srst1); + /* + * RTC/M41T62: + * Disable square wave output: Batterie will be drained + * quickly, when this output is not disabled + */ + val = i2c_reg_read(CFG_I2C_RTC_ADDR, 0xa); + val &= ~0x40; + i2c_reg_write(CFG_I2C_RTC_ADDR, 0xa, val); + return 0; } diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile index 5da96e9e1c..6ab1a26b15 100644 --- a/board/amcc/ebony/Makefile +++ b/board/amcc/ebony/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index ededb3e7e1..9bcdf5997f 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -104,7 +104,7 @@ int checkboard(void) return (0); } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -116,36 +116,6 @@ long int initdram(int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile index d06a402d17..318016d2ce 100644 --- a/board/amcc/katmai/Makefile +++ b/board/amcc/katmai/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 193083fd46..3a0b18f30d 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -258,36 +258,6 @@ u32 ddr_clktr(u32 default_val) { return (SDRAM_CLKTR_CLKP_90_DEG_ADV); } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile index 39328c2bda..df0a68f5d5 100644 --- a/board/amcc/kilauea/Makefile +++ b/board/amcc/kilauea/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_pll.o memory.o -SOBJS = init.o +COBJS = $(BOARD).o cmd_pll.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -38,7 +37,7 @@ clean: rm -f $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S deleted file mode 100644 index 8cd534cd6b..0000000000 --- a/board/amcc/kilauea/init.S +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on code provided from UDTech and AMCC - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - - /* - * DDR2 setup - */ - - /* Following the DDR Core Manual, here is the initialization */ - - /* Step 1 */ - - /* Step 2 */ - - /* Step 3 */ - - /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */ - mtsdram_as(SDRAM_MB0CF, 0x00006701); - - /* SET SDRAM_MB1CF - Not enabled */ - mtsdram_as(SDRAM_MB1CF, 0x00000000); - - /* SET SDRAM_MB2CF - Not enabled */ - mtsdram_as(SDRAM_MB2CF, 0x00000000); - - /* SET SDRAM_MB3CF - Not enabled */ - mtsdram_as(SDRAM_MB3CF, 0x00000000); - - /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ - mtsdram_as(SDRAM_CLKTR, 0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram_as(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram_as(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram_as(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram_as(SDRAM_MMODE, 0x00000442); - mtsdram_as(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram_as(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram_as(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram_as(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram_as(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram_as(SDRAM_INITPLR11, 0x81000442); - mtsdram_as(SDRAM_INITPLR12, 0x81010780); - mtsdram_as(SDRAM_INITPLR13, 0x81010400); - mtsdram_as(SDRAM_INITPLR14, 0x00000000); - mtsdram_as(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram_as(SDRAM_CODT, 0x0080f837); - mtsdram_as(SDRAM_MODT0, 0x01800000); - mtsdram_as(SDRAM_MODT1, 0x00000000); - - mtsdram_as(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram_as(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - lis r3,0x1 /* 400000 = wait 100ms */ - mtctr r3 - -pll_wait: - bdnz pll_wait - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram_as(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram_as(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram_as(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram_as(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mtsdram_as(SDRAM_MCOPT2, 0x28000000); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ - - blr diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c deleted file mode 100644 index 1d7a3fad97..0000000000 --- a/board/amcc/kilauea/memory.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <i2c.h> - -void sdram_init(void) -{ - return; -} - -long int initdram(int board_type) -{ - return (CFG_MBYTES_SDRAM << 20); -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - printf ("testdram\n"); -#if defined (CONFIG_NAND_U_BOOT) - return 0; -#endif - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x00001000; - uint *p; - - for (p = pstart; p < pend; p++) { - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } - - for (p = pstart; p < pend; p++) { - *p = 0x55555555; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test passed!!!\n"); -#endif - return 0; -} -#endif diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile index 5da96e9e1c..6ab1a26b15 100644 --- a/board/amcc/luan/Makefile +++ b/board/amcc/luan/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index f964511c57..b14b6e1b56 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -126,50 +126,6 @@ u32 ddr_clktr(u32 default_val) { } /************************************************************************* - * int testdram() - * - ************************************************************************/ -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *) 0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - - return 0; -} -#endif - - -/************************************************************************* * pci_pre_init * * This routine is called just prior to registering the hose and gives diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile index 39328c2bda..dc3edc11aa 100644 --- a/board/amcc/makalu/Makefile +++ b/board/amcc/makalu/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_pll.o memory.o +COBJS = $(BOARD).o cmd_pll.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 11c5b1971e..4d0f4609e6 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -1,8 +1,11 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * Based on code provided from Senao and AMCC + * Originally based on code provided from Senao and AMCC * * See file CREDITS for list of people who contributed to this * project. @@ -23,126 +26,6 @@ * MA 02111-1307 USA */ -#include <config.h> -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; - .globl ext_bus_cntlr_init ext_bus_cntlr_init: - - /* - * DDR2 setup - */ - - /* Following the DDR Core Manual, here is the initialization */ - - /* Step 1 */ - - /* Step 2 */ - - /* Step 3 */ - - /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram_as(SDRAM_MB0CF, 0x00005201); - - /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); - - /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ - mtsdram_as(SDRAM_CLKTR,0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram_as(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram_as(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram_as(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram_as(SDRAM_MMODE, 0x00000442); - mtsdram_as(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram_as(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram_as(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram_as(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram_as(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram_as(SDRAM_INITPLR11, 0x81000442); - mtsdram_as(SDRAM_INITPLR12, 0x81010780); - mtsdram_as(SDRAM_INITPLR13, 0x81010400); - mtsdram_as(SDRAM_INITPLR14, 0x00000000); - mtsdram_as(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram_as(SDRAM_CODT, 0x0080f837); - mtsdram_as(SDRAM_MODT0, 0x01800000); -#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */ - mtsdram_as(SDRAM_MODT1, 0x00000000); -#endif - - mtsdram_as(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram_as(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - lis r3,0x1 /* 400000 = wait 100ms */ - mtctr r3 - -pll_wait: - bdnz pll_wait - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram_as(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram_as(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram_as(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram_as(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mtsdram_as(SDRAM_MCOPT2, 0x28000000); - blr diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c deleted file mode 100644 index b03b60b8f4..0000000000 --- a/board/amcc/makalu/memory.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -void sdram_init(void) -{ - return; -} - -long int initdram(int board_type) -{ - /* - * Same as on Kilauea, Makalu generates exception 0x200 - * (machine check) after trap_init() in board_init_f, - * when SDRAM is initialized here (late) and d-cache is - * used earlier as INIT_RAM. - * So for now, initialize DDR2 in init.S very early and - * also use it for INIT_RAM. Then this exception doesn't - * occur. - */ -#if 0 - u32 val; - - /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram(SDRAM_MB0CF, 0x00005201); - - /* SET SDRAM_MB1CF - Not enabled */ - mtsdram(SDRAM_MB1CF, 0x00000000); - - /* SET SDRAM_MB2CF - Not enabled */ - mtsdram(SDRAM_MB2CF, 0x00000000); - - /* SET SDRAM_MB3CF - Not enabled */ - mtsdram(SDRAM_MB3CF, 0x00000000); - - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ - mtsdram(SDRAM_CLKTR, 0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram(SDRAM_MMODE, 0x00000442); - mtsdram(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram(SDRAM_INITPLR11, 0x81000442); - mtsdram(SDRAM_INITPLR12, 0x81010780); - mtsdram(SDRAM_INITPLR13, 0x81010400); - mtsdram(SDRAM_INITPLR14, 0x00000000); - mtsdram(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram(SDRAM_CODT, 0x0080f837); - mtsdram(SDRAM_MODT0, 0x01800000); - mtsdram(SDRAM_MODT1, 0x00000000); - - mtsdram(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP); - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mfsdram(SDRAM_MCOPT2, val); - val |= SDRAM_MCOPT2_DCEN_ENABLE; - mtsdram(SDRAM_MCOPT2, val); -#endif - return (CFG_MBYTES_SDRAM << 20); -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - printf ("testdram\n"); -#if defined (CONFIG_NAND_U_BOOT) - return 0; -#endif - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x00001000; - uint *p; - - for (p = pstart; p < pend; p++) { - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } - - for (p = pstart; p < pend; p++) { - *p = 0x55555555; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test passed!!!\n"); -#endif - return 0; -} -#endif diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile index a758650e59..6ab1a26b15 100644 --- a/board/amcc/ocotea/Makefile +++ b/board/amcc/ocotea/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 3bd1b81400..eea1e1e177 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -201,7 +201,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; @@ -214,36 +214,6 @@ long int initdram (int board_type) } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile index e1c9ad4d69..a5d501079a 100644 --- a/board/amcc/sequoia/Makefile +++ b/board/amcc/sequoia/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk index e62b8d30e4..5e04ee4e36 100644 --- a/board/amcc/sequoia/config.mk +++ b/board/amcc/sequoia/config.mk @@ -28,6 +28,10 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE TEXT_BASE = 0xFFFA0000 +# +# When defining CONFIG_VIDEO, TEXT_BASE needs to be 0xFFF80000 +# TEXT_BASE = 0xFFF80000 +# endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index b43ec48091..77e6c7b4d1 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -52,7 +52,7 @@ extern void denali_core_search_data_eye(void); * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) #if !defined(CONFIG_NAND_SPL) diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 6bcb3ab198..5ff9787d3d 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -329,44 +329,6 @@ int checkboard(void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) /* * Assign interrupts to PCI devices. diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile index 9731c6e332..0b9f970ead 100644 --- a/board/amcc/taihu/Makefile +++ b/board/amcc/taihu/Makefile @@ -37,7 +37,7 @@ clean: rm -f $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index eedde597b8..254e3eb837 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -78,10 +78,10 @@ int checkboard(void) } /************************************************************************* - * long int initdram + * phys_size_t initdram * ************************************************************************/ -long int initdram(int board) +phys_size_t initdram(int board) { return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */ } @@ -165,16 +165,20 @@ unsigned char spi_read(void) return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15); } -void taihu_spi_chipsel(int cs) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) { - gpio_write_bit(SPI_CS_GPIO0, cs); + return bus == 0 && cs == 0; } -spi_chipsel_type spi_chipsel[]= { - taihu_spi_chipsel -}; +void spi_cs_activate(struct spi_slave *slave) +{ + gpio_write_bit(SPI_CS_GPIO0, 1); +} -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio_write_bit(SPI_CS_GPIO0, 0); +} #ifdef CONFIG_PCI static unsigned char int_lines[32] = { @@ -196,45 +200,3 @@ int pci_pre_init(struct pci_controller *hose) return 1; } #endif /* CONFIG_PCI */ - -#ifdef CFG_DRAM_TEST -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - unsigned long msr; - unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024; - - msr = mfmsr(); - mtmsr(msr & ~(MSR_EE)); - - for (k = 0; k < total_kbytes ; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) - printf("%3d MB\r", k / 1024); - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - mtmsr(msr); - - return 0; -} -#endif /* CFG_DRAM_TEST */ diff --git a/board/amcc/taishan/Makefile b/board/amcc/taishan/Makefile index 462af001b4..9d20e0f6bf 100644 --- a/board/amcc/taishan/Makefile +++ b/board/amcc/taishan/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index f00397ed19..b6c306539e 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -196,36 +196,6 @@ int checkboard (void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x04000000; - uint *pend = (uint *) 0x0fc00000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile index 50fecc6d48..1939d51688 100644 --- a/board/amcc/walnut/Makefile +++ b/board/amcc/walnut/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index 292e02609e..28dcb66ebc 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -86,26 +86,10 @@ int checkboard(void) } /* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - -/* * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of * the necessary info for SDRAM controller configuration */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return spd_sdram(); } - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile index 261e5d49cc..b93f2c3890 100644 --- a/board/amcc/yosemite/Makefile +++ b/board/amcc/yosemite/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 212fab8d08..3b1f8e2d79 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -200,7 +200,7 @@ int checkboard(void) } /************************************************************************* - * sdram_init -- doesn't use serial presence detect. + * initdram -- doesn't use serial presence detect. * * Assumes: 256 MB, ECC, non-registered * PLB @ 133 MHz @@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -void sdram_init(void) +phys_size_t initdram(int board) { register uint reg; int tr1_bank1, tr1_bank2; @@ -327,57 +327,11 @@ void sdram_init(void) sdram_tr1_set(0x00000000, &tr1_bank1); sdram_tr1_set(0x08000000, &tr1_bank2); - mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) ); -} + mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); -/************************************************************************* - * long int initdram - * - ************************************************************************/ -long int initdram(int board) -{ - sdram_init(); return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile index 9f42279b46..0ff522c31c 100644 --- a/board/amcc/yucca/Makefile +++ b/board/amcc/yucca/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 11d1743355..6608893651 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -586,36 +586,6 @@ u32 ddr_clktr(u32 default_val) { return default_val; } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amirix/ap1000/Makefile b/board/amirix/ap1000/Makefile index 7b99d314f9..d0729348a9 100644 --- a/board/amirix/ap1000/Makefile +++ b/board/amirix/ap1000/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index 7d11b29b59..55277e72d5 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -133,7 +133,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { char *s = getenv ("dramsize"); diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S index 3aaa5c2f1a..65f13e17a6 100644 --- a/board/amirix/ap1000/init.S +++ b/board/amirix/ap1000/init.S @@ -28,7 +28,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c index 5e9e3a31ee..508e880403 100644 --- a/board/amirix/ap1000/serial.c +++ b/board/amirix/ap1000/serial.c @@ -19,9 +19,9 @@ * */ +#include <common.h> #include <asm/u-boot.h> #include <asm/processor.h> -#include <common.h> #include <command.h> #include <config.h> diff --git a/board/apollon/Makefile b/board/apollon/Makefile index 5348f2d302..9bac9a6c0a 100644 --- a/board/apollon/Makefile +++ b/board/apollon/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c index 7e39817a0f..8efa703951 100644 --- a/board/apollon/apollon.c +++ b/board/apollon/apollon.c @@ -153,10 +153,8 @@ void ether_init(void) do { __raw_writew(0x1, LAN_RESET_REGISTER); udelay(100); - if (cnt == 0) { - printf("1. eth reset err\n"); + if (cnt == 0) goto eth_reset_err_out; - } --cnt; } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); @@ -165,10 +163,8 @@ void ether_init(void) do { __raw_writew(0x0, LAN_RESET_REGISTER); udelay(100); - if (cnt == 0) { - printf("2. eth reset err\n"); + if (cnt == 0) goto eth_reset_err_out; - } --cnt; } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); udelay(1000); diff --git a/board/apollon/mem.h b/board/apollon/mem.h index 5bc96faa95..d4636f4051 100644 --- a/board/apollon/mem.h +++ b/board/apollon/mem.h @@ -67,7 +67,7 @@ # define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24)) /* CS1: Ethernet */ -# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011200 +# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011203 # define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01 # define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 # define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a diff --git a/board/armadillo/Makefile b/board/armadillo/Makefile index 1380e92cf6..b18e42bff3 100644 --- a/board/armadillo/Makefile +++ b/board/armadillo/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/assabet/Makefile b/board/assabet/Makefile index 872c7fbff8..03f0762a3b 100644 --- a/board/assabet/Makefile +++ b/board/assabet/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/atc/atc.c b/board/atc/atc.c index fe32155822..79527f4384 100644 --- a/board/atc/atc.c +++ b/board/atc/atc.c @@ -340,7 +340,7 @@ int misc_init_r(void) return (0); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/atmel/at91cap9adk/Makefile b/board/atmel/at91cap9adk/Makefile index e33af76c02..2d2ff2cbb9 100644 --- a/board/atmel/at91cap9adk/Makefile +++ b/board/atmel/at91cap9adk/Makefile @@ -2,6 +2,10 @@ # (C) Copyright 2003-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# # See file CREDITS for list of people who contributed to this # project. # @@ -41,7 +45,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index 5de52b9197..c5082a0925 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -30,6 +30,8 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> +#include <lcd.h> +#include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif @@ -70,6 +72,33 @@ static void at91cap9_serial_hw_init(void) #endif } +static void at91cap9_slowclock_hw_init(void) +{ + /* + * On AT91CAP9 revC CPUs, the slow clock can be based on an + * internal impreciseRC oscillator or an external 32kHz oscillator. + * Switch to the latter. + */ +#define ARCH_ID_AT91CAP9_REVB 0x399 +#define ARCH_ID_AT91CAP9_REVC 0x601 + if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) { + unsigned i, tmp = at91_sys_read(AT91_SCKCR); + if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) { + extern void timer_init(void); + timer_init(); + tmp |= AT91CAP9_SCKCR_OSC32EN; + at91_sys_write(AT91_SCKCR, tmp); + for (i = 0; i < 1200; i++) + udelay(1000); + tmp |= AT91CAP9_SCKCR_OSCSEL_32; + at91_sys_write(AT91_SCKCR, tmp); + udelay(200); + tmp &= ~AT91CAP9_SCKCR_RCEN; + at91_sys_write(AT91_SCKCR, tmp); + } + } +} + static void at91cap9_nor_hw_init(void) { unsigned long csa; @@ -116,7 +145,12 @@ static void at91cap9_nand_hw_init(void) at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | AT91_SMC_TDF_(1)); +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(1)); at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD); @@ -162,7 +196,7 @@ static void at91cap9_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -170,6 +204,11 @@ static void at91cap9_macb_hw_init(void) /* Wait for end hardware reset */ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | + AT91_RSTC_URSTEN); + /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PB22) | pin_to_mask(AT91_PIN_PB25) | @@ -228,6 +267,65 @@ static void at91cap9_uhp_hw_init(void) } #endif +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91CAP9_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */ +} + +static void at91cap9_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC); + + gd->fb_base = 0; +} +#endif + int board_init(void) { /* Enable Ctrlc */ @@ -239,6 +337,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; at91cap9_serial_hw_init(); + at91cap9_slowclock_hw_init(); at91cap9_nor_hw_init(); #ifdef CONFIG_CMD_NAND at91cap9_nand_hw_init(); @@ -252,7 +351,9 @@ int board_init(void) #ifdef CONFIG_USB_OHCI_NEW at91cap9_uhp_hw_init(); #endif - +#ifdef CONFIG_LCD + at91cap9_lcd_hw_init(); +#endif return 0; } diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c index 28091a4226..0432ef13d8 100644 --- a/board/atmel/at91cap9adk/nand.c +++ b/board/atmel/at91cap9adk/nand.c @@ -63,6 +63,9 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd) int board_nand_init(struct nand_chip *nand) { nand->eccmode = NAND_ECC_SOFT; +#ifdef CFG_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif nand->hwcontrol = at91cap9adk_nand_hwcontrol; nand->chip_delay = 20; diff --git a/board/atmel/at91rm9200dk/Makefile b/board/atmel/at91rm9200dk/Makefile index 5b4cdcfc39..2d806d0668 100755..100644 --- a/board/atmel/at91rm9200dk/Makefile +++ b/board/atmel/at91rm9200dk/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile index e6e4082c73..7c8a612e47 100644 --- a/board/atmel/at91sam9260ek/Makefile +++ b/board/atmel/at91sam9260ek/Makefile @@ -2,6 +2,10 @@ # (C) Copyright 2003-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# # See file CREDITS for list of people who contributed to this # project. # @@ -41,7 +45,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index b30aad8373..836a0c40bf 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -80,8 +80,8 @@ static void at91sam9260ek_nand_hw_init(void) /* Configure SMC CS3 for NAND/SmartMedia */ at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); @@ -90,7 +90,12 @@ static void at91sam9260ek_nand_hw_init(void) at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | AT91_SMC_TDF_(2)); +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); @@ -144,7 +149,7 @@ static void at91sam9260ek_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -154,7 +159,7 @@ static void at91sam9260ek_macb_hw_init(void) /* Restore NRST value */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0 << 8) | + (AT91_RSTC_ERSTL & (0x0 << 8)) | AT91_RSTC_URSTEN); /* Re-enable pull-up */ diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c index 7c1e6abd9a..9738f0fd48 100644 --- a/board/atmel/at91sam9260ek/nand.c +++ b/board/atmel/at91sam9260ek/nand.c @@ -68,6 +68,9 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { nand->eccmode = NAND_ECC_SOFT; +#ifdef CFG_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif nand->hwcontrol = at91sam9260ek_nand_hwcontrol; nand->dev_ready = at91sam9260ek_nand_ready; nand->chip_delay = 20; diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile new file mode 100644 index 0000000000..d7b063dec8 --- /dev/null +++ b/board/atmel/at91sam9261ek/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += at91sam9261ek.o +COBJS-y += led.o +COBJS-y += partition.o +COBJS-$(CONFIG_CMD_NAND) += nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c new file mode 100644 index 0000000000..647aab5256 --- /dev/null +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -0,0 +1,258 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/at91sam9261_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <lcd.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) +#include <net.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void at91sam9261ek_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +} + +#ifdef CONFIG_CMD_NAND +static void at91sam9261ek_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(AT91_PIN_PC15, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(AT91_PIN_PC14, 1); + + at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ +} +#endif + +#ifdef CONFIG_HAS_DATAFLASH +static void at91sam9261ek_spi_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ + + at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +static void at91sam9261ek_dm9000_hw_init(void) +{ + /* Configure SMC CS2 for DM9000 */ + at91_sys_write(AT91_SMC_SETUP(2), + AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(2), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | + AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); + at91_sys_write(AT91_SMC_CYCLE(2), + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); + at91_sys_write(AT91_SMC_MODE(2), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | + AT91_SMC_TDF_(1)); + + /* Configure Reset signal as output */ + at91_set_gpio_output(AT91_PIN_PC10, 0); + + /* Configure Interrupt pin as input, no pull-up */ + at91_set_gpio_input(AT91_PIN_PC11, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91SAM9261_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ +} + +static void at91sam9261ek_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + + gd->fb_base = AT91SAM9261_SRAM_BASE; +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of AT91SAM9261EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91sam9261ek_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + at91sam9261ek_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91sam9261ek_spi_hw_init(); +#endif +#ifdef CONFIG_DRIVER_DM9000 + at91sam9261ek_dm9000_hw_init(); +#endif +#ifdef CONFIG_LCD + at91sam9261ek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_DRIVER_DM9000 + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif diff --git a/board/atmel/at91sam9261ek/config.mk b/board/atmel/at91sam9261ek/config.mk new file mode 100644 index 0000000000..ff2cfd170b --- /dev/null +++ b/board/atmel/at91sam9261ek/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c new file mode 100644 index 0000000000..eb2bb23411 --- /dev/null +++ b/board/atmel/at91sam9261ek/led.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +#define RED_LED AT91_PIN_PA23 /* this is the power led */ +#define GREEN_LED AT91_PIN_PA13 /* this is the user1 led */ +#define YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */ + +void red_LED_on(void) +{ + at91_set_gpio_value(RED_LED, 1); +} + +void red_LED_off(void) +{ + at91_set_gpio_value(RED_LED, 0); +} + +void green_LED_on(void) +{ + at91_set_gpio_value(GREEN_LED, 0); +} + +void green_LED_off(void) +{ + at91_set_gpio_value(GREEN_LED, 1); +} + +void yellow_LED_on(void) +{ + at91_set_gpio_value(YELLOW_LED, 0); +} + +void yellow_LED_off(void) +{ + at91_set_gpio_value(YELLOW_LED, 1); +} + + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); + + at91_set_gpio_output(RED_LED, 1); + at91_set_gpio_output(GREEN_LED, 1); + at91_set_gpio_output(YELLOW_LED, 1); + + at91_set_gpio_value(RED_LED, 0); + at91_set_gpio_value(GREEN_LED, 1); + at91_set_gpio_value(YELLOW_LED, 1); +} diff --git a/board/atmel/at91sam9261ek/nand.c b/board/atmel/at91sam9261ek/nand.c new file mode 100644 index 0000000000..35b26dbefe --- /dev/null +++ b/board/atmel/at91sam9261ek/nand.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pio.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 22) /* our ALE is AD22 */ +#define MASK_CLE (1 << 21) /* our CLE is AD21 */ + +static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: + IO_ADDR_W |= MASK_CLE; + break; + case NAND_CTL_SETALE: + IO_ADDR_W |= MASK_ALE; + break; + case NAND_CTL_CLRNCE: + at91_set_gpio_value(AT91_PIN_PC14, 1); + break; + case NAND_CTL_SETNCE: + at91_set_gpio_value(AT91_PIN_PC14, 0); + break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +static int at91sam9261ek_nand_ready(struct mtd_info *mtd) +{ + return at91_get_gpio_value(AT91_PIN_PC15); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->eccmode = NAND_ECC_SOFT; +#ifdef CFG_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif + nand->hwcontrol = at91sam9261ek_nand_hwcontrol; + nand->dev_ready = at91sam9261ek_nand_ready; + nand->chip_delay = 20; + + return 0; +} diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c new file mode 100644 index 0000000000..975be17464 --- /dev/null +++ b/board/atmel/at91sam9261ek/partition.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson <ulf@atmel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, +}; diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile new file mode 100644 index 0000000000..00a6b00ddf --- /dev/null +++ b/board/atmel/at91sam9263ek/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += at91sam9263ek.o +COBJS-y += led.o +COBJS-y += partition.o +COBJS-$(CONFIG_CMD_NAND) += nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c new file mode 100644 index 0000000000..927fc912c9 --- /dev/null +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9263_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <lcd.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void at91sam9263ek_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +} + +#ifdef CONFIG_CMD_NAND +static void at91sam9263ek_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOCDE); + + /* Configure RDY/BSY */ + at91_set_gpio_input(AT91_PIN_PA22, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(AT91_PIN_PD15, 1); +} +#endif + +#ifdef CONFIG_HAS_DATAFLASH +static void at91sam9263ek_spi_hw_init(void) +{ + at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */ + + at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); +} +#endif + +#ifdef CONFIG_MACB +static void at91sam9263ek_macb_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUER); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + + at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ + at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ +#endif + +} +#endif + +#ifdef CONFIG_USB_OHCI_NEW +static void at91sam9263ek_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_gpio_output(AT91_PIN_PA21, 0); + at91_set_gpio_output(AT91_PIN_PA24, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91SAM9263_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */ +} + +static void at91sam9263ek_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); + + gd->fb_base = AT91SAM9263_SRAM0_BASE; +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of AT91SAM9263EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91sam9263ek_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + at91sam9263ek_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91sam9263ek_spi_hw_init(); +#endif +#ifdef CONFIG_MACB + at91sam9263ek_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91sam9263ek_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + at91sam9263ek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif diff --git a/board/atmel/at91sam9263ek/config.mk b/board/atmel/at91sam9263ek/config.mk new file mode 100644 index 0000000000..ff2cfd170b --- /dev/null +++ b/board/atmel/at91sam9263ek/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c new file mode 100644 index 0000000000..eb8d6ca04f --- /dev/null +++ b/board/atmel/at91sam9263ek/led.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +#define RED_LED AT91_PIN_PB7 /* this is the power led */ +#define GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ +#define YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */ + +void red_LED_on(void) +{ + at91_set_gpio_value(RED_LED, 1); +} + +void red_LED_off(void) +{ + at91_set_gpio_value(RED_LED, 0); +} + +void green_LED_on(void) +{ + at91_set_gpio_value(GREEN_LED, 0); +} + +void green_LED_off(void) +{ + at91_set_gpio_value(GREEN_LED, 1); +} + +void yellow_LED_on(void) +{ + at91_set_gpio_value(YELLOW_LED, 0); +} + +void yellow_LED_off(void) +{ + at91_set_gpio_value(YELLOW_LED, 1); +} + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE); + + at91_set_gpio_output(RED_LED, 1); + at91_set_gpio_output(GREEN_LED, 1); + at91_set_gpio_output(YELLOW_LED, 1); + + at91_set_gpio_value(RED_LED, 0); + at91_set_gpio_value(GREEN_LED, 1); + at91_set_gpio_value(YELLOW_LED, 1); +} diff --git a/board/atmel/at91sam9263ek/nand.c b/board/atmel/at91sam9263ek/nand.c new file mode 100644 index 0000000000..5079972652 --- /dev/null +++ b/board/atmel/at91sam9263ek/nand.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pio.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define MASK_CLE (1 << 22) /* our CLE is AD22 */ + +static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: + IO_ADDR_W |= MASK_CLE; + break; + case NAND_CTL_SETALE: + IO_ADDR_W |= MASK_ALE; + break; + case NAND_CTL_CLRNCE: + at91_set_gpio_value(AT91_PIN_PD15, 1); + break; + case NAND_CTL_SETNCE: + at91_set_gpio_value(AT91_PIN_PD15, 0); + break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +static int at91sam9263ek_nand_ready(struct mtd_info *mtd) +{ + return at91_get_gpio_value(AT91_PIN_PA22); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->eccmode = NAND_ECC_SOFT; +#ifdef CFG_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif + nand->hwcontrol = at91sam9263ek_nand_hwcontrol; + nand->dev_ready = at91sam9263ek_nand_ready; + nand->chip_delay = 20; + + return 0; +} diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c new file mode 100644 index 0000000000..eb1a724ab1 --- /dev/null +++ b/board/atmel/at91sam9263ek/partition.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson <ulf@atmel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, +}; diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile new file mode 100644 index 0000000000..90029cb872 --- /dev/null +++ b/board/atmel/at91sam9rlek/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += at91sam9rlek.o +COBJS-y += led.o +COBJS-y += partition.o +COBJS-$(CONFIG_CMD_NAND) += nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c new file mode 100644 index 0000000000..509e7c38e1 --- /dev/null +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9rl.h> +#include <asm/arch/at91sam9rl_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <lcd.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void at91sam9rlek_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +} + +#ifdef CONFIG_CMD_NAND +static void at91sam9rlek_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD); + + /* Configure RDY/BSY */ + at91_set_gpio_input(AT91_PIN_PD17, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(AT91_PIN_PB6, 1); + + at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ +} +#endif + +#ifdef CONFIG_HAS_DATAFLASH +static void at91sam9rlek_spi_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA28, 0); /* SPI0_NPCS0 */ + + at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91SAM9RL_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ +} +static void at91sam9rlek_lcd_hw_init(void) +{ + at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ + at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ + at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ + at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ + at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ + at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ + at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC); + + gd->fb_base = 0; +} +#endif + + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of AT91SAM9RLEK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91sam9rlek_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + at91sam9rlek_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91sam9rlek_spi_hw_init(); +#endif +#ifdef CONFIG_LCD + at91sam9rlek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} diff --git a/board/atmel/at91sam9rlek/config.mk b/board/atmel/at91sam9rlek/config.mk new file mode 100644 index 0000000000..ff2cfd170b --- /dev/null +++ b/board/atmel/at91sam9rlek/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c new file mode 100644 index 0000000000..8a7d8e0bf7 --- /dev/null +++ b/board/atmel/at91sam9rlek/led.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9rl.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +#define RED_LED AT91_PIN_PD14 /* this is the power led */ +#define GREEN_LED AT91_PIN_PD15 /* this is the user1 led */ +#define YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */ + +void red_LED_on(void) +{ + at91_set_gpio_value(RED_LED, 1); +} + +void red_LED_off(void) +{ + at91_set_gpio_value(RED_LED, 0); +} + +void green_LED_on(void) +{ + at91_set_gpio_value(GREEN_LED, 0); +} + +void green_LED_off(void) +{ + at91_set_gpio_value(GREEN_LED, 1); +} + +void yellow_LED_on(void) +{ + at91_set_gpio_value(YELLOW_LED, 0); +} + +void yellow_LED_off(void) +{ + at91_set_gpio_value(YELLOW_LED, 1); +} + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD); + + at91_set_gpio_output(RED_LED, 1); + at91_set_gpio_output(GREEN_LED, 1); + at91_set_gpio_output(YELLOW_LED, 1); + + at91_set_gpio_value(RED_LED, 0); + at91_set_gpio_value(GREEN_LED, 1); + at91_set_gpio_value(YELLOW_LED, 1); +} diff --git a/board/atmel/at91sam9rlek/nand.c b/board/atmel/at91sam9rlek/nand.c new file mode 100644 index 0000000000..5af1a31175 --- /dev/null +++ b/board/atmel/at91sam9rlek/nand.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9rl.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pio.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define MASK_CLE (1 << 22) /* our CLE is AD22 */ + +static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: + IO_ADDR_W |= MASK_CLE; + break; + case NAND_CTL_SETALE: + IO_ADDR_W |= MASK_ALE; + break; + case NAND_CTL_CLRNCE: + at91_set_gpio_value(AT91_PIN_PB6, 1); + break; + case NAND_CTL_SETNCE: + at91_set_gpio_value(AT91_PIN_PB6, 0); + break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +static int at91sam9rlek_nand_ready(struct mtd_info *mtd) +{ + return at91_get_gpio_value(AT91_PIN_PD17); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->eccmode = NAND_ECC_SOFT; +#ifdef CFG_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif + nand->hwcontrol = at91sam9rlek_nand_hwcontrol; + nand->dev_ready = at91sam9rlek_nand_ready; + nand->chip_delay = 20; + + return 0; +} diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c new file mode 100644 index 0000000000..eb1a724ab1 --- /dev/null +++ b/board/atmel/at91sam9rlek/partition.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson <ulf@atmel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, +}; diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index 1ccbe2c181..f2c3e79799 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -25,12 +25,12 @@ #include <asm/sdram.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> -#include <asm/arch/hmatrix2.h> +#include <asm/arch/hmatrix.h> DECLARE_GLOBAL_DATA_PTR; -static const struct sdram_info sdram = { - .phys_addr = CFG_SDRAM_BASE, +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_16BIT, .row_bits = 13, .col_bits = 9, .bank_bits = 2, @@ -47,8 +47,8 @@ static const struct sdram_info sdram = { int board_early_init_f(void) { - /* Set the SDRAM_ENABLE bit in the HEBI SFR */ - hmatrix2_writel(SFR4, 1 << 1); + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); gpio_enable_ebi(); gpio_enable_usart1(); @@ -60,13 +60,31 @@ int board_early_init_f(void) #if defined(CONFIG_MMC) gpio_enable_mmci(); #endif +#if defined(CONFIG_ATMEL_SPI) + gpio_enable_spi0(1 << 0); +#endif return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { - return sdram_init(&sdram); + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %u of %u MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; } void board_init_info(void) @@ -74,3 +92,25 @@ void board_init_info(void) gd->bd->bi_phy_id[0] = 0x01; gd->bd->bi_phy_id[1] = 0x03; } + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#include <spi.h> + +#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA3 + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1); +} +#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/atmel/atngw100/u-boot.lds b/board/atmel/atngw100/u-boot.lds index 34e347aecd..e736adf0fc 100644 --- a/board/atmel/atngw100/u-boot.lds +++ b/board/atmel/atngw100/u-boot.lds @@ -29,17 +29,10 @@ SECTIONS . = 0; _text = .; .text : { + *(.exception.text) *(.text) *(.text.*) } - - . = ALIGN(32); - __flashprog_start = .; - .flashprog : { - *(.flashprog) - } - . = ALIGN(32); - __flashprog_end = .; _etext = .; .rodata : { diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 28f64c4a6f..6371e2d4e3 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -25,13 +25,39 @@ #include <asm/sdram.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> -#include <asm/arch/hmatrix2.h> +#include <asm/arch/hmatrix.h> DECLARE_GLOBAL_DATA_PTR; -static const struct sdram_info sdram = { - .phys_addr = CFG_SDRAM_BASE, +static const struct sdram_config sdram_config = { +#if defined(CONFIG_ATSTK1006) + /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */ + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 2, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 4, + .txsr = 7, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +#else + /* MT48LC2M32B2P-5 (8 MB) on motherboard */ +#ifdef CONFIG_ATSTK1004 + .data_bits = SDRAM_DATA_16BIT, +#else + .data_bits = SDRAM_DATA_32BIT, +#endif +#ifdef CONFIG_ATSTK1000_16MB_SDRAM + /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */ + .row_bits = 12, +#else .row_bits = 11, +#endif .col_bits = 8, .bank_bits = 2, .cas = 3, @@ -43,12 +69,13 @@ static const struct sdram_info sdram = { .txsr = 5, /* 15.6 us */ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, +#endif }; int board_early_init_f(void) { - /* Set the SDRAM_ENABLE bit in the HEBI SFR */ - hmatrix2_writel(SFR4, 1 << 1); + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); gpio_enable_ebi(); gpio_enable_usart1(); @@ -63,9 +90,24 @@ int board_early_init_f(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { - return sdram_init(&sdram); + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %u of %u MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; } void board_init_info(void) diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index 40478258e7..12537f3142 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; flash_info_t flash_info[1]; -static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info) +static void flash_identify(uint16_t *flash, flash_info_t *info) { unsigned long flags; @@ -76,7 +76,7 @@ void flash_print_info(flash_info_t *info) info->size >> 10, info->sector_count); } -int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { unsigned long flags; unsigned long start_time; @@ -154,7 +154,7 @@ int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last) return ERR_OK; } -int __flashprog write_buff(flash_info_t *info, uchar *src, +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong count) { unsigned long flags; diff --git a/board/atmel/atstk1000/u-boot.lds b/board/atmel/atstk1000/u-boot.lds index 247812e103..0d3b19c640 100644 --- a/board/atmel/atstk1000/u-boot.lds +++ b/board/atmel/atstk1000/u-boot.lds @@ -29,17 +29,10 @@ SECTIONS . = 0; _text = .; .text : { + *(.exception.text) *(.text) *(.text.*) } - - . = ALIGN(32); - __flashprog_start = .; - .flashprog : { - *(.flashprog) - } - . = ALIGN(32); - __flashprog_end = .; _etext = .; .rodata : { diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile index ac4e583855..d2e689f1fa 100644 --- a/board/atum8548/Makefile +++ b/board/atum8548/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 2f6ae29d99..4d8c6fbae3 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -98,7 +98,7 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */ -long int +phys_size_t initdram(int board_type) { long dram_size = 0; diff --git a/board/atum8548/law.c b/board/atum8548/law.c index 3606cbb52f..b66fd7b297 100644 --- a/board/atum8548/law.c +++ b/board/atum8548/law.c @@ -48,14 +48,14 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(8, CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/barco/barco.c b/board/barco/barco.c index becbd0abda..72e7e0b050 100644 --- a/board/barco/barco.c +++ b/board/barco/barco.c @@ -83,7 +83,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/barco/barco_svc.h b/board/barco/barco_svc.h index 088f61e74e..bd924f2b18 100644 --- a/board/barco/barco_svc.h +++ b/board/barco/barco_svc.h @@ -59,7 +59,7 @@ typedef struct SBootInfo { /* barcohydra.c */ int checkboard(void); -long int initdram(int board_type); +phys_size_t initdram(int board_type); void pci_init_board(void); void check_flash(void); int write_flash(char *addr, char value); diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile index d0e147e4ba..9c1d0cc561 100644 --- a/board/bc3450/Makefile +++ b/board/bc3450/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index 56a73fe4d0..a728dc64d7 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -104,7 +104,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -205,7 +205,7 @@ long int initdram (int board_type) #elif defined(CONFIG_MGT5100) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index 6688095d23..b2d7acffee 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -46,7 +46,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 738f69c781..583560adb3 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -39,7 +39,7 @@ int checkboard(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { #ifdef DEBUG int brate; diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 1115df8327..21f6ad1b45 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -46,7 +46,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index c4dde92c1a..7a17dfa55b 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -48,7 +48,7 @@ int checkboard(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { #ifdef DEBUG printf("SDRAM attributes:\n"); diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index ea8c43680b..e5481bfc55 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -46,7 +46,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index e714177d7c..cd7a04dbfa 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -97,7 +97,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) } #endif /* CONFIG_BFIN_IDE */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { #ifdef DEBUG int brate; diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile index 73bef24baf..a1a4433fc1 100644 --- a/board/bf561-ezkit/Makefile +++ b/board/bf561-ezkit/Makefile @@ -46,7 +46,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index d504217a1a..7345b42cb4 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -39,7 +39,7 @@ int checkboard(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { #ifdef DEBUG int brate; diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c index 485e050b19..043143163a 100644 --- a/board/bmw/bmw.c +++ b/board/bmw/bmw.c @@ -51,7 +51,7 @@ int checkboard(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return 64*1024*1024; } diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c index ca8eb0cb02..7d2f746f45 100644 --- a/board/c2mon/c2mon.c +++ b/board/c2mon/c2mon.c @@ -108,7 +108,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/canmb/Makefile b/board/canmb/Makefile index 23d410d14e..b6b67d8e72 100644 --- a/board/canmb/Makefile +++ b/board/canmb/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index 1782b314f8..d3711d0779 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -82,7 +82,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -185,7 +185,7 @@ long int initdram (int board_type) #elif defined(CONFIG_MGT5100) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile index 50d07b8022..a806b18492 100644 --- a/board/cerf250/Makefile +++ b/board/cerf250/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile index f53404148a..cd3f962f28 100644 --- a/board/cm4008/Makefile +++ b/board/cm4008/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile index 5c20477d5d..952a8ae21b 100644 --- a/board/cm41xx/Makefile +++ b/board/cm41xx/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile index 8ebdb1aa28..d76e13a078 100644 --- a/board/cm5200/Makefile +++ b/board/cm5200/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 79fb71dc70..24e8db0c60 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -114,7 +114,7 @@ static mem_conf_t* get_mem_config(int board_type) /* * Initalize SDRAM - configure SDRAM controller, detect memory size. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT @@ -275,7 +275,7 @@ static void ft_blob_update(void *blob, bd_t *bd) ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); if (ret < 0) { - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } } diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile index f7a136034e..9745ebd378 100755..100644 --- a/board/cmc_pu2/Makefile +++ b/board/cmc_pu2/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cmi/Makefile b/board/cmi/Makefile index 6a4230486f..aeebb9ecb5 100644 --- a/board/cmi/Makefile +++ b/board/cmi/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c index cbf34f7854..8501cae21a 100644 --- a/board/cmi/cmi.c +++ b/board/cmi/cmi.c @@ -62,7 +62,7 @@ int checkboard(void) /* * Get RAM size. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */ } diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 86c7ee1eec..b928550504 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -32,7 +32,7 @@ int checkboard (void) return 0; }; -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM); diff --git a/board/cogent/Makefile b/board/cogent/Makefile index ced04dd725..afa134558f 100644 --- a/board/cogent/Makefile +++ b/board/cogent/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cogent/mb.c b/board/cogent/mb.c index 917132b3fb..619aea3c0c 100644 --- a/board/cogent/mb.c +++ b/board/cogent/mb.c @@ -233,7 +233,7 @@ int misc_init_f (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #ifdef CONFIG_CMA111 return (32L * 1024L * 1024L); diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c index 79eb473176..f4e867ce7d 100644 --- a/board/cpc45/cpc45.c +++ b/board/cpc45/cpc45.c @@ -61,7 +61,7 @@ int checkboard(void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { int m, row, col, bank, i, ref; unsigned long start, end; diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c index 0eb94efdaa..9e76c72d3e 100644 --- a/board/cpu86/cpu86.c +++ b/board/cpu86/cpu86.c @@ -273,7 +273,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c index a2fd19398b..f5a5de5d82 100644 --- a/board/cpu87/cpu87.c +++ b/board/cpu87/cpu87.c @@ -274,7 +274,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/cradle/Makefile b/board/cradle/Makefile index 90a7907936..1ae785db5f 100644 --- a/board/cradle/Makefile +++ b/board/cradle/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index a72ba4620b..f0dfa07fdc 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -170,7 +170,7 @@ int misc_init_r (void) } /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (L1_MEMSIZE); } diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile index cfdd60e056..21b513c29f 100644 --- a/board/cray/L1/Makefile +++ b/board/cray/L1/Makefile @@ -43,7 +43,7 @@ clean: $(obj)bootscript.image $(obj)bootscript.o distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend $(obj)$(BOARD).o : $(src)$(BOARD).c $(obj)bootscript.o diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 72a10d3a1b..4b6b3f4003 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -134,14 +134,3 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr - -/*----------------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Configures SDRAM memory banks. */ -/* NOTE: for CrayL1 we have ECC memory, so enable it. */ -/*....now done in C in L1.c:init_sdram for readability. */ -/*----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - blr diff --git a/board/csb226/Makefile b/board/csb226/Makefile index eee8f13525..c12dbea9cd 100644 --- a/board/csb226/Makefile +++ b/board/csb226/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/csb272/Makefile b/board/csb272/Makefile index 703a25c979..6d42bff750 100644 --- a/board/csb272/Makefile +++ b/board/csb272/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 24c6f0d986..5a585ae37f 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -27,6 +27,8 @@ #include <miiphy.h> #include <ppc4xx_enet.h> +void sdram_init(void); + /* * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator * @@ -118,12 +120,19 @@ int checkboard(void) * configured by initialization code * */ -long initdram (int board_type) +phys_size_t initdram (int board_type) { ulong tot_size; ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/csb472/Makefile b/board/csb472/Makefile index 703a25c979..6d42bff750 100644 --- a/board/csb472/Makefile +++ b/board/csb472/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 833bbce923..9dc130efc1 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -27,6 +27,8 @@ #include <miiphy.h> #include <ppc4xx_enet.h> +void sdram_init(void); + /* * board_early_init_f: do early board initialization * @@ -86,12 +88,19 @@ int checkboard(void) * configured by initialization code * */ -long initdram (int board_type) +phys_size_t initdram (int board_type) { ulong tot_size; ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/csb637/Makefile b/board/csb637/Makefile index ce263aa84e..ab28434a31 100644 --- a/board/csb637/Makefile +++ b/board/csb637/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c index 3edd27a3eb..ecf6328945 100644 --- a/board/cu824/cu824.c +++ b/board/cu824/cu824.c @@ -45,7 +45,7 @@ int checkboard (void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { long size; long new_bank0_end; diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile index 56b286f85e..e70d2c8e37 100644 --- a/board/dave/B2/Makefile +++ b/board/dave/B2/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile index cb7becb4db..1869f8ceee 100644 --- a/board/dave/PPChameleonEVB/Makefile +++ b/board/dave/PPChameleonEVB/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index e8302d9fc7..c9b288a413 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -203,7 +203,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/davinci/dv-evm/Makefile b/board/davinci/dv-evm/Makefile index fa0013811d..579efe2623 100644 --- a/board/davinci/dv-evm/Makefile +++ b/board/davinci/dv-evm/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak *~ .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### # This is for $(obj).depend target diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile index fa0013811d..579efe2623 100644 --- a/board/davinci/schmoogie/Makefile +++ b/board/davinci/schmoogie/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak *~ .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### # This is for $(obj).depend target diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile new file mode 100644 index 0000000000..fb31ee42b2 --- /dev/null +++ b/board/davinci/sffsdr/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/at32ap/pm.c b/board/davinci/sffsdr/board_init.S index c78d547f85..22d8adc18c 100644 --- a/cpu/at32ap/pm.c +++ b/board/davinci/sffsdr/board_init.S @@ -1,8 +1,9 @@ /* - * Copyright (C) 2006 Atmel Corporation + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * - * See file CREDITS for list of people who contributed to this - * project. + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,24 +20,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#include <common.h> -#ifdef CFG_POWER_MANAGER -#include <asm/errno.h> -#include <asm/io.h> +#include <config.h> -#include <asm/arch/memory-map.h> +.globl dv_board_init +dv_board_init: -#include "sm.h" - - -#ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) -#else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) -#endif - -DECLARE_GLOBAL_DATA_PTR; - - -#endif /* CFG_POWER_MANAGER */ + mov pc, lr diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk new file mode 100644 index 0000000000..f3b23d1c83 --- /dev/null +++ b/board/davinci/sffsdr/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> +# +# Copyright (C) 2008 Lyrtech <www.lyrtech.com> +# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> +# +# Lyrtech SFF SDR board (ARM926EJS) cpu +# +# SFF SDR board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 87FF'FFFF +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0, +# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc). +# +# we load ourself to 8400'0000 to provide at least 32MB spacing +# between us and the Integrity kernel image +TEXT_BASE = 0x84000000 diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c new file mode 100644 index 0000000000..b73484ae2b --- /dev/null +++ b/board/davinci/sffsdr/sffsdr.c @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> + +#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ +#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */ + +#define INTEGRITY_SYSCFG_OFFSET 0x7E8 +#define INTEGRITY_CHECKWORD_OFFSET 0x7F8 +#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF + +DECLARE_GLOBAL_DATA_PTR; + +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01); + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + switch (id) { + case DAVINCI_LPSC_VPSSSLV: + case DAVINCI_LPSC_EMAC: + case DAVINCI_LPSC_EMAC_WRAPPER: + case DAVINCI_LPSC_MDIO: + case DAVINCI_LPSC_USB: + case DAVINCI_LPSC_ATA: + case DAVINCI_LPSC_VLYNQ: + case DAVINCI_LPSC_UHPI: + case DAVINCI_LPSC_DDR_EMIF: + case DAVINCI_LPSC_AEMIF: + case DAVINCI_LPSC_MMC_SD: + case DAVINCI_LPSC_MEMSTICK: + case DAVINCI_LPSC_McBSP: + case DAVINCI_LPSC_GPIO: + *mdctl |= 0x200; + break; + } + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03); + while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ +} + +#if !defined(CFG_USE_DSPLINK) +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} +#endif /* CFG_USE_DSPLINK */ + +int board_init(void) +{ + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + +#if !defined(CFG_USE_DSPLINK) + /* Powerup the DSP */ + dsp_on(); +#endif /* CFG_USE_DSPLINK */ + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +/* Read ethernet MAC address from Integrity data structure inside EEPROM. */ +int read_mac_address(uint8_t *buf) +{ + u_int32_t value, mac[2], address; + + /* Read Integrity data structure checkword. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + if (value != INTEGRITY_CHECKWORD_VALUE) + return 1; + + /* Read SYSCFG structure offset. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + address = 0x800 + (int) value; /* Address of SYSCFG structure. */ + + /* Read NET CONFIG structure offset. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, address, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + address = 0x800 + (int) value; /* Address of NET CONFIG structure. */ + address += 12; /* Address of NET INTERFACE CONFIG structure. */ + + /* Read NET INTERFACE CONFIG 2 structure offset. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, address, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE + * CONFIG 2 structure. */ + + /* Read MAC address. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, address, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8)) + goto err; + + buf[0] = mac[0] >> 24; + buf[1] = mac[0] >> 16; + buf[2] = mac[0] >> 8; + buf[3] = mac[0]; + buf[4] = mac[1] >> 24; + buf[5] = mac[1] >> 16; + + return 0; + +err: + printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); + return 1; +} + +/* Platform dependent initialisation. */ +int misc_init_r(void) +{ + int i; + u_int8_t i2cbuf; + u_int8_t env_enetaddr[6], eeprom_enetaddr[6]; + char *tmp = getenv("ethaddr"); + char *end; + int clk; + + /* EMIF-A CS3 configuration for FPGA. */ + REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2); + printf("DDR Clock: %dMHz\n", (clk / 2)); + + /* Configure I2C switch (PCA9543) to enable channel 0. */ + i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0; + if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, + CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) { + printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); + return 1; + } + + /* Read Ethernet MAC address from the U-Boot environment. */ + for (i = 0; i < 6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + /* Read Ethernet MAC address from EEPROM. */ + if (read_mac_address(eeprom_enetaddr) == 0) { + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && + memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) { + printf("\nWarning: MAC addresses don't match:\n"); + printf("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + eeprom_enetaddr[0], eeprom_enetaddr[1], + eeprom_enetaddr[2], eeprom_enetaddr[3], + eeprom_enetaddr[4], eeprom_enetaddr[5]); + printf("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + env_enetaddr[0], env_enetaddr[1], + env_enetaddr[2], env_enetaddr[3], + env_enetaddr[4], env_enetaddr[5]) ; + debug("### Set MAC addr from environment\n"); + memcpy(eeprom_enetaddr, env_enetaddr, 6); + } + if (!tmp) { + char ethaddr[20]; + + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + eeprom_enetaddr[0], eeprom_enetaddr[1], + eeprom_enetaddr[2], eeprom_enetaddr[3], + eeprom_enetaddr[4], eeprom_enetaddr[5]) ; + debug("### Set environment from HW MAC addr = \"%s\"\n", + ethaddr); + setenv("ethaddr", ethaddr); + } + } + + if (!eth_hw_init()) { + printf("Ethernet init failed\n"); + } else { + printf("ETH PHY: %s\n", phy.name); + } + + /* On this platform, U-Boot is copied in RAM by the UBL, + * so we are always in the relocated state. */ + gd->flags |= GD_FLG_RELOC; + + return(0); +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/atmel/at91sam9260ek/u-boot.lds b/board/davinci/sffsdr/u-boot.lds index 996f401f0b..a4fcd1a9bb 100644 --- a/board/atmel/at91sam9260ek/u-boot.lds +++ b/board/davinci/sffsdr/u-boot.lds @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -22,26 +22,21 @@ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { . = 0x00000000; - . = ALIGN(4); - .text : + .text : { cpu/arm926ejs/start.o (.text) *(.text) } - . = ALIGN(4); .rodata : { *(.rodata) } - . = ALIGN(4); .data : { *(.data) } - . = ALIGN(4); .got : { *(.got) } @@ -52,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss : { *(.bss) } + .bss (NOLOAD) : { *(.bss) } _end = .; } diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile index fa0013811d..579efe2623 100644 --- a/board/davinci/sonata/Makefile +++ b/board/davinci/sonata/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak *~ .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### # This is for $(obj).depend target diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index a13eeeb123..629dc317e0 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -27,7 +27,7 @@ #include <asm/mipsregs.h> #include <asm/io.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ @@ -52,7 +52,7 @@ int checkboard (void) *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - proc_id = read_32bit_cp0_register(CP0_PRID); + proc_id = read_c0_prid(); switch (proc_id >> 24) { case 0: diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 27b51f73f0..13e6bfcf33 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> diff --git a/board/delta/Makefile b/board/delta/Makefile index 7213328609..648e00c314 100644 --- a/board/delta/Makefile +++ b/board/delta/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/dnp1110/Makefile b/board/dnp1110/Makefile index a024e550aa..c56e9d1e81 100644 --- a/board/dnp1110/Makefile +++ b/board/dnp1110/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c index 2e3f51998e..385b498d09 100644 --- a/board/eXalion/eXalion.c +++ b/board/eXalion/eXalion.c @@ -52,7 +52,7 @@ int checkflash (void) return (0); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { int i, cnt; volatile uchar *base = CFG_SDRAM_BASE; diff --git a/board/eltec/bab7xx/Makefile b/board/eltec/bab7xx/Makefile index f4b0b07d96..1e76d25f7a 100644 --- a/board/eltec/bab7xx/Makefile +++ b/board/eltec/bab7xx/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c index 555475e4d9..af52352374 100644 --- a/board/eltec/bab7xx/bab7xx.c +++ b/board/eltec/bab7xx/bab7xx.c @@ -162,7 +162,7 @@ long int dram_size (int board_type) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return dram_size (board_type); } diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile index 5ab96233ff..24cbfeee39 100644 --- a/board/eltec/elppc/Makefile +++ b/board/eltec/elppc/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c index 108adb13d5..1b70605e28 100644 --- a/board/eltec/elppc/elppc.c +++ b/board/eltec/elppc/elppc.c @@ -104,7 +104,7 @@ long int dram_size (int board_type) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return dram_size (board_type); } diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index 0ffbdf0e57..3666791e98 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -251,7 +251,7 @@ int misc_init_r (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile index b257739b0f..86b887029f 100644 --- a/board/emk/top5200/Makefile +++ b/board/emk/top5200/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c index ccbd72a79b..27886261c7 100644 --- a/board/emk/top5200/top5200.c +++ b/board/emk/top5200/top5200.c @@ -32,7 +32,7 @@ * initialize SDRAM/DDRAM controller. * TBD: get data from I2C EEPROM *****************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c index 84afaaa2b2..aca4991f54 100644 --- a/board/emk/top860/top860.c +++ b/board/emk/top860/top860.c @@ -76,7 +76,7 @@ int checkboard (void) /***************************************************************************** * Initialize DRAM controller *****************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/ep7312/Makefile b/board/ep7312/Makefile index 45ee6cd084..776a444eed 100644 --- a/board/ep7312/Makefile +++ b/board/ep7312/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile index be7e213a9b..dc40d9b94a 100644 --- a/board/ep8248/Makefile +++ b/board/ep8248/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c index 69975caa2e..4cfb2acc85 100644 --- a/board/ep8248/ep8248.c +++ b/board/ep8248/ep8248.c @@ -208,7 +208,7 @@ int board_early_init_f (void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { vu_char *bcsr = (vu_char *)CFG_BCSR; long int msize = 16L << (bcsr[2] & 3); diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile index f75249fc6a..b8bf320347 100644 --- a/board/ep8260/Makefile +++ b/board/ep8260/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c index b9e1df43d7..0e43c6df97 100644 --- a/board/ep8260/ep8260.c +++ b/board/ep8260/ep8260.c @@ -243,7 +243,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/ep82xxm/Makefile b/board/ep82xxm/Makefile index 349be1f8dc..c69c475a8d 100644 --- a/board/ep82xxm/Makefile +++ b/board/ep82xxm/Makefile @@ -37,7 +37,7 @@ clean: rm -f $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c index 27443d3dfb..03baf0b59a 100644 --- a/board/ep82xxm/ep82xxm.c +++ b/board/ep82xxm/ep82xxm.c @@ -219,7 +219,7 @@ int board_early_init_f (void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* Size in MB of SDRAM populated on board*/ long int msize = 256; diff --git a/board/ep88x/Makefile b/board/ep88x/Makefile index b2ffd28833..6b3706daae 100644 --- a/board/ep88x/Makefile +++ b/board/ep88x/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c index 5f57f36bbf..92e5f0c12c 100644 --- a/board/ep88x/ep88x.c +++ b/board/ep88x/ep88x.c @@ -86,7 +86,7 @@ int board_early_init_f (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long int msize; volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; diff --git a/board/eric/Makefile b/board/eric/Makefile index f27fca6d7b..81a455202a 100644 --- a/board/eric/Makefile +++ b/board/eric/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/eric/eric.c b/board/eric/eric.c index 5413ae15c7..972d485b5a 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -31,6 +31,8 @@ #define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */ #define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */ +void sdram_init(void); + int board_early_init_f (void) { @@ -119,7 +121,7 @@ int checkboard (void) */ /* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #ifndef CONFIG_ERIC int i; @@ -127,6 +129,12 @@ long int initdram (int board_type) int TotalSize; #endif + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); #ifdef CONFIG_ERIC /* diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile index 4283300d89..0fadf814ef 100644 --- a/board/esd/adciop/Makefile +++ b/board/esd/adciop/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c index 7a11a12cef..0f655b78a5 100644 --- a/board/esd/adciop/adciop.c +++ b/board/esd/adciop/adciop.c @@ -79,7 +79,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile index c57cd6bb52..9114606557 100644 --- a/board/esd/apc405/Makefile +++ b/board/esd/apc405/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 2cb743ef49..83657c8d5d 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -423,7 +423,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile index 4d75868ea8..ba92b24c8d 100644 --- a/board/esd/ar405/Makefile +++ b/board/esd/ar405/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index dfead3363c..3abcfe690e 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -190,28 +190,6 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - #if 1 /* test-only: some internal test routines... */ /* diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile index 308f752d09..98acb4b771 100644 --- a/board/esd/ash405/Makefile +++ b/board/esd/ash405/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 8a5b03bced..25360a6565 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -207,7 +207,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/canbt/Makefile b/board/esd/canbt/Makefile index 4d75868ea8..ba92b24c8d 100644 --- a/board/esd/canbt/Makefile +++ b/board/esd/canbt/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 055a397730..30fa605abb 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -181,22 +181,3 @@ int checkboard (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile index 0d4ab2d13a..1093c52756 100644 --- a/board/esd/cms700/Makefile +++ b/board/esd/cms700/Makefile @@ -49,7 +49,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 3d4f2371d9..ba27c030b7 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -141,7 +141,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile index 2d4e189977..9a5607f695 100644 --- a/board/esd/cpci2dp/Makefile +++ b/board/esd/cpci2dp/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 36bf329f81..54de0b8062 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -117,7 +117,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index ce7876c414..3867bd809c 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 69cb8cef56..b856705ff9 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -495,7 +495,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile index 673a5b9662..4a640f6638 100644 --- a/board/esd/cpci5200/Makefile +++ b/board/esd/cpci5200/Makefile @@ -47,7 +47,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index adb8597e1c..20130acfe8 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -84,7 +84,7 @@ static void sdram_start(int hi_addr) * is something else than 0x00000000. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { ulong dramsize = 0; ulong test1, test2; diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index f43e83f491..a479f0f5f8 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -1602,7 +1602,7 @@ dram_size(long int *base, long int maxsize) /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ -long int +phys_size_t initdram(int board_type) { int s0 = 0, s1 = 0; diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile index 4d75868ea8..ba92b24c8d 100644 --- a/board/esd/cpciiser4/Makefile +++ b/board/esd/cpciiser4/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index fcb8cbbe73..204117edf5 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -186,7 +186,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile index 082236593a..d736af8b97 100644 --- a/board/esd/dasa_sim/Makefile +++ b/board/esd/dasa_sim/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c index 2f8ab1a478..fb0c77e566 100644 --- a/board/esd/dasa_sim/dasa_sim.c +++ b/board/esd/dasa_sim/dasa_sim.c @@ -206,7 +206,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile index df487662fd..86bd4461de 100644 --- a/board/esd/dp405/Makefile +++ b/board/esd/dp405/Makefile @@ -46,7 +46,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index 240ab78aa7..bb3baa477e 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -122,7 +122,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile index 4d75868ea8..ba92b24c8d 100644 --- a/board/esd/du405/Makefile +++ b/board/esd/du405/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 69432138d3..78ae4ba67b 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -200,7 +200,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile index e996a0a8c3..909d007c47 100644 --- a/board/esd/du440/Makefile +++ b/board/esd/du440/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile index 0e5e57a5ad..c57d90cf6f 100644 --- a/board/esd/hh405/Makefile +++ b/board/esd/hh405/Makefile @@ -44,7 +44,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 279d9214e2..802491a313 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -644,7 +644,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile index 308f752d09..98acb4b771 100644 --- a/board/esd/hub405/Makefile +++ b/board/esd/hub405/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 25c8068fde..03b87c9dfc 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -229,7 +229,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile index 45efdb0dec..3fbb909969 100644 --- a/board/esd/mecp5200/Makefile +++ b/board/esd/mecp5200/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c index ea49f264ab..6d776b7a63 100644 --- a/board/esd/mecp5200/mecp5200.c +++ b/board/esd/mecp5200/mecp5200.c @@ -84,7 +84,7 @@ static void sdram_start(int hi_addr) * is something else than 0x00000000. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { ulong dramsize = 0; ulong test1, test2; diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile index 99d87c44ff..edf3c56862 100644 --- a/board/esd/ocrtc/Makefile +++ b/board/esd/ocrtc/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 261b8a54d0..7b0edd5958 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -101,7 +101,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile index 53f217fb2a..862e88d39f 100644 --- a/board/esd/pci405/Makefile +++ b/board/esd/pci405/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index c4ab072009..f740d595be 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -358,7 +358,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile index 2e54315704..efd24feef8 100644 --- a/board/esd/pf5200/Makefile +++ b/board/esd/pf5200/Makefile @@ -48,7 +48,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index 48b80bfc5f..7970f8988f 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -84,7 +84,7 @@ static void sdram_start(int hi_addr) * is something else than 0x00000000. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { ulong dramsize = 0; ulong test1, test2; diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index 0e5e57a5ad..c57d90cf6f 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -44,7 +44,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 57762b54ee..fc71e9a2a1 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -232,7 +232,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile index 50d0963d26..12c1ba730c 100644 --- a/board/esd/pmc405/Makefile +++ b/board/esd/pmc405/Makefile @@ -46,7 +46,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 7499671aaf..326d560352 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -157,7 +157,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile index 68b566c4a6..8c09efae7b 100644 --- a/board/esd/pmc440/Makefile +++ b/board/esd/pmc440/Makefile @@ -44,7 +44,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index 624c45791f..c7294c9945 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -50,7 +50,7 @@ extern void denali_core_search_data_eye(void); * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) #if !defined(CONFIG_NAND_SPL) diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c index 16724005b7..fabb7464fd 100644 --- a/board/esd/tasreg/tasreg.c +++ b/board/esd/tasreg/tasreg.c @@ -77,7 +77,7 @@ int checkboard (void) { }; -long int initdram (int board_type) { +phys_size_t initdram (int board_type) { unsigned long junk = 0xa5a59696; /* diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile index 308f752d09..98acb4b771 100644 --- a/board/esd/voh405/Makefile +++ b/board/esd/voh405/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 87a584979b..52534220a7 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -305,7 +305,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile index df487662fd..86bd4461de 100644 --- a/board/esd/vom405/Makefile +++ b/board/esd/vom405/Makefile @@ -46,7 +46,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index 8be552e2ea..af8efcff3e 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -129,7 +129,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile index 308f752d09..98acb4b771 100644 --- a/board/esd/wuh405/Makefile +++ b/board/esd/wuh405/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index dba3ce8884..0590fc78f8 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -205,7 +205,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long val; diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c index 3959eead27..f3c8662cdb 100644 --- a/board/esteem192e/esteem192e.c +++ b/board/esteem192e/esteem192e.c @@ -101,7 +101,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c index 67375e9fea..763760fd23 100644 --- a/board/etin/debris/debris.c +++ b/board/etin/debris/debris.c @@ -53,7 +53,7 @@ int checkflash (void) } #endif -long int initdram (int board_type) +phys_size_t initdram (int board_type) { int m, row, col, bank, i; unsigned long start, end; diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c index de62fa0973..bfd6854c5d 100644 --- a/board/etin/kvme080/kvme080.c +++ b/board/etin/kvme080/kvme080.c @@ -93,7 +93,7 @@ unsigned long setdram(int m, int row, int col, int bank) return (1 << (col + row + 3) ) * bank * m; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { unsigned int msr; long int size = 0; diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c index eb58b5d529..7806519e30 100644 --- a/board/etx094/etx094.c +++ b/board/etx094/etx094.c @@ -125,7 +125,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/evb4510/Makefile b/board/evb4510/Makefile index 4f98d702d5..3ab1aa038b 100644 --- a/board/evb4510/Makefile +++ b/board/evb4510/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c index fae6d1090d..9ae4465441 100644 --- a/board/evb64260/sdram_init.c +++ b/board/evb64260/sdram_init.c @@ -524,7 +524,7 @@ static long int dram_size (long int *base, long int maxsize) /* U-Boot interface function to SDRAM init - this is where all the * controlling logic happens */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong checkbank[4] = {[0 ... 3] = 0 }; int bank_no; diff --git a/board/exbitgen/Makefile b/board/exbitgen/Makefile index 5e297afedc..4f752a86b4 100644 --- a/board/exbitgen/Makefile +++ b/board/exbitgen/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index 39a97225f8..dc07d3df06 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -1,8 +1,10 @@ +#include <common.h> #include <asm/u-boot.h> #include <asm/processor.h> -#include <common.h> #include "exbitgen.h" +void sdram_init(void); + /* ************************************************************************ */ int board_early_init_f (void) /* ------------------------------------------------------------------------ -- @@ -69,7 +71,7 @@ int checkboard (void) } /* ************************************************************************ */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) /* ------------------------------------------------------------------------ -- * Purpose : Determines size of mounted DRAM. * Remarks : Size is determined by reading SDRAM configuration registers as @@ -83,6 +85,13 @@ long int initdram (int board_type) ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c index ae88994b2c..4dd5382876 100644 --- a/board/exbitgen/flash.c +++ b/board/exbitgen/flash.c @@ -28,10 +28,10 @@ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com */ +#include <common.h> #include <asm/u-boot.h> #include <asm/processor.h> #include <ppc4xx.h> -#include <common.h> flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/fads/fads.c b/board/fads/fads.c index 8f5736b414..9e601df1bc 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -600,7 +600,7 @@ static int initsdram(uint base, uint *noMbytes) /* ========================================================================= */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { uint sdramsz = 0; /* size of sdram in Mbytes */ uint base = 0; /* base of dram in bytes */ diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c index 9c553676ec..7caedc99a3 100644 --- a/board/flagadm/flagadm.c +++ b/board/flagadm/flagadm.c @@ -96,7 +96,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 6340b418ea..508e3b569b 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -53,7 +53,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c index 98424c898b..e5f47d2d93 100644 --- a/board/freescale/m52277evb/m52277evb.c +++ b/board/freescale/m52277evb/m52277evb.c @@ -36,7 +36,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); u32 dramsize, i; diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index 585854cd91..c2c8fe8590 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -37,7 +37,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index e8f621ba3f..c9ed341bbd 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -49,7 +49,7 @@ int checkboard (void) { }; -long int initdram (int board_type) { +phys_size_t initdram (int board_type) { unsigned long junk = 0xa5a59696; /* diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index 43aa84de22..f80a47c7b7 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -34,7 +34,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { int i; diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile index 9a0fa80538..ef0b19ed2c 100644 --- a/board/freescale/m5275evb/Makefile +++ b/board/freescale/m5275evb/Makefile @@ -23,18 +23,22 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a OBJS = $(BOARD).o mii.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index a1b2902935..be19e02751 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -36,7 +36,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 242eb1a188..f9fa9fb9cf 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -37,7 +37,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); u32 dramsize, i; diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index 26b87b99f0..a269ee6d44 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -37,7 +37,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); u32 dramsize, i; diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 6a0278252f..0480b54685 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -37,7 +37,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c index 539da78de9..6d7d27090f 100644 --- a/board/freescale/m547xevb/m547xevb.c +++ b/board/freescale/m547xevb/m547xevb.c @@ -38,7 +38,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile siu_t *siu = (siu_t *) (MMAP_SIU); volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c index 0372807486..e6510c9559 100644 --- a/board/freescale/m548xevb/m548xevb.c +++ b/board/freescale/m548xevb/m548xevb.c @@ -38,7 +38,7 @@ int checkboard(void) return 0; }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile siu_t *siu = (siu_t *) (MMAP_SIU); volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); diff --git a/board/freescale/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile index e3d757d5dd..995afbcd5c 100644 --- a/board/freescale/mpc7448hpc2/Makefile +++ b/board/freescale/mpc7448hpc2/Makefile @@ -40,7 +40,7 @@ clean: .PHONY: distclean distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c index 81846eba77..b3d83cc19f 100644 --- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c +++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c @@ -31,10 +31,7 @@ #include <common.h> #include <74xx_7xx.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -extern void ft_cpu_setup (void *blob, bd_t *bd); -#endif +#include <fdt_support.h> #undef DEBUG @@ -84,24 +81,16 @@ long int dram_size (int board_type) return 0x20000000; /* 256M bytes */ } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return dram_size (board_type); } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void -ft_board_setup (void *blob, bd_t *bd) +ft_board_setup(void *blob, bd_t *bd) { - u32 *p; - int len; - - ft_cpu_setup (blob, bd); - - p = ft_get_prop (blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32 (bd->bi_memstart); - *p = cpu_to_be32 (bd->bi_memsize); - } + ft_cpu_setup(blob, bd); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif diff --git a/board/freescale/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile index de7d847a5f..e1d4af0f90 100644 --- a/board/freescale/mpc8260ads/Makefile +++ b/board/freescale/mpc8260ads/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c index 548d813af5..8ab7d356c4 100644 --- a/board/freescale/mpc8260ads/mpc8260ads.c +++ b/board/freescale/mpc8260ads/mpc8260ads.c @@ -46,6 +46,10 @@ #ifdef CONFIG_PCI #include <pci.h> #endif +#ifdef CONFIG_OF_LIBFDT +#include <libfdt.h> +#include <fdt_support.h> +#endif /* * I/O Port configuration table @@ -304,7 +308,7 @@ int board_early_init_f (void) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #if CONFIG_ADSTYPE == CFG_PQ2FADS long int msize = 32; @@ -544,3 +548,26 @@ void pci_init_board(void) pci_mpc8250_init(&hose); } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_blob_update(void *blob, bd_t *bd) +{ + int ret; + + ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + + if (ret < 0) { + printf("ft_blob_update(): cannot set /memory/reg " + "property err:%s\n", fdt_strerror(ret)); + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_blob_update(blob, bd); +} +#endif diff --git a/board/freescale/mpc8266ads/Makefile b/board/freescale/mpc8266ads/Makefile index 291a1c9566..4ffb83f783 100644 --- a/board/freescale/mpc8266ads/Makefile +++ b/board/freescale/mpc8266ads/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c index 8f7273c41d..090a534134 100644 --- a/board/freescale/mpc8266ads/mpc8266ads.c +++ b/board/freescale/mpc8266ads/mpc8266ads.c @@ -251,7 +251,7 @@ int checkboard(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* Autoinit part stolen from board/sacsng/sacsng.c */ volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile index e97ba812c9..7c34c5e164 100644 --- a/board/freescale/mpc8313erdb/Makefile +++ b/board/freescale/mpc8313erdb/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 16ec4bbf54..afd8b9d5ed 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -104,7 +104,7 @@ static long fixed_sdram(void) return msize; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CFG_IMMR; volatile lbus83xx_t *lbc = &im->lbus; diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile index e97ba812c9..7c34c5e164 100644 --- a/board/freescale/mpc8315erdb/Makefile +++ b/board/freescale/mpc8315erdb/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index f97e3c7804..07e6486eea 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -101,7 +101,7 @@ static long fixed_sdram(void) return msize; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CFG_IMMR; u32 msize; diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile index acc954488f..c95f90eaab 100644 --- a/board/freescale/mpc8323erdb/Makefile +++ b/board/freescale/mpc8323erdb/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index afc0eee3b7..f5220abdb0 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -73,7 +73,7 @@ int board_early_init_f(void) int fixed_sdram(void); -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile index 5ec7a871d4..a97116c391 100644 --- a/board/freescale/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index c10b30f24e..4ad6e9d454 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -94,7 +94,7 @@ int board_early_init_r(void) int fixed_sdram(void); -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile index 5ec7a871d4..a97116c391 100644 --- a/board/freescale/mpc8349emds/Makefile +++ b/board/freescale/mpc8349emds/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 6c825969d3..9a312c37b6 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -59,7 +59,7 @@ int board_early_init_f (void) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *im = (immap_t *)CFG_IMMR; u32 msize = 0; @@ -253,29 +253,28 @@ void sdram_init(void) /* * The following are used to control the SPI chip selects for the SPI command. */ -#ifdef CONFIG_HARD_SPI +#ifdef CONFIG_MPC8XXX_SPI #define SPI_CS_MASK 0x80000000 -void spi_eeprom_chipsel(int cs) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) { volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; - if (cs) - iopd->dat &= ~SPI_CS_MASK; - else - iopd->dat |= SPI_CS_MASK; + iopd->dat &= ~SPI_CS_MASK; } -/* - * The SPI command uses this table of functions for controlling the SPI - * chip selects. - */ -spi_chipsel_type spi_chipsel[] = { - spi_eeprom_chipsel, -}; -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + iopd->dat |= SPI_CS_MASK; +} #endif /* CONFIG_HARD_SPI */ #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile index 265e341037..c81ba662fa 100644 --- a/board/freescale/mpc8349itx/Makefile +++ b/board/freescale/mpc8349itx/Makefile @@ -37,7 +37,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 0317bfe6d4..d3fc560df3 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -128,7 +128,7 @@ volatile static struct pci_controller hose[] = { }; #endif /* CONFIG_PCI */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile index 5ec7a871d4..a97116c391 100644 --- a/board/freescale/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 2119320da7..5c3b5dbc93 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -122,7 +122,7 @@ extern void ddr_enable_ecc(unsigned int dram_size); int fixed_sdram(void); void sdram_init(void); -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile index 53e0c48276..d1735041f9 100644 --- a/board/freescale/mpc8360erdk/Makefile +++ b/board/freescale/mpc8360erdk/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 3bcdda7334..61d7000147 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -266,7 +266,7 @@ int fixed_sdram(void) return msize; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void ddr_enable_ecc(unsigned int dram_size); diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c index e1e790b34f..8b44a0f38c 100644 --- a/board/freescale/mpc8360erdk/nand.c +++ b/board/freescale/mpc8360erdk/nand.c @@ -39,6 +39,24 @@ static const u32 upm_array[] = { 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ }; +static void upm_setup(struct fsl_upm *upm) +{ + int i; + + /* write upm array */ + out_be32(upm->mxmr, MxMR_OP_WARR); + + for (i = 0; i < 64; i++) { + out_be32(upm->mdr, upm_array[i]); + out_8(upm->io_addr, 0x0); + } + + /* normal operation */ + out_be32(upm->mxmr, MxMR_OP_NORM); + while (in_be32(upm->mxmr) != MxMR_OP_NORM) + eieio(); +} + static int dev_ready(void) { if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { @@ -52,10 +70,9 @@ static int dev_ready(void) static struct fsl_upm_nand fun = { .upm = { - .array = upm_array, .io_addr = (void *)CFG_NAND_BASE, }, - .width = 1, + .width = 8, .upm_cmd_offset = 8, .upm_addr_offset = 16, .dev_ready = dev_ready, @@ -68,5 +85,8 @@ int board_nand_init(struct nand_chip *nand) fun.upm.mxmr = &im->lbus.mamr; fun.upm.mdr = &im->lbus.mdr; fun.upm.mar = &im->lbus.mar; + + upm_setup(&fun.upm); + return fsl_upm_nand_init(nand, &fun); } diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile index 5ec7a871d4..a97116c391 100644 --- a/board/freescale/mpc837xemds/Makefile +++ b/board/freescale/mpc837xemds/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 40a505b1d4..40f1e63281 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -75,7 +75,7 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile index 5ec7a871d4..a97116c391 100644 --- a/board/freescale/mpc837xerdb/Makefile +++ b/board/freescale/mpc837xerdb/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index f73fd5aa55..aaefc18991 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -64,7 +64,7 @@ void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -long int initdram(int board_type) +phys_size_t initdram(int board_type) { immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile index be243885be..2d71cbc516 100644 --- a/board/freescale/mpc8540ads/Makefile +++ b/board/freescale/mpc8540ads/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index 785576a35a..3b8bd05ad1 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index a951b9e9a3..4f068cc884 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -41,12 +41,6 @@ void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); - -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { puts("Board: ADS\n"); @@ -67,7 +61,7 @@ int checkboard (void) } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -230,42 +224,6 @@ sdram_init(void) udelay(100); } - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index 3ae2e97577..98f153056d 100644 --- a/board/freescale/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c index 0ac223c53c..fbf2bdc07f 100644 --- a/board/freescale/mpc8541cds/law.c +++ b/board/freescale/mpc8541cds/law.c @@ -47,12 +47,12 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 62c8d63cdc..3669ba95d3 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -196,11 +196,6 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -245,7 +240,7 @@ int checkboard (void) return 0; } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -425,45 +420,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 53368b22b8..3a5ea00e80 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c index 433e509fc0..a82dedea3b 100644 --- a/board/freescale/mpc8544ds/law.c +++ b/board/freescale/mpc8544ds/law.c @@ -28,15 +28,15 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(4, CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(6, CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(7, CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(8, CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), /* contains both PCIE3 MEM & IO space */ - SET_LAW_ENTRY(9, CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index dd10af8092..f615b2384a 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -40,11 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); void sdram_init(void); -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -64,7 +59,7 @@ int checkboard (void) return 0; } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -83,45 +78,6 @@ initdram(int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index 3ae2e97577..98f153056d 100644 --- a/board/freescale/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 0ee53e2c13..34b9d1c4df 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -52,21 +52,21 @@ struct law_entry law_table[] = { #ifdef CFG_PCI1_MEM_PHYS - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), #endif #ifdef CFG_PCI2_MEM_PHYS - SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), #endif #ifdef CFG_PCIE1_MEM_PHYS - SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(8, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), #ifdef CFG_RIO_MEM_PHYS - SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif }; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index efe2a3a3de..0b037cc697 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -45,11 +45,6 @@ DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); void sdram_init(void); -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -93,7 +88,7 @@ int checkboard (void) return 0; } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -250,45 +245,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index 3ae2e97577..98f153056d 100644 --- a/board/freescale/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c index 0ac223c53c..fbf2bdc07f 100644 --- a/board/freescale/mpc8555cds/law.c +++ b/board/freescale/mpc8555cds/law.c @@ -47,12 +47,12 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 8acbba4208..9a65101dd2 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -194,11 +194,6 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -243,7 +238,7 @@ int checkboard (void) return 0; } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -422,45 +417,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #ifdef CONFIG_PCI /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile index be243885be..2d71cbc516 100644 --- a/board/freescale/mpc8560ads/Makefile +++ b/board/freescale/mpc8560ads/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index 785576a35a..3b8bd05ad1 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 8d4b8a8b5a..2c14a880e0 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -212,12 +212,6 @@ typedef struct bcsr_ { volatile unsigned char bcsr5; } bcsr_t; - -int board_early_init_f (void) -{ - return 0; -} - void reset_phy (void) { #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ @@ -270,7 +264,7 @@ int checkboard (void) } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -433,42 +427,6 @@ sdram_init(void) udelay(100); } - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index 8294d3bf43..ecdc4d3c22 100644 --- a/board/freescale/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index 5e96ea73a2..3bc24c5c9b 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -50,13 +50,13 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ - SET_LAW_ENTRY(7, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 4568aa1df5..2ccff7d81e 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -140,7 +140,7 @@ int checkboard (void) return 0; } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -292,45 +292,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc8568mds_config_table[] = { diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index e17a9cb8e6..a457c32e86 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -41,7 +41,7 @@ clean: .PHONY: distclean distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index b4d222d1ae..91b922b86b 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -29,16 +29,16 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(8, CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(9, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) + SET_LAW(CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 3a855b5903..c85f373c1a 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -113,7 +113,7 @@ int checkboard(void) } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -141,42 +141,6 @@ initdram(int board_type) } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - puts("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index 115df0532b..c096e1552e 100644 --- a/board/freescale/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -39,7 +39,7 @@ clean: .PHONY: distclean distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 245f420576..2d6c3c1759 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -47,18 +47,18 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW((CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), #if !defined(CONFIG_SPD_EEPROM) - SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), #endif - SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index bb1f927b95..cf540fc651 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -53,7 +53,7 @@ int checkboard(void) } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -81,42 +81,6 @@ initdram(int board_type) } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - puts("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile index a9a9299a83..493422d390 100644 --- a/board/funkwerk/vovpn-gw/Makefile +++ b/board/funkwerk/vovpn-gw/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c index 9b5429afa5..1c3f627a44 100644 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -318,7 +318,7 @@ do_reset (void *cmdtp, int flag, int argc, char *argv[]) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #ifndef CFG_RAMBOOT volatile immap_t *immap; diff --git a/board/g2000/Makefile b/board/g2000/Makefile index 3c5aa8680a..1c60447e85 100644 --- a/board/g2000/Makefile +++ b/board/g2000/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 2dfd87c78e..647f4b705b 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -131,7 +131,7 @@ long int init_sdram_static_settings(void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long int ret; @@ -149,41 +149,6 @@ long int initdram (int board_type) } -#if 1 /* test-only */ -void sdram_init(void) -{ - init_sdram_static_settings(); -} -#endif - - -#if 0 /* test-only */ -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} -#endif - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/gaisler/gr_cpci_ax2000/Makefile b/board/gaisler/gr_cpci_ax2000/Makefile index d58f50d99f..4a5d73b47c 100644 --- a/board/gaisler/gr_cpci_ax2000/Makefile +++ b/board/gaisler/gr_cpci_ax2000/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c index d99b45523a..105a74714b 100644 --- a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c +++ b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c @@ -22,7 +22,7 @@ #include <config.h> #include <asm/leon.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return 1; } diff --git a/board/gaisler/gr_ep2s60/Makefile b/board/gaisler/gr_ep2s60/Makefile index d58f50d99f..4a5d73b47c 100644 --- a/board/gaisler/gr_ep2s60/Makefile +++ b/board/gaisler/gr_ep2s60/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c index e8617f0755..2904d32586 100644 --- a/board/gaisler/gr_ep2s60/gr_ep2s60.c +++ b/board/gaisler/gr_ep2s60/gr_ep2s60.c @@ -22,7 +22,7 @@ #include <config.h> #include <asm/leon.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return 1; } diff --git a/board/gaisler/gr_xc3s_1500/Makefile b/board/gaisler/gr_xc3s_1500/Makefile index d58f50d99f..4a5d73b47c 100644 --- a/board/gaisler/gr_xc3s_1500/Makefile +++ b/board/gaisler/gr_xc3s_1500/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c index 1ee7024812..fc8cf84f99 100644 --- a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c +++ b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c @@ -22,7 +22,7 @@ #include <config.h> #include <asm/leon.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return 1; } diff --git a/board/gaisler/grsim/Makefile b/board/gaisler/grsim/Makefile index 6295109563..56123dc07b 100644 --- a/board/gaisler/grsim/Makefile +++ b/board/gaisler/grsim/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gaisler/grsim/grsim.c b/board/gaisler/grsim/grsim.c index 70a2f23c55..deccd3d0e7 100644 --- a/board/gaisler/grsim/grsim.c +++ b/board/gaisler/grsim/grsim.c @@ -26,7 +26,7 @@ #include <common.h> #include <asm/leon.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return 1; } diff --git a/board/gaisler/grsim_leon2/Makefile b/board/gaisler/grsim_leon2/Makefile index 6295109563..56123dc07b 100644 --- a/board/gaisler/grsim_leon2/Makefile +++ b/board/gaisler/grsim_leon2/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gaisler/grsim_leon2/grsim_leon2.c b/board/gaisler/grsim_leon2/grsim_leon2.c index 55dfe8286a..61445fe254 100644 --- a/board/gaisler/grsim_leon2/grsim_leon2.c +++ b/board/gaisler/grsim_leon2/grsim_leon2.c @@ -26,7 +26,7 @@ #include <common.h> #include <asm/leon.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return 1; } diff --git a/board/gcplus/Makefile b/board/gcplus/Makefile index 8a95d83703..7bc636bb9c 100644 --- a/board/gcplus/Makefile +++ b/board/gcplus/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index 73cc16d479..e3d0e435d4 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -158,7 +158,7 @@ int checkboard (void) /* * Initialize SDRAM */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c index c75507f61d..fc2116967a 100644 --- a/board/genietv/genietv.c +++ b/board/genietv/genietv.c @@ -118,7 +118,7 @@ static void PrintState (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &im->im_memctl; diff --git a/board/gth/gth.c b/board/gth/gth.c index b1fcbf5cc3..788a6a0948 100644 --- a/board/gth/gth.c +++ b/board/gth/gth.c @@ -265,7 +265,7 @@ int initsdram (uint base, uint * noMbytes) #endif } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { u32 *i; u32 j; diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index 6da80dc758..cea65c677f 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -36,7 +36,7 @@ static int wdi_status = 0; #define SDRAM_SIZE ((64*1024*1024)-(12*4096)) -#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096)) +#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096)) void inline log_serial_char(char c){ char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; @@ -83,7 +83,7 @@ void hw_watchdog_reset(void){ } } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ @@ -135,7 +135,7 @@ int checkboard (void) *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - proc_id = read_32bit_cp0_register(CP0_PRID); + proc_id = read_c0_prid(); switch (proc_id >> 24) { case 0: diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S index bf615c1bb1..4c4f0ebd2d 100644 --- a/board/gth2/lowlevel_init.S +++ b/board/gth2/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile index 17012dd71d..cb3c566d31 100644 --- a/board/gw8260/Makefile +++ b/board/gw8260/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c index 2719a9585f..42c9e0d108 100644 --- a/board/gw8260/gw8260.c +++ b/board/gw8260/gw8260.c @@ -606,7 +606,7 @@ int testdram (void) /* */ /* */ /*********************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c index 8fd081fef3..f9b57204f0 100644 --- a/board/hermes/hermes.c +++ b/board/hermes/hermes.c @@ -134,7 +134,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c index daab8334ee..5713a3384f 100644 --- a/board/hidden_dragon/hidden_dragon.c +++ b/board/hidden_dragon/hidden_dragon.c @@ -44,7 +44,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/hmi1001/Makefile b/board/hmi1001/Makefile index ddfd2ef8af..442e2d0df2 100644 --- a/board/hmi1001/Makefile +++ b/board/hmi1001/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 8bdfe78e41..8cfd75bd83 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -80,7 +80,7 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index 13e60e2226..91aaab1b08 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -364,7 +364,7 @@ misc_init_f (void) /* ------------------------------------------------------------------------- */ -long +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; diff --git a/board/icecube/Makefile b/board/icecube/Makefile index 7762ed3015..c94e24fc6a 100644 --- a/board/icecube/Makefile +++ b/board/icecube/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 07ba2459d8..760db73687 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -134,7 +134,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -259,7 +259,7 @@ long int initdram (int board_type) #elif defined(CONFIG_MGT5100) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c index 8da9d1c9a4..18aa8bf6dd 100644 --- a/board/icu862/icu862.c +++ b/board/icu862/icu862.c @@ -94,7 +94,7 @@ static long int dram_size (long int, long int *, long int); /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 081c375335..4f073fc319 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -29,7 +29,7 @@ int checkboard (void) { return 0; }; -long int initdram (int board_type) { +phys_size_t initdram (int board_type) { int i; /* diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index 7176770f68..44fc79cd58 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -276,7 +276,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -334,7 +334,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); if (ret < 0) { - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } } diff --git a/board/impa7/Makefile b/board/impa7/Makefile index b64d85f751..4cb13b74ab 100644 --- a/board/impa7/Makefile +++ b/board/impa7/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/imx31_litekit/Makefile b/board/imx31_litekit/Makefile index ea8c8897a9..218d9684a1 100644 --- a/board/imx31_litekit/Makefile +++ b/board/imx31_litekit/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/imx31_litekit/lowlevel_init.S b/board/imx31_litekit/lowlevel_init.S index 9d96db8b48..0003a42424 100644 --- a/board/imx31_litekit/lowlevel_init.S +++ b/board/imx31_litekit/lowlevel_init.S @@ -62,9 +62,9 @@ lowlevel_init: REG 0x43FAC26C, 0 /* SDCLK */ REG 0x43FAC270, 0 /* CAS */ REG 0x43FAC274, 0 /* RAS */ - REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */ + REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ REG 0x43FAC284, 0 /* DQM3 */ - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */ + REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ REG 0x43FAC28C, 0 REG 0x43FAC290, 0 REG 0x43FAC294, 0 diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile index cb0e8e83f3..5ed2b4bd9f 100644 --- a/board/imx31_phycore/Makefile +++ b/board/imx31_phycore/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S index 70f30c0cd9..c5d6eb05fe 100644 --- a/board/imx31_phycore/lowlevel_init.S +++ b/board/imx31_phycore/lowlevel_init.S @@ -63,9 +63,9 @@ lowlevel_init: REG 0x43FAC26C, 0 /* SDCLK */ REG 0x43FAC270, 0 /* CAS */ REG 0x43FAC274, 0 /* RAS */ - REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */ + REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ REG 0x43FAC284, 0 /* DQM3 */ - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */ + REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ REG 0x43FAC28C, 0 REG 0x43FAC290, 0 REG 0x43FAC294, 0 diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index c624b3d82e..ac7ad8f292 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -53,7 +53,7 @@ static ulong max_sdram_size(void) return size; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; ulong size, max_size = 0; @@ -63,7 +63,7 @@ long int initdram(int board_type) /* Can't probe for RAM size unless we are running from Flash. */ - if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) + if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) { return max_sdram_size(); } diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index 08f7f211f7..fe525ec70e 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile index ddfd2ef8af..442e2d0df2 100644 --- a/board/inka4x0/Makefile +++ b/board/inka4x0/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 46074e4649..a2e35ff0f6 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -92,7 +92,7 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/innokom/Makefile b/board/innokom/Makefile index 71c6bba364..afae217242 100644 --- a/board/innokom/Makefile +++ b/board/innokom/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/integratorap/Makefile b/board/integratorap/Makefile index 505121e071..f78de3a100 100644 --- a/board/integratorap/Makefile +++ b/board/integratorap/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/integratorcp/Makefile b/board/integratorcp/Makefile index e15ef73e2f..9201accb26 100644 --- a/board/integratorcp/Makefile +++ b/board/integratorcp/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c index 9dd809b678..375cd4d266 100644 --- a/board/ip860/ip860.c +++ b/board/ip860/ip860.c @@ -137,7 +137,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile index 3a28f5caf0..877afde1ce 100644 --- a/board/iphase4539/Makefile +++ b/board/iphase4539/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c index 0ca9cf5137..e5d0254a12 100644 --- a/board/iphase4539/iphase4539.c +++ b/board/iphase4539/iphase4539.c @@ -193,7 +193,7 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/ispan/Makefile b/board/ispan/Makefile index b2ffd28833..6b3706daae 100644 --- a/board/ispan/Makefile +++ b/board/ispan/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c index d39b8cd533..12fb91fb8a 100644 --- a/board/ispan/ispan.c +++ b/board/ispan/ispan.c @@ -356,7 +356,7 @@ static int hwc_board_type (char **str) return id; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long maxsize = hwc_main_sdram_size(); diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c index 7927ea9a50..4882f0450d 100644 --- a/board/ivm/ivm.c +++ b/board/ivm/ivm.c @@ -159,7 +159,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; diff --git a/board/ixdp425/Makefile b/board/ixdp425/Makefile index 5d4feb0f70..efeb31dba7 100644 --- a/board/ixdp425/Makefile +++ b/board/ixdp425/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/jse/Makefile b/board/jse/Makefile index e858c83f73..6be03ac541 100644 --- a/board/jse/Makefile +++ b/board/jse/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/jse/init.S b/board/jse/init.S index 231cd1caf5..c564ed3c94 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -93,13 +93,3 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr - - -/*----------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: This function is called by cpu/ppc4xx/start.S code */ -/* to get the SDRAM initialized. */ -/*----------------------------------------------------------------------- */ - .globl sdram_init -sdram_init: - blr diff --git a/board/jse/sdram.c b/board/jse/sdram.c index 9060d979d0..8ba6c454fd 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -30,7 +30,7 @@ * in lib_ppc/board.c to initialize the memory and return what I * found. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { /* Configure the SDRAMS */ diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile index aed3af000f..aa80a71982 100644 --- a/board/jupiter/Makefile +++ b/board/jupiter/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index efdc333493..7913c75376 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -92,7 +92,7 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile index 0207d1222a..363f6657ee 100644 --- a/board/kb9202/Makefile +++ b/board/kb9202/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/korat/Makefile b/board/korat/Makefile index fa19e6feaa..df74774bf7 100644 --- a/board/korat/Makefile +++ b/board/korat/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 4e377a142b..66d618072d 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -137,7 +137,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c index cd9ed13d6d..f07ef18703 100644 --- a/board/kup/kup4x/kup4x.c +++ b/board/kup/kup4x/kup4x.c @@ -134,7 +134,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c index 417dbbb05b..46f4da9e66 100644 --- a/board/lantec/lantec.c +++ b/board/lantec/lantec.c @@ -109,7 +109,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/lart/Makefile b/board/lart/Makefile index cbc07bd88a..9eeaa990ba 100644 --- a/board/lart/Makefile +++ b/board/lart/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/linkstation/Makefile b/board/linkstation/Makefile index 8d92d8a6c7..8f4da0c978 100644 --- a/board/linkstation/Makefile +++ b/board/linkstation/Makefile @@ -31,7 +31,7 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(OBJS)) $(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### diff --git a/board/linkstation/linkstation.c b/board/linkstation/linkstation.c index f6bc0a958d..241cf032d8 100644 --- a/board/linkstation/linkstation.c +++ b/board/linkstation/linkstation.c @@ -50,7 +50,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE)); } diff --git a/board/logodl/Makefile b/board/logodl/Makefile index 0c88a6e590..0795b6b2af 100644 --- a/board/logodl/Makefile +++ b/board/logodl/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/lpc2292sodimm/Makefile b/board/lpc2292sodimm/Makefile index 18a95d7f9b..4eeb03258b 100644 --- a/board/lpc2292sodimm/Makefile +++ b/board/lpc2292sodimm/Makefile @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJTS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/lpd7a40x/Makefile b/board/lpd7a40x/Makefile index 0e302d961f..446fd5bb82 100644 --- a/board/lpd7a40x/Makefile +++ b/board/lpd7a40x/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile index 8e397b411c..65923070c4 100644 --- a/board/lubbock/Makefile +++ b/board/lubbock/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index c68978aa98..4a2d8e4a4f 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -192,7 +192,7 @@ int checkboard (void) } /*********************************************************************** -F* Function: long int initdram (int board_type) P*A*Z* +F* Function: phys_size_t initdram (int board_type) P*A*Z* * P* Parameters: int board_type P* - Usually type of the board - ignored here. @@ -209,7 +209,7 @@ D* Design: wd@denx.de C* Coding: wd@denx.de V* Verification: dzu@denx.de ***********************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile index 2a9357146c..5bb266f799 100644 --- a/board/lwmon5/Makefile +++ b/board/lwmon5/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index b63fbdc0cd..85795b7c2a 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -275,44 +275,6 @@ int checkboard(void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 36b51007ea..0a13831156 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -158,7 +158,7 @@ static void program_ecc(u32 start_address, * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* CL=3 */ diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile index b403095f16..c562c600a4 100644 --- a/board/m501sk/Makefile +++ b/board/m501sk/Makefile @@ -34,13 +34,13 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c index 9caad6325a..e089d5f02f 100644 --- a/board/m5271evb/m5271evb.c +++ b/board/m5271evb/m5271evb.c @@ -29,7 +29,7 @@ int checkboard (void) { return 0; }; -long int initdram (int board_type) { +phys_size_t initdram (int board_type) { int i; diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c index 6dcda4f254..d17cb2ef98 100644 --- a/board/m5272c3/m5272c3.c +++ b/board/m5272c3/m5272c3.c @@ -31,7 +31,7 @@ int checkboard (void) { return 0; }; -long int initdram (int board_type) { +phys_size_t initdram (int board_type) { volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); sdp->sdram_sdtr = 0xf539; diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c index 7d6d1d6231..50e5e77368 100644 --- a/board/m5282evb/m5282evb.c +++ b/board/m5282evb/m5282evb.c @@ -32,7 +32,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { u32 dramsize, i, dramclk; diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c index 9a9bf809ea..414d879193 100644 --- a/board/mbx8xx/mbx8xx.c +++ b/board/mbx8xx/mbx8xx.c @@ -304,7 +304,7 @@ static ulong get_ramsize (dimm_t * dimm) return size; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile index 5869119697..e6e81ce3c1 100644 --- a/board/mcc200/Makefile +++ b/board/mcc200/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index a4c4644b4c..77ee3d7ed7 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -96,7 +96,7 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/mgcoge/Makefile b/board/mgcoge/Makefile index 1a1424406f..d4087ccbb6 100644 --- a/board/mgcoge/Makefile +++ b/board/mgcoge/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mgcoge/mgcoge.c b/board/mgcoge/mgcoge.c index e7c3fa00c7..51b6dc6016 100644 --- a/board/mgcoge/mgcoge.c +++ b/board/mgcoge/mgcoge.c @@ -249,7 +249,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -307,7 +307,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, sizeof(memory_data)); if (ret < 0) - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } else { @@ -327,7 +327,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, sizeof(flash_data)); if (ret < 0) - printf("ft_blob_update): cannot set /localbus/ranges " + printf("ft_blob_update(): cannot set /localbus/ranges " "property err:%s\n", fdt_strerror(ret)); } else { @@ -341,7 +341,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, sizeof(uchar) * 6); if (ret < 0) - printf("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " + printf("ft_blob_update(): cannot set /soc/cpm/ethernet/mac-address " "property err:%s\n", fdt_strerror(ret)); } else { diff --git a/board/mgsuvd/mgsuvd.c b/board/mgsuvd/mgsuvd.c index e0123bfa50..c51ea7e76e 100644 --- a/board/mgsuvd/mgsuvd.c +++ b/board/mgsuvd/mgsuvd.c @@ -66,7 +66,7 @@ int checkboard (void) return (0); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -164,7 +164,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, sizeof(memory_data)); if (ret < 0) - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } else { @@ -180,7 +180,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, sizeof(flash_data)); if (ret < 0) - printf("ft_blob_update): cannot set /localbus/ranges " + printf("ft_blob_update(): cannot set /localbus/ranges " "property err:%s\n", fdt_strerror(ret)); } else { @@ -195,7 +195,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data, sizeof(brg_data)); if (ret < 0) - printf("ft_blob_update): cannot set /soc/cpm/brg-frequency " + printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency " "property err:%s\n", fdt_strerror(ret)); } else { @@ -209,7 +209,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, sizeof(uchar) * 6); if (ret < 0) - printf("ft_blob_update): cannot set /soc/cpm/scc/mac-address " + printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address " "property err:%s\n", fdt_strerror(ret)); } else { diff --git a/board/ml2/Makefile b/board/ml2/Makefile index 731e8fea11..2a9366656f 100644 --- a/board/ml2/Makefile +++ b/board/ml2/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ml2/init.S b/board/ml2/init.S index 80f98c5bd9..9064d3b669 100644 --- a/board/ml2/init.S +++ b/board/ml2/init.S @@ -28,7 +28,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/ml2/ml2.c b/board/ml2/ml2.c index f32e512d4f..981e1decda 100644 --- a/board/ml2/ml2.c +++ b/board/ml2/ml2.c @@ -53,7 +53,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return 32 * 1024 * 1024; } diff --git a/board/ml2/serial.c b/board/ml2/serial.c index 659314572a..c18815bf88 100644 --- a/board/ml2/serial.c +++ b/board/ml2/serial.c @@ -19,9 +19,9 @@ * */ +#include <common.h> #include <asm/u-boot.h> #include <asm/processor.h> -#include <common.h> #include <command.h> #include <configs/ML2.h> diff --git a/board/modnet50/Makefile b/board/modnet50/Makefile index 45141fd9e5..bee5a8668b 100644 --- a/board/modnet50/Makefile +++ b/board/modnet50/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile index 698ead195c..22ce8e64f2 100644 --- a/board/motionpro/Makefile +++ b/board/motionpro/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 68257b861d..3b34062226 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -132,7 +132,7 @@ static void sdram_start(int hi_addr) /* * Initalize SDRAM - configure SDRAM controller, detect memory size. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c index 7208a17c1a..f8f152976c 100644 --- a/board/mousse/mousse.c +++ b/board/mousse/mousse.c @@ -55,7 +55,7 @@ int checkflash (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return CFG_RAM_SIZE; } diff --git a/board/mp2usb/Makefile b/board/mp2usb/Makefile index 423d77da3b..67efd725db 100644 --- a/board/mp2usb/Makefile +++ b/board/mp2usb/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile index 28d6cb9976..325d6d5722 100644 --- a/board/mpc8540eval/Makefile +++ b/board/mpc8540eval/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c index 273ec5c06f..cfcd73e9e1 100644 --- a/board/mpc8540eval/law.c +++ b/board/mpc8540eval/law.c @@ -43,11 +43,11 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), #ifndef CONFIG_RAM_AS_FLASH - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 8328b3a062..1ac333c815 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -61,7 +61,7 @@ int checkboard (void) return (0); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index f8f4329f73..53bf846586 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -44,7 +44,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 3351b5b840..f00a871dfd 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -178,19 +178,6 @@ ext_bus_cntlr_init: nop /* pass2 DCR errata #8 */ blr -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 9e8f9bbdd4..cf0afd1add 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -620,7 +620,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index 82c97d6d5d..adeba69ee0 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 7893d61f16..475741d2af 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -149,7 +149,7 @@ extern void mem_test_reloc(void); /* * Get RAM size. */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { unsigned char board_rev; unsigned long reg; diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 72143f0911..590c7da5bb 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -47,7 +47,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 39f2ea534a..838432525d 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -175,19 +175,6 @@ nop /* pass2 DCR errata #8 */ blr -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 38286081ae..6cba892e78 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -608,7 +608,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; int i, ds; diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 209322e51c..10bcb3b0a7 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -44,7 +44,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile index 17ca17ec5b..9f8fb807ab 100644 --- a/board/mpr2/Makefile +++ b/board/mpr2/Makefile @@ -30,25 +30,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := mpr2.o +COBJS := mpr2.o SOBJS := lowlevel_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile index d1af93700e..18745ecff3 100644 --- a/board/ms7720se/Makefile +++ b/board/ms7720se/Makefile @@ -27,25 +27,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := ms7720se.o +COBJS := ms7720se.o SOBJS := lowlevel_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c index ad76c0b2c7..af62cdfd28 100644 --- a/board/ms7720se/ms7720se.c +++ b/board/ms7720se/ms7720se.c @@ -40,7 +40,6 @@ int checkboard(void) int board_init(void) { - return 0; } diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile index 6dec0136c2..b203b6d4c7 100644 --- a/board/ms7722se/Makefile +++ b/board/ms7722se/Makefile @@ -24,25 +24,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := ms7722se.o +COBJS := ms7722se.o SOBJS := lowlevel_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c index 0d3d55cf5c..cf02242299 100644 --- a/board/ms7722se/ms7722se.c +++ b/board/ms7722se/ms7722se.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 + * Copyright (C) 2007,2008 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * Copyright (C) 2007 @@ -43,7 +43,7 @@ int board_init(void) return 0; } -int dram_init (void) +int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -53,7 +53,7 @@ int dram_init (void) return 0; } -void led_set_state (unsigned short value) +void led_set_state(unsigned short value) { - *((volatile unsigned short *) LED_BASE) = (value & 0xFF); + writew(value & 0xFF, LED_BASE); } diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile index f81d56cb44..01ddf69201 100644 --- a/board/ms7750se/Makefile +++ b/board/ms7750se/Makefile @@ -19,25 +19,29 @@ # include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := ms7750se.o +COBJS := ms7750se.o SOBJS := lowlevel_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend -################################################################# +######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend -################################################################# +######################################################################### diff --git a/board/munices/Makefile b/board/munices/Makefile index 09c63c3ee4..5862bed5cc 100644 --- a/board/munices/Makefile +++ b/board/munices/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/munices/munices.c b/board/munices/munices.c index 395909d7cd..162f89c500 100644 --- a/board/munices/munices.c +++ b/board/munices/munices.c @@ -74,7 +74,7 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c index 4408b07c55..b2b70e756d 100644 --- a/board/musenki/musenki.c +++ b/board/musenki/musenki.c @@ -45,7 +45,7 @@ int checkflash (void) } #endif -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/mvblm7/Makefile b/board/mvblm7/Makefile new file mode 100644 index 0000000000..cfbecfbe8f --- /dev/null +++ b/board/mvblm7/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mvblm7/config.mk b/board/mvblm7/config.mk new file mode 100644 index 0000000000..1d85f4fd0e --- /dev/null +++ b/board/mvblm7/config.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFFF00000 diff --git a/board/mvblm7/fpga.c b/board/mvblm7/fpga.c new file mode 100644 index 0000000000..a60af019a7 --- /dev/null +++ b/board/mvblm7/fpga.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ACEX1K.h> +#include <command.h> +#include "fpga.h" +#include "mvblm7.h" + +#ifdef FPGA_DEBUG +#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) +#else +#define fpga_debug(fmt, args...) +#endif + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, + 0 +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + passive_serial, + Altera_EP2C20_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mvblm7_init_fpga(void) +{ + fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n", + gd->reloc_off); + fpga_init(gd->reloc_off); + fpga_add(fpga_altera, &cyclone2); + fpga_config_fn(0, 1, 0); + udelay(60); + + return 1; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("SET config : %s\n", assert ? "low" : "high"); + if (assert) + dvo |= FPGA_CONFIG; + else + dvo &= ~FPGA_CONFIG; + + if (flush) + gpio->dat = dvo; + + return assert; +} + +int fpga_done_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + udelay(10); + fpga_debug("CONF_DONE check ... "); + if (gpio->dat & FPGA_CONF_DONE) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_status_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + fpga_debug("STATUS check ... "); + if (gpio->dat & FPGA_STATUS) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); + if (assert_clk) + dvo |= FPGA_CCLK; + else + dvo &= ~FPGA_CCLK; + + if (flush) + gpio->dat = dvo; + + return assert_clk; +} + +static inline int _write_fpga(u8 val, int dump) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int i; + u32 dvo = gpio->dat; + + if (dump) + fpga_debug(" %02x -> ", val); + for (i = 0; i < 8; i++) { + dvo &= ~FPGA_CCLK; + gpio->dat = dvo; + dvo &= ~FPGA_DIN; + if (dump) + fpga_debug("%d ", val&1); + if (val & 1) + dvo |= FPGA_DIN; + gpio->dat = dvo; + dvo |= FPGA_CCLK; + gpio->dat = dvo; + val >>= 1; + } + if (dump) + fpga_debug("\n"); + + return 0; +} + +int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i], 0); + fpga_debug("\n"); + + return FPGA_SUCCESS; +} diff --git a/board/mvblm7/fpga.h b/board/mvblm7/fpga.h new file mode 100644 index 0000000000..19277eb05f --- /dev/null +++ b/board/mvblm7/fpga.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mvblm7_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/board/mvblm7/mvblm7.c b/board/mvblm7/mvblm7.c new file mode 100644 index 0000000000..b07f91393c --- /dev/null +++ b/board/mvblm7/mvblm7.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc83xx.h> +#include <asm/mpc8349_pci.h> +#include <pci.h> +#include <spi.h> +#include <asm/mmu.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + +#include "mvblm7.h" + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & + LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + + udelay(300); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return CFG_DDR_SIZE; +} + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram(); + + /* return total bus RAM size(bytes) */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + puts("Board: Matrix Vision mvBlueLYNX-M7\n"); + + return 0; +} + +u8 *dhcp_vendorex_prep(u8 *e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + ptr = getenv("dhcp_vendor-class-identifier"); + if (ptr) { + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + /* DHCP_CLIENT_IDENTIFIER = 61 */ + ptr = getenv("dhcp_client_id"); + if (ptr) { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + +u8 *dhcp_vendorex_proc(u8 *popt) +{ + return NULL; +} + +#ifdef CONFIG_HARD_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + iopd->dat &= ~MVBLM7_MMC_CS; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + iopd->dat |= ~MVBLM7_MMC_CS; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} + +#endif diff --git a/board/mvblm7/mvblm7.h b/board/mvblm7/mvblm7.h new file mode 100644 index 0000000000..03e9f4170a --- /dev/null +++ b/board/mvblm7/mvblm7.h @@ -0,0 +1,21 @@ +#ifndef __MVBC_H__ +#define __MVBC_H__ + +#define MV_GPIO + +#define FPGA_CONFIG 0x80000000 +#define FPGA_CCLK 0x40000000 +#define FPGA_DIN 0x20000000 +#define FPGA_STATUS 0x10000000 +#define FPGA_CONF_DONE 0x08000000 +#define MMC_CS 0x04000000 + +#define WD_WDI 0x00400000 +#define WD_TS 0x00200000 +#define MAN_RST 0x00100000 + +#define MV_GPIO_DAT (WD_TS) +#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS) +#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) + +#endif diff --git a/board/mvblm7/mvblm7_autoscript b/board/mvblm7/mvblm7_autoscript new file mode 100644 index 0000000000..ec6e34ef05 --- /dev/null +++ b/board/mvblm7/mvblm7_autoscript @@ -0,0 +1,37 @@ +echo +echo "==== running autoscript ====" +echo +setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} +setenv ramkernel setenv kernel_boot \${loadaddr} +setenv flashkernel setenv kernel_boot \${mv_kernel_addr} +setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} +setenv bootfromflash run flashkernel cpird ramparam bootdtb +setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} +setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 +setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup +setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel +setenv set_static_ip setenv ipaddr \${static_ipaddr} +setenv set_static_nm setenv netmask \${static_netmask} +setenv set_static_gw setenv gatewayip \${static_gateway} +setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} +setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs +if test ${autoscr_boot} != no; +then + if test ${netboot} = yes; + then + bootp + if test $? = 0; + then + echo "=== bootp succeeded -> netboot ===" + run set_ip + run getdtb rundtb bootfromnet ramparam bootdtb + else + echo "=== netboot failed ===" + fi + fi + run set_static_ip set_static_nm set_static_gw set_ip + echo "=== bootfromflash ===" + run cpdtb rundtb bootfromflash +else + echo "=== boot stopped with autoscr_boot no ===" +fi diff --git a/board/mvblm7/pci.c b/board/mvblm7/pci.c new file mode 100644 index 0000000000..ef34a6b453 --- /dev/null +++ b/board/mvblm7/pci.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#include <pci.h> +#include <mpc83xx.h> +#include <fpga.h> +#include "mvblm7.h" +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +int mvblm7_load_fpga(void) +{ + size_t data_size = 0; + void *fpga_data = NULL; + char *datastr = getenv("fpgadata"); + char *sizestr = getenv("fpgadatasize"); + + if (datastr) + fpga_data = (void *)simple_strtoul(datastr, NULL, 16); + if (sizestr) + data_size = (size_t)simple_strtoul(sizestr, NULL, 16); + + return fpga_load(0, fpga_data, data_size); +} + +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + char *s; + int i; + int warmboot; + int load_fpga; + volatile immap_t *immr; + volatile pcictrl83xx_t *pci_ctrl; + volatile gpio83xx_t *gpio; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + struct pci_region *reg[] = { pci_regions }; + + load_fpga = 1; + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) &immr->clk; + pci_ctrl = immr->pci_ctrl; + pci_law = immr->sysconf.pcilaw; + gpio = (volatile gpio83xx_t *)&immr->gpio[0]; + + s = getenv("skip_fpga"); + if (s) { + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); + load_fpga = 0; + } + + gpio->dat = MV_GPIO_DAT; + gpio->odr = MV_GPIO_ODE; + if (load_fpga) + gpio->dir = MV_GPIO_OUT; + else + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + + printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, + immr->sysconf.sicrl); + + mvblm7_init_fpga(); + if (load_fpga) + mvblm7_load_fpga(); + + /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ + clk->occr = 0xc0000000; + + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + + for (i = 0; i < 1000; ++i) + udelay(1000); + + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c index ee8f3e3015..a979102ab5 100644 --- a/board/mvblue/mvblue.c +++ b/board/mvblue/mvblue.c @@ -76,7 +76,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/mvs1/mvs1.c b/board/mvs1/mvs1.c index f8a8cb7578..58b84f5ae1 100644 --- a/board/mvs1/mvs1.c +++ b/board/mvs1/mvs1.c @@ -136,7 +136,7 @@ static void test_dram (unsigned long *start, unsigned long *end) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile index 14a8b81c96..b68b1bdd25 100644 --- a/board/mx1ads/Makefile +++ b/board/mx1ads/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile index 516a8b90f3..f81f7acd57 100644 --- a/board/mx1fs2/Makefile +++ b/board/mx1fs2/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/mx31ads/Makefile b/board/mx31ads/Makefile index dfadd9685c..a12f39174b 100644 --- a/board/mx31ads/Makefile +++ b/board/mx31ads/Makefile @@ -35,7 +35,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c index 707e4b97d1..657abc46d8 100644 --- a/board/nc650/nc650.c +++ b/board/nc650/nc650.c @@ -128,7 +128,7 @@ static long int dram_size (long int, long int *, long int); /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index 1072b3f88a..38eb7c8118 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -404,7 +404,7 @@ void check_ram(unsigned int addr, unsigned int size) } } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index 53df61edbb..6722d53927 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index dc526fcd7a..c144741822 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -121,15 +121,6 @@ void hcu_led_set(u32 value) } /* - * sdram_init - Dummy implementation for start.S, spd_sdram or initdram - * used for HCUx - */ -void sdram_init(void) -{ - return; -} - -/* * hcu_get_slot */ u32 hcu_get_slot(void) @@ -163,7 +154,7 @@ int misc_init_r(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { long dram_size = 0; u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER); diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 5ffae65ea1..445677104c 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 6b1b53a4d0..80e84aebb8 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -40,28 +40,6 @@ void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) - #define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -111,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); + mtdcr(memcfga, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(ddrcfgd); + val = mfdcr(memcfgd); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ @@ -221,7 +199,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned int dram_size = 0; diff --git a/board/netstal/mcu25/Makefile b/board/netstal/mcu25/Makefile index 53df61edbb..6722d53927 100644 --- a/board/netstal/mcu25/Makefile +++ b/board/netstal/mcu25/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 2b21444e2d..ed171bfeb0 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -128,15 +128,6 @@ void hcu_led_set(u32 value) } /* - * sdram_init - Dummy implementation for start.S, spd_sdram or initdram - * used for HCUx - */ -void sdram_init(void) -{ - return; -} - -/* * hcu_get_slot */ u32 hcu_get_slot(void) @@ -170,7 +161,7 @@ int misc_init_r(void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { unsigned int dram_size = 64*1024*1024; init_ppc405_sdram(dram_size); diff --git a/board/netstar/Makefile b/board/netstar/Makefile index 88da2b9483..8d911b845b 100644 --- a/board/netstar/Makefile +++ b/board/netstar/Makefile @@ -84,7 +84,7 @@ clean: $(obj)crcek.bin distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/netta/netta.c b/board/netta/netta.c index 5a75e53e0d..1183f33ef8 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -337,7 +337,7 @@ void check_ram(unsigned int addr, unsigned int size) } } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index b216c5a8ef..a97c14cee7 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -402,7 +402,7 @@ void check_ram(unsigned int addr, unsigned int size) } } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index 856b7769cd..4140bac861 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -245,7 +245,7 @@ int checkboard(void) #define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23)) #define MCR_MCLF_MASK MCR_MCLF(15) -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile index b5203775a8..2ffed99f7a 100644 --- a/board/ns9750dev/Makefile +++ b/board/ns9750dev/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c index 4a426ec498..18840ff48f 100644 --- a/board/nx823/nx823.c +++ b/board/nx823/nx823.c @@ -157,7 +157,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/o2dnt/Makefile b/board/o2dnt/Makefile index f356bd39c7..58afd7b659 100644 --- a/board/o2dnt/Makefile +++ b/board/o2dnt/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c index 81a27002f4..a4eed3a436 100644 --- a/board/o2dnt/o2dnt.c +++ b/board/o2dnt/o2dnt.c @@ -67,7 +67,7 @@ static void sdram_start (int hi_addr) * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/omap1510inn/Makefile b/board/omap1510inn/Makefile index fe4b8d6524..cd222dbc16 100644 --- a/board/omap1510inn/Makefile +++ b/board/omap1510inn/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/omap1610inn/Makefile b/board/omap1610inn/Makefile index c375bc1353..1adcad64e0 100644 --- a/board/omap1610inn/Makefile +++ b/board/omap1610inn/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile index 2f2645a76b..f39eef0adb 100644 --- a/board/omap2420h4/Makefile +++ b/board/omap2420h4/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/omap5912osk/Makefile b/board/omap5912osk/Makefile index 8e14c699d3..e9bb0ecd72 100644 --- a/board/omap5912osk/Makefile +++ b/board/omap5912osk/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/omap730p2/Makefile b/board/omap730p2/Makefile index 104ff4e912..0d7ae6145c 100644 --- a/board/omap730p2/Makefile +++ b/board/omap730p2/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c index 6cc3cc5a3e..b61d399512 100644 --- a/board/oxc/oxc.c +++ b/board/oxc/oxc.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #ifndef CFG_RAMBOOT long size; diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S index 98bb394acb..b145e438f0 100644 --- a/board/pb1x00/lowlevel_init.S +++ b/board/pb1x00/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index 536c9544f5..82e2613e2d 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -27,7 +27,7 @@ #include <asm/mipsregs.h> #include <asm/io.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ @@ -51,7 +51,7 @@ int checkboard (void) *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - proc_id = read_32bit_cp0_register(CP0_PRID); + proc_id = read_c0_prid(); switch (proc_id >> 24) { case 0: diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index 1148c6aa27..c1917c11b4 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -63,7 +63,7 @@ u32 pcippc2_sdram_size (void) return in32 (REG (CPC0, RGBAN1)); } -long initdram (int board_type) +phys_size_t initdram (int board_type) { return cpc710_ram_init (); } diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile index 2a3cfbe1b3..40446884c8 100644 --- a/board/pcs440ep/Makefile +++ b/board/pcs440ep/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 620000a229..f66f3f233e 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -537,7 +537,7 @@ void spd_ddr_init_hang (void) } } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; @@ -553,44 +553,6 @@ long int initdram (int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile index fef0eb3094..faa26911b8 100644 --- a/board/pleb2/Makefile +++ b/board/pleb2/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/pm520/Makefile b/board/pm520/Makefile index 7762ed3015..c94e24fc6a 100644 --- a/board/pm520/Makefile +++ b/board/pm520/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index 14c3f1d442..83d9bcd025 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -84,7 +84,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -187,7 +187,7 @@ long int initdram (int board_type) #elif defined(CONFIG_MGT5100) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c index 1420e649d2..7ee3ab65c0 100644 --- a/board/pm826/pm826.c +++ b/board/pm826/pm826.c @@ -279,7 +279,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c index 98cd80bc8d..6038e9758d 100644 --- a/board/pm828/pm828.c +++ b/board/pm828/pm828.c @@ -312,7 +312,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/pm854/Makefile b/board/pm854/Makefile index be243885be..2d71cbc516 100644 --- a/board/pm854/Makefile +++ b/board/pm854/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/pm854/law.c b/board/pm854/law.c index cb6b37f95d..d74d17abdf 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 5d3252573e..555f6c0caa 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -71,7 +71,7 @@ int checkboard (void) } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; diff --git a/board/pm856/Makefile b/board/pm856/Makefile index be243885be..2d71cbc516 100644 --- a/board/pm856/Makefile +++ b/board/pm856/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/pm856/law.c b/board/pm856/law.c index cb6b37f95d..d74d17abdf 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 6386abcd3f..bf325f89ef 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -225,7 +225,7 @@ int checkboard (void) } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c index b2f348d4d6..d905b2965c 100644 --- a/board/pn62/pn62.c +++ b/board/pn62/pn62.c @@ -75,7 +75,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile index 5fbefeb71c..22332fb3dc 100644 --- a/board/ppmc7xx/Makefile +++ b/board/ppmc7xx/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c index 402ac5e201..061e01ec4f 100644 --- a/board/ppmc7xx/ppmc7xx.c +++ b/board/ppmc7xx/ppmc7xx.c @@ -29,7 +29,7 @@ extern void _start_warm(void); * the SDRAM was already initialised by board_asm_init (see init.S) so we just * return the size of RAM. */ -long initdram( int board_type ) +phys_size_t initdram( int board_type ) { return CFG_SDRAM_SIZE; } diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile index 7fd545b9d5..1d56d16183 100644 --- a/board/ppmc8260/Makefile +++ b/board/ppmc8260/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c index 2b20c26f17..f3c85096b3 100644 --- a/board/ppmc8260/ppmc8260.c +++ b/board/ppmc8260/ppmc8260.c @@ -199,7 +199,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile index 00dc180bbd..ef3accbf18 100644 --- a/board/prodrive/alpr/Makefile +++ b/board/prodrive/alpr/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 287f32e587..8d60936881 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -132,36 +132,6 @@ int checkboard (void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile index bf74a5a83b..8456df3630 100644 --- a/board/prodrive/p3mx/Makefile +++ b/board/prodrive/p3mx/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c index 0464860424..d881d38079 100644 --- a/board/prodrive/p3mx/sdram_init.c +++ b/board/prodrive/p3mx/sdram_init.c @@ -160,7 +160,7 @@ long int dram_size (long int *base, long int maxsize) #define SDRAM_NOP 0x5 #define SDRAM_SELF_REFRESH 0x7 -long int initdram (int board_type) +phys_size_t initdram (int board_type) { int tmp; int start; diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile index 261e5d49cc..b93f2c3890 100644 --- a/board/prodrive/p3p440/Makefile +++ b/board/prodrive/p3p440/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/prodrive/pdnb3/Makefile b/board/prodrive/pdnb3/Makefile index 096db6f7af..d07f25f981 100644 --- a/board/prodrive/pdnb3/Makefile +++ b/board/prodrive/pdnb3/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile index 3639cbaf58..301b4a0a5d 100644 --- a/board/psyent/pci5441/Makefile +++ b/board/psyent/pci5441/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c index ea80dd1395..0afef6f967 100644 --- a/board/psyent/pci5441/pci5441.c +++ b/board/psyent/pci5441/pci5441.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile index 2568a68ede..e23a17bc31 100644 --- a/board/psyent/pk1c20/Makefile +++ b/board/psyent/pk1c20/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c index 1924ae3d17..95b48bc57b 100644 --- a/board/psyent/pk1c20/pk1c20.c +++ b/board/psyent/pk1c20/pk1c20.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S index b9d03fc15e..1bd3edb815 100644 --- a/board/purple/lowlevel_init.S +++ b/board/purple/lowlevel_init.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #define MC_IOGP 0xBF800800 diff --git a/board/purple/purple.c b/board/purple/purple.c index 89cb906972..9775591129 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size) while (p4 < 32 && done == 0) { WRITE_MC_IOGP_1; - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size); + for (addr = CKSEG1 + 0x4000; + addr < CKSEG1ADDR (size); addr = addr + 4) { *(uint *) addr = 0xaa55aa55; } pass = 1; - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size) && pass == 1; + for (addr = CKSEG1 + 0x4000; + addr < CKSEG1ADDR (size) && pass == 1; addr = addr + 4) { if (*(uint *) addr != 0xaa55aa55) pass = 0; @@ -124,7 +124,7 @@ static void sdram_timing_init (ulong size) } } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* The only supported number of SDRAM banks is 4. */ @@ -138,7 +138,7 @@ long int initdram(int board_type) ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; void (* sdram_init) (ulong); - sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); + sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init); sdram_init(0x10000); @@ -260,14 +260,14 @@ void copy_code (ulong dest_addr) /* flush caches */ - start = KSEG0; + start = CKSEG0; end = start + CFG_DCACHE_SIZE; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); start += CFG_CACHELINE_SIZE; } - start = KSEG0; + start = CKSEG0; end = start + CFG_ICACHE_SIZE; while(start < end) { cache_unroll(start,Index_Invalidate_I); diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile index 32399f0e94..4892b42bc1 100644 --- a/board/pxa255_idp/Makefile +++ b/board/pxa255_idp/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S index 836e0271a1..b0f7072701 100644 --- a/board/qemu-mips/lowlevel_init.S +++ b/board/qemu-mips/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/mipsregs.h> diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c index 68690743d6..7a69a00f99 100644 --- a/board/qemu-mips/qemu-mips.c +++ b/board/qemu-mips/qemu-mips.c @@ -26,7 +26,7 @@ #include <asm/mipsregs.h> #include <asm/io.h> -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ @@ -38,7 +38,7 @@ int checkboard(void) u32 proc_id; u32 config1; - proc_id = read_32bit_cp0_register(CP0_PRID); + proc_id = read_c0_prid(); printf("Board: Qemu -M mips CPU: "); switch (proc_id) { case 0x00018000: @@ -51,7 +51,7 @@ int checkboard(void) printf("4KEc"); break; case 0x00019300: - config1 = read_mips32_cp0_config1(); + config1 = read_c0_config1(); if (config1 & 1) printf("24Kf"); else @@ -64,7 +64,7 @@ int checkboard(void) printf("R4000"); break; case 0x00018100: - config1 = read_mips32_cp0_config1(); + config1 = read_c0_config1(); if (config1 & 1) printf("5Kf"); else diff --git a/board/quad100hd/Makefile b/board/quad100hd/Makefile new file mode 100644 index 0000000000..f9db112e7c --- /dev/null +++ b/board/quad100hd/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o nand.o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/quad100hd/config.mk b/board/quad100hd/config.mk new file mode 100644 index 0000000000..1bdf5e4fcf --- /dev/null +++ b/board/quad100hd/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c new file mode 100644 index 0000000000..a36b89dd79 --- /dev/null +++ b/board/quad100hd/nand.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#if defined(CONFIG_CMD_NAND) +#include <asm/gpio.h> +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd) +{ + switch(cmd) { + case NAND_CTL_SETCLE: + gpio_write_bit(CFG_NAND_CLE, 1); + break; + case NAND_CTL_CLRCLE: + gpio_write_bit(CFG_NAND_CLE, 0); + break; + + case NAND_CTL_SETALE: + gpio_write_bit(CFG_NAND_ALE, 1); + break; + case NAND_CTL_CLRALE: + gpio_write_bit(CFG_NAND_ALE, 0); + break; + + case NAND_CTL_SETNCE: + gpio_write_bit(CFG_NAND_CE, 0); + break; + case NAND_CTL_CLRNCE: + gpio_write_bit(CFG_NAND_CE, 1); + break; + } +} + +static int quad100hd_nand_ready(struct mtd_info *mtd) +{ + return gpio_read_in_bit(CFG_NAND_RDY); +} + +/* + * Main initialization routine + */ +int board_nand_init(struct nand_chip *nand) +{ + /* Set address of hardware control function */ + nand->hwcontrol = quad100hd_hwcontrol; + nand->dev_ready = quad100hd_nand_ready; + nand->eccmode = NAND_ECC_SOFT; + /* 15 us command delay time */ + nand->chip_delay = 20; + + /* Return happy */ + return 0; +} +#endif /* CONFIG_CMD_NAND */ diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c new file mode 100644 index 0000000000..81186782b2 --- /dev/null +++ b/board/quad100hd/quad100hd.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * Based in part on board/icecube/icecube.c from PPCBoot + * (C) Copyright 2003 Intrinsyc Software + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <environment.h> +#include <logbuff.h> +#include <post.h> + +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* taken from PPCBoot */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); + mtdcr(uicpr, 0xFFFF7FFE); /* set int polarities */ + mtdcr(uictr, 0x00000000); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + + mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */ + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); +#ifdef DISPLAY_BOARD_INFO + sys_info_t sysinfo; +#endif + + puts("Board: Quad100hd"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + +#ifdef DISPLAY_BOARD_INFO + /* taken from ppcboot */ + get_sys_info(&sysinfo); + + printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz); + printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv * + 1000000)); + printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000); +#endif + + return 0; +} + +phys_size_t initdram(int board_type) +{ + return CFG_SDRAM_SIZE; +} diff --git a/board/quad100hd/u-boot.lds b/board/quad100hd/u-boot.lds new file mode 100644 index 0000000000..195d91b712 --- /dev/null +++ b/board/quad100hd/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c index afa6e113d8..345f127b63 100644 --- a/board/quantum/quantum.c +++ b/board/quantum/quantum.c @@ -102,7 +102,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile index ed609ea67e..e96a8aa986 100644 --- a/board/r2dplus/Makefile +++ b/board/r2dplus/Makefile @@ -19,25 +19,29 @@ # include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := r2dplus.o +COBJS := r2dplus.o SOBJS := lowlevel_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend -################################################################# +######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend -################################################################# +######################################################################### diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c index 2ee3ea2f3f..8fb8ff667a 100644 --- a/board/r2dplus/r2dplus.c +++ b/board/r2dplus/r2dplus.c @@ -24,6 +24,7 @@ #include <common.h> #include <ide.h> #include <asm/processor.h> +#include <asm/io.h> #include <asm/pci.h> int checkboard(void) @@ -37,7 +38,7 @@ int board_init(void) return 0; } -int dram_init (void) +int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -52,25 +53,26 @@ int board_late_init(void) return 0; } -#define FPGA_BASE 0xA4000000 -#define FPGA_CFCTL (FPGA_BASE + 0x04) -#define FPGA_CFPOW (FPGA_BASE + 0x06) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) +#define FPGA_BASE 0xA4000000 +#define FPGA_CFCTL (FPGA_BASE + 0x04) +#define CFCTL_EN (0x432) +#define FPGA_CFPOW (FPGA_BASE + 0x06) +#define CFPOW_ON (0x02) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) +#define CFCDINTCLR_EN (0x01) -void ide_set_reset (int idereset) +void ide_set_reset(int idereset) { /* if reset = 1 IDE reset will be asserted */ - if (idereset){ - (*(vu_short *)FPGA_CFCTL) = 0x432; - (*(vu_short *)FPGA_CFPOW) |= 0x02; - (*(vu_short *)FPGA_CFCDINTCLR) = 0x01; + if (idereset) { + outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */ + outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */ + outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */ } } -#if defined(CONFIG_PCI) static struct pci_controller hose; void pci_init_board(void) { - pci_sh7751_init( &hose ); + pci_sh7751_init(&hose); } -#endif /* CONFIG_PCI */ diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c index ffb4c0ecf9..c51e412f46 100644 --- a/board/r360mpi/r360mpi.c +++ b/board/r360mpi/r360mpi.c @@ -103,7 +103,7 @@ static long int dram_size (long int, long int *, long int); /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/r7780mp/Makefile b/board/r7780mp/Makefile index 554dca1d5f..c100e7e2ad 100644 --- a/board/r7780mp/Makefile +++ b/board/r7780mp/Makefile @@ -20,25 +20,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := r7780mp.o +COBJS := r7780mp.o SOBJS := lowlevel_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c index 1a37711d6f..19c35d3494 100644 --- a/board/r7780mp/r7780mp.c +++ b/board/r7780mp/r7780mp.c @@ -38,12 +38,12 @@ int checkboard(void) int board_init(void) { /* SCIF Enable */ - *(vu_short*)PHCR = 0x0000; + writew(0x0, PHCR); return 0; } -int dram_init (void) +int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -53,29 +53,27 @@ int dram_init (void) return 0; } -void led_set_state (unsigned short value) +void led_set_state(unsigned short value) { } -void ide_set_reset (int idereset) +void ide_set_reset(int idereset) { /* if reset = 1 IDE reset will be asserted */ - if (idereset){ - (*(vu_short *)FPGA_CFCTL) = 0x432; + if (idereset) { + writew(0x432, FPGA_CFCTL); #if defined(CONFIG_R7780MP) - (*(vu_short *)FPGA_CFPOW) |= 0x01; + writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); #else - (*(vu_short *)FPGA_CFPOW) |= 0x02; + writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); #endif - (*(vu_short *)FPGA_CFCDINTCLR) = 0x01; + writew(0x01, FPGA_CFCDINTCLR); } } -#if defined(CONFIG_PCI) static struct pci_controller hose; void pci_init_board(void) { - pci_sh7780_init( &hose ); + pci_sh7780_init(&hose); } -#endif diff --git a/board/rattler/Makefile b/board/rattler/Makefile index be7e213a9b..dc40d9b94a 100644 --- a/board/rattler/Makefile +++ b/board/rattler/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c index be7977dec4..ad75c21561 100644 --- a/board/rattler/rattler.c +++ b/board/rattler/rattler.c @@ -185,7 +185,7 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -long int initdram(int board_type) +phys_size_t initdram(int board_type) { long int msize = CFG_SDRAM_SIZE; diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c index 9e60c2b646..5b62af6146 100644 --- a/board/rbc823/rbc823.c +++ b/board/rbc823/rbc823.c @@ -142,7 +142,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c index 8cb03c7f84..e22dc52587 100644 --- a/board/rmu/rmu.c +++ b/board/rmu/rmu.c @@ -92,7 +92,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile index 4b0dc25d57..a749e26cce 100644 --- a/board/rpxsuper/Makefile +++ b/board/rpxsuper/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c index b4331f1cde..f633c5c476 100644 --- a/board/rpxsuper/rpxsuper.c +++ b/board/rpxsuper/rpxsuper.c @@ -225,7 +225,7 @@ int checkboard(void) /* ------------------------------------------------------------------------- */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c index 312d4b8605..eeec3b4dcd 100644 --- a/board/rsdproto/rsdproto.c +++ b/board/rsdproto/rsdproto.c @@ -282,7 +282,7 @@ int misc_init_f (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile index 9bb9c15525..de8a5b2a0d 100644 --- a/board/sacsng/Makefile +++ b/board/sacsng/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c index 25209e0546..c00f14ee60 100644 --- a/board/sacsng/sacsng.c +++ b/board/sacsng/sacsng.c @@ -22,8 +22,8 @@ * MA 02111-1307 USA */ -#include <asm/u-boot.h> #include <common.h> +#include <asm/u-boot.h> #include <ioports.h> #include <mpc8260.h> #include <i2c.h> @@ -159,7 +159,7 @@ int checkboard(void) /* ------------------------------------------------------------------------- */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -842,37 +842,30 @@ void show_boot_progress (int status) #define SPI_ADC_CS_MASK 0x00000800 #define SPI_DAC_CS_MASK 0x00001000 -void spi_adc_chipsel(int cs) +static const u32 cs_mask[] = { + SPI_ADC_CS_MASK, + SPI_DAC_CS_MASK, +}; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); +} + +void spi_cs_activate(struct spi_slave *slave) { volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); - if(cs) - iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */ - else - iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */ + iopd->pdat &= ~cs_mask[slave->cs]; } -void spi_dac_chipsel(int cs) +void spi_cs_deactivate(struct spi_slave *slave) { volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); - if(cs) - iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */ - else - iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */ + iopd->pdat |= cs_mask[slave->cs]; } -/* - * The SPI command uses this table of functions for controlling the SPI - * chip selects: it calls the appropriate function to control the SPI - * chip selects. - */ -spi_chipsel_type spi_chipsel[] = { - spi_adc_chipsel, - spi_dac_chipsel -}; -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); - #endif #endif /* CONFIG_MISC_INIT_R */ diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 8a831fa35f..51b1c75140 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -200,7 +200,7 @@ void sbcommon_fans(void) * Initialize sdram * ************************************************************************/ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile index 3b094ce1d4..49d240c4ca 100644 --- a/board/sandburst/karef/Makefile +++ b/board/sandburst/karef/Makefile @@ -56,7 +56,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile index c143e5e8ca..eb149108ac 100644 --- a/board/sandburst/metrobox/Makefile +++ b/board/sandburst/metrobox/Makefile @@ -54,7 +54,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend *~ + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c index aeb10a7434..7429647b80 100644 --- a/board/sandpoint/sandpoint.c +++ b/board/sandpoint/sandpoint.c @@ -50,7 +50,7 @@ int checkflash (void) } #endif -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/sbc2410x/Makefile b/board/sbc2410x/Makefile index a68c3832af..95f2ad120d 100644 --- a/board/sbc2410x/Makefile +++ b/board/sbc2410x/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile index 3c5aa8680a..1c60447e85 100644 --- a/board/sbc405/Makefile +++ b/board/sbc405/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index 0ae6d0ba45..7818cd7e55 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -96,7 +96,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return spd_sdram (); } diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c index 8a52f67418..175720d906 100644 --- a/board/sbc8240/sbc8240.c +++ b/board/sbc8240/sbc8240.c @@ -45,7 +45,7 @@ int checkboard (void) return 0; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { long size; long new_bank0_end; diff --git a/board/sbc8260/Makefile b/board/sbc8260/Makefile index 422dbc7139..034a55169c 100644 --- a/board/sbc8260/Makefile +++ b/board/sbc8260/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c index 48aefa010e..5781f6281b 100644 --- a/board/sbc8260/sbc8260.c +++ b/board/sbc8260/sbc8260.c @@ -208,7 +208,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile index 02cf569b5b..fd6bb2d29a 100644 --- a/board/sbc8349/Makefile +++ b/board/sbc8349/Makefile @@ -37,7 +37,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index e89b6e8248..4a44fda31e 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -52,7 +52,7 @@ int board_early_init_f (void) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *im = (immap_t *)CFG_IMMR; u32 msize = 0; diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index 4b2a9f61bc..bb96d95a3a 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index bcf3468ba6..ab54260b06 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -46,12 +46,12 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 9c8c6733f7..91b40e59f0 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -81,7 +81,7 @@ int checkboard (void) return 0; } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile index 4b2a9f61bc..bb96d95a3a 100644 --- a/board/sbc8560/Makefile +++ b/board/sbc8560/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c index e370853e96..10dedb481c 100644 --- a/board/sbc8560/law.c +++ b/board/sbc8560/law.c @@ -51,10 +51,10 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 8df4f3a975..2946ca1055 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -257,7 +257,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile index 115df0532b..c096e1552e 100644 --- a/board/sbc8641d/Makefile +++ b/board/sbc8641d/Makefile @@ -39,7 +39,7 @@ clean: .PHONY: distclean distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index d403873d9e..801c5b75f7 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -44,15 +44,15 @@ struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, 0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(6, CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(7, 0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), - SET_LAW_ENTRY(9, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), + SET_LAW(CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 519f332784..c724effa06 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -57,7 +57,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; diff --git a/board/sc3/Makefile b/board/sc3/Makefile index 4cc2b4171c..88989bd1c3 100644 --- a/board/sc3/Makefile +++ b/board/sc3/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index fbdc1d769c..3d1a6542dc 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -579,7 +579,7 @@ static int printSDRAMConfig(char reg, unsigned long cr) static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf}; #endif -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned int mems=0; unsigned long ul1; diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile index e19be51c30..0d2800d5e4 100644 --- a/board/sc520_cdp/Makefile +++ b/board/sc520_cdp/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile index 226c756bf4..e04172e3b9 100644 --- a/board/sc520_spunk/Makefile +++ b/board/sc520_spunk/Makefile @@ -42,7 +42,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile index 85b6b0474c..3bac4776d7 100644 --- a/board/scb9328/Makefile +++ b/board/scb9328/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sh7763rdp/Makefile b/board/sh7763rdp/Makefile new file mode 100644 index 0000000000..62a683d57f --- /dev/null +++ b/board/sh7763rdp/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2008 Renesas Solutions Corp. +# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +# Copyright (C) 2007 Kenati Technologies, Inc. +# +# board/sh7763rdp/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sh7763rdp.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sh7763rdp/config.mk b/board/sh7763rdp/config.mk new file mode 100644 index 0000000000..c52dbfd7b0 --- /dev/null +++ b/board/sh7763rdp/config.mk @@ -0,0 +1,11 @@ +# +# board/sh7763rdp/config.mk +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 + +# PLATFORM_CPPFLAGS += -DCONFIG_MULTIBOOT diff --git a/board/sh7763rdp/lowlevel_init.S b/board/sh7763rdp/lowlevel_init.S new file mode 100644 index 0000000000..2a44eee1ad --- /dev/null +++ b/board/sh7763rdp/lowlevel_init.S @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * Copyright (C) 2007 Kenati Technologies, Inc. + * + * board/sh7763rdp/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ + mov.l WDTCSR_D, r0 + mov.l r0, @r1 + + mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ + mov.l WDTST_D, r0 + mov.l r0, @r1 + + mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ + mov.l WDTBST_D, r0 + mov.l r0, @r1 + + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ + mov.l r0, @r1 + + mov.l MMUCR_A, r1 /* Address of MMU Control Register */ + mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */ + mov.l r0, @r1 + + mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */ + mov.l MSTPCR0_D, r0 + mov.l r0, @r1 + + mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */ + mov.l MSTPCR1_D, r0 + mov.l r0, @r1 + + mov.l RAMCR_A,r1 + mov.l RAMCR_D,r0 + mov.l r0, @r1 + + mov.l MMSELR_A,r1 + mov.l MMSELR_D,r0 + synco + mov.l r0, @r1 + + mov.l @r1,r2 /* execute two reads after setting MMSELR*/ + mov.l @r1,r2 + synco + + /* issue memory read */ + mov.l DDRSD_START_A,r1 /* memory address to read*/ + mov.l @r1,r0 + synco + + mov.l MIM8_A,r1 + mov.l MIM8_D,r0 + mov.l r0,@r1 + + mov.l MIMC_A,r1 + mov.l MIMC_D1,r0 + mov.l r0,@r1 + + mov.l STRC_A,r1 + mov.l STRC_D,r0 + mov.l r0,@r1 + + mov.l SDR4_A,r1 + mov.l SDR4_D,r0 + mov.l r0,@r1 + + mov.l MIMC_A,r1 + mov.l MIMC_D2,r0 + mov.l r0,@r1 + + nop + nop + nop + + mov.l SCR4_A,r1 + mov.l SCR4_D3,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D2,r0 + mov.l r0,@r1 + + mov.l SDMR02000_A,r1 + mov.l SDMR02000_D,r0 + mov.l r0,@r1 + + mov.l SDMR00B08_A,r1 + mov.l SDMR00B08_D,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D2,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D4,r0 + mov.l r0,@r1 + + nop + nop + nop + nop + + mov.l SCR4_A,r1 + mov.l SCR4_D4,r0 + mov.l r0,@r1 + + nop + nop + nop + nop + + mov.l SDMR00308_A,r1 + mov.l SDMR00308_D,r0 + mov.l r0,@r1 + + mov.l MIMC_A,r1 + mov.l MIMC_D3,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D1,r0 + mov.l DELAY60_D,r3 + +delay_loop_60: + mov.l r0,@r1 + dt r3 + bf delay_loop_60 + nop + + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_CACHE_D_2, r0 + mov.l r0, @r1 + +bsc_init: + mov.l BCR_A, r1 + mov.l BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 + mov.l r0, @r1 + + mov.l CS1BCR_A,r1 + mov.l CS1BCR_D,r0 + mov.l r0,@r1 + + mov.l CS2BCR_A, r1 + mov.l CS2BCR_D, r0 + mov.l r0, @r1 + + mov.l CS4BCR_A, r1 + mov.l CS4BCR_D, r0 + mov.l r0, @r1 + + mov.l CS5BCR_A, r1 + mov.l CS5BCR_D, r0 + mov.l r0, @r1 + + mov.l CS6BCR_A, r1 + mov.l CS6BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 + + mov.l CS1WCR_A, r1 + mov.l CS1WCR_D, r0 + mov.l r0, @r1 + + mov.l CS2WCR_A, r1 + mov.l CS2WCR_D, r0 + mov.l r0, @r1 + + mov.l CS4WCR_A, r1 + mov.l CS4WCR_D, r0 + mov.l r0, @r1 + + mov.l CS5WCR_A, r1 + mov.l CS5WCR_D, r0 + mov.l r0, @r1 + + mov.l CS6WCR_A, r1 + mov.l CS6WCR_D, r0 + mov.l r0, @r1 + + mov.l CS5PCR_A, r1 + mov.l CS5PCR_D, r0 + mov.l r0, @r1 + + mov.l CS6PCR_A, r1 + mov.l CS6PCR_D, r0 + mov.l r0, @r1 + + mov.l DELAY200_D,r3 + +delay_loop_200: + dt r3 + bf delay_loop_200 + nop + + mov.l PSEL0_A,r1 + mov.l PSEL0_D,r0 + mov.w r0,@r1 + + mov.l PSEL1_A,r1 + mov.l PSEL1_D,r0 + mov.w r0,@r1 + + mov.l ICR0_A,r1 + mov.l ICR0_D,r0 + mov.l r0,@r1 + + stc sr, r0 /* BL bit off(init=ON) */ + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + nop + + .align 2 + +DELAY60_D: .long 60 +DELAY200_D: .long 17800 + +CCR_A: .long 0xFF00001C +MMUCR_A: .long 0xFF000010 +RAMCR_A: .long 0xFF000074 + +/* Low power mode control */ +MSTPCR0_A: .long 0xFFC80030 +MSTPCR1_A: .long 0xFFC80038 + +/* RWBT */ +WDTST_A: .long 0xFFCC0000 +WDTCSR_A: .long 0xFFCC0004 +WDTBST_A: .long 0xFFCC0008 + +/* BSC */ +MMSELR_A: .long 0xFE600020 +BCR_A: .long 0xFF801000 +CS0BCR_A: .long 0xFF802000 +CS1BCR_A: .long 0xFF802010 +CS2BCR_A: .long 0xFF802020 +CS4BCR_A: .long 0xFF802040 +CS5BCR_A: .long 0xFF802050 +CS6BCR_A: .long 0xFF802060 +CS0WCR_A: .long 0xFF802008 +CS1WCR_A: .long 0xFF802018 +CS2WCR_A: .long 0xFF802028 +CS4WCR_A: .long 0xFF802048 +CS5WCR_A: .long 0xFF802058 +CS6WCR_A: .long 0xFF802068 +CS5PCR_A: .long 0xFF802070 +CS6PCR_A: .long 0xFF802080 +DDRSD_START_A: .long 0xAC000000 + +/* INTC */ +ICR0_A: .long 0xFFD00000 + +/* DDR I/F */ +MIM8_A: .long 0xFE800008 +MIMC_A: .long 0xFE80000C +SCR4_A: .long 0xFE800014 +STRC_A: .long 0xFE80001C +SDR4_A: .long 0xFE800034 +SDMR00308_A: .long 0xFE900308 +SDMR00B08_A: .long 0xFE900B08 +SDMR02000_A: .long 0xFE902000 + +/* GPIO */ +PSEL0_A: .long 0xFFEF0070 +PSEL1_A: .long 0xFFEF0072 + +CCR_CACHE_ICI_D:.long 0x00000800 +CCR_CACHE_D_2: .long 0x00000103 +MMU_CONTROL_TI_D:.long 0x00000004 +RAMCR_D: .long 0x00000200 +MSTPCR0_D: .long 0x00000000 +MSTPCR1_D: .long 0x00000000 + +MMSELR_D: .long 0xa5a50000 +BCR_D: .long 0x00000000 +CS0BCR_D: .long 0x77777770 +CS1BCR_D: .long 0x77777670 +CS2BCR_D: .long 0x77777670 +CS4BCR_D: .long 0x77777670 +CS5BCR_D: .long 0x77777670 +CS6BCR_D: .long 0x77777670 +CS0WCR_D: .long 0x7777770F +CS1WCR_D: .long 0x22000002 +CS2WCR_D: .long 0x7777770F +CS4WCR_D: .long 0x7777770F +CS5WCR_D: .long 0x7777770F +CS6WCR_D: .long 0x7777770F +CS5PCR_D: .long 0x77000000 +CS6PCR_D: .long 0x77000000 +ICR0_D: .long 0x00E00000 +MIM8_D: .long 0x00000000 +MIMC_D1: .long 0x01d10008 +MIMC_D2: .long 0x01d10009 +MIMC_D3: .long 0x01d10209 +SCR4_D1: .long 0x00000001 +SCR4_D2: .long 0x00000002 +SCR4_D3: .long 0x00000003 +SCR4_D4: .long 0x00000004 +STRC_D: .long 0x000f3980 +SDR4_D: .long 0x00000300 +SDMR00308_D: .long 0x00000000 +SDMR00B08_D: .long 0x00000000 +SDMR02000_D: .long 0x00000000 +PSEL0_D: .long 0x00000001 +PSEL1_D: .long 0x00000244 +SR_MASK_D: .long 0xEFFFFF0F +WDTST_D: .long 0x5A000FFF +WDTCSR_D: .long 0xA5000000 +WDTBST_D: .long 0x55000000 diff --git a/board/sh7763rdp/sh7763rdp.c b/board/sh7763rdp/sh7763rdp.c new file mode 100644 index 0000000000..92ac7b7a96 --- /dev/null +++ b/board/sh7763rdp/sh7763rdp.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * Copyright (C) 2007 Kenati Technologies, Inc. + * + * board/sh7763rdp/sh7763rdp.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +#define CPU_CMDREG 0xB1000006 +#define PDCR 0xffef0006 +#define PECR 0xffef0008 +#define PFCR 0xffef000a +#define PGCR 0xffef000c +#define PHCR 0xffef000e +#define PJCR 0xffef0012 +#define PKCR 0xffef0014 +#define PLCR 0xffef0016 +#define PMCR 0xffef0018 +#define PSEL1 0xffef0072 +#define PSEL2 0xffef0074 +#define PSEL3 0xffef0076 + +int checkboard(void) +{ + puts("BOARD: Renesas SH7763 RDP\n"); + return 0; +} + +int board_init(void) +{ + vu_short dat; + + /* Enable mode */ + writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); + + /* GPIO Setting (eth1) */ + dat = inw(PSEL1); + writew(((dat & ~0xff00) | 0x2400), PSEL1); + writew(0, PFCR); + writew(0, PGCR); + writew(0, PHCR); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} diff --git a/board/sh7763rdp/u-boot.lds b/board/sh7763rdp/u-boot.lds new file mode 100644 index 0000000000..c07f0d80ed --- /dev/null +++ b/board/sh7763rdp/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007,2008 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/shannon/Makefile b/board/shannon/Makefile index 37774a90c4..16ed4cf413 100644 --- a/board/shannon/Makefile +++ b/board/shannon/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile index e053c7d661..c5695f98cb 100644 --- a/board/siemens/CCM/Makefile +++ b/board/siemens/CCM/Makefile @@ -22,23 +22,30 @@ # include $(TOPDIR)/config.mk + ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqm8xx) +$(shell mkdir -p $(obj)../../tqc/tqm8xx) endif LIB = $(obj)lib$(BOARD).a COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ - ../../tqm8xx/load_sernum_ethaddr.o + ../../tqc/tqm8xx/load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) +$(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c index 5a32e45e28..d653763285 100644 --- a/board/siemens/CCM/ccm.c +++ b/board/siemens/CCM/ccm.c @@ -155,7 +155,7 @@ static void init_leds (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c index e498937b65..9c0ff02783 100644 --- a/board/siemens/IAD210/IAD210.c +++ b/board/siemens/IAD210/IAD210.c @@ -100,7 +100,7 @@ const uint sdram_table[] = { /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c index c77e35912e..1b27f336b2 100644 --- a/board/siemens/IAD210/atm.c +++ b/board/siemens/IAD210/atm.c @@ -1,4 +1,3 @@ - #include <common.h> #include <mpc8xx.h> #include <commproc.h> @@ -7,7 +6,7 @@ #include <linux/stddef.h> #define SYNC __asm__("sync") -#define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) +#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) #define FALSE 1 #define TRUE 0 @@ -160,7 +159,7 @@ int atmMemInit() g_atm.csram = &csram[0]; memset(&(g_atm.csram), 0x00, g_atm.csram_size); - g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4); + g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4); g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES); g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd); diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile index edc1820007..6ef49c2ce9 100644 --- a/board/siemens/SCM/Makefile +++ b/board/siemens/SCM/Makefile @@ -22,23 +22,30 @@ # include $(TOPDIR)/config.mk + ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqm8xx/) +$(shell mkdir -p $(obj)../../tqc/tqm8xx) endif LIB = $(obj)lib$(BOARD).a COBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \ - ../../tqm8xx/load_sernum_ethaddr.o + ../../tqc/tqm8xx/load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) +$(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index 8783aafe9a..6a9dd25835 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -306,7 +306,7 @@ int power_on_reset (void) return gd->reset_status & RSR_CSRS ? 0 : 1; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/siemens/SMN42/Makefile b/board/siemens/SMN42/Makefile index 2c7b54b081..4e75b6f7a3 100644 --- a/board/siemens/SMN42/Makefile +++ b/board/siemens/SMN42/Makefile @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJTS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c index 2309069a60..5647f7af04 100644 --- a/board/siemens/pcu_e/pcu_e.c +++ b/board/siemens/pcu_e/pcu_e.c @@ -156,7 +156,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 798e1855bd..dcd34726b0 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -496,7 +496,7 @@ const uint sdram_table[] = /* ------------------------------------------------------------------------- */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c index 593eb4ee80..86478871bc 100644 --- a/board/sl8245/sl8245.c +++ b/board/sl8245/sl8245.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { #ifndef CFG_RAMBOOT long size; diff --git a/board/smdk2400/Makefile b/board/smdk2400/Makefile index 57c76e5b30..90cb2b8f60 100644 --- a/board/smdk2400/Makefile +++ b/board/smdk2400/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/smdk2410/Makefile b/board/smdk2410/Makefile index 8617b27f6e..5d0cd722d0 100644 --- a/board/smdk2410/Makefile +++ b/board/smdk2410/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c index 637f1250e9..ba5a8fb0a1 100644 --- a/board/snmc/qs850/qs850.c +++ b/board/snmc/qs850/qs850.c @@ -143,7 +143,7 @@ int checkboard (void) #define REFRESH_INIT_LOOPS (0) -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c index a11d863010..17c9356217 100644 --- a/board/snmc/qs860t/qs860t.c +++ b/board/snmc/qs860t/qs860t.c @@ -115,7 +115,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/socrates/Makefile b/board/socrates/Makefile index 6453f2480f..a41fead8f4 100644 --- a/board/socrates/Makefile +++ b/board/socrates/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a # -COBJS := $(BOARD).o law.o tlb.o sdram.o +COBJS := $(BOARD).o law.o tlb.o sdram.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -41,7 +41,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/socrates/config.mk b/board/socrates/config.mk index 1cf5d380df..4f1729440a 100644 --- a/board/socrates/config.mk +++ b/board/socrates/config.mk @@ -25,6 +25,5 @@ # # socrates board # default CCARBAR is at 0xff700000 -# assume U-Boot is less than 256k # -TEXT_BASE = 0xfffc0000 +TEXT_BASE = 0xfffa0000 diff --git a/board/socrates/law.c b/board/socrates/law.c index 5f4b8ca4f9..35c4a900a9 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -33,13 +33,12 @@ /* * LAW(Local Access Window) configuration: * - * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x0000_0000 0x2fff_ffff DDR 512M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xc000_0000 0xc00f_ffff FPGA 1M + * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * 0xfc00_0000 0xffff_ffff FLASH 64M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. @@ -47,11 +46,13 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), +#if defined(CFG_FPGA_BASE) + SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/nand.c b/board/socrates/nand.c new file mode 100644 index 0000000000..fc82ecbb73 --- /dev/null +++ b/board/socrates/nand.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CFG_NAND_BASE) +#include <nand.h> +#include <asm/errno.h> +#include <asm/io.h> + +static int state; +static void nand_write_byte(struct mtd_info *mtd, u_char byte); +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); +static void nand_write_word(struct mtd_info *mtd, u16 word); +static u_char nand_read_byte(struct mtd_info *mtd); +static u16 nand_read_word(struct mtd_info *mtd); +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); +static int nand_device_ready(struct mtd_info *mtdinfo); +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd); + +#define FPGA_NAND_CMD_MASK (0x7 << 28) +#define FPGA_NAND_CMD_COMMAND (0x0 << 28) +#define FPGA_NAND_CMD_ADDR (0x1 << 28) +#define FPGA_NAND_CMD_READ (0x2 << 28) +#define FPGA_NAND_CMD_WRITE (0x3 << 28) +#define FPGA_NAND_BUSY (0x1 << 15) +#define FPGA_NAND_ENABLE (0x1 << 31) +#define FPGA_NAND_DATA_SHIFT 16 + +/** + * nand_write_byte - write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + */ +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); +} + +/** + * nand_write_word - write one word to the chip + * @mtd: MTD device structure + * @word: data word to write + */ +static void nand_write_word(struct mtd_info *mtd, u16 word) +{ + nand_write_buf(mtd, (const uchar *)&word, sizeof(word)); +} + +/** + * nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + long val; + + if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) { + /* Write data */ + val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE; + } else { + /* Write address or command */ + val = state; + } + + for (i = 0; i < len; i++) { + out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT)); + } +} + + +/** + * nand_read_byte - read one byte from the chip + * @mtd: MTD device structure + */ +static u_char nand_read_byte(struct mtd_info *mtd) +{ + u8 byte; + nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); + return byte; +} + +/** + * nand_read_word - read one word from the chip + * @mtd: MTD device structure + */ +static u16 nand_read_word(struct mtd_info *mtd) +{ + u16 word; + nand_read_buf(mtd, (uchar *)&word, sizeof(word)); + return word; +} + +/** + * nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + int val; + + val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; + + out_be32(this->IO_ADDR_W, val); + for (i = 0; i < len; i++) { + buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff; + } +} + +/** + * nand_verify_buf - Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + if (buf[i] != nand_read_byte(mtd)); + return -EFAULT; + } + return 0; +} + +/** + * nand_device_ready - Check the NAND device is ready for next command. + * @mtd: MTD device structure + */ +static int nand_device_ready(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + + if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) + return 0; /* busy */ + return 1; +} + +/** + * nand_hwcontrol - NAND control functions wrapper. + * @mtd: MTD device structure + * @cmd: Command + */ +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + + switch(cmd) { + case NAND_CTL_CLRALE: + state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ + break; + case NAND_CTL_CLRCLE: + state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ + break; + case NAND_CTL_SETCLE: + state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND; + break; + case NAND_CTL_SETALE: + state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR; + break; + case NAND_CTL_SETNCE: + state |= FPGA_NAND_ENABLE; + break; + case NAND_CTL_CLRNCE: + state &= ~FPGA_NAND_ENABLE; + break; + default: + printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd); + break; + } +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->hwcontrol = nand_hwcontrol; + nand->eccmode = NAND_ECC_SOFT; + nand->dev_ready = nand_device_ready; + nand->write_byte = nand_write_byte; + nand->read_byte = nand_read_byte; + nand->write_word = nand_write_word; + nand->read_word = nand_read_word; + nand->write_buf = nand_write_buf; + nand->read_buf = nand_read_buf; + nand->verify_buf = nand_verify_buf; + + return 0; +} + +#endif diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 329eaccd5d..768fe05a24 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -76,7 +76,7 @@ long int sdram_setup(int casl) } #endif -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index cb5899485a..d791f1135f 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -35,7 +35,11 @@ #include <flash.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/io.h> +#if defined(CFG_FPGA_BASE) +#include "upm_table.h" +#endif DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ @@ -45,6 +49,9 @@ ulong flash_get_size (ulong base, int banknum); int checkboard (void) { + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + char *src; + int f; char *s = getenv("serial#"); puts("Board: Socrates"); @@ -55,8 +62,15 @@ int checkboard (void) putc('\n'); #ifdef CONFIG_PCI - printf ("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); + /* Check the PCI_clk sel bit */ + if (in_be32(&gur->porpllsr) & (1<<15)) { + src = "SYSCLK"; + f = CONFIG_SYS_CLK_FREQ; + } else { + src = "PCI_CLK"; + f = CONFIG_PCI_CLK_FREQ; + } + printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); #else printf ("PCI1: disabled\n"); #endif @@ -65,7 +79,10 @@ int checkboard (void) * Initialize local bus. */ local_bus_init (); - +#if defined(CFG_FPGA_BASE) + /* Init UPMA for FPGA access */ + upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); +#endif return 0; } @@ -207,5 +224,15 @@ ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); + +#if defined (CFG_FPGA_BASE) + memset(val, 0, sizeof(val)); + val[0] = CFG_FPGA_BASE; + rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property \"fpga\", err=%s\n", + fdt_strerror(rc)); +#endif } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index b80caea5e0..aea99ada20 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = { /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), /* * TLB 2: 256M Non-cacheable, guarded @@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), +#if defined(CFG_FPGA_BASE) /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half + * TLB 4: 1M Non-cacheable, guarded + * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), + 0, 4, BOOKE_PAGESZ_1M, 1), +#endif /* * TLB 6: 64M Non-cacheable, guarded diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h new file mode 100644 index 0000000000..ea64a59a0c --- /dev/null +++ b/board/socrates/upm_table.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __UPM_TABLE_H +#define __UPM_TABLE_H + +/* UPM Table Configuration Code for FPGA access */ +static const unsigned int UPMTableA[] = +{ + 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, /* Words 0 to 3 */ + 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, /* Words 4 to 7 */ + 0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, /* Words 8 to 11 */ + 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, /* Words 12 to 15 */ + 0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, /* Words 16 to 19 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ + 0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, /* Words 24 to 27 */ + 0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, /* Words 28 to 31 */ + 0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 32 to 35 */ + 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 36 to 39 */ + 0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ + 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ +}; + +#endif diff --git a/board/sorcery/Makefile b/board/sorcery/Makefile index e02916f708..434d348980 100644 --- a/board/sorcery/Makefile +++ b/board/sorcery/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c index 165e9e2999..2b789d4741 100644 --- a/board/sorcery/sorcery.c +++ b/board/sorcery/sorcery.c @@ -27,7 +27,7 @@ #include <asm/mmu.h> #include <pci.h> -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong size; diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c index 1f5dcb5d3e..a32aad0ee4 100644 --- a/board/spc1920/spc1920.c +++ b/board/spc1920/spc1920.c @@ -82,7 +82,7 @@ const uint sdram_table[] = { _NOT_USED_, _NOT_USED_, _NOT_USED_, }; -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c index c79b9b0dd5..6387f8a65c 100644 --- a/board/spd8xx/spd8xx.c +++ b/board/spd8xx/spd8xx.c @@ -143,7 +143,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/ssv/adnpesc1/Makefile b/board/ssv/adnpesc1/Makefile index 5b87b75e76..40f04b81f0 100644 --- a/board/ssv/adnpesc1/Makefile +++ b/board/ssv/adnpesc1/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c index 2ec3a728d7..71de20899e 100644 --- a/board/ssv/adnpesc1/adnpesc1.c +++ b/board/ssv/adnpesc1/adnpesc1.c @@ -57,7 +57,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return (0); } @@ -69,25 +69,24 @@ long int initdram (int board_type) #define SPI_RTC_CS_MASK 0x00000001 -void spi_rtc_chipsel(int cs) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) { nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; - if (cs) - spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */ - else - spi->slaveselect = 0; /* deactivate (0) */ + spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */ } -/* - * The SPI command uses this table of functions for controlling the SPI - * chip selects: it calls the appropriate function to control the SPI - * chip selects. - */ -spi_chipsel_type spi_chipsel[] = { - spi_rtc_chipsel -}; -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); +void spi_cs_deactivate(struct spi_slave *slave) +{ + nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; + + spi->slaveselect = 0; /* deactivate (0) */ +} #endif diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile index 28d6cb9976..325d6d5722 100644 --- a/board/stxgp3/Makefile +++ b/board/stxgp3/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c index 312b3c5571..a7e9ceb033 100644 --- a/board/stxgp3/law.c +++ b/board/stxgp3/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index f04ffa8046..218e8053f1 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -275,7 +275,7 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); } -long int +phys_size_t initdram (int board_type) { long dram_size = 0; diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile index f1f5d0b1bf..e29cf95e3c 100644 --- a/board/stxssa/Makefile +++ b/board/stxssa/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/stxssa/law.c b/board/stxssa/law.c index 2b25292988..8730cdfc4e 100644 --- a/board/stxssa/law.c +++ b/board/stxssa/law.c @@ -47,14 +47,14 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), /* Map the whole localbus, including flash and reset latch. */ - SET_LAW_ENTRY(6, CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 08177e1aec..2c4b54642a 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -291,7 +291,7 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); } -long int +phys_size_t initdram (int board_type) { long dram_size = 0; diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index 87a2022761..a750374393 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -399,7 +399,7 @@ void check_ram(unsigned int addr, unsigned int size) #define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) -long int initdram(int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c index b900e6bd1b..06fb18b344 100644 --- a/board/svm_sc8xx/svm_sc8xx.c +++ b/board/svm_sc8xx/svm_sc8xx.c @@ -100,7 +100,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/sx1/Makefile b/board/sx1/Makefile index 609ca75c4d..4c11030ed6 100644 --- a/board/sx1/Makefile +++ b/board/sx1/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S index df318067b9..5fce8567d7 100644 --- a/board/tb0229/lowlevel_init.S +++ b/board/tb0229/lowlevel_init.S @@ -10,7 +10,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c index d08b422451..921bd3adcd 100644 --- a/board/tb0229/tb0229.c +++ b/board/tb0229/tb0229.c @@ -32,7 +32,7 @@ void pci_init_board (void) } #endif -long int initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size (CFG_SDRAM_BASE, 0x8000000); } diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c index 0ee4bf30ea..4c9192341e 100644 --- a/board/tb0229/vr4131-pci.c +++ b/board/tb0229/vr4131-pci.c @@ -13,34 +13,34 @@ #include <pci.h> #include <asm/addrspace.h> -#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00) -#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04) -#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08) -#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c) -#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10) -#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14) -#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18) -#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c) -#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24) -#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28) -#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c) -#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30) -#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34) -#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38) -#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c) -#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60) -#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) -#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) -#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) -#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) -#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) -#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) -#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10) -#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14) -#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18) +#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00) +#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04) +#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08) +#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c) +#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10) +#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14) +#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18) +#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c) +#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24) +#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28) +#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c) +#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30) +#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34) +#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38) +#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c) +#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60) +#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) +#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) +#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) +#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) +#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) +#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) +#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) +#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) +#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) +#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10) +#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14) +#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18) /*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ /*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ diff --git a/board/total5200/Makefile b/board/total5200/Makefile index 10e5fc3406..a8abd7d781 100644 --- a/board/total5200/Makefile +++ b/board/total5200/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c index c8d4c67102..868ebd5f54 100644 --- a/board/total5200/total5200.c +++ b/board/total5200/total5200.c @@ -36,7 +36,7 @@ #include "mt48lc16m16a2-75.h" #endif -long int initdram (int board_type) +phys_size_t initdram (int board_type) { sdram_conf_t sdram_conf; diff --git a/board/tqm5200/Makefile b/board/tqc/tqm5200/Makefile index a5ce7bd46f..ce125e2b96 100644 --- a/board/tqm5200/Makefile +++ b/board/tqc/tqm5200/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend cam5200_flash.o: cam5200_flash.c $(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $< diff --git a/board/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index b3f095d807..b3f095d807 100644 --- a/board/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index 7472ca9e97..7472ca9e97 100644 --- a/board/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c diff --git a/board/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c index 214dca65e5..214dca65e5 100644 --- a/board/tqm5200/cmd_tb5200.c +++ b/board/tqc/tqm5200/cmd_tb5200.c diff --git a/board/tqm5200/config.mk b/board/tqc/tqm5200/config.mk index d72dfe7481..d72dfe7481 100644 --- a/board/tqm5200/config.mk +++ b/board/tqc/tqm5200/config.mk diff --git a/board/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h index 3f1e1691bb..3f1e1691bb 100644 --- a/board/tqm5200/mt48lc16m16a2-75.h +++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h diff --git a/board/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index f9891dbb74..8b8e461374 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -104,7 +104,7 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/tqm8260/Makefile b/board/tqc/tqm8260/Makefile index 61221fdca2..61221fdca2 100644 --- a/board/tqm8260/Makefile +++ b/board/tqc/tqm8260/Makefile diff --git a/board/tqm8260/config.mk b/board/tqc/tqm8260/config.mk index 1fe99524c6..1fe99524c6 100644 --- a/board/tqm8260/config.mk +++ b/board/tqc/tqm8260/config.mk diff --git a/board/tqm8260/flash.c b/board/tqc/tqm8260/flash.c index 056fe810b3..056fe810b3 100644 --- a/board/tqm8260/flash.c +++ b/board/tqc/tqm8260/flash.c diff --git a/board/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c index 736c410ede..f201045d95 100644 --- a/board/tqm8260/tqm8260.c +++ b/board/tqc/tqm8260/tqm8260.c @@ -283,7 +283,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/tqm8272/Makefile b/board/tqc/tqm8272/Makefile index 6730263512..6730263512 100644 --- a/board/tqm8272/Makefile +++ b/board/tqc/tqm8272/Makefile diff --git a/board/tqm8272/config.mk b/board/tqc/tqm8272/config.mk index af7a81e335..af7a81e335 100644 --- a/board/tqm8272/config.mk +++ b/board/tqc/tqm8272/config.mk diff --git a/board/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index 7bd64012c4..29099f5ed1 100644 --- a/board/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -30,10 +30,6 @@ #include <pci.h> #include <asm/m8260_pci.h> #endif -#if CONFIG_OF_FLAT_TREE -#include <ft_build.h> -#include <image.h> -#endif #if 0 #define deb_printf(fmt,arg...) \ @@ -559,7 +555,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/tqm834x/Makefile b/board/tqc/tqm834x/Makefile index 4c0d20417e..8889726aeb 100644 --- a/board/tqm834x/Makefile +++ b/board/tqc/tqm834x/Makefile @@ -40,7 +40,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/tqm834x/config.mk b/board/tqc/tqm834x/config.mk index f172c4ede0..f172c4ede0 100644 --- a/board/tqm834x/config.mk +++ b/board/tqc/tqm834x/config.mk diff --git a/board/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index e3d0309d90..e3d0309d90 100644 --- a/board/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c diff --git a/board/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index aea985ccc6..278780dde5 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -85,7 +85,7 @@ int board_early_init_r (void) { /************************************************************************** * DRAM initalization and size detection */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long bank_size; long size; diff --git a/board/tqm85xx/Makefile b/board/tqc/tqm85xx/Makefile index 52f5ef9454..adda9d45b7 100644 --- a/board/tqm85xx/Makefile +++ b/board/tqc/tqm85xx/Makefile @@ -25,8 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o sdram.o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += sdram.o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_NAND) += nand.o + +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) @@ -38,7 +44,7 @@ clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/tqm85xx/config.mk b/board/tqc/tqm85xx/config.mk index 52e84ad772..52e84ad772 100644 --- a/board/tqm85xx/config.mk +++ b/board/tqc/tqm85xx/config.mk diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c new file mode 100644 index 0000000000..de3ea00e38 --- /dev/null +++ b/board/tqc/tqm85xx/law.c @@ -0,0 +1,86 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * Standard mapping: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M + * 0xef00_0000 0xefff_ffff PCI express IO 16M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M + * + * Big FLASH mapping: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xa000_ffff CCSR 1M + * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M + * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M + * 0xaf00_0000 0xafff_ffff PCI express IO 16M + * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M + * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#ifdef CONFIG_TQM_BIGFLASH +#define LAW_3_SIZE LAW_SIZE_1G +#define LAW_5_SIZE LAW_SIZE_256M +#else +#define LAW_3_SIZE LAW_SIZE_128M +#define LAW_5_SIZE LAW_SIZE_512M +#endif + +struct law_entry law_table[] = { + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), +#ifdef CONFIG_PCIE1 + SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), +#else /* !CONFIG_PCIE1 */ + SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), +#endif /* CONFIG_PCIE1 */ +#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) + SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), +#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ +#ifdef CONFIG_PCIE1 + SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), +#endif /* CONFIG_PCIE */ +}; + +int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c new file mode 100644 index 0000000000..9c5c12c844 --- /dev/null +++ b/board/tqc/tqm85xx/nand.c @@ -0,0 +1,469 @@ +/* + * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> + * + * (C) Copyright 2006 + * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <ioports.h> + +#include <nand.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern uint get_lbc_clock (void); + +/* index of UPM RAM array run pattern for NAND command cycle */ +#define CFG_NAN_UPM_WRITE_CMD_OFS 0x08 + +/* index of UPM RAM array run pattern for NAND address cycle */ +#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x10 + +/* Structure for table with supported UPM timings */ +struct upm_freq { + ulong freq; + const u32 *upm_patt; + uchar gpl4_disable; + uchar ehtr; + uchar ead; +}; + +/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */ + +/* UPM pattern for bus clock = 25 MHz */ +static const u32 upm_patt_25[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 33.3 MHz */ +static const u32 upm_patt_33[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 41.7 MHz */ +static const u32 upm_patt_42[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 50 MHz */ +static const u32 upm_patt_50[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 66.7 MHz */ +static const u32 upm_patt_67[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 83.3 MHz */ +static const u32 upm_patt_83[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 100 MHz */ +static const u32 upm_patt_100[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 133.3 MHz */ +static const u32 upm_patt_133[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 166.7 MHz */ +static const u32 upm_patt_167[] = { + /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* Supported UPM timings */ +struct upm_freq upm_freq_table[] = { + /* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */ + {25000000, upm_patt_25, 1, 0, 0}, + {33333333, upm_patt_33, 1, 0, 0}, + {41666666, upm_patt_42, 1, 0, 0}, + {50000000, upm_patt_50, 0, 0, 0}, + {66666666, upm_patt_67, 0, 0, 0}, + {83333333, upm_patt_83, 0, 0, 0}, + {100000000, upm_patt_100, 0, 1, 1}, + {133333333, upm_patt_133, 0, 1, 1}, + {166666666, upm_patt_167, 0, 1, 1}, +}; + +#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq)) + +volatile const u32 *nand_upm_patt; + +/* + * write into UPMB ram + */ +static void upmb_write (u_char addr, ulong val) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + out_be32 (&lbc->mdr, val); + + clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK, + MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); + + /* dummy access to perform write */ + out_8 ((void __iomem *)CFG_NAND0_BASE, 0); + + clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); +} + +/* + * Initialize UPM for NAND flash access. + */ +static void nand_upm_setup (volatile ccsr_lbc_t *lbc) +{ + uint i; + uint or3 = CFG_OR3_PRELIM; + uint clock = get_lbc_clock (); + + out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */ + out_be32 (&lbc->br3, CFG_BR3_PRELIM); + + /* + * Search appropriate UPM table for bus clock. + * If the bus clock exceeds a tolerated value, take the UPM timing for + * the next higher supported frequency to ensure that access works + * (even the access may be slower then). + */ + for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++) + ; + + if (i >= UPM_FREQS) + /* no valid entry found */ + /* take last entry with configuration for max. bus clock */ + i--; + + if (upm_freq_table[i].ehtr) { + /* EHTR must be set due to TQM8548 timing specification */ + or3 |= OR_UPM_EHTR; + } + if (upm_freq_table[i].ead) + /* EAD must be set due to TQM8548 timing specification */ + or3 |= OR_UPM_EAD; + + out_be32 (&lbc->or3, or3); + + /* Assign address of table */ + nand_upm_patt = upm_freq_table[i].upm_patt; + + for (i = 0; i < 64; i++) { + upmb_write (i, *nand_upm_patt); + nand_upm_patt++; + } + + /* Put UPM back to normal operation mode */ + if (upm_freq_table[i].gpl4_disable) + /* GPL4 must be disabled according to timing specification */ + out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS); + + return; +} + +static struct fsl_upm_nand fun = { + .width = 8, + .upm_cmd_offset = 0x08, + .upm_addr_offset = 0x10, + .chip_delay = NAND_BIG_DELAY_US, +}; + +void board_nand_select_device (struct nand_chip *nand, int chip) +{ +} + +int board_nand_init (struct nand_chip *nand) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + if (!nand_upm_patt) + nand_upm_setup (lbc); + + fun.upm.io_addr = nand->IO_ADDR_R; + fun.upm.mxmr = (void __iomem *)&lbc->mbmr; + fun.upm.mdr = (void __iomem *)&lbc->mdr; + fun.upm.mar = (void __iomem *)&lbc->mar; + + return fsl_upm_nand_init (nand, &fun); +} diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c new file mode 100644 index 0000000000..33bc4077e5 --- /dev/null +++ b/board/tqc/tqm85xx/sdram.c @@ -0,0 +1,371 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/mmu.h> + +struct sdram_conf_s { + unsigned long size; + unsigned long reg; +#ifdef CONFIG_TQM8548 + unsigned long refresh; +#endif /* CONFIG_TQM8548 */ +}; + +typedef struct sdram_conf_s sdram_conf_t; + +#ifdef CONFIG_TQM8548 +sdram_conf_t ddr_cs_conf[] = { + {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ + {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ + {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ +}; +#else /* !CONFIG_TQM8548 */ +sdram_conf_t ddr_cs_conf[] = { + {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ + {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ + {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ + {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ +}; +#endif /* CONFIG_TQM8548 */ + +#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) + +int cas_latency (void); + +/* + * Autodetect onboard DDR SDRAM on 85xx platforms + * + * NOTE: Some of the hardcoded values are hardware dependant, + * so this should be extended for other future boards + * using this routine! + */ +long int sdram_setup (int casl) +{ + int i; + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); +#ifdef CONFIG_TQM8548 + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#else /* !CONFIG_TQM8548 */ + unsigned long cfg_ddr_timing1; + unsigned long cfg_ddr_mode; +#endif /* CONFIG_TQM8548 */ + + /* + * Disable memory controller. + */ + ddr->cs0_config = 0; + ddr->sdram_cfg = 0; + +#ifdef CONFIG_TQM8548 + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; + ddr->cs0_config = ddr_cs_conf[0].reg; + ddr->timing_cfg_3 = 0x00010000; + + /* TIMING CFG 1, 533MHz + * PRETOACT: 4 Clocks + * ACTTOPRE: 12 Clocks + * ACTTORW: 4 Clocks + * CASLAT: 4 Clocks + * REFREC: 34 Clocks + * WRREC: 4 Clocks + * ACTTOACT: 3 Clocks + * WRTORD: 2 Clocks + */ + ddr->timing_cfg_1 = 0x4C47A432; + + /* TIMING CFG 2, 533MHz + * ADD_LAT: 3 Clocks + * CPO: READLAT + 1 + * WR_LAT: 3 Clocks + * RD_TO_PRE: 2 Clocks + * WR_DATA_DELAY: 1/2 Clock + * CKE_PLS: 1 Clock + * FOUR_ACT: 13 Clocks + */ + ddr->timing_cfg_2 = 0x3318484D; + + /* DDR SDRAM Mode, 533MHz + * MRS: Extended Mode Register + * OUT: Outputs enabled + * RDQS: no + * DQS: enabled + * OCD: default state + * RTT: 75 Ohms + * Posted CAS: 3 Clocks + * ODS: reduced strength + * DLL: enabled + * MR: Mode Register + * PD: fast exit + * WR: 4 Clocks + * DLL: no DLL reset + * TM: normal + * CAS latency: 4 Clocks + * BT: sequential + * Burst length: 4 + */ + ddr->sdram_mode = 0x439E0642; + + /* DDR SDRAM Interval, 533MHz + * REFINT: 1040 Clocks + * BSTOPRE: 256 + */ + ddr->sdram_interval = (1040 << 16) | 0x100; + + /* + * workaround for erratum DD10 of MPC8458 family below rev. 2.0: + * DDR IO receiver must be set to an acceptable bias point by modifying + * a hidden register. + */ + if (SVR_REV (get_svr ()) < 0x20) { + gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ + } + + /* DDR SDRAM CFG 2 + * FRC_SR: normal mode + * SR_IE: no self-refresh interrupt + * DLL_RST_DIS: don't care, leave at reset value + * DQS_CFG: differential DQS signals + * ODT_CFG: assert ODT to internal IOs only during reads to DRAM + * LVWx_CFG: don't care, leave at reset value + * NUM_PR: 1 refresh will be issued at a time + * DM_CFG: don't care, leave at reset value + * D_INIT: no data initialization + */ + ddr->sdram_cfg_2 = 0x04401000; + + /* DDR SDRAM MODE 2 + * MRS: Extended Mode Register 2 + */ + ddr->sdram_mode_2 = 0x8000C000; + + /* DDR SDRAM CLK CNTL + * CLK_ADJUST: 1/2 Clock 0x02000000 + * CLK_ADJUST: 5/8 Clock 0x02800000 + */ + ddr->sdram_clk_cntl = 0x02800000; + + /* wait for clock stabilization */ + asm ("sync;isync;msync"); + udelay(1000); + + /* DDR SDRAM CLK CNTL + * MEM_EN: enabled + * SREN: don't care, leave at reset value + * ECC_EN: no error report + * RD_EN: no register DIMMs + * SDRAM_TYPE: DDR2 + * DYN_PWR: no power management + * 32_BE: don't care, leave at reset value + * 8_BE: 4 beat burst + * NCAP: don't care, leave at reset value + * 2T_EN: 1T Timing + * BA_INTLV_CTL: no interleaving + * x32_EN: x16 organization + * PCHB8: MA[10] for auto-precharge + * HSE: half strength for single and 2-layer stacks + * (full strength for 3- and 4-layer stacks no yet considered) + * MEM_HALT: no halt + * BI: automatic initialization + */ + ddr->sdram_cfg = 0x83000008; + asm ("sync; isync; msync"); + udelay(1000); + +#else /* !CONFIG_TQM8548 */ + switch (casl) { + case 20: + cfg_ddr_timing1 = 0x47405331 | (3 << 16); + cfg_ddr_mode = 0x40020002 | (2 << 4); + break; + + case 25: + cfg_ddr_timing1 = 0x47405331 | (4 << 16); + cfg_ddr_mode = 0x40020002 | (6 << 4); + break; + + case 30: + default: + cfg_ddr_timing1 = 0x47405331 | (5 << 16); + cfg_ddr_mode = 0x40020002 | (3 << 4); + break; + } + + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; + ddr->cs0_config = ddr_cs_conf[0].reg; + ddr->timing_cfg_1 = cfg_ddr_timing1; + ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ + ddr->sdram_mode = cfg_ddr_mode; + ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ + ddr->err_disable = 0x0000000D; + + asm ("sync; isync; msync"); + udelay (1000); + + ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ + asm ("sync; isync; msync"); + udelay (1000); +#endif /* CONFIG_TQM8548 */ + + for (i = 0; i < N_DDR_CS_CONF; i++) { + ddr->cs0_config = ddr_cs_conf[i].reg; + + if (get_ram_size (0, ddr_cs_conf[i].size) == + ddr_cs_conf[i].size) { + /* + * size detected -> set Chip Select Bounds Register + */ + ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24; + + break; + } + } + +#ifdef CONFIG_TQM8548 + if (i < N_DDR_CS_CONF) { + /* Adjust refresh rate for DDR2 */ + + ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000; + + ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) | + (ddr_cs_conf[i].refresh & 0x0000F000); + + return ddr_cs_conf[i].size; + } +#endif /* CONFIG_TQM8548 */ + + /* return size if detected, else return 0 */ + return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; +} + +void board_add_ram_info (int use_default) +{ + int casl; + + if (use_default) + casl = CONFIG_DDR_DEFAULT_CL; + else + casl = cas_latency (); + + puts (" (CL="); + switch (casl) { + case 20: + puts ("2)"); + break; + + case 25: + puts ("2.5)"); + break; + + case 30: + puts ("3)"); + break; + } +} + +phys_size_t initdram (int board_type) +{ + long dram_size = 0; + int casl; + +#if defined(CONFIG_DDR_DLL) + /* + * This DLL-Override only used on TQM8540 and TQM8560 + */ + { + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + int i, x; + + x = 10; + + /* + * Work around to stabilize DDR DLL + */ + gur->ddrdllcr = 0x81000000; + asm ("sync; isync; msync"); + udelay (200); + while (gur->ddrdllcr != 0x81000100) { + gur->devdisr = gur->devdisr | 0x00010000; + asm ("sync; isync; msync"); + for (i = 0; i < x; i++) + ; + gur->devdisr = gur->devdisr & 0xfff7ffff; + asm ("sync; isync; msync"); + x++; + } + } +#endif + + casl = cas_latency (); + dram_size = sdram_setup (casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + puts ("Problem with CAS lantency"); + board_add_ram_info (1); + puts (", using default CL!\n"); + casl = CONFIG_DDR_DEFAULT_CL; + dram_size = sdram_setup (casl); + puts (" "); + } + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test passed.\n"); + return 0; +} +#endif diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c new file mode 100644 index 0000000000..380448a4f5 --- /dev/null +++ b/board/tqc/tqm85xx/tlb.c @@ -0,0 +1,248 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024, + CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024, + CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024, + CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + +#ifndef CONFIG_TQM_BIGFLASH + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000, + CFG_FLASH_BASE + 0x4000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, + CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M PCI express MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M PCI express MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000, + CFG_PCIE1_MEM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#else /* !CONFIG_PCIE */ + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000, + CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif /* CONFIG_PCIE */ + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe0000000 1M CCSRBAR + * 0xe2000000 16M PCI1 IO + * 0xe3000000 16M CAN and NAND Flash + */ + SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, + CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 9: 16M Non-cacheable, guarded + * 0xef000000 16M PCI express IO + */ + SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_16M, 1), +#endif /* CONFIG_PCIE */ + +#else /* CONFIG_TQM_BIGFLASH */ + + /* + * TLB 0,1,2,3: 1G Non-cacheable, guarded + * 0xc0000000 1G FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000, + CFG_FLASH_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000, + CFG_FLASH_BASE + 0x20000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000, + CFG_FLASH_BASE + 0x30000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, + CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xc0000000 256M PCI express MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), +#else /* !CONFIG_PCIE */ + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xb0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + +#endif /* CONFIG_PCIE */ + + /* + * TLB 7: 64M Non-cacheable, guarded + * 0xa0000000 1M CCSRBAR + * 0xa2000000 16M PCI1 IO + * 0xa3000000 16M CAN and NAND Flash + */ + SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 8+9: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, + CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 10: 16M Non-cacheable, guarded + * 0xaf000000 16M PCI express IO + */ + SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif /* CONFIG_PCIE */ + +#endif /* CONFIG_TQM_BIGFLASH */ +}; + +int num_tlb_entries = ARRAY_SIZE (tlb_table); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c new file mode 100644 index 0000000000..f1c2e58edd --- /dev/null +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -0,0 +1,744 @@ +/* + * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> + * + * (C) Copyright 2006 + * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de. + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <asm/io.h> +#include <ioports.h> +#include <flash.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +void local_bus_init (void); +ulong flash_get_size (ulong base, int banknum); + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init (void); +#endif + +#ifdef CONFIG_CPM2 +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A: conf, ppar, psor, pdir, podr, pdat */ + { + {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */ + {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */ + {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */ + {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */ + {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */ + {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */ + {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */ + {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */ + {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */ + {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */ + {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */ + {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */ + {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */ + {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */ + {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */ + {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */ + {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */ + {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */ + {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */ + {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */ + {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */ + {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */ + {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */ + {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */ + {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */ + {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */ + {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */ + {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */ + {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */ + {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */ + }, + + /* Port B: conf, ppar, psor, pdir, podr, pdat */ + { + {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */ + {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */ + {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */ + {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */ + {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */ + {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */ + {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */ + {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */ + {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */ + {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */ + {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */ + {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */ + {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */ + {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */ + {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */ + {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */ + {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */ + {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */ + {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */ + {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */ + {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */ + }, + + /* Port C: conf, ppar, psor, pdir, podr, pdat */ + { + {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */ + {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */ + {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */ + {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */ + {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */ + {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */ + {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */ + {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */ + {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */ + {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */ + {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */ + {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */ + {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */ + {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */ + {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */ + {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */ + {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */ + {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */ + {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */ + {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */ + {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */ + {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */ + {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */ + {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */ + {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */ + {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */ + {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */ + {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */ + {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */ + {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */ + {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */ + {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */ + }, + + /* Port D: conf, ppar, psor, pdir, podr, pdat */ + { +#ifdef CONFIG_TQM8560 + {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ + {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ + {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ +#else /* !CONFIG_TQM8560 */ + {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */ + {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */ + {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */ +#endif /* CONFIG_TQM8560 */ + {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ + {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ + {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */ + {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */ + {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */ + {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */ + {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */ + {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */ + {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */ + {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */ + {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */ + {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */ + {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */ + {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */ + {0, 0, 0, 1, 0, 0}, /* PD14: LED */ + {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */ + {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */ + {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */ + {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */ + {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */ + {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */ + {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */ + {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */ + {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */ + {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */ + {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */ + } +}; +#endif /* CONFIG_CPM2 */ + +#define CASL_STRING1 "casl=xx" +#define CASL_STRING2 "casl=" + +static const int casl_table[] = { 20, 25, 30 }; +#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) + +int cas_latency (void) +{ + char *s = getenv ("serial#"); + int casl; + int val; + int i; + + casl = CONFIG_DDR_DEFAULT_CL; + + if (s != NULL) { + if (strncmp(s + strlen (s) - strlen (CASL_STRING1), + CASL_STRING2, strlen (CASL_STRING2)) == 0) { + val = simple_strtoul (s + strlen (s) - 2, NULL, 10); + + for (i = 0; i < N_CASL; ++i) { + if (val == casl_table[i]) { + return val; + } + } + } + } + + return casl; +} + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + printf ("Board: %s", CONFIG_BOARDNAME); + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + /* + * Initialize local bus. + */ + local_bus_init (); + + return 0; +} + +int misc_init_r (void) +{ + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Recalculate CS configuration if second FLASH bank is available + */ + if (flash_info[0].size > 0) { + memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | + (CFG_OR1_PRELIM & 0x00007fff); + memctl->br1 = gd->bd->bi_flashstart | + (CFG_BR1_PRELIM & 0x00007fff); + /* + * Re-check to get correct base address for bank 1 + */ + flash_get_size (gd->bd->bi_flashstart, 0); + } else { + memctl->or1 = 0; + memctl->br1 = 0; + } + + /* + * If bank 1 is equipped, bank 0 is mapped after bank 1 + */ + memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | + (CFG_OR0_PRELIM & 0x00007fff); + memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | + (CFG_BR0_PRELIM & 0x00007fff); + /* + * Re-check to get correct base address for bank 0 + */ + flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + +#ifdef CFG_ENV_ADDR_REDUND + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); +#endif + + return 0; +} + +#ifdef CONFIG_CAN_DRIVER +/* + * Initialize UPMC RAM + */ +static void upmc_write (u_char addr, uint val) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + out_be32 (&lbc->mdr, val); + + clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK, + MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); + + /* dummy access to perform write */ + out_8 ((void __iomem *)CFG_CAN_BASE, 0); + + /* normal operation */ + clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); +} +#endif /* CONFIG_CAN_DRIVER */ + +uint get_lbc_clock (void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + sys_info_t sys_info; + ulong clkdiv = lbc->lcrr & 0x0f; + + get_sys_info (&sys_info); + + if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { +#ifdef CONFIG_MPC8548 + /* + * Yes, the entire PQ38 family use the same + * bit-representation for twice the clock divider value. + */ + clkdiv *= 2; +#endif + return sys_info.freqSystemBus / clkdiv; + } + + puts("Invalid clock divider value in CFG_LBC_LCRR\n"); + + return 0; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + uint lbc_mhz = get_lbc_clock () / 1000000; + +#ifdef CONFIG_MPC8548 + uint svr = get_svr (); + uint lcrr; + + /* + * MPC revision < 2.0 + * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: + * Modify engineering use only register at address 0xE_0F20. + * "1. Read register at offset 0xE_0F20 + * 2. And value with 0x0000_FFFF + * 3. OR result with 0x0000_0004 + * 4. Write result back to offset 0xE_0F20." + * + * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: + * Modify engineering use only register at address 0xE_0F20. + * "1. Read register at offset 0xE_0F20 + * 2. And value with 0xFFFF_FFDF + * 3. Write result back to offset 0xE_0F20." + * + * Since it is the same register, we do the modification in one step. + */ + if (SVR_MAJ (svr) < 2) { + uint dummy = gur->lbiuiplldcr1; + dummy &= 0x0000FFDF; + dummy |= 0x00000004; + gur->lbiuiplldcr1 = dummy; + } + + lcrr = CFG_LBC_LCRR; + + /* + * Local Bus Clock > 83.3 MHz. According to timing + * specifications set LCRR[EADC] to 2 delay cycles. + */ + if (lbc_mhz > 83) { + lcrr &= ~LCRR_EADC; + lcrr |= LCRR_EADC_2; + } + + /* + * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 + * disable PLL bypass for Local Bus Clock > 83 MHz. + */ + if (lbc_mhz >= 66) + lcrr &= (~LCRR_DBYP); /* DLL Enabled */ + + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + + lbc->lcrr = lcrr; + asm ("sync;isync;msync"); + + /* + * According to MPC8548ERMAD Rev.1.3 read back LCRR + * and terminate with isync + */ + lcrr = lbc->lcrr; + asm ("isync;"); + + /* let DLL stabilize */ + udelay (500); + +#else /* !CONFIG_MPC8548 */ + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + if (lbc_mhz < 66) { + lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ + lbc->ltedr = 0xa4c80000; /* DK: !!! */ + + } else if (lbc_mhz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr (); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + udelay (200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm ("sync;isync;msync"); + } +#endif /* !CONFIG_MPC8548 */ + +#ifdef CONFIG_CAN_DRIVER + /* + * According to timing specifications EAD must be + * set if Local Bus Clock is > 83 MHz. + */ + if (lbc_mhz > 83) + out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD); + else + out_be32 (&lbc->or2, CFG_OR2_CAN); + out_be32 (&lbc->br2, CFG_BR2_CAN); + + /* LGPL4 is UPWAIT */ + out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); + + /* Initialize UPMC for CAN: single read */ + upmc_write (0x00, 0xFFFFED00); + upmc_write (0x01, 0xCCFFCC00); + upmc_write (0x02, 0x00FFCF00); + upmc_write (0x03, 0x00FFCF00); + upmc_write (0x04, 0x00FFDC00); + upmc_write (0x05, 0x00FFCF00); + upmc_write (0x06, 0x00FFED00); + upmc_write (0x07, 0x3FFFCC07); + + /* Initialize UPMC for CAN: single write */ + upmc_write (0x18, 0xFFFFED00); + upmc_write (0x19, 0xCCFFEC00); + upmc_write (0x1A, 0x00FFED80); + upmc_write (0x1B, 0x00FFED80); + upmc_write (0x1C, 0x00FFFC00); + upmc_write (0x1D, 0x0FFFEC00); + upmc_write (0x1E, 0x0FFFEF00); + upmc_write (0x1F, 0x3FFFEC05); +#endif /* CONFIG_CAN_DRIVER */ +} + +/* + * Initialize PCI Devices, report devices found. + */ +static int first_free_busno; + +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +static struct pci_controller pci1_hose; +#endif /* CONFIG_PCI || CONFIG_PCI1 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +static inline void init_pci1(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + /* PORDEVSR[15] */ + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + /* PORDEVSR[14] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + /* PORPLLSR[16] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || + (host_agent == 6); + + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333333) ? "33" : + (pci_speed == 66666666) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter"); + + + /* inbound */ + pci_set_region (hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region (hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region (hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect (hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init (hose); + + printf (" PCI on bus %02x..%02x\n", + hose->first_busno, hose->last_busno); + + first_free_busno = hose->last_busno + 1; +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + ushort reg16 = + PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | + PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + uint dev = PCI_BDF(hose->first_busno, 0, 0); + + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + puts ("PCI-X will only work at 66 MHz\n"); + + pci_hose_write_config_word (hose, dev, PCIX_COMMAND, + reg16); + } +#endif + } else { + puts ("PCI1: disabled\n"); + } +#else /* !(CONFIG_PCI || CONFIG_PCI1) */ + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif /* CONFIG_PCI || CONFIG_PCI1) */ +} + +static inline void init_pcie1(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_PCIE1 + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || + (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("PCIe: %s, base address %x", + pcie_ep ? "End point" : "Root complex", (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (", with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + puts ("\n"); + + /* inbound */ + pci_set_region (hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region (hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region (hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init (hose); + printf (" PCIe on bus %02x..%02x\n", + hose->first_busno, hose->last_busno); + + first_free_busno = hose->last_busno + 1; + + } else { + printf ("PCIe: disabled\n"); + } +#else /* !CONFIG_PCIE1 */ + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif /* CONFIG_PCIE1 */ +} + +void pci_init_board (void) +{ + init_pci1(); + init_pcie1(); +} + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup (void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + ft_cpu_setup (blob, bd); + + node = fdt_path_offset (blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) + path = fdt_getprop (blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); + } +#endif /* CONFIG_PCI || CONFIG_PCI1 */ +#ifdef CONFIG_PCIE1 + path = fdt_getprop (blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); + } +#endif /* CONFIG_PCIE1 */ + } +} +#endif /* CONFIG_OF_BOARD_SETUP */ + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ +#ifdef CONFIG_PS2MULT + ps2mult_early_init (); +#endif /* CONFIG_PS2MULT */ + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ diff --git a/board/tqm85xx/u-boot.lds b/board/tqc/tqm85xx/u-boot.lds index 8cb551ae4b..8cb551ae4b 100644 --- a/board/tqm85xx/u-boot.lds +++ b/board/tqc/tqm85xx/u-boot.lds diff --git a/board/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile index b48934b429..b48934b429 100644 --- a/board/tqm8xx/Makefile +++ b/board/tqc/tqm8xx/Makefile diff --git a/board/tqm8xx/config.mk b/board/tqc/tqm8xx/config.mk index 9d6080b84a..9d6080b84a 100644 --- a/board/tqm8xx/config.mk +++ b/board/tqc/tqm8xx/config.mk diff --git a/board/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c index 4342ebc841..4342ebc841 100644 --- a/board/tqm8xx/flash.c +++ b/board/tqc/tqm8xx/flash.c diff --git a/board/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c index 143f36801d..143f36801d 100644 --- a/board/tqm8xx/load_sernum_ethaddr.c +++ b/board/tqc/tqm8xx/load_sernum_ethaddr.c diff --git a/board/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 18bf2a8302..96b6103fc7 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -139,7 +139,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 8c46e4677f..8c46e4677f 100644 --- a/board/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds diff --git a/board/tqm8xx/u-boot.lds.debug b/board/tqc/tqm8xx/u-boot.lds.debug index c33581d250..c33581d250 100644 --- a/board/tqm8xx/u-boot.lds.debug +++ b/board/tqc/tqm8xx/u-boot.lds.debug diff --git a/board/tqm85xx/law.c b/board/tqm85xx/law.c deleted file mode 100644 index 224af6ca77..0000000000 --- a/board/tqm85xx/law.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c deleted file mode 100644 index 788a48cd13..0000000000 --- a/board/tqm85xx/sdram.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <asm/mmu.h> - -struct sdram_conf_s { - unsigned long size; - unsigned long reg; -}; - -typedef struct sdram_conf_s sdram_conf_t; - -sdram_conf_t ddr_cs_conf[] = { - {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ - {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ - {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ - {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ -}; - -#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) - -int cas_latency(void); - -/* - * Autodetect onboard DDR SDRAM on 85xx platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -long int sdram_setup(int casl) -{ - int i; - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); - unsigned long cfg_ddr_timing1; - unsigned long cfg_ddr_mode; - - /* - * Disable memory controller. - */ - ddr->cs0_config = 0; - ddr->sdram_cfg = 0; - - switch (casl) { - case 20: - cfg_ddr_timing1 = 0x47405331 | (3 << 16); - cfg_ddr_mode = 0x40020002 | (2 << 4); - break; - - case 25: - cfg_ddr_timing1 = 0x47405331 | (4 << 16); - cfg_ddr_mode = 0x40020002 | (6 << 4); - break; - - case 30: - default: - cfg_ddr_timing1 = 0x47405331 | (5 << 16); - cfg_ddr_mode = 0x40020002 | (3 << 4); - break; - } - - ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; - ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_1 = cfg_ddr_timing1; - ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ - ddr->sdram_mode = cfg_ddr_mode; - ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ - ddr->err_disable = 0x0000000D; - - asm ("sync;isync;msync"); - udelay(1000); - - ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ - asm ("sync; isync; msync"); - udelay(1000); - - for (i=0; i<N_DDR_CS_CONF; i++) { - ddr->cs0_config = ddr_cs_conf[i].reg; - - if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { - /* - * OK, size detected -> all done - */ - return ddr_cs_conf[i].size; - } - } - - return 0; /* nothing found ! */ -} - -void board_add_ram_info(int use_default) -{ - int casl; - - if (use_default) - casl = CONFIG_DDR_DEFAULT_CL; - else - casl = cas_latency(); - - puts(" (CL="); - switch (casl) { - case 20: - puts("2)"); - break; - - case 25: - puts("2.5)"); - break; - - case 30: - puts("3)"); - break; - } -} - -long int initdram (int board_type) -{ - long dram_size = 0; - int casl; - -#if defined(CONFIG_DDR_DLL) - /* - * This DLL-Override only used on TQM8540 and TQM8560 - */ - { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; i<x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - - casl = cas_latency(); - dram_size = sdram_setup(casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - puts("Problem with CAS lantency"); - board_add_ram_info(1); - puts(", using default CL!\n"); - casl = CONFIG_DDR_DEFAULT_CL; - dram_size = sdram_setup(casl); - puts(" "); - } - - return dram_size; -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test passed.\n"); - return 0; -} -#endif diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c deleted file mode 100644 index ad26caeea2..0000000000 --- a/board/tqm85xx/tlb.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c deleted file mode 100644 index 8fa0162d83..0000000000 --- a/board/tqm85xx/tqm85xx.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <ioports.h> -#include <flash.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -void local_bus_init (void); -ulong flash_get_size (ulong base, int banknum); - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); -#endif - -#ifdef CONFIG_CPM2 -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; -#endif /* CONFIG_CPM2 */ - -#define CASL_STRING1 "casl=xx" -#define CASL_STRING2 "casl=" - -static const int casl_table[] = { 20, 25, 30 }; -#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) - -int cas_latency(void) -{ - char *s = getenv("serial#"); - int casl; - int val; - int i; - - casl = CONFIG_DDR_DEFAULT_CL; - - if (s != NULL) { - if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2, - strlen(CASL_STRING2)) == 0) { - val = simple_strtoul(s + strlen(s) - 2, NULL, 10); - - for (i=0; i<N_CASL; ++i) { - if (val == casl_table[i]) { - return val; - } - } - } - } - - return casl; -} - -int checkboard (void) -{ - char *s = getenv("serial#"); - - printf("Board: %s", CONFIG_BOARDNAME); - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - -#ifdef CONFIG_PCI - printf ("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf ("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -int misc_init_r (void) -{ - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); - } - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { - memctl->or1 = 0; - memctl->br1 = 0; - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - } - - return 0; -} - -/* - * Initialize Local Bus - */ -void local_bus_init (void) -{ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ - lbc->ltedr = 0xa4c80000; /* DK: !!! */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr (); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - udelay (200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm ("sync;isync;msync"); - } -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - {} -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void pci_init_board (void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init (&hose); -#endif /* CONFIG_PCI */ -} - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ diff --git a/board/trab/Makefile b/board/trab/Makefile index fbe1c3640f..2402577a50 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -60,7 +60,7 @@ clean: rm -f $(SOBJS) $(OBJS) $(OBJS_FKT) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/trab/memory.c b/board/trab/memory.c index 8614be7bad..052432e9d9 100644 --- a/board/trab/memory.c +++ b/board/trab/memory.c @@ -460,7 +460,7 @@ int memory_post_test (int flags) { int ret = 0; bd_t *bd = gd->bd; - unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? + phys_size_t memsize = (bd->bi_memsize >= 256 << 20 ? 256 << 20 : bd->bi_memsize) - (1 << 20); diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile index 115e17ded9..44c0d495ef 100644 --- a/board/trizepsiv/Makefile +++ b/board/trizepsiv/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c index a5dd95d78e..896f9693e3 100644 --- a/board/uc100/uc100.c +++ b/board/uc100/uc100.c @@ -169,7 +169,7 @@ int checkboard (void) /* * Initialize SDRAM */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/uc101/Makefile b/board/uc101/Makefile index ddfd2ef8af..442e2d0df2 100644 --- a/board/uc101/Makefile +++ b/board/uc101/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/uc101/uc101.c b/board/uc101/uc101.c index f726513965..69ba5078d4 100644 --- a/board/uc101/uc101.c +++ b/board/uc101/uc101.c @@ -146,7 +146,7 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c index 834fd84079..e2a961a3a3 100644 --- a/board/utx8245/utx8245.c +++ b/board/utx8245/utx8245.c @@ -46,7 +46,7 @@ int checkboard(void) } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { long size; long new_bank0_end; diff --git a/board/v37/v37.c b/board/v37/v37.c index 2e47573024..2067fedfca 100644 --- a/board/v37/v37.c +++ b/board/v37/v37.c @@ -90,7 +90,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/v38b/Makefile b/board/v38b/Makefile index b21bd6f6c5..0b227dac0f 100644 --- a/board/v38b/Makefile +++ b/board/v38b/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index ec032eef8d..8815a0cb4a 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -71,7 +71,7 @@ static void sdram_start(int hi_addr) #endif /* !CFG_RAMBOOT */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/versatile/Makefile b/board/versatile/Makefile index 1fad0a7ee3..044a429899 100644 --- a/board/versatile/Makefile +++ b/board/versatile/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile index 9386bb0e7a..e7c1cbb312 100644 --- a/board/voiceblue/Makefile +++ b/board/voiceblue/Makefile @@ -62,7 +62,7 @@ clean: distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/w7o/Makefile b/board/w7o/Makefile index 46b8c8923a..e481bb2880 100644 --- a/board/w7o/Makefile +++ b/board/w7o/Makefile @@ -43,7 +43,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index c56c269dae..0e3b84c613 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -31,6 +31,7 @@ #include <watchdog.h> unsigned long get_dram_size (void); +void sdram_init(void); /* * Macros to transform values @@ -151,8 +152,15 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + return get_dram_size (); } diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile index 58a70ccd75..0669b0ebba 100644 --- a/board/wepep250/Makefile +++ b/board/wepep250/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c index 8826667cdc..4742aafc5e 100644 --- a/board/westel/amx860/amx860.c +++ b/board/westel/amx860/amx860.c @@ -61,7 +61,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile index 9a79f7d981..7dd2ea04a6 100644 --- a/board/xaeniax/Makefile +++ b/board/xaeniax/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile index 05ad23524f..9215d77bb0 100644 --- a/board/xilinx/ml300/Makefile +++ b/board/xilinx/ml300/Makefile @@ -58,7 +58,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S index f753df851a..a282c9ae22 100644 --- a/board/xilinx/ml300/init.S +++ b/board/xilinx/ml300/init.S @@ -42,7 +42,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c index 58bfac0716..5d493eeb73 100644 --- a/board/xilinx/ml300/ml300.c +++ b/board/xilinx/ml300/ml300.c @@ -79,7 +79,7 @@ checkboard(void) return (0); } -long int +phys_size_t initdram(int board_type) { return 128 * 1024 * 1024; diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c index ba41f856e4..993dfa30f6 100644 --- a/board/xilinx/ml300/serial.c +++ b/board/xilinx/ml300/serial.c @@ -36,9 +36,9 @@ * */ +#include <common.h> #include <asm/u-boot.h> #include <asm/processor.h> -#include <common.h> #include <command.h> #include <config.h> diff --git a/board/xilinx/ml401/Makefile b/board/xilinx/ml401/Makefile index ee9b6d5d29..10b47b2ae5 100644 --- a/board/xilinx/ml401/Makefile +++ b/board/xilinx/ml401/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/xilinx/xupv2p/Makefile b/board/xilinx/xupv2p/Makefile index ee9b6d5d29..10b47b2ae5 100644 --- a/board/xilinx/xupv2p/Makefile +++ b/board/xilinx/xupv2p/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/xm250/Makefile b/board/xm250/Makefile index 0a6eb320ac..a174f66199 100644 --- a/board/xm250/Makefile +++ b/board/xm250/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/xpedite1k/Makefile b/board/xpedite1k/Makefile index 5da96e9e1c..6ab1a26b15 100644 --- a/board/xpedite1k/Makefile +++ b/board/xpedite1k/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index 8411cf06f7..bc7e3bd17c 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -104,7 +104,7 @@ int checkboard (void) } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile index 3f80a1d515..fc239358b2 100644 --- a/board/xsengine/Makefile +++ b/board/xsengine/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/zeus/Makefile b/board/zeus/Makefile index f0d4e9f3f4..55fb4c4343 100644 --- a/board/zeus/Makefile +++ b/board/zeus/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 4ab853f8f5..0113d4845e 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -208,56 +208,11 @@ static u32 detect_sdram_size(void) return size; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { return detect_sdram_size(); } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - unsigned long msr; - unsigned long total_kbytes; - - total_kbytes = detect_sdram_size(); - - msr = mfmsr(); - mtmsr(msr & ~(MSR_EE)); - - for (k = 0; k < total_kbytes ; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - mtmsr(msr); - - return 0; -} -#endif - static int default_env_var(char *buf, char *var) { char *ptr; diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile index be7e213a9b..dc40d9b94a 100644 --- a/board/zpc1900/Makefile +++ b/board/zpc1900/Makefile @@ -38,7 +38,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c index 7db535e8a4..103ef714fd 100644 --- a/board/zpc1900/zpc1900.c +++ b/board/zpc1900/zpc1900.c @@ -220,7 +220,7 @@ void nvram_write(long dest, const void *src, size_t count) } #endif /* CFG_NVRAM_ACCESS_ROUTINE */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { vu_char *bcsr = (vu_char *)CFG_BCSR; volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile index d72dc98f01..89542356b7 100644 --- a/board/zylonite/Makefile +++ b/board/zylonite/Makefile @@ -39,7 +39,7 @@ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/common/Makefile b/common/Makefile index 9678799227..42871087a4 100644 --- a/common/Makefile +++ b/common/Makefile @@ -113,12 +113,12 @@ COBJS-y += env_dataflash.o COBJS-y += env_flash.o COBJS-y += env_eeprom.o COBJS-y += env_onenand.o +COBJS-y += env_sf.o COBJS-y += env_nvram.o COBJS-y += env_nowhere.o COBJS-y += exports.o COBJS-y += flash.o COBJS-y += fpga.o -COBJS-y += ft_build.o COBJS-y += hush.o COBJS-y += kgdb.o COBJS-y += lcd.o @@ -143,6 +143,7 @@ COBJS-y += xyzModem.o COBJS-y += cmd_mac.o COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o COBJS-$(CONFIG_MP) += cmd_mp.o +COBJS-$(CONFIG_CMD_SF) += cmd_sf.o COBJS := $(COBJS-y) SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 731c1d255d..caa467d026 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; static void print_num(const char *, ulong); #ifndef CONFIG_ARM /* PowerPC and other */ +static void print_lnum(const char *, u64); #ifdef CONFIG_PPC static void print_str(const char *, const char *); @@ -47,7 +48,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("bd address", (ulong)bd ); #endif print_num ("memstart", bd->bi_memstart ); - print_num ("memsize", bd->bi_memsize ); + print_lnum ("memsize", bd->bi_memsize ); print_num ("flashstart", bd->bi_flashstart ); print_num ("flashsize", bd->bi_flashsize ); print_num ("flashoffset", bd->bi_flashoffset ); @@ -59,18 +60,18 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif print_num ("bootflags", bd->bi_bootflags ); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ + defined(CONFIG_405EP) || defined(CONFIG_XILINX_405) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) print_str ("procfreq", strmhz(buf, bd->bi_procfreq)); print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq)); -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_405) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq)); #endif -#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ +#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ #if defined(CONFIG_CPM2) print_str ("vco", strmhz(buf, bd->bi_vco)); print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq)); @@ -81,7 +82,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq)); #endif print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); -#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ +#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ #if defined(CONFIG_MPC8220) print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); @@ -132,7 +133,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) bd_t *bd = gd->bd; print_num ("memstart", (ulong)bd->bi_memstart); - print_num ("memsize", (ulong)bd->bi_memsize); + print_lnum ("memsize", (u64)bd->bi_memsize); print_num ("flashstart", (ulong)bd->bi_flashstart); print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); @@ -158,7 +159,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) bd_t *bd = gd->bd; print_num ("mem start", (ulong)bd->bi_memstart); - print_num ("mem size", (ulong)bd->bi_memsize); + print_lnum ("mem size", (u64)bd->bi_memsize); print_num ("flash start", (ulong)bd->bi_flashstart); print_num ("flash size", (ulong)bd->bi_flashsize); print_num ("flash offset", (ulong)bd->bi_flashoffset); @@ -188,7 +189,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i; bd_t *bd = gd->bd; print_num ("mem start ", (ulong)bd->bi_memstart); - print_num ("mem size ", (ulong)bd->bi_memsize); + print_lnum ("mem size ", (u64)bd->bi_memsize); print_num ("flash start ", (ulong)bd->bi_flashstart); print_num ("flash size ", (ulong)bd->bi_flashsize); print_num ("flash offset ", (ulong)bd->bi_flashoffset); @@ -220,7 +221,7 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) print_num("bd address ", (ulong) bd); #endif print_num("memstart ", bd->bi_memstart); - print_num("memsize ", bd->bi_memsize); + print_lnum("memsize ", bd->bi_memsize); print_num("flashstart ", bd->bi_flashstart); print_num("CFG_MONITOR_BASE ", CFG_MONITOR_BASE); print_num("CFG_ENV_ADDR ", CFG_ENV_ADDR); @@ -257,7 +258,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char buf[32]; print_num ("memstart", (ulong)bd->bi_memstart); - print_num ("memsize", (ulong)bd->bi_memsize); + print_lnum ("memsize", (u64)bd->bi_memsize); print_num ("flashstart", (ulong)bd->bi_flashstart); print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); @@ -328,7 +329,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num("boot_params", (ulong)bd->bi_boot_params); print_num("memstart", (ulong)bd->bi_memstart); - print_num("memsize", (ulong)bd->bi_memsize); + print_lnum("memsize", (u64)bd->bi_memsize); print_num("flashstart", (ulong)bd->bi_flashstart); print_num("flashsize", (ulong)bd->bi_flashsize); print_num("flashoffset", (ulong)bd->bi_flashoffset); @@ -352,7 +353,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("boot_params", (ulong)bd->bi_boot_params); print_num ("memstart", (ulong)bd->bi_memstart); - print_num ("memsize", (ulong)bd->bi_memsize); + print_lnum ("memsize", (u64)bd->bi_memsize); print_num ("flashstart", (ulong)bd->bi_flashstart); print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); @@ -408,6 +409,13 @@ static void print_num(const char *name, ulong value) printf ("%-12s= 0x%08lX\n", name, value); } +#ifndef CONFIG_ARM +static void print_lnum(const char *name, u64 value) +{ + printf ("%-12s= 0x%.8llX\n", name, value); +} +#endif + #if defined(CONFIG_PPC) || defined(CONFIG_M68K) static void print_str(const char *name, const char *str) { diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 0d67132363..959689ea7a 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -127,7 +127,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong os_data, os_len; ulong image_start, image_end; ulong load_start, load_end; - ulong mem_start, mem_size; + ulong mem_start; + phys_size_t mem_size; struct lmb lmb; @@ -141,7 +142,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) mem_start = getenv_bootm_low(); mem_size = getenv_bootm_size(); - lmb_add(&lmb, mem_start, mem_size); + lmb_add(&lmb, (phys_addr_t)mem_start, mem_size); board_lmb_reserve(&lmb); diff --git a/common/cmd_df.c b/common/cmd_df.c new file mode 100644 index 0000000000..5f650442c0 --- /dev/null +++ b/common/cmd_df.c @@ -0,0 +1,37 @@ +/* + * Command for accessing DataFlash. + * + * Copyright (C) 2008 Atmel Corporation + */ +#include <common.h> +#include <df.h> + +static int do_df(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + const char *cmd; + + /* need at least two arguments */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "init") == 0) { + df_init(0, 0, 1000000); + return 0; + } + + if (strcmp(cmd, "info") == 0) { + df_show_info(); + return 0; + } + +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + sf, 2, 1, do_serial_flash, + "sf - Serial flash sub-system\n", + "probe [bus:]cs - init flash device on given SPI bus and CS\n") diff --git a/common/cmd_doc.c b/common/cmd_doc.c index 83aba3744e..d7b2f535f3 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -206,7 +206,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; #if defined(CONFIG_FIT) - const void *fit_hdr; + const void *fit_hdr = NULL; #endif show_boot_progress (34); @@ -275,12 +275,6 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-130); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (131); puts ("Fit image detected...\n"); cnt = fit_get_size (fit_hdr); @@ -304,8 +298,15 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) - fit_print_contents ((const void *)addr); + if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format (fit_hdr)) { + show_boot_progress (-130); + puts ("** Bad FIT image format\n"); + return 1; + } + show_boot_progress (131); + fit_print_contents (fit_hdr); + } #endif /* Loading ok, update default load address */ diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index 0293d186ab..e4fbf29a22 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -787,7 +787,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *ep; int rcode = 0; #if defined(CONFIG_FIT) - const void *fit_hdr; + const void *fit_hdr = NULL; #endif switch (argc) { @@ -847,10 +847,6 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - puts ("** Bad FIT image format\n"); - return 1; - } puts ("Fit image detected...\n"); imsize = fit_get_size (fit_hdr); @@ -879,8 +875,13 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) - fit_print_contents ((const void *)addr); + if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format (fit_hdr)) { + puts ("** Bad FIT image format\n"); + return 1; + } + fit_print_contents (fit_hdr); + } #endif /* Loading ok, update default load address */ diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index ede65ae75a..d3b19ddc1f 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -46,6 +46,11 @@ static int fdt_parse_prop(char **newval, int count, char *data, int *len); static int fdt_print(const char *pathp, char *prop, int depth); /* + * The working_fdt points to our working flattened device tree. + */ +struct fdt_header *working_fdt; + +/* * Flattened Device Tree command, see the help for parameter definitions. */ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) @@ -62,7 +67,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* * Set the address [and length] of the fdt. */ - fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16); + working_fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16); if (!fdt_valid()) { return 1; @@ -75,15 +80,15 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Optional new length */ len = simple_strtoul(argv[3], NULL, 16); - if (len < fdt_totalsize(fdt)) { + if (len < fdt_totalsize(working_fdt)) { printf ("New length %d < existing length %d, " "ignoring.\n", - len, fdt_totalsize(fdt)); + len, fdt_totalsize(working_fdt)); } else { /* * Open in place with a new length. */ - err = fdt_open_into(fdt, fdt, len); + err = fdt_open_into(working_fdt, working_fdt, len); if (err != 0) { printf ("libfdt fdt_open_into(): %s\n", fdt_strerror(err)); @@ -92,9 +97,9 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /******************************************************************** - * Move the fdt + * Move the working_fdt ********************************************************************/ - } else if ((argv[1][0] == 'm') && (argv[1][1] == 'o')) { + } else if (strncmp(argv[1], "mo", 2) == 0) { struct fdt_header *newaddr; int len; int err; @@ -107,7 +112,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* * Set the address and length of the fdt. */ - fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16); + working_fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16); if (!fdt_valid()) { return 1; } @@ -119,13 +124,13 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * current length. */ if (argc <= 4) { - len = fdt_totalsize(fdt); + len = fdt_totalsize(working_fdt); } else { len = simple_strtoul(argv[4], NULL, 16); - if (len < fdt_totalsize(fdt)) { + if (len < fdt_totalsize(working_fdt)) { printf ("New length 0x%X < existing length " "0x%X, aborting.\n", - len, fdt_totalsize(fdt)); + len, fdt_totalsize(working_fdt)); return 1; } } @@ -133,18 +138,18 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* * Copy to the new location. */ - err = fdt_open_into(fdt, newaddr, len); + err = fdt_open_into(working_fdt, newaddr, len); if (err != 0) { printf ("libfdt fdt_open_into(): %s\n", fdt_strerror(err)); return 1; } - fdt = newaddr; + working_fdt = newaddr; /******************************************************************** * Make a new node ********************************************************************/ - } else if ((argv[1][0] == 'm') && (argv[1][1] == 'k')) { + } else if (strncmp(argv[1], "mk", 2) == 0) { char *pathp; /* path */ char *nodep; /* new node to add */ int nodeoffset; /* node offset from libfdt */ @@ -161,7 +166,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) pathp = argv[2]; nodep = argv[3]; - nodeoffset = fdt_path_offset (fdt, pathp); + nodeoffset = fdt_path_offset (working_fdt, pathp); if (nodeoffset < 0) { /* * Not found or something else bad happened. @@ -170,7 +175,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) fdt_strerror(nodeoffset)); return 1; } - err = fdt_add_subnode(fdt, nodeoffset, nodep); + err = fdt_add_subnode(working_fdt, nodeoffset, nodep); if (err < 0) { printf ("libfdt fdt_add_subnode(): %s\n", fdt_strerror(err)); @@ -178,7 +183,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /******************************************************************** - * Set the value of a property in the fdt. + * Set the value of a property in the working_fdt. ********************************************************************/ } else if (argv[1][0] == 's') { char *pathp; /* path */ @@ -206,7 +211,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return ret; } - nodeoffset = fdt_path_offset (fdt, pathp); + nodeoffset = fdt_path_offset (working_fdt, pathp); if (nodeoffset < 0) { /* * Not found or something else bad happened. @@ -216,7 +221,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - ret = fdt_setprop(fdt, nodeoffset, prop, data, len); + ret = fdt_setprop(working_fdt, nodeoffset, prop, data, len); if (ret < 0) { printf ("libfdt fdt_setprop(): %s\n", fdt_strerror(ret)); return 1; @@ -259,7 +264,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /******************************************************************** * Remove a property/node ********************************************************************/ - } else if ((argv[1][0] == 'r') && (argv[1][1] == 'm')) { + } else if (strncmp(argv[1], "rm", 2) == 0) { int nodeoffset; /* node offset from libfdt */ int err; @@ -267,7 +272,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Get the path. The root node is an oddball, the offset * is zero and has no name. */ - nodeoffset = fdt_path_offset (fdt, argv[2]); + nodeoffset = fdt_path_offset (working_fdt, argv[2]); if (nodeoffset < 0) { /* * Not found or something else bad happened. @@ -281,14 +286,14 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * otherwise delete the node. */ if (argc > 3) { - err = fdt_delprop(fdt, nodeoffset, argv[3]); + err = fdt_delprop(working_fdt, nodeoffset, argv[3]); if (err < 0) { printf("libfdt fdt_delprop(): %s\n", fdt_strerror(err)); return err; } } else { - err = fdt_del_node(fdt, nodeoffset); + err = fdt_del_node(working_fdt, nodeoffset); if (err < 0) { printf("libfdt fdt_del_node(): %s\n", fdt_strerror(err)); @@ -300,38 +305,43 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Display header info ********************************************************************/ } else if (argv[1][0] == 'h') { - u32 version = fdt_version(fdt); - printf("magic:\t\t\t0x%x\n", fdt_magic(fdt)); - printf("totalsize:\t\t0x%x (%d)\n", fdt_totalsize(fdt), fdt_totalsize(fdt)); - printf("off_dt_struct:\t\t0x%x\n", fdt_off_dt_struct(fdt)); - printf("off_dt_strings:\t\t0x%x\n", fdt_off_dt_strings(fdt)); - printf("off_mem_rsvmap:\t\t0x%x\n", fdt_off_mem_rsvmap(fdt)); + u32 version = fdt_version(working_fdt); + printf("magic:\t\t\t0x%x\n", fdt_magic(working_fdt)); + printf("totalsize:\t\t0x%x (%d)\n", fdt_totalsize(working_fdt), + fdt_totalsize(working_fdt)); + printf("off_dt_struct:\t\t0x%x\n", + fdt_off_dt_struct(working_fdt)); + printf("off_dt_strings:\t\t0x%x\n", + fdt_off_dt_strings(working_fdt)); + printf("off_mem_rsvmap:\t\t0x%x\n", + fdt_off_mem_rsvmap(working_fdt)); printf("version:\t\t%d\n", version); - printf("last_comp_version:\t%d\n", fdt_last_comp_version(fdt)); + printf("last_comp_version:\t%d\n", + fdt_last_comp_version(working_fdt)); if (version >= 2) printf("boot_cpuid_phys:\t0x%x\n", - fdt_boot_cpuid_phys(fdt)); + fdt_boot_cpuid_phys(working_fdt)); if (version >= 3) printf("size_dt_strings:\t0x%x\n", - fdt_size_dt_strings(fdt)); + fdt_size_dt_strings(working_fdt)); if (version >= 17) printf("size_dt_struct:\t\t0x%x\n", - fdt_size_dt_struct(fdt)); - printf("number mem_rsv:\t\t0x%x\n", fdt_num_mem_rsv(fdt)); + fdt_size_dt_struct(working_fdt)); + printf("number mem_rsv:\t\t0x%x\n", + fdt_num_mem_rsv(working_fdt)); printf("\n"); /******************************************************************** * Set boot cpu id ********************************************************************/ - } else if ((argv[1][0] == 'b') && (argv[1][1] == 'o') && - (argv[1][2] == 'o')) { + } else if (strncmp(argv[1], "boo", 3) == 0) { unsigned long tmp = simple_strtoul(argv[2], NULL, 16); - fdt_set_boot_cpuid_phys(fdt, tmp); + fdt_set_boot_cpuid_phys(working_fdt, tmp); /******************************************************************** * memory command ********************************************************************/ - } else if ((argv[1][0] == 'm') && (argv[1][1] == 'e')) { + } else if (strncmp(argv[1], "me", 2) == 0) { uint64_t addr, size; int err; #ifdef CFG_64BIT_STRTOUL @@ -341,23 +351,23 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[2], NULL, 16); size = simple_strtoul(argv[3], NULL, 16); #endif - err = fdt_fixup_memory(fdt, addr, size); + err = fdt_fixup_memory(working_fdt, addr, size); if (err < 0) return err; /******************************************************************** * mem reserve commands ********************************************************************/ - } else if ((argv[1][0] == 'r') && (argv[1][1] == 's')) { + } else if (strncmp(argv[1], "rs", 2) == 0) { if (argv[2][0] == 'p') { uint64_t addr, size; - int total = fdt_num_mem_rsv(fdt); + int total = fdt_num_mem_rsv(working_fdt); int j, err; printf("index\t\t start\t\t size\n"); printf("-------------------------------" "-----------------\n"); for (j = 0; j < total; j++) { - err = fdt_get_mem_rsv(fdt, j, &addr, &size); + err = fdt_get_mem_rsv(working_fdt, j, &addr, &size); if (err < 0) { printf("libfdt fdt_get_mem_rsv(): %s\n", fdt_strerror(err)); @@ -379,7 +389,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[3], NULL, 16); size = simple_strtoul(argv[4], NULL, 16); #endif - err = fdt_add_mem_rsv(fdt, addr, size); + err = fdt_add_mem_rsv(working_fdt, addr, size); if (err < 0) { printf("libfdt fdt_add_mem_rsv(): %s\n", @@ -388,7 +398,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } } else if (argv[2][0] == 'd') { unsigned long idx = simple_strtoul(argv[3], NULL, 16); - int err = fdt_del_mem_rsv(fdt, idx); + int err = fdt_del_mem_rsv(working_fdt, idx); if (err < 0) { printf("libfdt fdt_del_mem_rsv(): %s\n", @@ -403,12 +413,12 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } #ifdef CONFIG_OF_BOARD_SETUP /* Call the board-specific fixup routine */ - else if (argv[1][0] == 'b') - ft_board_setup(fdt, gd->bd); + else if (strncmp(argv[1], "boa", 3) == 0) + ft_board_setup(working_fdt, gd->bd); #endif /* Create a chosen node */ else if (argv[1][0] == 'c') - fdt_chosen(fdt, 0, 0, 1); + fdt_chosen(working_fdt, 0, 0, 1); else { /* Unrecognized command */ printf ("Usage:\n%s\n", cmdtp->usage); @@ -424,12 +434,12 @@ static int fdt_valid(void) { int err; - if (fdt == NULL) { + if (working_fdt == NULL) { printf ("The address of the fdt is invalid (NULL).\n"); return 0; } - err = fdt_check_header(fdt); + err = fdt_check_header(working_fdt); if (err == 0) return 1; /* valid */ @@ -439,17 +449,19 @@ static int fdt_valid(void) * Be more informative on bad version. */ if (err == -FDT_ERR_BADVERSION) { - if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) { - printf (" - too old, fdt $d < %d", - fdt_version(fdt), + if (fdt_version(working_fdt) < + FDT_FIRST_SUPPORTED_VERSION) { + printf (" - too old, fdt %d < %d", + fdt_version(working_fdt), FDT_FIRST_SUPPORTED_VERSION); - fdt = NULL; + working_fdt = NULL; } - if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) { - printf (" - too new, fdt $d > %d", - fdt_version(fdt), + if (fdt_last_comp_version(working_fdt) > + FDT_LAST_SUPPORTED_VERSION) { + printf (" - too new, fdt %d > %d", + fdt_version(working_fdt), FDT_LAST_SUPPORTED_VERSION); - fdt = NULL; + working_fdt = NULL; } return 0; } @@ -534,7 +546,7 @@ static int fdt_parse_prop(char **newval, int count, char *data, int *len) newp = newval[++stridx]; } if (*newp != ']') { - printf("Unexpected character '%c'\n", *newval); + printf("Unexpected character '%c'\n", *newp); return 1; } } else { @@ -645,7 +657,7 @@ static void print_data(const void *data, int len) /****************************************************************************/ /* - * Recursively print (a portion of) the fdt. The depth parameter + * Recursively print (a portion of) the working_fdt. The depth parameter * determines how deeply nested the fdt is printed. */ static int fdt_print(const char *pathp, char *prop, int depth) @@ -661,7 +673,7 @@ static int fdt_print(const char *pathp, char *prop, int depth) int level = 0; /* keep track of nesting level */ const struct fdt_property *fdt_prop; - nodeoffset = fdt_path_offset (fdt, pathp); + nodeoffset = fdt_path_offset (working_fdt, pathp); if (nodeoffset < 0) { /* * Not found or something else bad happened. @@ -675,7 +687,7 @@ static int fdt_print(const char *pathp, char *prop, int depth) * Print only the given property and then return. */ if (prop) { - nodep = fdt_getprop (fdt, nodeoffset, prop, &len); + nodep = fdt_getprop (working_fdt, nodeoffset, prop, &len); if (len == 0) { /* no property value */ printf("%s %s\n", pathp, prop); @@ -697,10 +709,10 @@ static int fdt_print(const char *pathp, char *prop, int depth) * print the node and all subnodes. */ while(level >= 0) { - tag = fdt_next_tag(fdt, nodeoffset, &nextoffset); + tag = fdt_next_tag(working_fdt, nodeoffset, &nextoffset); switch(tag) { case FDT_BEGIN_NODE: - pathp = fdt_get_name(fdt, nodeoffset, NULL); + pathp = fdt_get_name(working_fdt, nodeoffset, NULL); if (level <= depth) { if (pathp == NULL) pathp = "/* NULL pointer error */"; @@ -724,9 +736,9 @@ static int fdt_print(const char *pathp, char *prop, int depth) } break; case FDT_PROP: - fdt_prop = fdt_offset_ptr(fdt, nodeoffset, + fdt_prop = fdt_offset_ptr(working_fdt, nodeoffset, sizeof(*fdt_prop)); - pathp = fdt_string(fdt, + pathp = fdt_string(working_fdt, fdt32_to_cpu(fdt_prop->nameoff)); len = fdt32_to_cpu(fdt_prop->len); nodep = fdt_prop->data; @@ -751,7 +763,7 @@ static int fdt_print(const char *pathp, char *prop, int depth) } break; case FDT_NOP: - printf("/* NOP */\n", &tabs[MAX_LEVEL - level]); + printf("%s/* NOP */\n", &tabs[MAX_LEVEL - level]); break; case FDT_END: return 1; diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 65607022eb..97a873d1c9 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -367,7 +367,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; #if defined(CONFIG_FIT) - const void *fit_hdr; + const void *fit_hdr = NULL; #endif show_boot_progress (41); @@ -465,12 +465,6 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-140); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (141); puts ("Fit image detected...\n"); cnt = fit_get_size (fit_hdr); @@ -496,8 +490,15 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) - fit_print_contents ((const void *)addr); + if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format (fit_hdr)) { + show_boot_progress (-140); + puts ("** Bad FIT image format\n"); + return 1; + } + show_boot_progress (141); + fit_print_contents (fit_hdr); + } #endif /* Loading ok, update default load address */ diff --git a/common/cmd_log.c b/common/cmd_log.c index c6e72ac3c0..fdcc57571a 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -66,6 +66,12 @@ static logbuff_t *log; #endif static char *lbuf; +unsigned long __logbuffer_base(void) +{ + return CFG_SDRAM_BASE + gd->bd->bi_memsize - LOGBUFF_LEN; +} +unsigned long logbuffer_base (void) __attribute__((weak, alias("__logbuffer_base"))); + void logbuff_init_ptrs (void) { unsigned long tag, post_word; @@ -75,7 +81,7 @@ void logbuff_init_ptrs (void) log = (logbuff_t *)CONFIG_ALT_LH_ADDR; lbuf = (char *)CONFIG_ALT_LB_ADDR; #else - log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1; + log = (logbuff_t *)(logbuffer_base ()) - 1; lbuf = (char *)log->buf; #endif diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 37eb41b20e..e20c1af353 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -37,8 +37,6 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); #endif -extern nand_info_t nand_info[]; /* info for NAND chips */ - static int nand_dump_oob(nand_info_t *nand, ulong off) { return 0; @@ -486,7 +484,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, image_header_t *hdr; int jffs2 = 0; #if defined(CONFIG_FIT) - const void *fit_hdr; + const void *fit_hdr = NULL; #endif s = strchr(cmd, '.'); @@ -528,12 +526,6 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-150); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (151); puts ("Fit image detected...\n"); cnt = fit_get_size (fit_hdr); @@ -566,8 +558,15 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, #if defined(CONFIG_FIT) /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) - fit_print_contents ((const void *)addr); + if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format (fit_hdr)) { + show_boot_progress (-150); + puts ("** Bad FIT image format\n"); + return 1; + } + show_boot_progress (151); + fit_print_contents (fit_hdr); + } #endif /* Loading ok, update default load address */ @@ -954,7 +953,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; #if defined(CONFIG_FIT) - const void *fit_hdr; + const void *fit_hdr = NULL; #endif show_boot_progress (52); @@ -1023,12 +1022,6 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-150); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (151); puts ("Fit image detected...\n"); cnt = fit_get_size (fit_hdr); @@ -1052,8 +1045,15 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) - fit_print_contents ((const void *)addr); + if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format (fit_hdr)) { + show_boot_progress (-150); + puts ("** Bad FIT image format\n"); + return 1; + } + show_boot_progress (151); + fit_print_contents (fit_hdr); + } #endif /* Loading ok, update default load address */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 9c5d1fcb90..85a0f94f0f 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -58,8 +58,9 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CFG_ENV_IS_IN_DATAFLASH) && \ !defined(CFG_ENV_IS_IN_NAND) && \ !defined(CFG_ENV_IS_IN_ONENAND) && \ + !defined(CFG_ENV_IS_IN_SPI_FLASH) && \ !defined(CFG_ENV_IS_NOWHERE) -# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE} +# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|SPI_FLASH|NOWHERE} #endif #define XMK_STR(x) #x @@ -179,11 +180,12 @@ int _do_setenv (int flag, int argc, char *argv[]) * Ethernet Address and serial# can be set only once, * ver is readonly. */ + if ( #ifdef CONFIG_HAS_UID /* Allow serial# forced overwrite with 0xdeaf4add flag */ - if ( ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || + ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || #else - if ( (strcmp (name, "serial#") == 0) || + (strcmp (name, "serial#") == 0) || #endif ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) @@ -379,13 +381,13 @@ int _do_setenv (int flag, int argc, char *argv[]) return 0; } -void setenv (char *varname, char *varvalue) +int setenv (char *varname, char *varvalue) { char *argv[4] = { "setenv", varname, varvalue, NULL }; if (varvalue == NULL) - _do_setenv (0, 2, argv); + return _do_setenv (0, 2, argv); else - _do_setenv (0, 3, argv); + return _do_setenv (0, 3, argv); } #ifdef CONFIG_HAS_UID diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 69028f3b6b..e648f7d601 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -212,7 +212,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; #if defined(CONFIG_FIT) - const void *fit_hdr; + const void *fit_hdr = NULL; #endif switch (argc) { @@ -291,10 +291,6 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - puts ("** Bad FIT image format\n"); - return 1; - } puts ("Fit image detected...\n"); cnt = fit_get_size (fit_hdr); @@ -317,8 +313,13 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) - fit_print_contents ((const void *)addr); + if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format (fit_hdr)) { + puts ("** Bad FIT image format\n"); + return 1; + } + fit_print_contents (fit_hdr); + } #endif /* Loading ok, update default load address */ diff --git a/common/cmd_sf.c b/common/cmd_sf.c new file mode 100644 index 0000000000..8c0a7514df --- /dev/null +++ b/common/cmd_sf.c @@ -0,0 +1,191 @@ +/* + * Command for accessing SPI flash. + * + * Copyright (C) 2008 Atmel Corporation + */ +#include <common.h> +#include <spi_flash.h> + +#include <asm/io.h> + +#ifndef CONFIG_SF_DEFAULT_SPEED +# define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#endif + +static struct spi_flash *flash; + +static int do_spi_flash_probe(int argc, char *argv[]) +{ + unsigned int bus = 0; + unsigned int cs; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + char *endp; + struct spi_flash *new; + + if (argc < 2) + goto usage; + + cs = simple_strtoul(argv[1], &endp, 0); + if (*argv[1] == 0 || (*endp != 0 && *endp != ':')) + goto usage; + if (*endp == ':') { + if (endp[1] == 0) + goto usage; + + bus = cs; + cs = simple_strtoul(endp + 1, &endp, 0); + if (*endp != 0) + goto usage; + } + + if (argc >= 3) { + speed = simple_strtoul(argv[2], &endp, 0); + if (*argv[2] == 0 || *endp != 0) + goto usage; + } + if (argc >= 4) { + mode = simple_strtoul(argv[3], &endp, 0); + if (*argv[3] == 0 || *endp != 0) + goto usage; + } + + new = spi_flash_probe(bus, cs, speed, mode); + if (!new) { + printf("Failed to initialize SPI flash at %u:%u\n", bus, cs); + return 1; + } + + if (flash) + spi_flash_free(flash); + flash = new; + + printf("%u KiB %s at %u:%u is now current device\n", + flash->size >> 10, flash->name, bus, cs); + + return 0; + +usage: + puts("Usage: sf probe [bus:]cs [hz] [mode]\n"); + return 1; +} + +static int do_spi_flash_read_write(int argc, char *argv[]) +{ + unsigned long addr; + unsigned long offset; + unsigned long len; + void *buf; + char *endp; + int ret; + + if (argc < 4) + goto usage; + + addr = simple_strtoul(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + goto usage; + offset = simple_strtoul(argv[2], &endp, 16); + if (*argv[2] == 0 || *endp != 0) + goto usage; + len = simple_strtoul(argv[3], &endp, 16); + if (*argv[3] == 0 || *endp != 0) + goto usage; + + buf = map_physmem(addr, len, MAP_WRBACK); + if (!buf) { + puts("Failed to map physical memory\n"); + return 1; + } + + if (strcmp(argv[0], "read") == 0) + ret = spi_flash_read(flash, offset, len, buf); + else + ret = spi_flash_write(flash, offset, len, buf); + + unmap_physmem(buf, len); + + if (ret) { + printf("SPI flash %s failed\n", argv[0]); + return 1; + } + + return 0; + +usage: + printf("Usage: sf %s addr offset len\n", argv[0]); + return 1; +} + +static int do_spi_flash_erase(int argc, char *argv[]) +{ + unsigned long offset; + unsigned long len; + char *endp; + int ret; + + if (argc < 3) + goto usage; + + offset = simple_strtoul(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + goto usage; + len = simple_strtoul(argv[2], &endp, 16); + if (*argv[2] == 0 || *endp != 0) + goto usage; + + ret = spi_flash_erase(flash, offset, len); + if (ret) { + printf("SPI flash %s failed\n", argv[0]); + return 1; + } + + return 0; + +usage: + puts("Usage: sf erase offset len\n"); + return 1; +} + +static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + const char *cmd; + + /* need at least two arguments */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "probe") == 0) + return do_spi_flash_probe(argc - 1, argv + 1); + + /* The remaining commands require a selected device */ + if (!flash) { + puts("No SPI flash selected. Please run `sf probe'\n"); + return 1; + } + + if (strcmp(cmd, "read") == 0 || strcmp(cmd, "write") == 0) + return do_spi_flash_read_write(argc - 1, argv + 1); + if (strcmp(cmd, "erase") == 0) + return do_spi_flash_erase(argc - 1, argv + 1); + +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + sf, 5, 1, do_spi_flash, + "sf - SPI flash sub-system\n", + "probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n" + " and chip select\n" + "sf read addr offset len - read `len' bytes starting at\n" + " `offset' to memory at `addr'\n" + "sf write addr offset len - write `len' bytes from memory\n" + " at `addr' to flash at `offset'\n" + "sf erase offset len - erase `len' bytes from `offset'\n"); diff --git a/common/cmd_spi.c b/common/cmd_spi.c index 7604422141..40ee7e7dd3 100644 --- a/common/cmd_spi.c +++ b/common/cmd_spi.c @@ -37,20 +37,20 @@ # define MAX_SPI_BYTES 32 /* Maximum number of bytes we can handle */ #endif -/* - * External table of chip select functions (see the appropriate board - * support for the actual definition of the table). - */ -extern spi_chipsel_type spi_chipsel[]; -extern int spi_chipsel_cnt; +#ifndef CONFIG_DEFAULT_SPI_BUS +# define CONFIG_DEFAULT_SPI_BUS 0 +#endif +#ifndef CONFIG_DEFAULT_SPI_MODE +# define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 +#endif /* * Values from last command. */ -static int device; -static int bitlen; -static uchar dout[MAX_SPI_BYTES]; -static uchar din[MAX_SPI_BYTES]; +static unsigned int device; +static int bitlen; +static uchar dout[MAX_SPI_BYTES]; +static uchar din[MAX_SPI_BYTES]; /* * SPI read/write @@ -65,6 +65,7 @@ static uchar din[MAX_SPI_BYTES]; int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + struct spi_slave *slave; char *cp = 0; uchar tmp; int j; @@ -101,19 +102,24 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } - if ((device < 0) || (device >= spi_chipsel_cnt)) { - printf("Invalid device %d, giving up.\n", device); - return 1; - } if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) { printf("Invalid bitlen %d, giving up.\n", bitlen); return 1; } - debug ("spi_chipsel[%d] = %08X\n", - device, (uint)spi_chipsel[device]); + /* FIXME: Make these parameters run-time configurable */ + slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000, + CONFIG_DEFAULT_SPI_MODE); + if (!slave) { + printf("Invalid device %d, giving up.\n", device); + return 1; + } + + debug ("spi chipsel = %08X\n", device); - if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) { + spi_claim_bus(slave); + if(spi_xfer(slave, bitlen, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END) != 0) { printf("Error with the SPI transaction.\n"); rcode = 1; } else { @@ -123,6 +129,8 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf("\n"); } + spi_release_bus(slave); + spi_free_slave(slave); return rcode; } diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 9be86b874d..f2795d3f40 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -316,7 +316,7 @@ int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; block_dev_desc_t *stor_dev; #if defined(CONFIG_FIT) - const void *fit_hdr; + const void *fit_hdr = NULL; #endif switch (argc) { @@ -404,10 +404,6 @@ int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - puts ("** Bad FIT image format\n"); - return 1; - } puts ("Fit image detected...\n"); cnt = fit_get_size (fit_hdr); @@ -430,8 +426,13 @@ int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_FIT) /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) - fit_print_contents ((const void *)addr); + if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format (fit_hdr)) { + puts ("** Bad FIT image format\n"); + return 1; + } + fit_print_contents (fit_hdr); + } #endif /* Loading ok, update default load address */ diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 20c206913c..c51351e961 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1,3 +1,5 @@ +#include <common.h> + #if 0 /* Moved to malloc.h */ /* ---------- To make a malloc.h, start cutting here ------------ */ @@ -947,7 +949,6 @@ void malloc_stats(); #endif /* 0 */ #endif /* 0 */ /* Moved to malloc.h */ -#include <common.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/common/env_common.c b/common/env_common.c index a49481244e..d51c2114de 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -50,7 +50,6 @@ extern void env_relocate_spec (void); extern uchar env_get_char_spec(int); static uchar env_get_char_init (int index); -uchar (*env_get_char)(int) = env_get_char_init; /************************************************************************ * Default settings to be used when no valid environment is found @@ -134,7 +133,8 @@ uchar default_environment[] = { "\0" }; -#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ +#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ \ + || defined(CFG_ENV_IS_IN_SPI_FLASH) int default_environment_size = sizeof(default_environment); #endif @@ -182,6 +182,19 @@ uchar env_get_char_memory (int index) } #endif +uchar env_get_char (int index) +{ + uchar c; + + /* if relocated to RAM */ + if (gd->flags & GD_FLG_RELOC) + c = env_get_char_memory(index); + else + c = env_get_char_init(index); + + return (c); +} + uchar *env_get_addr (int index) { if (gd->env_valid) { @@ -191,6 +204,23 @@ uchar *env_get_addr (int index) } } +void set_default_env(void) +{ + if (sizeof(default_environment) > ENV_SIZE) { + puts ("*** Error - default environment is too large\n\n"); + return; + } + + memset(env_ptr, 0, sizeof(env_t)); + memcpy(env_ptr->data, default_environment, + sizeof(default_environment)); +#ifdef CFG_REDUNDAND_ENVIRONMENT + env_ptr->flags = 0xFF; +#endif + env_crc_update (); + gd->env_valid = 1; +} + void env_relocate (void) { DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, @@ -215,11 +245,6 @@ void env_relocate (void) DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); #endif - /* - * After relocation to RAM, we can always use the "memory" functions - */ - env_get_char = env_get_char_memory; - if (gd->env_valid == 0) { #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ puts ("Using default environment\n\n"); @@ -227,22 +252,7 @@ void env_relocate (void) puts ("*** Warning - bad CRC, using default environment\n\n"); show_boot_progress (-60); #endif - - if (sizeof(default_environment) > ENV_SIZE) - { - puts ("*** Error - default environment is too large\n\n"); - return; - } - - memset (env_ptr, 0, sizeof(env_t)); - memcpy (env_ptr->data, - default_environment, - sizeof(default_environment)); -#ifdef CFG_REDUNDAND_ENVIRONMENT - env_ptr->flags = 0xFF; -#endif - env_crc_update (); - gd->env_valid = 1; + set_default_env(); } else { env_relocate_spec (); diff --git a/common/env_nand.c b/common/env_nand.c index 70d05ad15a..104f0856af 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008 + * Stuart Wood, Lab X Technologies <stuart.wood@labxtechnologies.com> + * * (C) Copyright 2004 * Jian Zhang, Texas Instruments, jzhang@ti.com. @@ -53,13 +56,14 @@ #error CONFIG_INFERNO not supported yet #endif +#ifndef CFG_ENV_RANGE +#define CFG_ENV_RANGE CFG_ENV_SIZE +#endif + int nand_legacy_rw (struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -/* info for NAND chips, defined in drivers/mtd/nand/nand.c */ -extern nand_info_t nand_info[]; - /* references to names in env_common.c */ extern uchar default_environment[]; extern int default_environment_size; @@ -91,8 +95,8 @@ uchar env_get_char_spec (int index) /* this is called before nand_init() * so we can't read Nand to validate env data. * Mark it OK for now. env_relocate() in env_common.c - * will call our relocate function which will does - * the real validation. + * will call our relocate function which does the real + * validation. * * When using a NAND boot image (like sequoia_nand), the environment * can be embedded or attached to the U-Boot image in NAND flash. This way @@ -151,35 +155,71 @@ int env_init(void) * The legacy NAND code saved the environment in the first NAND device i.e., * nand_dev_desc + 0. This is also the behaviour using the new NAND code. */ +int writeenv(size_t offset, u_char *buf) +{ + size_t end = offset + CFG_ENV_RANGE; + size_t amount_saved = 0; + size_t blocksize; + + u_char *char_ptr; + + blocksize = nand_info[0].erasesize; + + while (amount_saved < CFG_ENV_SIZE && offset < end) { + if (nand_block_isbad(&nand_info[0], offset)) { + offset += blocksize; + } else { + char_ptr = &buf[amount_saved]; + if (nand_write(&nand_info[0], offset, &blocksize, + char_ptr)) + return 1; + offset += blocksize; + amount_saved += blocksize; + } + } + if (amount_saved != CFG_ENV_SIZE) + return 1; + + return 0; +} #ifdef CFG_ENV_OFFSET_REDUND int saveenv(void) { size_t total; int ret = 0; + nand_erase_options_t nand_erase_options; env_ptr->flags++; total = CFG_ENV_SIZE; + nand_erase_options.length = CFG_ENV_RANGE; + nand_erase_options.quiet = 0; + nand_erase_options.jffs2 = 0; + nand_erase_options.scrub = 0; + + if (CFG_ENV_RANGE < CFG_ENV_SIZE) + return 1; if(gd->env_valid == 1) { - puts ("Erasing redundant Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + puts ("Erasing redundant Nand...\n"); + nand_erase_options.offset = CFG_ENV_OFFSET_REDUND; + if (nand_erase_opts(&nand_info[0], &nand_erase_options)) return 1; + puts ("Writing to redundant Nand... "); - ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, - (u_char*) env_ptr); + ret = writeenv(CFG_ENV_OFFSET_REDUND, (u_char *) env_ptr); } else { - puts ("Erasing Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET, CFG_ENV_SIZE)) + puts ("Erasing Nand...\n"); + nand_erase_options.offset = CFG_ENV_OFFSET; + if (nand_erase_opts(&nand_info[0], &nand_erase_options)) return 1; puts ("Writing to Nand... "); - ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, - (u_char*) env_ptr); + ret = writeenv(CFG_ENV_OFFSET, (u_char *) env_ptr); } - if (ret || total != CFG_ENV_SIZE) + if (ret) { + puts("FAILED!\n"); return 1; + } puts ("done\n"); gd->env_valid = (gd->env_valid == 2 ? 1 : 2); @@ -190,16 +230,26 @@ int saveenv(void) { size_t total; int ret = 0; + nand_erase_options_t nand_erase_options; + + nand_erase_options.length = CFG_ENV_RANGE; + nand_erase_options.quiet = 0; + nand_erase_options.jffs2 = 0; + nand_erase_options.scrub = 0; + nand_erase_options.offset = CFG_ENV_OFFSET; - puts ("Erasing Nand..."); - if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) + if (CFG_ENV_RANGE < CFG_ENV_SIZE) + return 1; + puts ("Erasing Nand...\n"); + if (nand_erase_opts(&nand_info[0], &nand_erase_options)) return 1; puts ("Writing to Nand... "); total = CFG_ENV_SIZE; - ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); - if (ret || total != CFG_ENV_SIZE) + if (writeenv(CFG_ENV_OFFSET, (u_char *) env_ptr)) { + puts("FAILED!\n"); return 1; + } puts ("done\n"); return ret; @@ -207,6 +257,33 @@ int saveenv(void) #endif /* CFG_ENV_OFFSET_REDUND */ #endif /* CMD_SAVEENV */ +int readenv (size_t offset, u_char * buf) +{ + size_t end = offset + CFG_ENV_RANGE; + size_t amount_loaded = 0; + size_t blocksize; + + u_char *char_ptr; + + blocksize = nand_info[0].erasesize; + + while (amount_loaded < CFG_ENV_SIZE && offset < end) { + if (nand_block_isbad(&nand_info[0], offset)) { + offset += blocksize; + } else { + char_ptr = &buf[amount_loaded]; + if (nand_read(&nand_info[0], offset, &blocksize, char_ptr)) + return 1; + offset += blocksize; + amount_loaded += blocksize; + } + } + if (amount_loaded != CFG_ENV_SIZE) + return 1; + + return 0; +} + #ifdef CFG_ENV_OFFSET_REDUND void env_relocate_spec (void) { @@ -220,10 +297,10 @@ void env_relocate_spec (void) tmp_env1 = (env_t *) malloc(CFG_ENV_SIZE); tmp_env2 = (env_t *) malloc(CFG_ENV_SIZE); - nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, - (u_char*) tmp_env1); - nand_read(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, - (u_char*) tmp_env2); + if (readenv(CFG_ENV_OFFSET, (u_char *) tmp_env1)) + puts("No Valid Environment Area Found\n"); + if (readenv(CFG_ENV_OFFSET_REDUND, (u_char *) tmp_env2)) + puts("No Valid Reundant Environment Area Found\n"); crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); @@ -272,7 +349,7 @@ void env_relocate_spec (void) int ret; total = CFG_ENV_SIZE; - ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); + ret = readenv(CFG_ENV_OFFSET, (u_char *) env_ptr); if (ret || total != CFG_ENV_SIZE) return use_default(); @@ -286,19 +363,7 @@ void env_relocate_spec (void) static void use_default() { puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); - - if (default_environment_size > CFG_ENV_SIZE){ - puts ("*** Error - default environment is too large\n\n"); - return; - } - - memset (env_ptr, 0, sizeof(env_t)); - memcpy (env_ptr->data, - default_environment, - default_environment_size); - env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); - gd->env_valid = 1; - + set_default_env(); } #endif diff --git a/common/env_sf.c b/common/env_sf.c new file mode 100644 index 0000000000..d641a9a73c --- /dev/null +++ b/common/env_sf.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Andreas Heppel <aheppel@sysgo.de> + * + * (C) Copyright 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#ifdef CFG_ENV_IS_IN_SPI_FLASH + +#include <environment.h> +#include <spi_flash.h> + +#ifndef CFG_ENV_SPI_BUS +# define CFG_ENV_SPI_BUS 0 +#endif +#ifndef CFG_ENV_SPI_CS +# define CFG_ENV_SPI_CS 0 +#endif +#ifndef CFG_ENV_SPI_MAX_HZ +# define CFG_ENV_SPI_MAX_HZ 1000000 +#endif +#ifndef CFG_ENV_SPI_MODE +# define CFG_ENV_SPI_MODE SPI_MODE_3 +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* references to names in env_common.c */ +extern uchar default_environment[]; +extern int default_environment_size; + +char * env_name_spec = "SPI Flash"; +env_t *env_ptr; + +static struct spi_flash *env_flash; + +uchar env_get_char_spec(int index) +{ + return *((uchar *)(gd->env_addr + index)); +} + +int saveenv(void) +{ + if (!env_flash) { + puts("Environment SPI flash not initialized\n"); + return 1; + } + + puts("Erasing SPI flash..."); + if (spi_flash_erase(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE)) + return 1; + + puts("Writing to SPI flash..."); + if (spi_flash_write(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE, env_ptr)) + return 1; + + puts("done\n"); + return 0; +} + +void env_relocate_spec(void) +{ + int ret; + + env_flash = spi_flash_probe(CFG_ENV_SPI_BUS, CFG_ENV_SPI_CS, + CFG_ENV_SPI_MAX_HZ, CFG_ENV_SPI_MODE); + if (!env_flash) + goto err_probe; + + ret = spi_flash_read(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE, env_ptr); + if (ret) + goto err_read; + + if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) + goto err_crc; + + gd->env_valid = 1; + + return; + +err_read: + spi_flash_free(env_flash); + env_flash = NULL; +err_probe: +err_crc: + puts("*** Warning - bad CRC, using default environment\n\n"); + + if (default_environment_size > CFG_ENV_SIZE) { + gd->env_valid = 0; + puts("*** Error - default environment is too large\n\n"); + return; + } + + memset(env_ptr, 0, sizeof(env_t)); + memcpy(env_ptr->data, default_environment, default_environment_size); + env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); + gd->env_valid = 1; +} + +int env_init(void) +{ + /* SPI flash isn't usable before relocation */ + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; + + return 0; +} + +#endif /* CFG_ENV_IS_IN_SPI_FLASH */ diff --git a/common/fdt_support.c b/common/fdt_support.c index 75077442d8..3828228204 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -35,11 +35,6 @@ */ DECLARE_GLOBAL_DATA_PTR; -/* - * fdt points to our working device tree. - */ -struct fdt_header *fdt; - /** * fdt_find_and_setprop: Find a node and set it's property @@ -68,7 +63,7 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, } #ifdef CONFIG_OF_STDOUT_VIA_ALIAS -static int fdt_fixup_stdout(void *fdt, int choosenoff) +static int fdt_fixup_stdout(void *fdt, int chosenoff) { int err = 0; #ifdef CONFIG_CONS_INDEX @@ -87,7 +82,7 @@ static int fdt_fixup_stdout(void *fdt, int choosenoff) err = -FDT_ERR_NOSPACE; if (p) { memcpy(p, path, len); - err = fdt_setprop(fdt, choosenoff, + err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", p, len); free(p); } diff --git a/common/ft_build.c b/common/ft_build.c deleted file mode 100644 index b951178a1d..0000000000 --- a/common/ft_build.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * OF flat tree builder - * Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com> - * Updated by: Matthew McClintock <msm@freescale.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <malloc.h> -#include <environment.h> - -#ifdef CONFIG_OF_FLAT_TREE - -#include <asm/errno.h> -#include <stddef.h> - -#include <ft_build.h> -#include <linux/ctype.h> - -#undef DEBUG - -/* align addr on a size boundary - adjust address up if needed -- Cort */ -#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1))) -#ifndef CONFIG_OF_BOOT_CPU -#define CONFIG_OF_BOOT_CPU 0 -#endif -#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64)) - -static void ft_put_word(struct ft_cxt *cxt, u32 v) -{ - memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p); - - *(u32 *) cxt->p = cpu_to_be32(v); - cxt->p += sizeof(u32); - cxt->p_end += sizeof(u32); -} - -static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz) -{ - int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz, - sizeof(u32))) - cxt->p; - - memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p); - - /* make sure the last bytes are zeroed */ - memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0, - (aligned_size % sizeof(u32))); - - memcpy(cxt->p, data, sz); - - cxt->p += aligned_size; - cxt->p_end += aligned_size; -} - -void ft_begin_node(struct ft_cxt *cxt, const char *name) -{ - ft_put_word(cxt, OF_DT_BEGIN_NODE); - ft_put_bin(cxt, name, strlen(name) + 1); -} - -void ft_end_node(struct ft_cxt *cxt) -{ - ft_put_word(cxt, OF_DT_END_NODE); -} - -void ft_nop(struct ft_cxt *cxt) -{ - ft_put_word(cxt, OF_DT_NOP); -} - -static int lookup_string(struct ft_cxt *cxt, const char *name) -{ - u8 *p; - - p = cxt->p; - while (p < cxt->p_end) { - if (strcmp((char *)p, name) == 0) - return p - cxt->p; - p += strlen((char *)p) + 1; - } - - return -1; -} - -void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz) -{ - int off = 0; - - off = lookup_string(cxt, name); - if (off == -1) { - memcpy(cxt->p_end, name, strlen(name) + 1); - off = cxt->p_end - cxt->p; - cxt->p_end += strlen(name) + 1; - } - - /* now put offset from beginning of *STRUCTURE* */ - /* will be fixed up at the end */ - ft_put_word(cxt, OF_DT_PROP); - ft_put_word(cxt, sz); - ft_put_word(cxt, off); - ft_put_bin(cxt, data, sz); -} - -void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str) -{ - ft_prop(cxt, name, str, strlen(str) + 1); -} - -void ft_prop_int(struct ft_cxt *cxt, const char *name, int val) -{ - u32 v = cpu_to_be32((u32) val); - - ft_prop(cxt, name, &v, sizeof(u32)); -} - -/* pick up and start working on a tree in place */ -void ft_init_cxt(struct ft_cxt *cxt, void *blob) -{ - struct boot_param_header *bph = blob; - - memset(cxt, 0, sizeof(*cxt)); - - cxt->bph = bph; - bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU; - - /* find beginning and end of reserve map table (zeros in last entry) */ - cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap; - while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 && - ((uint64_t *)cxt->p_rsvmap)[1] != 0 ) { - cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; - } - - cxt->p_start = (u8 *)bph + bph->off_dt_struct; - cxt->p_end = (u8 *)bph + bph->totalsize; - cxt->p = (u8 *)bph + bph->off_dt_strings; -} - -/* add a reserver physical area to the rsvmap */ -void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend) -{ - memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap, - cxt->p_end - cxt->p_rsvmap); - - ((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart); - ((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend); - ((u64 *)cxt->p_rsvmap)[2] = 0; - ((u64 *)cxt->p_rsvmap)[3] = 0; - - cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; - cxt->p_start += SIZE_OF_RSVMAP_ENTRY; - cxt->p += SIZE_OF_RSVMAP_ENTRY; - cxt->p_end += SIZE_OF_RSVMAP_ENTRY; -} - -void ft_end_tree(struct ft_cxt *cxt) -{ - ft_put_word(cxt, OF_DT_END); -} - -/* update the boot param header with correct values */ -void ft_finalize_tree(struct ft_cxt *cxt) { - struct boot_param_header *bph = cxt->bph; - - bph->totalsize = cxt->p_end - (u8 *)bph; - bph->off_dt_struct = cxt->p_start - (u8 *)bph; - bph->off_dt_strings = cxt->p - (u8 *)bph; - bph->dt_strings_size = cxt->p_end - cxt->p; -} - -static int is_printable_string(const void *data, int len) -{ - const char *s = data; - const char *ss; - - /* zero length is not */ - if (len == 0) - return 0; - - /* must terminate with zero */ - if (s[len - 1] != '\0') - return 0; - - ss = s; - while (*s && isprint(*s)) - s++; - - /* not zero, or not done yet */ - if (*s != '\0' || (s + 1 - ss) < len) - return 0; - - return 1; -} - -static void print_data(const void *data, int len) -{ - int i; - const u8 *s; - - /* no data, don't print */ - if (len == 0) - return; - - if (is_printable_string(data, len)) { - puts(" = \""); - puts(data); - puts("\""); - return; - } - - switch (len) { - case 1: /* byte */ - printf(" = <%02x>", (*(u8 *) data) & 0xff); - break; - case 2: /* half-word */ - printf(" = <%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); - break; - case 4: /* word */ - printf(" = <%x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); - break; - case 8: /* double-word */ - printf(" = <%qx>", be64_to_cpu(*(uint64_t *) data)); - break; - default: /* anything else... hexdump */ - printf(" = ["); - for (i = 0, s = data; i < len; i++) - printf("%02x%s", s[i], i < len - 1 ? " " : ""); - printf("]"); - - break; - } -} - -void ft_dump_blob(const void *bphp) -{ - const struct boot_param_header *bph = bphp; - const uint64_t *p_rsvmap = (const uint64_t *) - ((const char *)bph + be32_to_cpu(bph->off_mem_rsvmap)); - const u32 *p_struct = (const u32 *) - ((const char *)bph + be32_to_cpu(bph->off_dt_struct)); - const u32 *p_strings = (const u32 *) - ((const char *)bph + be32_to_cpu(bph->off_dt_strings)); - u32 tag; - const u32 *p; - const char *s, *t; - int depth, sz, shift; - int i; - uint64_t addr, size; - - if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { - /* not valid tree */ - return; - } - - depth = 0; - shift = 4; - - for (i = 0;; i++) { - addr = be64_to_cpu(p_rsvmap[i * 2]); - size = be64_to_cpu(p_rsvmap[i * 2 + 1]); - if (addr == 0 && size == 0) - break; - - printf("/memreserve/ %qx %qx;\n", addr, size); - } - - p = p_struct; - while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { - - /* printf("tag: 0x%08x (%d)\n", tag, p - p_struct); */ - - if (tag == OF_DT_BEGIN_NODE) { - s = (const char *)p; - p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); - - printf("%*s%s {\n", depth * shift, "", s); - - depth++; - continue; - } - - if (tag == OF_DT_END_NODE) { - depth--; - - printf("%*s};\n", depth * shift, ""); - continue; - } - - if (tag == OF_DT_NOP) { - printf("%*s[NOP]\n", depth * shift, ""); - continue; - } - - if (tag != OF_DT_PROP) { - fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n", - depth * shift, "", tag, --p); - break; - } - sz = be32_to_cpu(*p++); - s = (const char *)p_strings + be32_to_cpu(*p++); - t = (const char *)p; - p = (const u32 *)_ALIGN((unsigned long)p + sz, 4); - printf("%*s%s", depth * shift, "", s); - print_data(t, sz); - printf(";\n"); - } -} - -void ft_backtrack_node(struct ft_cxt *cxt) -{ - int i = 4; - - while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE) - i += 4; - - memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p); - - cxt->p_end -= i; - cxt->p -= i; -} - -void *ft_get_prop(void *bphp, const char *propname, int *szp) -{ - struct boot_param_header *bph = bphp; - uint32_t *p_struct = - (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); - uint32_t *p_strings = - (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); - uint32_t version = be32_to_cpu(bph->version); - uint32_t tag; - uint32_t *p; - char *s, *t; - char *ss; - int sz; - static char path[256], prop[256]; - - path[0] = '\0'; - - p = p_struct; - while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { - - if (tag == OF_DT_BEGIN_NODE) { - s = (char *)p; - p = (uint32_t *) _ALIGN((unsigned long)p + strlen(s) + - 1, 4); - strcat(path, s); - strcat(path, "/"); - continue; - } - - if (tag == OF_DT_END_NODE) { - path[strlen(path) - 1] = '\0'; - ss = strrchr(path, '/'); - if (ss != NULL) - ss[1] = '\0'; - continue; - } - - if (tag == OF_DT_NOP) - continue; - - if (tag != OF_DT_PROP) - break; - - sz = be32_to_cpu(*p++); - s = (char *)p_strings + be32_to_cpu(*p++); - if (version < 0x10 && sz >= 8) - p = (uint32_t *) _ALIGN((unsigned long)p, 8); - t = (char *)p; - p = (uint32_t *) _ALIGN((unsigned long)p + sz, 4); - - strcpy(prop, path); - strcat(prop, s); - - if (strcmp(prop, propname) == 0) { - *szp = sz; - return t; - } - } - - return NULL; -} - -/********************************************************************/ - -void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end) -{ - u32 *p; - int len; - struct ft_cxt cxt; - ulong clock; - - /* disable OF tree; booting old kernel */ - if (getenv("disable_of") != NULL) { - memcpy(blob, bd, sizeof(*bd)); - return; - } - -#ifdef DEBUG - printf ("recieved oftree\n"); - ft_dump_blob(blob); -#endif - - ft_init_cxt(&cxt, blob); - - if (initrd_start && initrd_end) - ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1); - - /* back into root */ - ft_backtrack_node(&cxt); - - ft_begin_node(&cxt, "chosen"); - ft_prop_str(&cxt, "name", "chosen"); - - ft_prop_str(&cxt, "bootargs", getenv("bootargs")); - ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */ - if (initrd_start && initrd_end) { - ft_prop_int(&cxt, "linux,initrd-start", initrd_start); - ft_prop_int(&cxt, "linux,initrd-end", initrd_end); - } -#ifdef OF_STDOUT_PATH - ft_prop_str(&cxt, "linux,stdout-path", OF_STDOUT_PATH); -#endif - - ft_end_node(&cxt); - - ft_end_node(&cxt); /* end root */ - - ft_end_tree(&cxt); - ft_finalize_tree(&cxt); - -#ifdef CONFIG_PPC - clock = bd->bi_intfreq; - p = ft_get_prop(blob, "/cpus/" OF_CPU "/clock-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - -#ifdef OF_TBCLK - clock = OF_TBCLK; - p = ft_get_prop(blob, "/cpus/" OF_CPU "/timebase-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); -#endif -#endif /* __powerpc__ */ - -#ifdef CONFIG_OF_BOARD_SETUP - ft_board_setup(blob, bd); -#endif - - /* in case the size changed in the platform code */ - ft_finalize_tree(&cxt); - -#ifdef DEBUG - printf("final OF-tree\n"); - ft_dump_blob(blob); -#endif -} -#endif diff --git a/common/image.c b/common/image.c index 67e594df69..ddd9e8ba04 100644 --- a/common/image.c +++ b/common/image.c @@ -35,6 +35,10 @@ #include <dataflash.h> #endif +#ifdef CONFIG_LOGBUFFER +#include <logbuff.h> +#endif + #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) #include <rtc.h> #endif @@ -431,11 +435,16 @@ ulong getenv_bootm_low(void) #endif } -ulong getenv_bootm_size(void) +phys_size_t getenv_bootm_size(void) { char *s = getenv ("bootm_size"); if (s) { - ulong tmp = simple_strtoul (s, NULL, 16); + phys_size_t tmp; +#ifdef CFG_64BIT_STRTOUL + tmp = (phys_size_t)simple_strtoull (s, NULL, 16); +#else + tmp = (phys_size_t)simple_strtoul (s, NULL, 16); +#endif return tmp; } @@ -1013,6 +1022,12 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len, initrd_high = ~0; } + +#ifdef CONFIG_LOGBUFFER + /* Prevent initrd from overwriting logbuffer */ + lmb_reserve(lmb, logbuffer_base() - LOGBUFF_OVERHEAD, LOGBUFF_RESERVE); +#endif + debug ("## initrd_high = 0x%08lx, copy_to_ram = %d\n", initrd_high, initrd_copy_to_ram); @@ -1024,9 +1039,9 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len, lmb_reserve(lmb, rd_data, rd_len); } else { if (initrd_high) - *initrd_start = lmb_alloc_base (lmb, rd_len, 0x1000, initrd_high); + *initrd_start = (ulong)lmb_alloc_base (lmb, rd_len, 0x1000, initrd_high); else - *initrd_start = lmb_alloc (lmb, rd_len, 0x1000); + *initrd_start = (ulong)lmb_alloc (lmb, rd_len, 0x1000); if (*initrd_start == 0) { puts ("ramdisk - allocation error\n"); @@ -1079,7 +1094,7 @@ int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end, char *cmdline; char *s; - cmdline = (char *)lmb_alloc_base(lmb, CFG_BARGSIZE, 0xf, + cmdline = (char *)(ulong)lmb_alloc_base(lmb, CFG_BARGSIZE, 0xf, CFG_BOOTMAPSZ + bootmap_base); if (cmdline == NULL) @@ -1115,7 +1130,7 @@ int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end, */ int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base) { - *kbd = (bd_t *)lmb_alloc_base(lmb, sizeof(bd_t), 0xf, + *kbd = (bd_t *)(ulong)lmb_alloc_base(lmb, sizeof(bd_t), 0xf, CFG_BOOTMAPSZ + bootmap_base); if (*kbd == NULL) return -1; diff --git a/common/lcd.c b/common/lcd.c index 914dc2ef7c..ebf377aa89 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -50,6 +50,11 @@ #include <lcdvideo.h> #endif +#if defined(CONFIG_ATMEL_LCD) +#include <atmel_lcdc.h> +#include <nand.h> +#endif + #ifdef CONFIG_LCD /************************************************************************/ @@ -474,14 +479,22 @@ ulong lcd_setmem (ulong addr) static void lcd_setfgcolor (int color) { +#ifdef CONFIG_ATMEL_LCD + lcd_color_fg = color; +#else lcd_color_fg = color & 0x0F; +#endif } /*----------------------------------------------------------------------*/ static void lcd_setbgcolor (int color) { +#ifdef CONFIG_ATMEL_LCD + lcd_color_bg = color; +#else lcd_color_bg = color & 0x0F; +#endif } /*----------------------------------------------------------------------*/ @@ -508,7 +521,11 @@ static int lcd_getbgcolor (void) #ifdef CONFIG_LCD_LOGO void bitmap_plot (int x, int y) { +#ifdef CONFIG_ATMEL_LCD + uint *cmap; +#else ushort *cmap; +#endif ushort i, j; uchar *bmap; uchar *fb; @@ -533,6 +550,8 @@ void bitmap_plot (int x, int y) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); +#elif defined(CONFIG_ATMEL_LCD) + cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0)); #endif WATCHDOG_RESET(); @@ -540,11 +559,26 @@ void bitmap_plot (int x, int y) /* Set color map */ for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) { ushort colreg = bmp_logo_palette[i]; +#ifdef CONFIG_ATMEL_LCD + uint lut_entry; +#ifdef CONFIG_ATMEL_LCD_BGR555 + lut_entry = ((colreg & 0x000F) << 11) | + ((colreg & 0x00F0) << 2) | + ((colreg & 0x0F00) >> 7); +#else /* CONFIG_ATMEL_LCD_RGB565 */ + lut_entry = ((colreg & 0x000F) << 1) | + ((colreg & 0x00F0) << 3) | + ((colreg & 0x0F00) << 4); +#endif + *(cmap + BMP_LOGO_OFFSET) = lut_entry; + cmap++; +#else /* !CONFIG_ATMEL_LCD */ #ifdef CFG_INVERT_COLORS *cmap++ = 0xffff - colreg; #else *cmap++ = colreg; #endif +#endif /* CONFIG_ATMEL_LCD */ } WATCHDOG_RESET(); @@ -578,7 +612,9 @@ void bitmap_plot (int x, int y) */ int lcd_display_bitmap(ulong bmp_image, int x, int y) { -#if !defined(CONFIG_MCC200) +#ifdef CONFIG_ATMEL_LCD + uint *cmap; +#elif !defined(CONFIG_MCC200) ushort *cmap; #endif ushort i, j; @@ -633,6 +669,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); +#elif defined(CONFIG_ATMEL_LCD) + cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0)); #else # error "Don't know location of color map" #endif @@ -708,6 +746,10 @@ static void *lcd_logo (void) #ifdef CONFIG_LCD_INFO char info[80]; char temp[32]; +#ifdef CONFIG_ATMEL_LCD + int i; + ulong dram_size, nand_size; +#endif #endif /* CONFIG_LCD_INFO */ #ifdef CONFIG_SPLASH_SCREEN @@ -765,6 +807,40 @@ static void *lcd_logo (void) # endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_MPC823 */ +#ifdef CONFIG_ATMEL_LCD +# ifdef CONFIG_LCD_INFO + sprintf (info, "%s", U_BOOT_VERSION); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info)); + + sprintf (info, "(C) 2008 ATMEL Corp"); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT, + (uchar *)info, strlen(info)); + + sprintf (info, "at91support@atmel.com"); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2, + (uchar *)info, strlen(info)); + + sprintf (info, "%s CPU at %s MHz", + AT91_CPU_NAME, + strmhz(temp, AT91_MAIN_CLOCK)); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3, + (uchar *)info, strlen(info)); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + sprintf (info, " %ld MB SDRAM, %ld MB NAND", + dram_size >> 20, + nand_size >> 20 ); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4, + (uchar *)info, strlen(info)); +# endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_ATMEL_LCD */ + + #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length)); #else diff --git a/common/main.c b/common/main.c index a17b60b3aa..79ad2912a7 100644 --- a/common/main.c +++ b/common/main.c @@ -509,7 +509,7 @@ void reset_cmd_timeout(void) */ #define putnstr(str,n) do { \ - printf ("%.*s", n, str); \ + printf ("%.*s", (int)n, str); \ } while (0) #define CTL_CH(c) ((c) - 'a' + 1) @@ -940,12 +940,6 @@ int readline_into_buffer (const char *const prompt, char * buffer) int rc; static int initted = 0; - if (!initted) { - hist_init(); - initted = 1; - } - - /* * History uses a global array which is not * writable until after relocation to RAM. diff --git a/common/soft_i2c.c b/common/soft_i2c.c index c5d7e205e5..5ef7f303b8 100644 --- a/common/soft_i2c.c +++ b/common/soft_i2c.c @@ -252,6 +252,7 @@ static uchar read_byte(int ack) * Read 8 bits, MSB first. */ I2C_TRISTATE; + I2C_SDA(1); data = 0; for(j = 0; j < 8; j++) { I2C_SCL(0); diff --git a/common/soft_spi.c b/common/soft_spi.c index e4250616c2..c13165030d 100644 --- a/common/soft_spi.c +++ b/common/soft_spi.c @@ -29,6 +29,8 @@ #if defined(CONFIG_SOFT_SPI) +#include <malloc.h> + /*----------------------------------------------------------------------- * Definitions */ @@ -39,6 +41,15 @@ #define PRINTD(fmt,args...) #endif +struct soft_spi_slave { + struct spi_slave slave; + unsigned int mode; +}; + +static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) +{ + return container_of(slave, struct soft_spi_slave, slave); +} /*=====================================================================*/ /* Public Functions */ @@ -56,6 +67,57 @@ void spi_init (void) #endif } +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct soft_spi_slave *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = malloc(sizeof(struct soft_spi_slave)); + if (!ss) + return NULL; + + ss->slave.bus = bus; + ss->slave.cs = cs; + ss->mode = mode; + + /* TODO: Use max_hz to limit the SCK rate */ + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct soft_spi_slave *ss = to_soft_spi(slave); + + free(ss); +} + +int spi_claim_bus(struct spi_slave *slave) +{ +#ifdef CFG_IMMR + volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif + struct soft_spi_slave *ss = to_soft_spi(slave); + + /* + * Make sure the SPI clock is in idle state as defined for + * this slave. + */ + if (ss->mode & SPI_CPOL) + SPI_SCL(1); + else + SPI_SCL(0); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Nothing to do */ +} /*----------------------------------------------------------------------- * SPI transfer @@ -68,50 +130,54 @@ void spi_init (void) * and "din" can point to the same memory location, in which case the * input data overwrites the output data (since both are buffered by * temporary variables, this is OK). - * - * If the chipsel() function is not NULL, it is called with a parameter - * of '1' (chip select active) at the start of the transfer and again with - * a parameter of '0' at the end of the transfer. - * - * If the chipsel() function _is_ NULL, it the responsibility of the - * caller to make the appropriate chip select active before calling - * spi_xfer() and making it inactive after spi_xfer() returns. */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { #ifdef CFG_IMMR volatile immap_t *immr = (immap_t *)CFG_IMMR; #endif - uchar tmpdin = 0; - uchar tmpdout = 0; - int j; + struct soft_spi_slave *ss = to_soft_spi(slave); + uchar tmpdin = 0; + uchar tmpdout = 0; + const u8 *txd = dout; + u8 *rxd = din; + int cpol = ss->mode & SPI_CPOL; + int cpha = ss->mode & SPI_CPHA; + unsigned int j; - PRINTD("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", - (int)chipsel, *(uint *)dout, *(uint *)din, bitlen); + PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen); - if(chipsel != NULL) { - (*chipsel)(1); /* select the target chip */ - } + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); for(j = 0; j < bitlen; j++) { /* * Check if it is time to work on a new byte. */ if((j % 8) == 0) { - tmpdout = *dout++; + tmpdout = *txd++; if(j != 0) { - *din++ = tmpdin; + *rxd++ = tmpdin; } tmpdin = 0; } - SPI_SCL(0); + + if (!cpha) + SPI_SCL(!cpol); SPI_SDA(tmpdout & 0x80); SPI_DELAY; - SPI_SCL(1); + if (cpha) + SPI_SCL(!cpol); + else + SPI_SCL(cpol); + tmpdin <<= 1; + tmpdin |= SPI_READ; + tmpdout <<= 1; SPI_DELAY; - tmpdin <<= 1; - tmpdin |= SPI_READ; - tmpdout <<= 1; + if (cpha) + SPI_SCL(cpol); } /* * If the number of bits isn't a multiple of 8, shift the last @@ -120,14 +186,10 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) */ if((bitlen % 8) != 0) tmpdin <<= 8 - (bitlen % 8); - *din++ = tmpdin; - - SPI_SCL(0); /* SPI wants the clock left low for idle */ + *rxd++ = tmpdin; - if(chipsel != NULL) { - (*chipsel)(0); /* deselect the target chip */ - - } + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); return(0); } @@ -172,6 +172,8 @@ else CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes endif +CFLAGS += $(call cc-option,-fno-stack-protector) + # avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) # this option have to be placed behind -Wall -- that's why it is here ifeq ($(ARCH),nios) diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index 9c8998b604..ea43c9a9bf 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -44,8 +44,9 @@ #include <74xx_7xx.h> #include <asm/cache.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <fdt_support.h> #endif #ifdef CONFIG_AMIGAONEG3SE @@ -301,29 +302,19 @@ watchdog_reset(void) /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_OF_FLAT_TREE -void -ft_cpu_setup (void *blob, bd_t *bd) +#ifdef CONFIG_OF_LIBFDT +void ft_cpu_setup(void *blob, bd_t *bd) { - u32 *p; - ulong clock; - int len; - - clock = bd->bi_busfreq; + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 4, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); - p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32 (clock); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -#if defined(CONFIG_TSI108_ETH) - p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len); - memcpy (p, bd->bi_enetaddr, 6); -#endif - -#if defined(CONFIG_HAS_ETH1) - p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len); - memcpy (p, bd->bi_enet1addr, 6); -#endif + fdt_fixup_ethernet(blob, bd); } #endif /* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index b5834b91e3..42b0f72ac0 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -316,7 +316,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -327,7 +327,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -414,7 +414,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c index 1cad8f9d8c..f498599419 100644 --- a/cpu/arm1136/mx31/serial.c +++ b/cpu/arm1136/mx31/serial.c @@ -63,6 +63,7 @@ #define URXD_FRMERR (1<<12) #define URXD_BRK (1<<11) #define URXD_PRERR (1<<10) +#define URXD_RX_DATA (0xFF) #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ @@ -165,7 +166,7 @@ void serial_setbrg (void) int serial_getc (void) { while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); - return __REG(UART_PHYS + URXD); + return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ } void serial_putc (const char c) diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c index 4edcc9a1b9..260d393cf0 100644 --- a/cpu/arm920t/at91rm9200/lxt972.c +++ b/cpu/arm920t/at91rm9200/lxt972.c @@ -29,6 +29,7 @@ #include <common.h> #include <at91rm9200_net.h> #include <net.h> +#include <miiphy.h> #include <lxt971a.h> #ifdef CONFIG_DRIVER_ETHER @@ -51,8 +52,8 @@ unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) unsigned short Id1, Id2; at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2); + at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1); + at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2); at91rm9200_EmacDisableMDIO (p_mac); if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) @@ -169,18 +170,18 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) unsigned short value; /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value)) + if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value)) return FALSE; /* Restart Auto_negotiation */ - value |= PHY_COMMON_CTRL_RES_AUTO; - if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value)) + value |= PHY_BMCR_RST_NEG; + if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value)) return FALSE; /*check AutoNegotiate complete */ udelay (10000); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value); - if (!(value & PHY_COMMON_STAT_AN_COMP)) + at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value); + if (!(value & PHY_BMSR_AUTN_COMP)) return FALSE; return (lxt972_GetLinkSpeed (p_mac)); diff --git a/cpu/arm926ejs/at91sam9/config.mk b/cpu/arm926ejs/at91sam9/config.mk index ca2cae181b..83040ebe73 100644 --- a/cpu/arm926ejs/at91sam9/config.mk +++ b/cpu/arm926ejs/at91sam9/config.mk @@ -1,2 +1,3 @@ PLATFORM_CPPFLAGS += -march=armv5te PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) +LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91sam9/u-boot.lds diff --git a/board/atmel/at91cap9adk/u-boot.lds b/cpu/arm926ejs/at91sam9/u-boot.lds index 996f401f0b..996f401f0b 100644 --- a/board/atmel/at91cap9adk/u-boot.lds +++ b/cpu/arm926ejs/at91sam9/u-boot.lds diff --git a/cpu/arm926ejs/at91sam9/usb.c b/cpu/arm926ejs/at91sam9/usb.c index 441349df3a..2a92f734dd 100644 --- a/cpu/arm926ejs/at91sam9/usb.c +++ b/cpu/arm926ejs/at91sam9/usb.c @@ -33,7 +33,11 @@ int usb_cpu_init(void) { /* Enable USB host clock. */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP); +#ifdef CONFIG_AT91SAM9261 + at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0); +#else at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP); +#endif return 0; } @@ -42,7 +46,11 @@ int usb_cpu_stop(void) { /* Disable USB host clock. */ at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP); +#ifdef CONFIG_AT91SAM9261 + at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0); +#else at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP); +#endif return 0; } diff --git a/cpu/arm926ejs/davinci/lxt972.c b/cpu/arm926ejs/davinci/lxt972.c index 6eeb6e5ee9..8130b48de0 100644 --- a/cpu/arm926ejs/davinci/lxt972.c +++ b/cpu/arm926ejs/davinci/lxt972.c @@ -27,6 +27,7 @@ #include <common.h> #include <net.h> +#include <miiphy.h> #include <lxt971a.h> #include <asm/arch/emac_defs.h> @@ -36,11 +37,11 @@ int lxt972_is_phy_connected(int phy_addr) { - u_int16_t id1, id2; + u_int16_t id1, id2; - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1)) + if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1)) return(0); - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2)) + if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2)) return(0); if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) @@ -51,8 +52,8 @@ int lxt972_is_phy_connected(int phy_addr) int lxt972_get_link_speed(int phy_addr) { - u_int16_t stat1, tmp; - volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + u_int16_t stat1, tmp; + volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR; if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) return(0); @@ -70,37 +71,23 @@ int lxt972_get_link_speed(int phy_addr) if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) return(0); - /* Speed doesn't matter, there is no setting for it in EMAC... */ - if (stat1 & PHY_LXT971_STAT2_100BTX) { - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE; } else { - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; } - return(0); + return(1); } int lxt972_init_phy(int phy_addr) { - int ret = 1; + int ret = 1; if (!lxt972_get_link_speed(phy_addr)) { /* Try another time */ @@ -116,22 +103,21 @@ int lxt972_init_phy(int phy_addr) int lxt972_auto_negotiate(int phy_addr) { - u_int16_t tmp; - + u_int16_t tmp; - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp)) + if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) return(0); /* Restart Auto_negotiation */ - tmp |= PHY_COMMON_CTRL_RES_AUTO; - dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp); + tmp |= PHY_BMCR_RST_NEG; + dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); /*check AutoNegotiate complete */ udelay (10000); - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp)) + if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) return(0); - if (!(tmp & PHY_COMMON_STAT_AN_COMP)) + if (!(tmp & PHY_BMSR_AUTN_COMP)) return(0); return (lxt972_get_link_speed(phy_addr)); diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index ffc770fd1b..36468e6c3a 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -240,7 +240,8 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in return 0; case 1: /* Uncorrectable error */ - DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "ECC UNCORRECTED_ERROR 1\n"); return(-1); case 12: /* Correctable error */ @@ -256,7 +257,9 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; - DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); + MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC " + "error at offset: %d, bit: %d\n", + find_byte, find_bit); page_data[find_byte] ^= (1 << find_bit); @@ -266,7 +269,8 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) return(0); } - DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "UNCORRECTED_ERROR default\n"); return(-1); } } diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index f69b1f3854..33dc427681 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -27,13 +27,18 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(CPU).a -START := start.o -SOBJS := entry.o -COBJS := cpu.o hsdramc.o exception.o cache.o -COBJS += interrupts.o pio.o atmel_mci.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) +START-y += start.o + +COBJS-y += cpu.o +COBJS-y += hsdramc.o +COBJS-y += exception.o +COBJS-y += cache.o +COBJS-y += interrupts.o +COBJS-y += pio.o + +SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START-y)) all: $(obj).depend $(START) $(LIB) diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile index d276712118..740423563e 100644 --- a/cpu/at32ap/at32ap700x/Makefile +++ b/cpu/at32ap/at32ap700x/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(SOC).a -COBJS := gpio.o +COBJS := gpio.o clk.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c new file mode 100644 index 0000000000..b3aa03495f --- /dev/null +++ b/cpu/at32ap/at32ap700x/clk.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2005-2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> + +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> + +#include "sm.h" + +void clk_init(void) +{ + uint32_t cksel; + + /* in case of soft resets, disable watchdog */ + sm_writel(WDT_CTRL, SM_BF(KEY, 0x55)); + sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa)); + +#ifdef CONFIG_PLL + /* Initialize the PLL */ + sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) + | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) + | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) + | SM_BF(PLLOPT, CFG_PLL0_OPT) + | SM_BF(PLLOSC, 0) + | SM_BIT(PLLEN))); + + /* Wait for lock */ + while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; +#endif + + /* Set up clocks for the CPU and all peripheral buses */ + cksel = 0; + if (CFG_CLKDIV_CPU) + cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); + if (CFG_CLKDIV_HSB) + cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); + if (CFG_CLKDIV_PBA) + cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); + if (CFG_CLKDIV_PBB) + cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); + sm_writel(PM_CKSEL, cksel); + +#ifdef CONFIG_PLL + /* Use PLL0 as main clock */ + sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); +#endif +} diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 859124a91f..56ba2f90c6 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -21,8 +21,11 @@ */ #include <common.h> +#include <asm/io.h> + #include <asm/arch/chip-features.h> #include <asm/arch/gpio.h> +#include <asm/arch/memory-map.h> /* * Lots of small functions here. We depend on --gc-sections getting @@ -142,3 +145,55 @@ void gpio_enable_mmci(void) gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ } #endif + +#ifdef AT32AP700x_CHIP_HAS_SPI +void gpio_enable_spi0(unsigned long cs_mask) +{ + gpio_select_periph_A(GPIO_PIN_PA0, 0); /* MISO */ + gpio_select_periph_A(GPIO_PIN_PA1, 0); /* MOSI */ + gpio_select_periph_A(GPIO_PIN_PA2, 0); /* SCK */ + + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PA3, 1); + gpio_select_pio(GPIO_PIN_PA3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PA4, 1); + gpio_select_pio(GPIO_PIN_PA4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PA5, 1); + gpio_select_pio(GPIO_PIN_PA5, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA20, 1); + gpio_select_pio(GPIO_PIN_PA20, GPIOF_OUTPUT); + } +} + +void gpio_enable_spi1(unsigned long cs_mask) +{ + gpio_select_periph_B(GPIO_PIN_PA0, 0); /* MISO */ + gpio_select_periph_B(GPIO_PIN_PB1, 0); /* MOSI */ + gpio_select_periph_B(GPIO_PIN_PB5, 0); /* SCK */ + + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PB2, 1); + gpio_select_pio(GPIO_PIN_PB2, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PB3, 1); + gpio_select_pio(GPIO_PIN_PB3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PB4, 1); + gpio_select_pio(GPIO_PIN_PB4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA27, 1); + gpio_select_pio(GPIO_PIN_PA27, GPIOF_OUTPUT); + } +} +#endif diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/at32ap700x/sm.h index 6492c8e81d..6492c8e81d 100644 --- a/cpu/at32ap/sm.h +++ b/cpu/at32ap/at32ap700x/sm.h diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 311466b781..0ba836180e 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -30,7 +30,6 @@ #include <asm/arch/memory-map.h> #include "hsmc3.h" -#include "sm.h" /* Sanity checks */ #if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \ @@ -44,47 +43,9 @@ DECLARE_GLOBAL_DATA_PTR; -static void pm_init(void) -{ - uint32_t cksel; - -#ifdef CONFIG_PLL - /* Initialize the PLL */ - sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) - | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) - | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) - | SM_BF(PLLOPT, CFG_PLL0_OPT) - | SM_BF(PLLOSC, 0) - | SM_BIT(PLLEN))); - - /* Wait for lock */ - while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; -#endif - - /* Set up clocks for the CPU and all peripheral buses */ - cksel = 0; - if (CFG_CLKDIV_CPU) - cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); - if (CFG_CLKDIV_HSB) - cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); - if (CFG_CLKDIV_PBA) - cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); - if (CFG_CLKDIV_PBB) - cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); - sm_writel(PM_CKSEL, cksel); - - gd->cpu_hz = get_cpu_clk_rate(); - -#ifdef CONFIG_PLL - /* Use PLL0 as main clock */ - sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); -#endif -} - int cpu_init(void) { extern void _evba(void); - char *p; gd->cpu_hz = CFG_OSC0_HZ; @@ -95,16 +56,15 @@ int cpu_init(void) hsmc3_writel(PULSE0, 0x0b0a0906); hsmc3_writel(SETUP0, 0x00010002); - pm_init(); + clk_init(); + /* Update the CPU speed according to the PLL configuration */ + gd->cpu_hz = get_cpu_clk_rate(); + + /* Set up the exception handler table and enable exceptions */ sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); - /* Lock everything that mess with the flash in the icache */ - for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ); - p += CFG_ICACHE_LINESZ) - asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory"); - return 0; } diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S deleted file mode 100644 index a6fc68867a..0000000000 --- a/cpu/at32ap/entry.S +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <asm/sysreg.h> -#include <asm/ptrace.h> - - .section .text.exception,"ax" - .global _evba - .type _evba,@function - .align 10 -_evba: - .irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 - .align 2 - rjmp unknown_exception - .endr - - .global timer_interrupt_handler - .type timer_interrupt_handler,@function - .align 2 -timer_interrupt_handler: - /* - * Increment timer_overflow and re-write COMPARE with 0xffffffff. - * - * We're running at interrupt level 3, so we don't need to save - * r8-r12 or lr to the stack. - */ - lda.w r8, timer_overflow - ld.w r9, r8[0] - mov r10, -1 - mtsr SYSREG_COMPARE, r10 - sub r9, -1 - st.w r8[0], r9 - rete - - .type unknown_exception, @function -unknown_exception: - pushm r0-r12 - sub r8, sp, REG_R12 - REG_R0 - 4 - mov r9, lr - mfsr r10, SYSREG_RAR_EX - mfsr r11, SYSREG_RSR_EX - pushm r8-r11 - mfsr r12, SYSREG_ECR - mov r11, sp - rcall do_unknown_exception -1: rjmp 1b diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c index 0672685cd0..dc9c3002a4 100644 --- a/cpu/at32ap/exception.c +++ b/cpu/at32ap/exception.c @@ -111,7 +111,8 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) printf("CPU Mode: %s\n", cpu_modes[mode]); /* Avoid exception loops */ - if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end) + if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE) + || regs->sp >= gd->stack_end) printf("\nStack pointer seems bogus, won't do stack dump\n"); else dump_mem("\nStack: ", regs->sp, gd->stack_end); diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index 1fcfe75d74..992612b462 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -30,39 +30,32 @@ #include "hsdramc1.h" -unsigned long sdram_init(const struct sdram_info *info) +unsigned long sdram_init(void *sdram_base, const struct sdram_config *config) { - unsigned long *sdram = (unsigned long *)uncached(info->phys_addr); unsigned long sdram_size; - unsigned long tmp; - unsigned long bus_hz; + uint32_t cfgreg; unsigned int i; - if (!info->refresh_period) - panic("ERROR: SDRAM refresh period == 0. " - "Please update the board code\n"); - - tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) - | HSDRAMC1_BF(NR, info->row_bits - 11) - | HSDRAMC1_BF(NB, info->bank_bits - 1) - | HSDRAMC1_BF(CAS, info->cas) - | HSDRAMC1_BF(TWR, info->twr) - | HSDRAMC1_BF(TRC, info->trc) - | HSDRAMC1_BF(TRP, info->trp) - | HSDRAMC1_BF(TRCD, info->trcd) - | HSDRAMC1_BF(TRAS, info->tras) - | HSDRAMC1_BF(TXSR, info->txsr)); - -#ifdef CFG_SDRAM_16BIT - tmp |= HSDRAMC1_BIT(DBW); - sdram_size = 1 << (info->row_bits + info->col_bits - + info->bank_bits + 1); -#else - sdram_size = 1 << (info->row_bits + info->col_bits - + info->bank_bits + 2); -#endif - - hsdramc1_writel(CR, tmp); + cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8) + | HSDRAMC1_BF(NR, config->row_bits - 11) + | HSDRAMC1_BF(NB, config->bank_bits - 1) + | HSDRAMC1_BF(CAS, config->cas) + | HSDRAMC1_BF(TWR, config->twr) + | HSDRAMC1_BF(TRC, config->trc) + | HSDRAMC1_BF(TRP, config->trp) + | HSDRAMC1_BF(TRCD, config->trcd) + | HSDRAMC1_BF(TRAS, config->tras) + | HSDRAMC1_BF(TXSR, config->txsr)); + + if (config->data_bits == SDRAM_DATA_16BIT) + cfgreg |= HSDRAMC1_BIT(DBW); + + hsdramc1_writel(CR, cfgreg); + + /* Send a NOP to turn on the clock (necessary on some chips) */ + hsdramc1_writel(MR, HSDRAMC1_MODE_NOP); + hsdramc1_readl(MR); + writel(0, sdram_base); /* * Initialization sequence for SDRAM, from the data sheet: @@ -77,7 +70,7 @@ unsigned long sdram_init(const struct sdram_info *info) */ hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE); hsdramc1_readl(MR); - writel(0, sdram); + writel(0, sdram_base); /* * 3. Eight auto-refresh (CBR) cycles are provided @@ -85,58 +78,41 @@ unsigned long sdram_init(const struct sdram_info *info) hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH); hsdramc1_readl(MR); for (i = 0; i < 8; i++) - writel(0, sdram); + writel(0, sdram_base); /* * 4. A mode register set (MRS) cycle is issued to program * SDRAM parameters, in particular CAS latency and burst * length. * - * CAS from info struct, burst length 1, serial burst type + * The address will be chosen by the SDRAMC automatically; we + * just have to make sure BA[1:0] are set to 0. */ hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE); hsdramc1_readl(MR); - writel(0, sdram + (info->cas << 4)); + writel(0, sdram_base); /* - * 5. A Normal Mode command is provided, 3 clocks after tMRD - * is met. - * - * From the timing diagram, it looks like tMRD is 3 - * cycles...try a dummy read from the peripheral bus. + * 5. The application must go into Normal Mode, setting Mode + * to 0 in the Mode Register and performing a write access + * at any location in the SDRAM. */ - hsdramc1_readl(MR); hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL); hsdramc1_readl(MR); - writel(0, sdram); + writel(0, sdram_base); /* * 6. Write refresh rate into SDRAMC refresh timer count * register (refresh rate = timing between refresh cycles). - * - * 15.6 us is a typical value for a burst of length one */ - bus_hz = get_sdram_clk_rate(); - hsdramc1_writel(TR, info->refresh_period); - - printf("SDRAM: %u MB at address 0x%08lx\n", - sdram_size >> 20, info->phys_addr); - - printf("Testing SDRAM..."); - for (i = 0; i < sdram_size / 4; i++) - sdram[i] = i; - - for (i = 0; i < sdram_size / 4; i++) { - tmp = sdram[i]; - if (tmp != i) { - printf("FAILED at address 0x%08lx\n", - info->phys_addr + i * 4); - printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i); - return 0; - } - } - - puts("OK\n"); + hsdramc1_writel(TR, config->refresh_period); + + if (config->data_bits == SDRAM_DATA_16BIT) + sdram_size = 1 << (config->row_bits + config->col_bits + + config->bank_bits + 1); + else + sdram_size = 1 << (config->row_bits + config->col_bits + + config->bank_bits + 2); return sdram_size; } diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c index bef1f30d79..160838eeeb 100644 --- a/cpu/at32ap/interrupts.c +++ b/cpu/at32ap/interrupts.c @@ -98,18 +98,16 @@ void set_timer(unsigned long t) */ void udelay(unsigned long usec) { - unsigned long now, end; + unsigned long cycles; + unsigned long base; + unsigned long now; - now = sysreg_read(COUNT); + base = sysreg_read(COUNT); + cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100; - end = ((usec * (get_tbclk() / 10000)) + 50) / 100; - end += now; - - while (now > end) - now = sysreg_read(COUNT); - - while (now < end) + do { now = sysreg_read(COUNT); + } while ((now - base) < cycles); } static int set_interrupt_handler(unsigned int nr, void (*handler)(void), diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c index 9ba0b8ea8b..f64004b659 100644 --- a/cpu/at32ap/pio.c +++ b/cpu/at32ap/pio.c @@ -58,3 +58,59 @@ void gpio_select_periph_B(unsigned int pin, int use_pullup) else pio2_writel(base, PUDR, mask); } + +void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (gpiof_flags & GPIOF_OUTPUT) { + if (gpiof_flags & GPIOF_MULTIDRV) + pio2_writel(base, MDER, mask); + else + pio2_writel(base, MDDR, mask); + pio2_writel(base, PUDR, mask); + pio2_writel(base, OER, mask); + } else { + if (gpiof_flags & GPIOF_PULLUP) + pio2_writel(base, PUER, mask); + else + pio2_writel(base, PUDR, mask); + if (gpiof_flags & GPIOF_DEGLITCH) + pio2_writel(base, IFER, mask); + else + pio2_writel(base, IFDR, mask); + pio2_writel(base, ODR, mask); + } + + pio2_writel(base, PER, mask); +} + +void gpio_set_value(unsigned int pin, int value) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (value) + pio2_writel(base, SODR, mask); + else + pio2_writel(base, CODR, mask); +} + +int gpio_get_value(unsigned int pin) +{ + void *base = gpio_pin_to_addr(pin); + int value; + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + value = pio2_readl(base, PDSR); + return (value >> (pin & 0x1f)) & 1; +} diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S index ab8c2b73d8..907e9b1534 100644 --- a/cpu/at32ap/start.S +++ b/cpu/at32ap/start.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005-2006 Atmel Corporation + * Copyright (C) 2005-2008 Atmel Corporation * * See file CREDITS for list of people who contributed to this * project. @@ -20,12 +20,9 @@ * MA 02111-1307 USA */ #include <config.h> +#include <asm/ptrace.h> #include <asm/sysreg.h> -#ifndef PART_SPECIFIC_BOOTSTRAP -# define PART_SPECIFIC_BOOTSTRAP -#endif - #define SYSREG_MMUCR_I_OFFSET 2 #define SYSREG_MMUCR_S_OFFSET 4 @@ -34,11 +31,115 @@ | SYSREG_BIT(FE) | SYSREG_BIT(RE) \ | SYSREG_BIT(IBE) | SYSREG_BIT(IEE)) - .text + /* + * To save some space, we use the same entry point for + * exceptions and reset. This avoids lots of alignment padding + * since the reset vector is always suitably aligned. + */ + .section .exception.text, "ax", @progbits .global _start + .global _evba + .type _start, @function + .type _evba, @function _start: - PART_SPECIFIC_BOOTSTRAP + .size _start, 0 +_evba: + .org 0x00 + rjmp unknown_exception /* Unrecoverable exception */ + .org 0x04 + rjmp unknown_exception /* TLB multiple hit */ + .org 0x08 + rjmp unknown_exception /* Bus error data fetch */ + .org 0x0c + rjmp unknown_exception /* Bus error instruction fetch */ + .org 0x10 + rjmp unknown_exception /* NMI */ + .org 0x14 + rjmp unknown_exception /* Instruction address */ + .org 0x18 + rjmp unknown_exception /* ITLB protection */ + .org 0x1c + rjmp unknown_exception /* Breakpoint */ + .org 0x20 + rjmp unknown_exception /* Illegal opcode */ + .org 0x24 + rjmp unknown_exception /* Unimplemented instruction */ + .org 0x28 + rjmp unknown_exception /* Privilege violation */ + .org 0x2c + rjmp unknown_exception /* Floating-point */ + .org 0x30 + rjmp unknown_exception /* Coprocessor absent */ + .org 0x34 + rjmp unknown_exception /* Data Address (read) */ + .org 0x38 + rjmp unknown_exception /* Data Address (write) */ + .org 0x3c + rjmp unknown_exception /* DTLB Protection (read) */ + .org 0x40 + rjmp unknown_exception /* DTLB Protection (write) */ + .org 0x44 + rjmp unknown_exception /* DTLB Modified */ + + .org 0x50 + rjmp unknown_exception /* ITLB Miss */ + .org 0x60 + rjmp unknown_exception /* DTLB Miss (read) */ + .org 0x70 + rjmp unknown_exception /* DTLB Miss (write) */ + + .size _evba, . - _evba + + .align 2 + .type unknown_exception, @function +unknown_exception: + /* Figure out whether we're handling an exception (Exception + * mode) or just booting (Supervisor mode). */ + csrfcz SYSREG_M1_OFFSET + brcc at32ap_cpu_bootstrap + + /* This is an exception. Complain. */ + pushm r0-r12 + sub r8, sp, REG_R12 - REG_R0 - 4 + mov r9, lr + mfsr r10, SYSREG_RAR_EX + mfsr r11, SYSREG_RSR_EX + pushm r8-r11 + mfsr r12, SYSREG_ECR + mov r11, sp + rcall do_unknown_exception +1: rjmp 1b + + /* The COUNT/COMPARE timer interrupt handler */ + .global timer_interrupt_handler + .type timer_interrupt_handler,@function + .align 2 +timer_interrupt_handler: + /* + * Increment timer_overflow and re-write COMPARE with 0xffffffff. + * + * We're running at interrupt level 3, so we don't need to save + * r8-r12 or lr to the stack. + */ + lda.w r8, timer_overflow + ld.w r9, r8[0] + mov r10, -1 + mtsr SYSREG_COMPARE, r10 + sub r9, -1 + st.w r8[0], r9 + rete + /* + * CPU bootstrap after reset is handled here. SoC code may + * override this in case they need to initialize oscillators, + * etc. + */ + .section .text.at32ap_cpu_bootstrap, "ax", @progbits + .global at32ap_cpu_bootstrap + .weak at32ap_cpu_bootstrap + .type at32ap_cpu_bootstrap, @function + .align 2 +at32ap_cpu_bootstrap: /* Reset the Status Register */ mov r0, lo(SR_INIT) orh r0, hi(SR_INIT) @@ -66,9 +167,16 @@ _start: lddpc pc, 1f .align 2 -1: .long 2f +1: .long at32ap_low_level_init + .size _start, . - _start -2: lddpc sp, sp_init + /* Common CPU bootstrap code after oscillator/cache/etc. init */ + .section .text.avr32ap_low_level_init, "ax", @progbits + .global at32ap_low_level_init + .type at32ap_low_level_init, @function + .align 2 +at32ap_low_level_init: + lddpc sp, sp_init /* Initialize the GOT pointer */ lddpc r6, got_init @@ -90,6 +198,7 @@ got_init: * Relocate the u-boot image into RAM and continue from there. * Does not return. */ + .section .text.relocate_code,"ax",@progbits .global relocate_code .type relocate_code,@function relocate_code: @@ -162,3 +271,5 @@ in_ram: .align 2 got_init_reloc: .long 3b - _GLOBAL_OFFSET_TABLE_ + + .size relocate_code, . - relocate_code diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile index 92dcc167e8..5091781239 100644 --- a/cpu/mips/Makefile +++ b/cpu/mips/Makefile @@ -25,13 +25,16 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ - cpu.o interrupts.o incaip_clock.o -SOBJS = incaip_wdt.o cache.o +SOBJS-y = cache.o +COBJS-y = cpu.o interrupts.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o +COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o +COBJS-$(CONFIG_PURPLE) += asc_serial.o +COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c index 3498b61e8b..be686c2ae8 100644 --- a/cpu/mips/asc_serial.c +++ b/cpu/mips/asc_serial.c @@ -4,8 +4,6 @@ #include <config.h> -#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP) - #ifdef CONFIG_PURPLE #define serial_init asc_serial_init #define serial_putc asc_serial_putc @@ -368,4 +366,3 @@ int serial_tstc (void) return res; } -#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */ diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index d70c5fe987..d0cf8e0c1b 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -23,8 +23,6 @@ */ #include <config.h> -#ifdef CONFIG_AU1X00 - #if defined(CFG_DISCOVER_PHY) #error "PHY not supported yet" /* We just assume that we are running 100FD for now */ @@ -33,20 +31,20 @@ /* I assume ethernet behaves like au1000 */ -#ifdef CONFIG_AU1000 +#ifdef CONFIG_SOC_AU1000 /* Base address differ between cpu:s */ #define ETH0_BASE AU1000_ETH0_BASE #define MAC0_ENABLE AU1000_MAC0_ENABLE #else -#ifdef CONFIG_AU1100 +#ifdef CONFIG_SOC_AU1100 #define ETH0_BASE AU1100_ETH0_BASE #define MAC0_ENABLE AU1100_MAC0_ENABLE #else -#ifdef CONFIG_AU1500 +#ifdef CONFIG_SOC_AU1500 #define ETH0_BASE AU1500_ETH0_BASE #define MAC0_ENABLE AU1500_MAC0_ENABLE #else -#ifdef CONFIG_AU1550 +#ifdef CONFIG_SOC_AU1550 #define ETH0_BASE AU1550_ETH0_BASE #define MAC0_ENABLE AU1550_MAC0_ENABLE #else @@ -307,5 +305,3 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } - -#endif /* CONFIG_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index 42c668ee3d..63097940ac 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -26,9 +26,6 @@ */ #include <config.h> - -#ifdef CONFIG_AU1X00 - #include <common.h> #include <asm/au1x00.h> @@ -132,4 +129,3 @@ int serial_tstc (void) } return 0; } -#endif /* CONFIG_SERIAL_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index dbf72dc6f8..1ca8aafbbc 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -35,7 +35,7 @@ #include <config.h> -#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI) +#ifdef CONFIG_USB_OHCI /* #include <pci.h> no PCI on the AU1x00 */ diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 1b0efc34a7..ee5d411e4b 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/asm.h> #include <asm/regdef.h> #include <asm/mipsregs.h> @@ -41,7 +40,7 @@ */ #define MIPS_MAX_CACHE_SIZE 0x10000 -#define INDEX_BASE KSEG0 +#define INDEX_BASE CKSEG0 .macro cache_op op addr .set push @@ -219,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra) /* * Now clear that much memory starting from zero. */ - PTR_LI a0, KSEG1 + PTR_LI a0, CKSEG1 PTR_ADDU a1, a0, v0 2: PTR_ADDIU a0, 64 f_fill64 a0, -64, zero @@ -319,7 +318,7 @@ LEAF(dcache_enable) .globl mips_cache_lock .ent mips_cache_lock mips_cache_lock: - li a1, K0BASE - CACHE_LOCK_SIZE + li a1, CKSEG0 - CACHE_LOCK_SIZE addu a0, a1 li a2, CACHE_LOCK_SIZE li a3, CFG_CACHELINE_SIZE diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index e267bba469..0f58d25b89 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size) void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { - write_32bit_cp0_register(CP0_ENTRYLO0, low0); - write_32bit_cp0_register(CP0_PAGEMASK, pagemask); - write_32bit_cp0_register(CP0_ENTRYLO1, low1); - write_32bit_cp0_register(CP0_ENTRYHI, hi); - write_32bit_cp0_register(CP0_INDEX, index); + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); tlb_write_indexed(); } diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 329386bd33..3ade3cd6fd 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -24,7 +24,6 @@ #include <config.h> -#include <version.h> #include <asm/regdef.h> diff --git a/cpu/mips/start.S b/cpu/mips/start.S index d881879d77..09e4aab250 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/mipsregs.h> diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c index 8455c92761..8000fabd4a 100644 --- a/cpu/mpc512x/traps.c +++ b/cpu/mpc512x/traps.c @@ -34,7 +34,13 @@ DECLARE_GLOBAL_DATA_PTR; extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +/* + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. + */ +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* * Trap & Exception support diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 414759e74c..4d5d141ea2 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -305,6 +305,11 @@ void ft_cpu_setup (void *blob, bd_t *bd) { char * cpu_path = "/cpus/" OF_CPU; +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + fdt_fixup_ethernet(blob, bd); +#endif + do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 75c6ab2985..940f5c0a10 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -33,6 +33,10 @@ #include <mpc8260.h> #include <asm/m8260_pci.h> #include <asm/io.h> +#ifdef CONFIG_OF_LIBFDT +#include <libfdt.h> +#include <fdt_support.h> +#endif #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 DECLARE_GLOBAL_DATA_PTR; @@ -449,4 +453,12 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); } +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) +{ + do_fixup_by_prop_u32(blob, "device_type", "pci", 4, + "clock-frequency", bd->pci_clk, 1); +} +#endif + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 36de78d270..52e4476d85 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -44,7 +44,6 @@ int checkcpu(void) char buf[32]; int i; -#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} const struct cpu_type { char name[15]; u32 partid; @@ -358,3 +357,23 @@ int dma_xfer(void *dest, u32 count, void *src) return ((int)dma_check()); } #endif /*CONFIG_DDR_ECC*/ + +#ifdef CONFIG_TSEC_ENET +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif + return 0; +} +#endif diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index fb184d816b..67c9e570c3 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -181,8 +181,13 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CFG_SICRH +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313) + /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ + im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH; +#else im->sysconf.sicrh = CFG_SICRH; #endif +#endif #ifdef CFG_SICRL im->sysconf.sicrl = CFG_SICRL; #endif diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 309eb30e8e..c182174791 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -557,7 +557,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -568,7 +568,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -655,7 +655,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 98733834e0..0d50549f2d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -29,41 +29,45 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -struct cpu_type { - char name[15]; - u32 soc_ver; +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8533, 8533), + CPU_TYPE_ENTRY(8533, 8533_E), + CPU_TYPE_ENTRY(8540, 8540), + CPU_TYPE_ENTRY(8541, 8541), + CPU_TYPE_ENTRY(8541, 8541_E), + CPU_TYPE_ENTRY(8543, 8543), + CPU_TYPE_ENTRY(8543, 8543_E), + CPU_TYPE_ENTRY(8544, 8544), + CPU_TYPE_ENTRY(8544, 8544_E), + CPU_TYPE_ENTRY(8545, 8545), + CPU_TYPE_ENTRY(8545, 8545_E), + CPU_TYPE_ENTRY(8547, 8547_E), + CPU_TYPE_ENTRY(8548, 8548), + CPU_TYPE_ENTRY(8548, 8548_E), + CPU_TYPE_ENTRY(8555, 8555), + CPU_TYPE_ENTRY(8555, 8555_E), + CPU_TYPE_ENTRY(8560, 8560), + CPU_TYPE_ENTRY(8567, 8567), + CPU_TYPE_ENTRY(8567, 8567_E), + CPU_TYPE_ENTRY(8568, 8568), + CPU_TYPE_ENTRY(8568, 8568_E), + CPU_TYPE_ENTRY(8572, 8572), + CPU_TYPE_ENTRY(8572, 8572_E), }; -#define CPU_TYPE_ENTRY(x) {#x, SVR_##x} +struct cpu_type *identify_cpu(u32 ver) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].soc_ver == ver) + return &cpu_type_list[i]; -struct cpu_type cpu_type_list [] = { - CPU_TYPE_ENTRY(8533), - CPU_TYPE_ENTRY(8533_E), - CPU_TYPE_ENTRY(8540), - CPU_TYPE_ENTRY(8541), - CPU_TYPE_ENTRY(8541_E), - CPU_TYPE_ENTRY(8543), - CPU_TYPE_ENTRY(8543_E), - CPU_TYPE_ENTRY(8544), - CPU_TYPE_ENTRY(8544_E), - CPU_TYPE_ENTRY(8545), - CPU_TYPE_ENTRY(8545_E), - CPU_TYPE_ENTRY(8547_E), - CPU_TYPE_ENTRY(8548), - CPU_TYPE_ENTRY(8548_E), - CPU_TYPE_ENTRY(8555), - CPU_TYPE_ENTRY(8555_E), - CPU_TYPE_ENTRY(8560), - CPU_TYPE_ENTRY(8567), - CPU_TYPE_ENTRY(8567_E), - CPU_TYPE_ENTRY(8568), - CPU_TYPE_ENTRY(8568_E), - CPU_TYPE_ENTRY(8572), - CPU_TYPE_ENTRY(8572_E), -}; + return NULL; +} int checkcpu (void) { @@ -74,9 +78,13 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; - int i; - u32 ddr_ratio; + struct cpu_type *cpu; +#ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; +#else + u32 ddr_ratio = 0; +#endif svr = get_svr(); ver = SVR_SOC_VER(svr); @@ -85,14 +93,15 @@ int checkcpu (void) puts("CPU: "); - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) - if (cpu_type_list[i].soc_ver == ver) { - puts(cpu_type_list[i].name); - break; - } + cpu = identify_cpu(ver); + if (cpu) { + puts(cpu->name); - if (i == ARRAY_SIZE(cpu_type_list)) + if (svr & 0x80000) + puts("E"); + } else { puts("Unknown"); + } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); @@ -118,7 +127,7 @@ int checkcpu (void) puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); - ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", @@ -159,7 +168,7 @@ int checkcpu (void) } #ifdef CONFIG_CPM2 - printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); @@ -279,3 +288,98 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif +/* + * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF) + * are hardcoded as "1"."size" is the number or entries, not a sizeof. + */ +void upmconfig (uint upm, uint * table, uint size) +{ + int i, mdr, mad, old_mad = 0; + volatile u32 *mxmr; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + int loopval = 0x00004440; + volatile u32 *brp,*orp; + volatile u8* dummy = NULL; + int upmmask; + + switch (upm) { + case UPMA: + mxmr = &lbc->mamr; + upmmask = BR_MS_UPMA; + break; + case UPMB: + mxmr = &lbc->mbmr; + upmmask = BR_MS_UPMB; + break; + case UPMC: + mxmr = &lbc->mcmr; + upmmask = BR_MS_UPMC; + break; + default: + printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); + hang(); + } + + /* Find the address for the dummy write transaction */ + for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; + i++, brp += 2, orp += 2) { + + /* Look for a valid BR with selected UPM */ + if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) { + dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT); + break; + } + } + + if (i == 8) { + printf("Error: %s() could not find matching BR\n", __FUNCTION__); + hang(); + } + + for (i = 0; i < size; i++) { + /* 1 */ + out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */ + /* 2 */ + out_be32(&lbc->mdr, table[i]); + /* 3 */ + mdr = in_be32(&lbc->mdr); + /* 4 */ + *(volatile u8 *)dummy = 0; + /* 5 */ + do { + mad = in_be32(mxmr) & 0x3f; + } while (mad <= old_mad && !(!mad && i == (size-1))); + old_mad = mad; + } + out_be32(mxmr, loopval); /* OP_NORMAL */ +} + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC) +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif +#if defined(CONFIG_MPC85XX_FEC) + tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); +#else +#if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); +#endif +#if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); +#endif +#endif + return 0; +} +#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index e3240b519e..736aef1725 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -148,6 +148,12 @@ void cpu_init_early_f(void) } #endif + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + init_laws(); invalidate_tlb(0); init_tlbs(); @@ -168,12 +174,6 @@ void cpu_init_f (void) disable_tlb(14); disable_tlb(15); - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - #ifdef CONFIG_CPM2 config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif @@ -254,16 +254,7 @@ void cpu_init_f (void) int cpu_init_r(void) { -#ifdef CONFIG_CLEAR_LAW0 -#ifdef CONFIG_FSL_LAW - disable_law(0); -#else - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); - - /* clear alternate boot location LAW (used for sdram, or ddr bank) */ - ecm->lawar0 = 0; -#endif -#endif + puts ("L2: "); #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; @@ -281,17 +272,17 @@ int cpu_init_r(void) case 0x20000000: if (ver == SVR_8548 || ver == SVR_8548_E || ver == SVR_8544 || ver == SVR_8568_E) { - printf ("L2 cache 512KB:"); + puts ("512 KB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; } else { - printf ("L2 cache 256KB:"); + puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; } break; case 0x10000000: - printf ("L2 cache 256KB:"); + puts("256 KB "); if (ver == SVR_8544 || ver == SVR_8544_E) { cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ } @@ -299,18 +290,18 @@ int cpu_init_r(void) case 0x30000000: case 0x00000000: default: - printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); + printf(" unknown size (0x%08x)\n", cache_ctl); return -1; } if (l2cache->l2ctl & 0x80000000) { - printf(" already enabled."); + puts("already enabled"); l2srbar = l2cache->l2srbar0; #ifdef CFG_INIT_L2_ADDR if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { l2srbar = CFG_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR); + printf("moving to 0x%08x", CFG_INIT_L2_ADDR); } #endif /* CFG_INIT_L2_ADDR */ puts("\n"); @@ -318,10 +309,10 @@ int cpu_init_r(void) asm("msync;isync"); l2cache->l2ctl = cache_ctl; /* invalidate & enable */ asm("msync;isync"); - printf(" enabled\n"); + puts("enabled\n"); } #else - printf("L2 cache: disabled\n"); + puts("disabled\n"); #endif #ifdef CONFIG_QE uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bb87740baa..92952e6d6e 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -26,6 +26,7 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/processor.h> extern void ft_qe_setup(void *blob); #ifdef CONFIG_MP @@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_L2_CACHE +/* return size in kilobytes */ +static inline u32 l2cache_size(void) +{ + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; + u32 ver = SVR_SOC_VER(get_svr()); + + switch (l2siz_field) { + case 0x0: + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 128; + else + return 256; + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 256; + else + return 512; + break; + case 0x3: + return 1024; + break; + } + + return 0; +} + +static inline void ft_fixup_l2cache(void *blob) +{ + int len, off; + u32 *ph; + struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); + char compat_buf[38]; + + const u32 line_size = 32; + const u32 num_ways = 8; + const u32 size = l2cache_size() * 1024; + const u32 num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + if (off < 0) { + debug("no cpu node fount\n"); + return; + } + + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + return ; + } + + off = fdt_node_offset_by_phandle(blob, *ph); + if (off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + + if (cpu) { + len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller", + cpu->name); + sprintf(&compat_buf[len + 1], "cache"); + } + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-line-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 2); + fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); +} +#else +#define ft_fixup_l2cache(x) +#endif + +static inline void ft_fixup_cache(void *blob) +{ + int off; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + u32 l1cfg0 = mfspr(SPRN_L1CFG0); + u32 l1cfg1 = mfspr(SPRN_L1CFG1); + u32 isize, iline_size, inum_sets, inum_ways; + u32 dsize, dline_size, dnum_sets, dnum_ways; + + /* d-side config */ + dsize = (l1cfg0 & 0x7ff) * 1024; + dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; + dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; + dnum_sets = dsize / (dline_size * dnum_ways); + + fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-size", dsize); + fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); + + /* i-side config */ + isize = (l1cfg1 & 0x7ff) * 1024; + inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; + iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; + inum_sets = isize / (iline_size * inum_ways); + + fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-size", isize); + fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); + + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + ft_fixup_l2cache(blob); +} + + void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ @@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); #endif + + ft_fixup_cache(blob); } diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index e3a824999c..8e321eb073 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1090,7 +1090,7 @@ setup_laws_and_tlbs(unsigned int memsize) */ #ifdef CONFIG_FSL_LAW - set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); + set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); #endif /* diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 2381fb0654..0eab69448c 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -50,10 +50,12 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; extern unsigned long search_exception_table(unsigned long); /* - * End of memory as shown by board info and determined by DDR setup. + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) - +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) { @@ -214,10 +216,10 @@ MachineCheckException(struct pt_regs *regs) if (machinecheck_count > 1) { regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08x\n", + printf("Skipping current instr, Returning to 0x%08lx\n", regs->nip); } else { - printf("Returning back to 0x%08x\n",regs->nip); + printf("Returning back to 0x%08lx\n",regs->nip); } } @@ -300,7 +302,7 @@ ExtIntException(struct pt_regs *regs) printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx", regs->nip, regs->msr, regs->trap); vect = pic->iack0; - printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect); + printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect); show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); machinecheck_count++; @@ -308,7 +310,7 @@ ExtIntException(struct pt_regs *regs) printf("Returning back to 0x%08x\n",regs->nip); #else regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08x\n",regs->nip); + printf("Skipping current instr, Returning to 0x%08lx\n",regs->nip); #endif } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 3c7476445d..7d2b591d9f 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -26,6 +26,7 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> +#include <asm/mmu.h> #include <mpc86xx.h> #include <asm/fsl_law.h> @@ -268,13 +269,14 @@ dma_xfer(void *dest, uint count, void *src) /* * Print out the state of various machine registers. - * Currently prints out LAWs and BR0/OR0 + * Currently prints out LAWs, BR0/OR0, and BATs */ void mpc86xx_reginfo(void) { immap_t *immap = (immap_t *)CFG_IMMR; ccsr_lbc_t *lbc = &immap->im_lbc; + print_bats(); print_laws(); printf ("Local Bus Controller Registers\n" @@ -288,3 +290,29 @@ void mpc86xx_reginfo(void) printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); } + +#ifdef CONFIG_TSEC_ENET +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif +#if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); +#endif +#if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); +#endif + return 0; +} +#endif /* CONFIG_TSEC_ENET */ diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 0efd855a39..78ba1ea8e5 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -119,8 +119,5 @@ void cpu_init_f(void) */ int cpu_init_r(void) { -#ifdef CONFIG_FSL_LAW - disable_law(0); -#endif return 0; } diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 5cc0c266f0..e26db7c3bf 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1183,7 +1183,7 @@ spd_sdram(void) * Set up LAWBAR for DDR 1 space. */ #ifdef CONFIG_FSL_LAW - set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); + set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); #endif debug("Interleaved memory size is 0x%08lx\n", memsize_total); @@ -1238,7 +1238,7 @@ spd_sdram(void) * Set up LAWBAR for DDR 1 space. */ #ifdef CONFIG_FSL_LAW - set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); + set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); #endif } @@ -1265,7 +1265,7 @@ spd_sdram(void) * Set up LAWBAR for DDR 2 space. */ #ifdef CONFIG_FSL_LAW - set_law(8, + set_next_law( (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE), law_size_ddr2, LAW_TRGT_IF_DDR_2); #endif diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 04c2e1331b..5695c3e453 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -43,7 +43,13 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; /* Returns 0 if exception not found and fixup otherwise. */ extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +/* + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. + */ +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* * Trap & Exception support diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c index f37146b793..6408180147 100644 --- a/cpu/nios/spi.c +++ b/cpu/nios/spi.c @@ -63,10 +63,10 @@ static char quickhex (int i) return hex_digit[i]; } -static void memdump (void *pv, int num) +static void memdump (const void *pv, int num) { int i; - unsigned char *pc = (unsigned char *) pv; + const unsigned char *pc = (const unsigned char *) pv; for (i = 0; i < num; i++) printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); @@ -83,26 +83,64 @@ static void memdump (void *pv, int num) #endif /* DEBUG */ +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* TODO: Add support for different modes and speeds */ + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + /* * SPI transfer: * * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf * for more informations. */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, + void *din, unsigned long flags) { + const u8 *txd = dout; + u8 *rxd = din; int j; - DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", - (int)chipsel, *(uint *)dout, *(uint *)din, bitlen)); + DPRINT(("spi_xfer: slave %u:%u dout %08X din %08X bitlen %d\n", + slave->bus, slave->cs, *(uint *)dout, *(uint *)din, bitlen)); - memdump((void*)dout, (bitlen + 7) / 8); + memdump(dout, (bitlen + 7) / 8); - if(chipsel != NULL) { - chipsel(1); /* select the target chip */ - } + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); - if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */ + if (!(flags & SPI_XFER_END) || bitlen > CFG_NIOS_SPIBITS) { + /* leave chip select active */ spi->control |= NIOS_SPI_SSO; } @@ -114,11 +152,11 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) while ((spi->status & NIOS_SPI_TRDY) == 0) ; - spi->txdata = (unsigned)(dout[j]); + spi->txdata = (unsigned)(txd[j]); while ((spi->status & NIOS_SPI_RRDY) == 0) ; - din[j] = (unsigned char)(spi->rxdata & 0xff); + rxd[j] = (unsigned char)(spi->rxdata & 0xff); #elif (CFG_NIOS_SPIBITS == 16) j++, j++) { @@ -126,15 +164,15 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) while ((spi->status & NIOS_SPI_TRDY) == 0) ; if ((j+1) < ((bitlen + 7) / 8)) - spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]); + spi->txdata = (unsigned)((txd[j] << 8) | txd[j+1]); else - spi->txdata = (unsigned)(dout[j] << 8); + spi->txdata = (unsigned)(txd[j] << 8); while ((spi->status & NIOS_SPI_RRDY) == 0) ; - din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); + rxd[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); if ((j+1) < ((bitlen + 7) / 8)) - din[j+1] = (unsigned char)(spi->rxdata & 0xff); + rxd[j+1] = (unsigned char)(spi->rxdata & 0xff); #else #error "*** unsupported value of CFG_NIOS_SPIBITS ***" @@ -142,15 +180,14 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) } - if (bitlen > CFG_NIOS_SPIBITS) { + if (bitlen > CFG_NIOS_SPIBITS && (flags & SPI_XFER_END)) { spi->control &= ~NIOS_SPI_SSO; } - if(chipsel != NULL) { - chipsel(0); /* deselect the target chip */ - } + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); - memdump((void*)din, (bitlen + 7) / 8); + memdump(din, (bitlen + 7) / 8); return 0; } diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index b9cf5cbfcc..9efcedefed 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -53,6 +53,8 @@ #include <ppc4xx.h> #include <asm/mmu.h> +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR)) @@ -79,157 +81,6 @@ void __spd_ddr_init_hang (void) } void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); -/*----------------------------------------------------------------------------- - | Memory Controller Options 0 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ -#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ -#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ -#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ -#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ -#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ -#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ - -/*----------------------------------------------------------------------------- - | Memory Controller Options 1 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ -#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM DEVPOT Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DEVOPT_DLL 0x80000000 -#define SDRAM_DEVOPT_DS 0x40000000 - -/*-----------------------------------------------------------------------------+ - | SDRAM MCSTS Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTS_MRSC 0x80000000 -#define SDRAM_MCSTS_SRMS 0x40000000 -#define SDRAM_MCSTS_CIS 0x20000000 - -/*----------------------------------------------------------------------------- - | SDRAM Refresh Timer Register - +-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFFF0000 -#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) -#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) - -/*-----------------------------------------------------------------------------+ - | SDRAM UABus Base Address Reg - +-----------------------------------------------------------------------------*/ -#define SDRAM_UABBA_UBBA_MASK 0x0000000F - -/*-----------------------------------------------------------------------------+ - | Memory Bank 0-7 configuration - +-----------------------------------------------------------------------------*/ -#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ -#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ -#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ -#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ -#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ -#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ -#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ -#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ -#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ -#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ -#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ -#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ -#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ -#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ -#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM TR0 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR0_SDWR_MASK 0x80000000 -#define SDRAM_TR0_SDWR_2_CLK 0x00000000 -#define SDRAM_TR0_SDWR_3_CLK 0x80000000 -#define SDRAM_TR0_SDWD_MASK 0x40000000 -#define SDRAM_TR0_SDWD_0_CLK 0x00000000 -#define SDRAM_TR0_SDWD_1_CLK 0x40000000 -#define SDRAM_TR0_SDCL_MASK 0x01800000 -#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 -#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 -#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 -#define SDRAM_TR0_SDPA_MASK 0x000C0000 -#define SDRAM_TR0_SDPA_2_CLK 0x00040000 -#define SDRAM_TR0_SDPA_3_CLK 0x00080000 -#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 -#define SDRAM_TR0_SDCP_MASK 0x00030000 -#define SDRAM_TR0_SDCP_2_CLK 0x00000000 -#define SDRAM_TR0_SDCP_3_CLK 0x00010000 -#define SDRAM_TR0_SDCP_4_CLK 0x00020000 -#define SDRAM_TR0_SDCP_5_CLK 0x00030000 -#define SDRAM_TR0_SDLD_MASK 0x0000C000 -#define SDRAM_TR0_SDLD_1_CLK 0x00000000 -#define SDRAM_TR0_SDLD_2_CLK 0x00004000 -#define SDRAM_TR0_SDRA_MASK 0x0000001C -#define SDRAM_TR0_SDRA_6_CLK 0x00000000 -#define SDRAM_TR0_SDRA_7_CLK 0x00000004 -#define SDRAM_TR0_SDRA_8_CLK 0x00000008 -#define SDRAM_TR0_SDRA_9_CLK 0x0000000C -#define SDRAM_TR0_SDRA_10_CLK 0x00000010 -#define SDRAM_TR0_SDRA_11_CLK 0x00000014 -#define SDRAM_TR0_SDRA_12_CLK 0x00000018 -#define SDRAM_TR0_SDRA_13_CLK 0x0000001C -#define SDRAM_TR0_SDRD_MASK 0x00000003 -#define SDRAM_TR0_SDRD_2_CLK 0x00000001 -#define SDRAM_TR0_SDRD_3_CLK 0x00000002 -#define SDRAM_TR0_SDRD_4_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ - | SDRAM TR1 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR1_RDSS_MASK 0xC0000000 -#define SDRAM_TR1_RDSS_TR0 0x00000000 -#define SDRAM_TR1_RDSS_TR1 0x40000000 -#define SDRAM_TR1_RDSS_TR2 0x80000000 -#define SDRAM_TR1_RDSS_TR3 0xC0000000 -#define SDRAM_TR1_RDSL_MASK 0x00C00000 -#define SDRAM_TR1_RDSL_STAGE1 0x00000000 -#define SDRAM_TR1_RDSL_STAGE2 0x00400000 -#define SDRAM_TR1_RDSL_STAGE3 0x00800000 -#define SDRAM_TR1_RDCD_MASK 0x00000800 -#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 -#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 -#define SDRAM_TR1_RDCT_MASK 0x000001FF -#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) -#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) -#define SDRAM_TR1_RDCT_MIN 0x00000000 -#define SDRAM_TR1_RDCT_MAX 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM WDDCTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 -#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 -#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 -#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 -#define SDRAM_WDDCTR_DCD_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM CLKTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 -#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 -#define SDRAM_CLKTR_DCDT_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM DLYCAL Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - /*-----------------------------------------------------------------------------+ | General Definition +-----------------------------------------------------------------------------*/ @@ -296,10 +147,6 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long num_dimm_banks); static void program_tr1(void); -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes); -#endif - static unsigned long program_bxcr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -418,7 +265,7 @@ long int spd_sdram(void) { /* * If ecc is enabled, initialize the parity bits. */ - program_ecc(total_size); + ecc_init(CFG_SDRAM_BASE, total_size); #endif return total_size; @@ -1402,45 +1249,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, return(bank_base_addr); } - -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes) -{ - unsigned long bank_base_addr; - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long cfg0; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); - - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) - address_increment = 4; - else - address_increment = 8; - - current_address = (unsigned long)(bank_base_addr); - end_address = (unsigned long)(bank_base_addr) + num_bytes; - - while (current_address < end_address) { - *((unsigned long*)current_address) = 0x00000000; - current_address += address_increment; - } - - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_CHK); - } -} -#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index ec76b718bc..c28fc463b5 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -3,9 +3,12 @@ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a * DDR2 controller (non Denali Core). Those currently are: * - * 405: 405EX + * 405: 405EX(r) * 440/460: 440SP/440SPe/460EX/460GT * + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -45,6 +48,8 @@ #include <asm/mmu.h> #include <asm/cache.h> +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) @@ -384,7 +389,7 @@ static unsigned long sdram_memsize(void) * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned char spd0[MAX_SPD_BYTES]; @@ -3064,9 +3069,127 @@ static void ppc440sp_sdram_register_dump(void) dcr_data = mfdcr(SDRAM_R3BAS); printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); } -#else +#else /* !defined(DEBUG) */ static void ppc440sp_sdram_register_dump(void) { } -#endif -#endif /* CONFIG_SPD_EEPROM */ +#endif /* defined(DEBUG) */ +#elif defined(CONFIG_405EX) +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory + * banks. The configuration is performed using static, compile- + * time parameters. + *---------------------------------------------------------------------------*/ +phys_size_t initdram(int board_type) +{ + /* + * Only run this SDRAM init code once. For NAND booting + * targets like Kilauea, we call initdram() early from the + * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). + * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) + * which calls initdram() again. This time the controller + * mustn't be reconfigured again since we're already running + * from SDRAM. + */ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + unsigned long val; + + /* Set Memory Bank Configuration Registers */ + + mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); + mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); + mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); + mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); + + /* Set Memory Clock Timing Register */ + + mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); + + /* Set Refresh Time Register */ + + mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR); + + /* Set SDRAM Timing Registers */ + + mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); + mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); + mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); + + /* Set Mode and Extended Mode Registers */ + + mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE); + mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); + + /* Set Memory Controller Options 1 Register */ + + mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); + + /* Set Manual Initialization Control Registers */ + + mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); + mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); + mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); + mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); + mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); + mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); + mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); + mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); + mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); + mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); + mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); + mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); + mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); + mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); + mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); + mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); + + /* Set On-Die Termination Registers */ + + mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT); + mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0); + mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1); + + /* Set Write Timing Register */ + + mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); + + /* + * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and + * SDRAM0_MCOPT2[IPTR] = 1 + */ + + mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT | + SDRAM_MCOPT2_IPTR_EXECUTE)); + + /* + * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the + * completion of initialization. + */ + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); + + /* Set Delay Control Registers */ + + mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR); + mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC); + mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC); + mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC); + + /* + * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: + */ + + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); + +#if defined(CONFIG_DDR_ECC) + ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); +#endif /* defined(CONFIG_DDR_ECC) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ + + return (CFG_MBYTES_SDRAM << 20); +} +#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */ diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index ffbc222e7a..a7587d4351 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -98,14 +98,14 @@ DECLARE_GLOBAL_DATA_PTR; #define UDIV_SUBTRACT 0 #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPe) || \ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART2_SDR sdr_uart2 #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART3_SDR sdr_uart3 #endif diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 178c5c6742..800bb41d01 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -45,6 +45,7 @@ COBJS += cpu.o COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o +COBJS += ecc.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c index 22156dd9de..8b2954c16c 100644 --- a/cpu/ppc4xx/commproc.c +++ b/cpu/ppc4xx/commproc.c @@ -30,29 +30,25 @@ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -#if defined(CFG_POST_ALT_WORD_ADDR) -void post_word_store (ulong a) -{ - out_be32((void *)CFG_POST_ALT_WORD_ADDR, a); -} +#if defined(CFG_POST_WORD_ADDR) +# define _POST_ADDR ((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR)) +#elif defined(CFG_POST_ALT_WORD_ADDR) +# define _POST_ADDR (CFG_POST_ALT_WORD_ADDR) +#endif -ulong post_word_load (void) -{ - return in_be32((void *)CFG_POST_ALT_WORD_ADDR); -} -#else /* CFG_POST_ALT_WORD_ADDR */ void post_word_store (ulong a) { - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - *(volatile ulong *) save_addr = a; + volatile void *save_addr = (volatile void *)(_POST_ADDR); + + out_be32(save_addr, a); } ulong post_word_load (void) { - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - return *(volatile ulong *) save_addr; + volatile void *save_addr = (volatile void *)(_POST_ADDR); + + return in_be32(save_addr); } -#endif /* CFG_POST_ALT_WORD_ADDR */ #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 42eabfe568..ac64279051 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -32,73 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#ifdef CFG_INIT_DCACHE_CS -# if (CFG_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr -# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) -# define PBxAP_VAL CFG_EBC_PB0AP -# define PBxCR_VAL CFG_EBC_PB0CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr -# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) -# define PBxAP_VAL CFG_EBC_PB1AP -# define PBxCR_VAL CFG_EBC_PB1CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr -# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) -# define PBxAP_VAL CFG_EBC_PB2AP -# define PBxCR_VAL CFG_EBC_PB2CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr -# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) -# define PBxAP_VAL CFG_EBC_PB3AP -# define PBxCR_VAL CFG_EBC_PB3CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr -# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) -# define PBxAP_VAL CFG_EBC_PB4AP -# define PBxCR_VAL CFG_EBC_PB4CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr -# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) -# define PBxAP_VAL CFG_EBC_PB5AP -# define PBxCR_VAL CFG_EBC_PB5CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr -# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) -# define PBxAP_VAL CFG_EBC_PB6AP -# define PBxCR_VAL CFG_EBC_PB6CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr -# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) -# define PBxAP_VAL CFG_EBC_PB7AP -# define PBxCR_VAL CFG_EBC_PB7CR -# endif -# endif -#endif /* CFG_INIT_DCACHE_CS */ - #ifndef CFG_PLL_RECONFIG #define CFG_PLL_RECONFIG 0 #endif @@ -205,8 +138,8 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) - unsigned long val; +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX) + u32 val; #endif reconfigure_pll(CFG_PLL_RECONFIG); @@ -339,6 +272,22 @@ cpu_init_f (void) reset_4xx_watchdog(); #endif /* CONFIG_WATCHDOG */ + +#if defined(CONFIG_460EX) + /* + * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and + * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata + * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA + */ + mfsdr(SDR0_AHB_CFG, val); + val |= 0x80; + val &= ~0x40; + mtsdr(SDR0_AHB_CFG, val); + mfsdr(SDR0_USB2HOST_CFG, val); + val &= ~0xf00; + val |= 0x400; + mtsdr(SDR0_USB2HOST_CFG, val); +#endif /* CONFIG_460EX */ } /* @@ -353,24 +302,6 @@ int cpu_init_r (void) uint pvr = get_pvr(); #endif -#ifdef CFG_INIT_DCACHE_CS - /* - * Flush and invalidate dcache, then disable CS for temporary stack. - * Afterwards, this CS can be used for other purposes - */ - dcache_disable(); /* flush and invalidate dcache */ - mtebc(PBxAP, 0); - mtebc(PBxCR, 0); /* disable CS for temporary stack */ - -#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) - /* - * Write new value into CS register - */ - mtebc(PBxAP, PBxAP_VAL); - mtebc(PBxCR, PBxCR_VAL); -#endif -#endif /* CFG_INIT_DCACHE_CS */ - /* * Write Ethernetaddress into on-chip register */ diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index ad805b937b..3bd637567c 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -1022,7 +1022,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[], * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_ranks[MAXDIMMS]; diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c new file mode 100644 index 0000000000..a2eb07bd75 --- /dev/null +++ b/cpu/ppc4xx/ecc.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung@artesyncp.com + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements generic DRAM ECC initialization for + * PowerPC processors using a SDRAM DDR/DDR2 controller, + * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and + * 460EX/GT. + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> +#include <asm/io.h> + +#include "ecc.h" + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ + defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) +/* + * void ecc_init() + * + * Description: + * This routine initializes a range of DRAM ECC memory with known + * data and enables ECC checking. + * + * TO DO: + * - Improve performance by utilizing cache. + * - Further generalize to make usable by other 4xx variants (e.g. + * 440EPx, et al). + * + * Input(s): + * start - A pointer to the start of memory covered by ECC requiring + * initialization. + * size - The size, in bytes, of the memory covered by ECC requiring + * initialization. + * + * Output(s): + * start - A pointer to the start of memory covered by ECC with + * CFG_ECC_PATTERN written to all locations and ECC data + * primed. + * + * Returns: + * N/A + */ +void ecc_init(unsigned long * const start, unsigned long size) +{ + const unsigned long pattern = CFG_ECC_PATTERN; + unsigned long * const end = (unsigned long * const)((long)start + size); + unsigned long * current = start; + unsigned long mcopt1; + long increment; + + if (start >= end) + return; + + mfsdram(SDRAM_ECC_CFG, mcopt1); + + /* Enable ECC generation without checking or reporting */ + + mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | + SDRAM_ECC_CFG_MCHK_GEN)); + + increment = sizeof(u32); + +#if defined(CONFIG_440) + /* + * Look at the geometry of SDRAM (data width) to determine whether we + * can skip words when writing. + */ + + if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32) + increment = sizeof(u64); +#endif /* defined(CONFIG_440) */ + + while (current < end) { + *current = pattern; + current = (unsigned long *)((long)current + increment); + } + + /* Wait until the writes are finished. */ + + sync(); + + /* Enable ECC generation with checking and no reporting */ + + mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | + SDRAM_ECC_CFG_MCHK_CHK)); +} +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ +#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h new file mode 100644 index 0000000000..aecf291a8b --- /dev/null +++ b/cpu/ppc4xx/ecc.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * + * Copyright (c) 2007 DENX Software Engineering, GmbH + * Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements ECC initialization for PowerPC processors + * using the SDRAM DDR2 controller, including the 405EX(r), + * 440SP(E), 460EX and 460GT. + * + */ + +#ifndef _ECC_H_ +#define _ECC_H_ + +#if !defined(CFG_ECC_PATTERN) +#define CFG_ECC_PATTERN 0x00000000 +#endif /* !defined(CFG_ECC_PATTERN) */ + +/* + * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register + * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT + * we need to make some processor dependant defines used later on by the + * driver. + */ + +/* For 440GP/GX/EP/GR */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) +#define SDRAM_ECC_CFG SDRAM_CFG0 +#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK +#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN +#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK +#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK +#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32 +#endif + +/* For 405EX/440SP/SPe/460EX/GT */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#define SDRAM_ECC_CFG SDRAM_MCOPT1 +#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK +#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN +#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK +#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK +#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32 +#endif + +extern void ecc_init(unsigned long * const start, unsigned long size); + +#endif /* _ECC_H_ */ diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index 37d3fa8ef7..df99f5314b 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -52,7 +52,7 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val) } mask = 0x80000000 >> pin; - mask2 = 0xc0000000 >> (pin2 << 1); + mask2 = 0xc0000000 >> pin2; /* first set TCR to 0 */ out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask); diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 2724d91f0f..7d60ad667f 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -31,6 +31,7 @@ #include <ppc4xx.h> #include <asm/processor.h> #include "sdram.h" +#include "ecc.h" #ifdef CONFIG_SDRAM_BANK0 @@ -163,7 +164,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) /* * Autodetect onboard SDRAM on 405 platforms */ -void sdram_init(void) +phys_size_t initdram(int board_type) { ulong speed; ulong sdtr1; @@ -231,9 +232,15 @@ void sdram_init(void) mtsdram(mem_mcopt1, 0); } #endif - return; + + /* + * OK, size detected -> all done + */ + return mb0cf[i].size; } } + + return 0; } #else /* CONFIG_440 */ @@ -332,49 +339,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -#ifdef CONFIG_SDRAM_ECC -static void ecc_init(ulong start, ulong size) -{ - ulong current_addr; /* current byte address */ - ulong end_addr; /* end of memory region */ - ulong addr_inc; /* address skip between writes */ - ulong cfg0_reg; /* for restoring ECC state */ - - /* - * TODO: Enable dcache before running this test (speedup) - */ - - mfsdram(mem_cfg0, cfg0_reg); - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); - - /* - * look at geometry of SDRAM (data width) to determine whether we - * can skip words when writing - */ - if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) - addr_inc = 4; - else - addr_inc = 8; - - current_addr = start; - end_addr = start + size; - - while (current_addr < end_addr) { - *((ulong *)current_addr) = 0x00000000; - current_addr += addr_inc; - } - - /* - * TODO: Flush dcache and disable it again - */ - - /* - * Enable ecc checking and parity errors - */ - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); -} -#endif - /* * Autodetect onboard DDR SDRAM on 440 platforms * @@ -382,7 +346,7 @@ static void ecc_init(ulong start, ulong size) * so this should be extended for other future boards * using this routine! */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { int i; int tr1_bank1; diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index ef47ffc952..34bd7214e7 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -754,7 +754,7 @@ ulong get_OPB_freq (void) return sys_info.freqOPB; } -#elif defined(CONFIG_XILINX_ML300) +#elif defined(CONFIG_XILINX_405) extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 0008170128..426bf3c6f9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -3,6 +3,8 @@ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> * * See file CREDITS for list of people who contributed to this * project. @@ -79,34 +81,100 @@ # if (CFG_INIT_DCACHE_CS == 0) # define PBxAP pb0ap # define PBxCR pb0cr +# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +# define PBxAP_VAL CFG_EBC_PB0AP +# define PBxCR_VAL CFG_EBC_PB0CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 1) # define PBxAP pb1ap # define PBxCR pb1cr +# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +# define PBxAP_VAL CFG_EBC_PB1AP +# define PBxCR_VAL CFG_EBC_PB1CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 2) # define PBxAP pb2ap # define PBxCR pb2cr +# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +# define PBxAP_VAL CFG_EBC_PB2AP +# define PBxCR_VAL CFG_EBC_PB2CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 3) # define PBxAP pb3ap # define PBxCR pb3cr +# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +# define PBxAP_VAL CFG_EBC_PB3AP +# define PBxCR_VAL CFG_EBC_PB3CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 4) # define PBxAP pb4ap # define PBxCR pb4cr +# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +# define PBxAP_VAL CFG_EBC_PB4AP +# define PBxCR_VAL CFG_EBC_PB4CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 5) # define PBxAP pb5ap # define PBxCR pb5cr +# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +# define PBxAP_VAL CFG_EBC_PB5AP +# define PBxCR_VAL CFG_EBC_PB5CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 6) # define PBxAP pb6ap # define PBxCR pb6cr +# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +# define PBxAP_VAL CFG_EBC_PB6AP +# define PBxCR_VAL CFG_EBC_PB6CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 7) # define PBxAP pb7ap # define PBxCR pb7cr +# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +# define PBxAP_VAL CFG_EBC_PB7AP +# define PBxCR_VAL CFG_EBC_PB7CR +# endif +# endif +# ifndef PBxAP_VAL +# define PBxAP_VAL 0 +# endif +# ifndef PBxCR_VAL +# define PBxCR_VAL 0 +# endif +/* + * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB + * used as temporary stack pointer for the primordial stack + */ +# ifndef CFG_INIT_DCACHE_PBxAR +# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +# endif /* CFG_INIT_DCACHE_PBxAR */ +# ifndef CFG_INIT_DCACHE_PBxCR +# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) +# endif /* CFG_INIT_DCACHE_PBxCR */ +# ifndef CFG_INIT_RAM_PATTERN +# define CFG_INIT_RAM_PATTERN 0xDEADDEAD # endif #endif /* CFG_INIT_DCACHE_CS */ @@ -114,6 +182,27 @@ #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! #endif +/* + * Unless otherwise overriden, enable two 128MB cachable instruction regions + * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering + * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions. + */ +#if !defined(CFG_FLASH_BASE) +/* If not already defined, set it to the "last" 128MByte region */ +# define CFG_FLASH_BASE 0xf8000000 +#endif +#if !defined(CFG_ICACHE_SACR_VALUE) +# define CFG_ICACHE_SACR_VALUE \ + (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_FLASH_BASE)) +#endif /* !defined(CFG_ICACHE_SACR_VALUE) */ + +#if !defined(CFG_DCACHE_SACR_VALUE) +# define CFG_DCACHE_SACR_VALUE \ + (0x00000000) +#endif /* !defined(CFG_DCACHE_SACR_VALUE) */ + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ @@ -128,7 +217,6 @@ .extern ext_bus_cntlr_init - .extern sdram_init #ifdef CONFIG_NAND_U_BOOT .extern reconfig_tlb0 #endif @@ -401,97 +489,6 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /* Continue from 'normal' start */ /*----------------------------------------------------------------*/ 2: - -#if defined(CONFIG_NAND_SPL) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - /* - * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM) - */ - lis r2,0x7fff - ori r2,r2,0xffff - mfdcr r1,isram0_dpc - and r1,r1,r2 /* Disable parity check */ - mtdcr isram0_dpc,r1 - mfdcr r1,isram0_pmeg - and r1,r1,r2 /* Disable pwr mgmt */ - mtdcr isram0_pmeg,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r1,0x4000 /* BAS = 8000_0000 */ - ori r1,r1,0x4580 /* 16k */ - mtdcr isram0_sb0cr,r1 -#endif -#endif -#if defined(CONFIG_440EP) - /* - * On 440EP with no internal SRAM, we setup SDRAM very early - * and copy the NAND_SPL to SDRAM and jump to it - */ - /* Clear Dcache to use as RAM */ - addis r3,r0,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - addis r4,r0,CFG_INIT_RAM_END@h - ori r4,r4,CFG_INIT_RAM_END@l - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ran3 - addi r5,r5,0x0001 -..d_ran3: - mtctr r5 -..d_ag3: - dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag3 - /*----------------------------------------------------------------*/ - /* Setup the stack in internal SRAM */ - /*----------------------------------------------------------------*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l - li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ - sync - bl early_sdram_init - sync -#endif /* CONFIG_440EP */ - - /* - * Copy SPL from cache into internal SRAM - */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop - - /* - * Jump to code in RAM - */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr - -start_ram: - sync - isync -#endif /* CONFIG_NAND_SPL */ - bl 3f b _start @@ -746,7 +743,7 @@ _start: stw r0,+12(r1) /* Save return addr (underflow vect) */ #ifdef CONFIG_NAND_SPL - bl nand_boot /* will not return */ + bl nand_boot_common /* will not return */ #else GET_GOT @@ -840,16 +837,16 @@ _start: /* make sure above stores all comlete before going on */ sync - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - addis r1,r0,0xc000 - addi r1,r1,0x0001 - mticcr r1 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r1, CFG_ICACHE_SACR_VALUE@h + ori r1, r1, CFG_ICACHE_SACR_VALUE@l + mticcr r1 + isync - addis r1,r0,0x0000 - addi r1,r1,0x0000 - mtdccr r1 /* data cache */ + /* Set-up dcache cacheability. */ + lis r1, CFG_DCACHE_SACR_VALUE@h + ori r1, r1, CFG_DCACHE_SACR_VALUE@l + mtdccr r1 addis r1,r0,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ @@ -892,39 +889,33 @@ _start: /* dbsr is cleared by setting bits to 1) */ mtdbsr r4 /* clear/reset the dbsr */ - /*----------------------------------------------------------------------- */ - /* Invalidate I and D caches. Enable I cache for defined memory regions */ - /* to speed things up. Leave the D cache disabled for now. It will be */ - /* enabled/left disabled later based on user selected menu options. */ - /* Be aware that the I cache may be disabled later based on the menu */ - /* options as well. See miscLib/main.c. */ - /*----------------------------------------------------------------------- */ + /* Invalidate the i- and d-caches. */ bl invalidate_icache bl invalidate_dcache - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - lis r4,0xc000 - ori r4,r4,0x0001 - mticcr r4 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r4, CFG_ICACHE_SACR_VALUE@h + ori r4, r4, CFG_ICACHE_SACR_VALUE@l + mticcr r4 isync - lis r4,0x0000 - ori r4,r4,0x0000 - mtdccr r4 /* data cache */ + /* Set-up dcache cacheability. */ + lis r4, CFG_DCACHE_SACR_VALUE@h + ori r4, r4, CFG_DCACHE_SACR_VALUE@l + mtdccr r4 -#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX) +#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ bl ext_bus_cntlr_init #endif + #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) /* - * Boards like the Kilauea (405EX) don't have OCM and can't use - * DCache for init-ram. So setup stack here directly after the - * SDRAM is initialized. + * For boards that don't have OCM and can't use the data cache + * for their primordial stack, setup stack here directly after the + * SDRAM is initialized in ext_bus_cntlr_init. */ lis r1, CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ @@ -1007,83 +998,90 @@ _start: #endif /* CONFIG_405EZ */ #endif -#ifdef CONFIG_NAND_SPL + /*----------------------------------------------------------------------- */ + /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ + /*----------------------------------------------------------------------- */ +#ifdef CFG_INIT_DCACHE_CS + li r4, PBxAP + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxAR@h + ori r4, r4, CFG_INIT_DCACHE_PBxAR@l + mtdcr ebccfgd, r4 + + addi r4, 0, PBxCR + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxCR@h + ori r4, r4, CFG_INIT_DCACHE_PBxCR@l + mtdcr ebccfgd, r4 + /* - * Copy SPL from cache into internal SRAM + * Enable the data cache for the 128MB storage access control region + * at CFG_INIT_RAM_ADDR. */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop + mfdccr r4 + oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + mtdccr r4 /* - * Jump to code in RAM + * Preallocate data cache lines to be used to avoid a subsequent + * cache miss and an ensuing machine check exception when exceptions + * are enabled. */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr + li r0, 0 -start_ram: - sync - isync -#endif /* CONFIG_NAND_SPL */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l - /*----------------------------------------------------------------------- */ - /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ - /*----------------------------------------------------------------------- */ -#ifdef CFG_INIT_DCACHE_CS - /*----------------------------------------------------------------------- */ - /* Memory Bank x (nothingness) initialization 1GB+64MEG */ - /* used as temporary stack pointer for stage0 */ - /*----------------------------------------------------------------------- */ - li r4,PBxAP - mtdcr ebccfga,r4 - lis r4,0x0380 - ori r4,r4,0x0480 - mtdcr ebccfgd,r4 - - addi r4,0,PBxCR - mtdcr ebccfga,r4 - lis r4,0x400D - ori r4,r4,0xa000 - mtdcr ebccfgd,r4 - - /* turn on data cache for this region */ - lis r4,0x0080 - mtdccr r4 + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + + /* + * Convert the size, in bytes, to the number of cache lines/blocks + * to preallocate. + */ + clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) + srwi r5, r4, L1_CACHE_SHIFT + beq ..load_counter + addi r5, r5, 0x0001 +..load_counter: + mtctr r5 - /* set stack pointer and clear stack to known value */ + /* Preallocate the computed number of cache blocks. */ +..alloc_dcache_block: + dcba r0, r3 + addi r3, r3, L1_CACHE_BYTES + bdnz ..alloc_dcache_block + sync - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + /* + * Load the initial stack pointer and data area and convert the size, + * in bytes, to the number of words to initialize to a known value. + */ + lis r1, CFG_INIT_RAM_ADDR@h + ori r1, r1, CFG_INIT_SP_OFFSET@l - li r4,2048 /* we store 2048 words to stack */ + lis r4, (CFG_INIT_RAM_END >> 2)@h + ori r4, r4, (CFG_INIT_RAM_END >> 2)@l mtctr r4 - lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ - ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ + lis r2, CFG_INIT_RAM_ADDR@h + ori r2, r2, CFG_INIT_RAM_END@l - lis r4,0xdead /* we store 0xdeaddead in the stack */ - ori r4,r4,0xdead + lis r4, CFG_INIT_RAM_PATTERN@h + ori r4, r4, CFG_INIT_RAM_PATTERN@l ..stackloop: - stwu r4,-4(r2) + stwu r4, -4(r2) bdnz ..stackloop - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Make room for stack frame header and clear final stack frame so + * that stack backtraces terminate cleanly. + */ + stwu r0, -4(r1) + stwu r0, -4(r1) + /* * Set up a dummy frame to store reset vector as return address. * this causes stack underflow to reset board. @@ -1120,13 +1118,8 @@ start_ram: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* CFG_INIT_DCACHE_CS */ - /*----------------------------------------------------------------------- */ - /* Initialize SDRAM Controller */ - /*----------------------------------------------------------------------- */ - bl sdram_init - #ifdef CONFIG_NAND_SPL - bl nand_boot /* will not return */ + bl nand_boot_common /* will not return */ #else GET_GOT /* initialize GOT access */ @@ -1328,33 +1321,72 @@ in32r: * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize + * r3 = Relocated stack pointer + * r4 = Relocated global data pointer + * r5 = Relocated text pointer */ .globl relocate_code relocate_code: -#ifdef CONFIG_4xx_DCACHE +#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) /* - * We need to flush the Init Data before the dcache will be - * invalidated + * We need to flush the initial global data (gd_t) before the dcache + * will be invalidated. */ - /* save regs */ - mr r9,r3 - mr r10,r4 - mr r11,r5 + /* Save registers */ + mr r9, r3 + mr r10, r4 + mr r11, r5 - mr r3,r4 - addi r4,r4,0x200 /* should be enough for init data */ + /* Flush initial global data range */ + mr r3, r4 + addi r4, r4, CFG_GBL_DATA_SIZE@l bl flush_dcache_range - /* restore regs */ - mr r3,r9 - mr r4,r10 - mr r5,r11 -#endif +#if defined(CFG_INIT_DCACHE_CS) + /* + * Undo the earlier data cache set-up for the primordial stack and + * data area. First, invalidate the data cache and then disable data + * cacheability for that area. Finally, restore the EBC values, if + * any. + */ + + /* Invalidate the primordial stack and data area in cache */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + add r4, r4, r3 + + bl invalidate_dcache_range + + /* Disable cacheability for the region */ + mfdccr r3 + lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + and r3, r3, r4 + mtdccr r3 + + /* Restore the EBC parameters */ + li r3, PBxAP + mtdcr ebccfga, r3 + lis r3, PBxAP_VAL@h + ori r3, r3, PBxAP_VAL@l + mtdcr ebccfgd, r3 + + li r3, PBxCR + mtdcr ebccfga, r3 + lis r3, PBxCR_VAL@h + ori r3, r3, PBxCR_VAL@l + mtdcr ebccfgd, r3 +#endif /* defined(CFG_INIT_DCACHE_CS) */ + + /* Restore registers */ + mr r3, r9 + mr r4, r10 + mr r5, r11 +#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */ #ifdef CFG_INIT_RAM_DCACHE /* @@ -1396,13 +1428,13 @@ relocate_code: addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ #else addi r1,r0,0x0000 /* Default TLB entry is #0 */ -#endif +#endif /* CFG_TLB_FOR_BOOT_FLASH */ tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ sync isync -#endif +#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Init Data pointer */ mr r10, r5 /* Save copy of Destination Address */ @@ -1425,7 +1457,7 @@ relocate_code: /* First our own GOT */ add r14, r14, r15 - /* the the one used by the C code */ + /* then the one used by the C code */ add r30, r30, r15 /* @@ -2024,3 +2056,75 @@ pll_wait: blr function_epilog(mftlb1) #endif /* CONFIG_440 */ + +#if defined(CONFIG_NAND_SPL) +/* + * void nand_boot_relocate(dst, src, bytes) + * + * r3 = Destination address to copy code to (in SDRAM) + * r4 = Source address to copy code from + * r5 = size to copy in bytes + */ +nand_boot_relocate: + mr r6,r3 + mr r7,r4 + mflr r8 + + /* + * Copy SPL from icache into SDRAM + */ + subi r3,r3,4 + subi r4,r4,4 + srwi r5,r5,2 + mtctr r5 +..spl_loop: + lwzu r0,4(r4) + stwu r0,4(r3) + bdnz ..spl_loop + + /* + * Calculate "corrected" link register, so that we "continue" + * in execution in destination range + */ + sub r3,r7,r6 /* r3 = src - dst */ + sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ + mtlr r8 + blr + +nand_boot_common: + /* + * First initialize SDRAM. It has to be available *before* calling + * nand_boot(). + */ + lis r3,CFG_SDRAM_BASE@h + ori r3,r3,CFG_SDRAM_BASE@l + bl initdram + + /* + * Now copy the 4k SPL code into SDRAM and continue execution + * from there. + */ + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l + lis r4,CFG_NAND_BOOT_SPL_SRC@h + ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l + lis r5,CFG_NAND_BOOT_SPL_SIZE@h + ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l + bl nand_boot_relocate + + /* + * We're running from SDRAM now!!! + * + * It is necessary for 4xx systems to relocate from running at + * the original location (0xfffffxxx) to somewhere else (SDRAM + * preferably). This is because CS0 needs to be reconfigured for + * NAND access. And we can't reconfigure this CS when currently + * "running" from it. + */ + + /* + * Finally call nand_boot() to load main NAND U-Boot image from + * NAND and jump to it. + */ + bl nand_boot /* will not return */ +#endif /* CONFIG_NAND_SPL */ diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 38b6f89555..8b7e32a17b 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -170,7 +170,7 @@ MachineCheckException(struct pt_regs *regs) val = get_esr(); -#if !defined(CONFIG_440) +#if !defined(CONFIG_440) && !defined(CONFIG_405EX) if (val& ESR_IMCP) { printf("Instruction"); mtspr(ESR, val & ~ESR_IMCP); @@ -179,7 +179,7 @@ MachineCheckException(struct pt_regs *regs) } printf(" machine check.\n"); -#elif defined(CONFIG_440) +#elif defined(CONFIG_440) || defined(CONFIG_405EX) if (val& ESR_IMCP){ printf("Instruction Synchronous Machine Check exception\n"); mtspr(SPRN_ESR, val & ~ESR_IMCP); @@ -187,10 +187,15 @@ MachineCheckException(struct pt_regs *regs) val = mfspr(MCSR); if (val & MCSR_IB) printf("Instruction Read PLB Error\n"); +#if defined(CONFIG_440) if (val & MCSR_DRB) printf("Data Read PLB Error\n"); if (val & MCSR_DWB) printf("Data Write PLB Error\n"); +#else + if (val & MCSR_DB) + printf("Data PLB Error\n"); +#endif if (val & MCSR_TLBP) printf("TLB Parity Error\n"); if (val & MCSR_ICP){ diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 039ce0f579..4495a808f5 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -119,7 +119,7 @@ mmc_block_read(uchar * dst, ulong src, ulong len) MMC_RDTO = 0xffff; MMC_NOB = 1; MMC_BLKLEN = len; - mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, + mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl, MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | MMC_CMDAT_DATA_EN); @@ -568,7 +568,7 @@ mmc_init(int verbose) MMC_SPI = MMC_SPI_DISABLE; /* reset */ - mmc_cmd(MMC_CMD_RESET, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); + mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); udelay(200000); retries = 3; while (retries--) { @@ -578,7 +578,10 @@ mmc_init(int verbose) break; } - resp = mmc_cmd(SD_CMD_APP_OP_COND, 0x0020, 0, MMC_CMDAT_R3 | (retries < 2 ? 0 : MMC_CMDAT_INIT)); /* Select 3.2-3.3 and 3.3-3.4V */ + /* Select 3.2-3.3 and 3.3-3.4V */ + resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0020, 0, + MMC_CMDAT_R3 | (retries < 2 ? 0 + : MMC_CMDAT_INIT)); if (resp[0] & 0x80000000) { mmc_dev.if_type = IF_TYPE_SD; debug("Detected SD card\n"); @@ -616,7 +619,7 @@ mmc_init(int verbose) memcpy(cid_resp, resp, sizeof(cid_resp)); /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RCA, 0, 0, MMC_CMDAT_R1); + resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1); if (IF_TYPE_SD == mmc_dev.if_type) rca = ((resp[0] & 0xffff0000) >> 16); resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2); diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 1cdb7091d7..23005e20f9 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -128,7 +128,7 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ diff --git a/cpu/sh3/Makefile b/cpu/sh3/Makefile index 7679248bfe..587413d2e1 100644 --- a/cpu/sh3/Makefile +++ b/cpu/sh3/Makefile @@ -31,19 +31,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o cache.o +SOBJS = start.o +COBJS = cpu.o interrupts.o watchdog.o time.o cache.o -all: .depend $(START) $(LIB) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile index 1bb8bd7729..d3c5eef6be 100644 --- a/cpu/sh4/Makefile +++ b/cpu/sh4/Makefile @@ -28,19 +28,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o cache.o +SOBJS = start.o +COBJS = cpu.o interrupts.o watchdog.o time.o cache.o -all: .depend $(START) $(LIB) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### diff --git a/disk/part.c b/disk/part.c index 316e254739..5c4bf6b614 100644 --- a/disk/part.c +++ b/disk/part.c @@ -109,7 +109,7 @@ void dev_print (block_dev_desc_t *dev_desc) lbaint_t lba512; #endif - switch (dev_desc->type) { + switch (dev_desc->if_type) { case IF_TYPE_SCSI: printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n", dev_desc->target,dev_desc->lun, @@ -124,7 +124,7 @@ void dev_print (block_dev_desc_t *dev_desc) dev_desc->revision, dev_desc->product); break; - case DEV_TYPE_UNKNOWN: + case IF_TYPE_UNKNOWN: default: puts ("not available\n"); return; diff --git a/doc/README.mvblm7 b/doc/README.mvblm7 new file mode 100644 index 0000000000..3ee9396540 --- /dev/null +++ b/doc/README.mvblm7 @@ -0,0 +1,84 @@ +Matrix Vision mvBlueLYNX-M7 (mvBL-M7) +------------------------------------- + +1. Board Description + + The mvBL-M7 is a 120x120mm single board computing platform + with strong focus on stereo image processing applications. + + Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) + on any port (requires add-on board). + +2 System Components + +2.1 CPU + Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. + 512MByte DDR-II memory @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 SD-Card slot connected to SPI. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2 PCI + A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. + +2.3 FPGA + Altera Cyclone-II EP2C20/35 with PCI DMA engines. + Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. + Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. + +2.3.1 I/O @ FPGA + 2x8 Outputs : Infineon High-Side Switches to Main Supply. + 2x8 Inputs : Programmable input threshold + trigger capabilities + 2 dedicated flash interfaces for illuminator boards. + Cross trigger for chaining several boards. + +2.4 I2C + Bus1: + MAX5381 DAC @ 0x60 for 1st digital input threshold. + LM75 @ 0x90 for temperature monitoring. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + 1st image sensor interface (slave adresses depend on sensor) + Bus2: + MAX5381 DAC @ 0x60 for 2nd digital input threshold. + 2nd image sensor interface (slave adresses depend on sensor) + +3 Flash layout. + + reset vector is 0xFFF00100, i.e. "HIGHBOOT". + + FF800000 environment + FF802000 redundant environment + FF804000 u-boot script image + FF806000 redundant u-boot script image + FF808000 device tree blob + FF80A000 redundant device tree blob + FF80C000 tbd. + FF80E000 tbd. + FF810000 kernel + FFC00000 root FS + FFF00000 u-boot + FFF80000 FPGA raw bit file + + mtd partitions are propagated to linux kernel via device tree blob. + +4 Booting + + On startup the bootscript @ FF804000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + 3. device tree blob - name is stored in "dtb_name" + Fallback files are the flash versions. diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 5f1298dcdc..a09cd2a603 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -29,6 +29,7 @@ COBJS-y += ahci.o COBJS-y += ata_piix.o COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o COBJS-$(CONFIG_LIBATA) += libata.o +COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o COBJS-y += sil680.o COBJS-y += sym53c8xx.o COBJS-y += systemace.o diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index d14f5bc6bf..d441a30ed5 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -248,6 +248,10 @@ int init_sata(int dev) else printf(" %s ", sata->name); + /* Wait PHY RDY signal changed for 500ms */ + ata_wait_register(®->hstatus, HSTATUS_PHY_RDY, + HSTATUS_PHY_RDY, 500); + /* Check PHYRDY */ val32 = in_le32(®->hstatus); if (val32 & HSTATUS_PHY_RDY) { @@ -258,6 +262,10 @@ int init_sata(int dev) return -1; } + /* Wait for signature updated, which is 1st D2H */ + ata_wait_register(®->hstatus, HSTATUS_SIGNATURE, + HSTATUS_SIGNATURE, 10000); + if (val32 & HSTATUS_SIGNATURE) { sig = in_le32(®->sig); debug("Signature updated, the sig =%08x\n\r", sig); diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c new file mode 100644 index 0000000000..8399737ff5 --- /dev/null +++ b/drivers/block/sata_sil3114.c @@ -0,0 +1,839 @@ +/* + * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved. + * Author: Tor Krill <tor@excito.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This is a driver for Silicon Image sil3114 sata chip modelled on + * the ata_piix driver + */ + +#include <common.h> +#include <pci.h> +#include <command.h> +#include <config.h> +#include <asm/byteorder.h> +#include <asm/io.h> +#include <ide.h> +#include <libata.h> +#include "sata_sil3114.h" + +/* Convert sectorsize to wordsize */ +#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2) + +/* Forwards */ +u8 sil3114_spin_up (int num); +u8 sil3114_spin_down (int num); +static int sata_bus_softreset (int num); +static void sata_identify (int num, int dev); +static u8 check_power_mode (int num); +static void sata_port (struct sata_ioports *ioport); +static void set_Feature_cmd (int num, int dev); +static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, + unsigned int max, u8 usealtstatus); +static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus); +static void msleep (int count); + +static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */ +extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE]; + +static struct sata_port port[CFG_SATA_MAX_DEVICE]; + +static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words) +{ + while (words--) { + __raw_writew (*sect_buf++, (void *)ioaddr->data_addr); + } +} + +static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words) +{ + while (words--) { + *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr); + } + return 0; +} + +static int sata_bus_softreset (int num) +{ + u8 status = 0; + + port[num].dev_mask = 1; + + port[num].ctl_reg = 0x08; /*Default value of control reg */ + writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); + udelay (10); + writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); + udelay (10); + writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); + + /* spec mandates ">= 2ms" before checking status. + * We wait 150ms, because that was the magic delay used for + * ATAPI devices in Hale Landis's ATADRVR, for the period of time + * between when the ATA command register is written, and then + * status is checked. Because waiting for "a while" before + * checking status is fine, post SRST, we perform this magic + * delay here as well. + */ + msleep (150); + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0); + while ((status & ATA_BUSY)) { + msleep (100); + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0); + } + + if (status & ATA_BUSY) { + printf ("ata%u is slow to respond,plz be patient\n", port); + } + + while ((status & ATA_BUSY)) { + msleep (100); + status = sata_chk_status (&port[num].ioaddr, 0); + } + + if (status & ATA_BUSY) { + printf ("ata%u failed to respond : ", port); + printf ("bus reset failed\n"); + port[num].dev_mask = 0; + return 1; + } + return 0; +} + +static void sata_identify (int num, int dev) +{ + u8 cmd = 0, status = 0, devno = num; + u16 iobuf[ATA_SECTOR_WORDS]; + u64 n_sectors = 0; + + memset (iobuf, 0, sizeof (iobuf)); + + if (!(port[num].dev_mask & 0x01)) { + printf ("dev%d is not present on port#%d\n", dev, num); + return; + } + + debug ("port=%d dev=%d\n", num, dev); + + status = 0; + cmd = ATA_CMD_ID_ATA; /*Device Identify Command */ + writeb (cmd, port[num].ioaddr.command_addr); + readb (port[num].ioaddr.altstatus_addr); + udelay (10); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0); + if (status & ATA_ERR) { + printf ("\ndevice not responding\n"); + port[num].dev_mask &= ~0x01; + return; + } + + input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS); + + ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS); + + debug ("Specific config: %x\n", iobuf[2]); + + /* we require LBA and DMA support (bits 8 & 9 of word 49) */ + if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) { + debug ("ata%u: no dma/lba\n", num); + } +#ifdef DEBUG + ata_dump_id (iobuf); +#endif + n_sectors = ata_id_n_sectors (iobuf); + + if (n_sectors == 0) { + port[num].dev_mask &= ~0x01; + return; + } + ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision, + ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision)); + ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor, + ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor)); + ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product, + ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product)); + + /* TODO - atm we asume harddisk ie not removable */ + sata_dev_desc[devno].removable = 0; + + sata_dev_desc[devno].lba = (u32) n_sectors; + debug ("lba=0x%x\n", sata_dev_desc[devno].lba); + +#ifdef CONFIG_LBA48 + if (iobuf[83] & (1 << 10)) { + sata_dev_desc[devno].lba48 = 1; + } else { + sata_dev_desc[devno].lba48 = 0; + } +#endif + + /* assuming HD */ + sata_dev_desc[devno].type = DEV_TYPE_HARDDISK; + sata_dev_desc[devno].blksz = ATA_SECT_SIZE; + sata_dev_desc[devno].lun = 0; /* just to fill something in... */ +} + +static void set_Feature_cmd (int num, int dev) +{ + u8 status = 0; + + if (!(port[num].dev_mask & 0x01)) { + debug ("dev%d is not present on port#%d\n", dev, num); + return; + } + + writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr); + writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr); + writeb (0, port[num].ioaddr.lbal_addr); + writeb (0, port[num].ioaddr.lbam_addr); + writeb (0, port[num].ioaddr.lbah_addr); + + writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); + writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr); + + udelay (50); + msleep (150); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0); + if ((status & (ATA_BUSY | ATA_ERR))) { + printf ("Error : status 0x%02x\n", status); + port[num].dev_mask &= ~0x01; + } +} + +u8 sil3114_spin_down (int num) +{ + u8 status = 0; + + debug ("Spin down disk\n"); + + if (!(port[num].dev_mask & 0x01)) { + debug ("Device ata%d is not present\n", num); + return 1; + } + + if ((status = check_power_mode (num)) == 0x00) { + debug ("Already in standby\n"); + return 0; + } + + if (status == 0x01) { + printf ("Failed to check power mode on ata%d\n", num); + return 1; + } + + if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) { + printf ("Device ata%d not ready\n", num); + return 1; + } + + writeb (0x00, port[num].ioaddr.feature_addr); + + writeb (0x00, port[num].ioaddr.nsect_addr); + writeb (0x00, port[num].ioaddr.lbal_addr); + writeb (0x00, port[num].ioaddr.lbam_addr); + writeb (0x00, port[num].ioaddr.lbah_addr); + + writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); + writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0); + if ((status & (ATA_BUSY | ATA_ERR))) { + printf ("Error waiting for disk spin down: status 0x%02x\n", + status); + port[num].dev_mask &= ~0x01; + return 1; + } + return 0; +} + +u8 sil3114_spin_up (int num) +{ + u8 status = 0; + + debug ("Spin up disk\n"); + + if (!(port[num].dev_mask & 0x01)) { + debug ("Device ata%d is not present\n", num); + return 1; + } + + if ((status = check_power_mode (num)) != 0x00) { + if (status == 0x01) { + printf ("Failed to check power mode on ata%d\n", num); + return 1; + } else { + /* should be up and running already */ + return 0; + } + } + + if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) { + printf ("Device ata%d not ready\n", num); + return 1; + } + + debug ("Stautus of device check: %d\n", status); + + writeb (0x00, port[num].ioaddr.feature_addr); + + writeb (0x00, port[num].ioaddr.nsect_addr); + writeb (0x00, port[num].ioaddr.lbal_addr); + writeb (0x00, port[num].ioaddr.lbam_addr); + writeb (0x00, port[num].ioaddr.lbah_addr); + + writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); + writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0); + if ((status & (ATA_BUSY | ATA_ERR))) { + printf ("Error waiting for disk spin up: status 0x%02x\n", + status); + port[num].dev_mask &= ~0x01; + return 1; + } + + /* Wait for disk to enter Active state */ + do { + msleep (10); + status = check_power_mode (num); + } while ((status == 0x00) || (status == 0x80)); + + if (status == 0x01) { + printf ("Falied waiting for disk to spin up\n"); + return 1; + } + + return 0; +} + +/* Return value is not the usual here + * 0x00 - Device stand by + * 0x01 - Operation failed + * 0x80 - Device idle + * 0xff - Device active +*/ +static u8 check_power_mode (int num) +{ + u8 status = 0; + u8 res = 0; + if (!(port[num].dev_mask & 0x01)) { + debug ("Device ata%d is not present\n", num); + return 1; + } + + if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) { + printf ("Device ata%d not ready\n", num); + return 1; + } + + writeb (0, port[num].ioaddr.feature_addr); + writeb (0, port[num].ioaddr.nsect_addr); + writeb (0, port[num].ioaddr.lbal_addr); + writeb (0, port[num].ioaddr.lbam_addr); + writeb (0, port[num].ioaddr.lbah_addr); + + writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); + writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0); + if ((status & (ATA_BUSY | ATA_ERR))) { + printf + ("Error waiting for check power mode complete : status 0x%02x\n", + status); + port[num].dev_mask &= ~0x01; + return 1; + } + res = readb (port[num].ioaddr.nsect_addr); + debug ("Check powermode: %d\n", res); + return res; + +} + +static void sata_port (struct sata_ioports *ioport) +{ + ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA; + ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR; + ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE; + ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT; + ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL; + ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM; + ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH; + ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE; + ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS; + ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD; +} + +static u8 wait_for_irq (int num, unsigned int max) +{ + + u32 port = iobase[5]; + switch (num) { + case 0: + port += VND_TF_CNST_CH0; + break; + case 1: + port += VND_TF_CNST_CH1; + break; + case 2: + port += VND_TF_CNST_CH2; + break; + case 3: + port += VND_TF_CNST_CH3; + break; + default: + return 1; + } + + do { + if (readl (port) & VND_TF_CNST_INTST) { + break; + } + udelay (1000); + max--; + } while ((max > 0)); + + return (max == 0); +} + +static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, + unsigned int max, u8 usealtstatus) +{ + u8 status; + + do { + if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) { + break; + } + udelay (1000); + max--; + } while ((status & bits) && (max > 0)); + + return status; +} + +static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus) +{ + if (!usealtstatus) { + return readb (ioaddr->status_addr); + } else { + return readb (ioaddr->altstatus_addr); + } +} + +static void msleep (int count) +{ + int i; + + for (i = 0; i < count; i++) + udelay (1000); +} + +/* Read up to 255 sectors + * + * Returns sectors read +*/ +static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff, + uchar lba48) +{ + + u8 sr = 0; + u8 status; + u64 blknr = (u64) block; + + if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) { + printf ("Device ata%d not ready\n", device); + return 0; + } + + /* Set up transfer */ +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + writeb (0, port[device].ioaddr.nsect_addr); + writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr); + writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr); + writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr); + } +#endif + writeb (blkcnt, port[device].ioaddr.nsect_addr); + writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr); + writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr); + writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr); + +#ifdef CONFIG_LBA48 + if (lba48) { + writeb (ATA_LBA, port[device].ioaddr.device_addr); + writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr); + } else +#endif + { + writeb (ATA_LBA | ((blknr >> 24) & 0xF), + port[device].ioaddr.device_addr); + writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr); + } + + status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1); + + if (status & ATA_BUSY) { + u8 err = 0; + + printf ("Device %d not responding status %d\n", device, status); + err = readb (port[device].ioaddr.error_addr); + printf ("Error reg = 0x%x\n", err); + + return (sr); + } + while (blkcnt--) { + + if (wait_for_irq (device, 500)) { + printf ("ata%u irq failed\n", device); + return sr; + } + + status = sata_chk_status (&port[device].ioaddr, 0); + if (status & ATA_ERR) { + printf ("ata%u error %d\n", device, + readb (port[device].ioaddr.error_addr)); + return sr; + } + /* Read one sector */ + input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS); + buff += ATA_SECTOR_WORDS; + sr++; + + } + return sr; +} + +ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff) +{ + ulong n = 0, sread; + u16 *buffer = (u16 *) buff; + u8 status = 0; + u64 blknr = (u64) block; + unsigned char lba48 = 0; + +#ifdef CONFIG_LBA48 + if (blknr > 0xfffffff) { + if (!sata_dev_desc[device].lba48) { + printf ("Drive doesn't support 48-bit addressing\n"); + return 0; + } + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + + while (blkcnt > 0) { + + if (blkcnt > 255) { + sread = 255; + } else { + sread = blkcnt; + } + + status = do_one_read (device, blknr, sread, buffer, lba48); + if (status != sread) { + printf ("Read failed\n"); + return n; + } + + blkcnt -= sread; + blknr += sread; + n += sread; + buffer += sread * ATA_SECTOR_WORDS; + } + return n; +} + +ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff) +{ + ulong n = 0; + u16 *buffer = (u16 *) buff; + unsigned char status = 0, num = 0; + u64 blknr = (u64) block; +#ifdef CONFIG_LBA48 + unsigned char lba48 = 0; + + if (blknr > 0xfffffff) { + if (!sata_dev_desc[device].lba48) { + printf ("Drive doesn't support 48-bit addressing\n"); + return 0; + } + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + /*Port Number */ + num = device; + + while (blkcnt-- > 0) { + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", port[num].port_no); + return n; + } +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + writeb (0, port[num].ioaddr.nsect_addr); + writeb ((blknr >> 24) & 0xFF, + port[num].ioaddr.lbal_addr); + writeb ((blknr >> 32) & 0xFF, + port[num].ioaddr.lbam_addr); + writeb ((blknr >> 40) & 0xFF, + port[num].ioaddr.lbah_addr); + } +#endif + writeb (1, port[num].ioaddr.nsect_addr); + writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr); + writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr); + writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr); +#ifdef CONFIG_LBA48 + if (lba48) { + writeb (ATA_LBA, port[num].ioaddr.device_addr); + writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr); + } else +#endif + { + writeb (ATA_LBA | ((blknr >> 24) & 0xF), + port[num].ioaddr.device_addr); + writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr); + } + + msleep (50); + /*may take up to 4 sec */ + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0); + if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) { + printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n", + device, (ulong) blknr, status); + return (n); + } + + output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS); + readb (port[num].ioaddr.altstatus_addr); + udelay (50); + + ++n; + ++blknr; + buffer += ATA_SECTOR_WORDS; + } + return n; +} + +/* Driver implementation */ +static u8 sil_get_device_cache_line (pci_dev_t pdev) +{ + u8 cache_line = 0; + pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line); + return cache_line; +} + +int init_sata (int dev) +{ + static u8 init_done = 0; + static int res = 1; + pci_dev_t devno; + u8 cls = 0; + u16 cmd = 0; + u32 sconf = 0; + + if (init_done) { + return res; + } + + init_done = 1; + + if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) { + res = 1; + return res; + } + + /* Read out all BARs, even though we only use MMIO from BAR5 */ + pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]); + + if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) || + (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) || + (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) { + printf ("Error no base addr for SATA controller\n"); + res = 1; + return res; + } + + /* mask off unused bits */ + iobase[0] &= 0xfffffffc; + iobase[1] &= 0xfffffff8; + iobase[2] &= 0xfffffffc; + iobase[3] &= 0xfffffff8; + iobase[4] &= 0xfffffff0; + iobase[5] &= 0xfffffc00; + + /* from sata_sil in Linux kernel */ + cls = sil_get_device_cache_line (devno); + if (cls) { + cls >>= 3; + cls++; /* cls = (line_size/8)+1 */ + writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0); + writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1); + writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2); + writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3); + } else { + printf ("Cache line not set. Driver may not function\n"); + } + + /* Enable operation */ + pci_read_config_word (devno, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word (devno, PCI_COMMAND, cmd); + + /* Disable interrupt usage */ + pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf); + sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK); + pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf); + + res = 0; + return res; +} + +/* Check if device is connected to port */ +int sata_bus_probe (int portno) +{ + u32 port = iobase[5]; + u32 val; + switch (portno) { + case 0: + port += VND_SSTATUS_CH0; + break; + case 1: + port += VND_SSTATUS_CH1; + break; + case 2: + port += VND_SSTATUS_CH2; + break; + case 3: + port += VND_SSTATUS_CH3; + break; + default: + return 0; + } + val = readl (port); + if ((val & SATA_DET_PRES) == SATA_DET_PRES) { + return 1; + } else { + return 0; + } +} + +int sata_phy_reset (int portno) +{ + u32 port = iobase[5]; + u32 val; + switch (portno) { + case 0: + port += VND_SCONTROL_CH0; + break; + case 1: + port += VND_SCONTROL_CH1; + break; + case 2: + port += VND_SCONTROL_CH2; + break; + case 3: + port += VND_SCONTROL_CH3; + break; + default: + return 0; + } + val = readl (port); + writel (val | SATA_SC_DET_RST, port); + msleep (150); + writel (val & ~SATA_SC_DET_RST, port); + return 0; +} + +int scan_sata (int dev) +{ + /* A bit brain dead, but the code has a legacy */ + switch (dev) { + case 0: + port[0].port_no = 0; + port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0; + port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr = + (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS; + port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0; + break; + case 1: + port[1].port_no = 0; + port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1; + port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr = + (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS; + port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1; + break; + case 2: + port[2].port_no = 0; + port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2; + port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr = + (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS; + port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2; + break; + case 3: + port[3].port_no = 0; + port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3; + port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr = + (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS; + port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3; + break; + default: + printf ("Tried to scan unknown port: ata%d\n", dev); + return 1; + } + + /* Initialize other registers */ + sata_port (&port[dev].ioaddr); + + /* Check for attached device */ + if (!sata_bus_probe (dev)) { + port[dev].port_state = 0; + debug ("SATA#%d port is not present\n", dev); + } else { + debug ("SATA#%d port is present\n", dev); + if (sata_bus_softreset (dev)) { + /* soft reset failed, try a hard one */ + sata_phy_reset (dev); + if (sata_bus_softreset (dev)) { + port[dev].port_state = 0; + } else { + port[dev].port_state = 1; + } + } else { + port[dev].port_state = 1; + } + } + if (port[dev].port_state == 1) { + /* Probe device and set xfer mode */ + sata_identify (dev, 0); + set_Feature_cmd (dev, 0); + } + + return 0; +} diff --git a/drivers/block/sata_sil3114.h b/drivers/block/sata_sil3114.h new file mode 100644 index 0000000000..8f2301ac95 --- /dev/null +++ b/drivers/block/sata_sil3114.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved. + * Author: Tor Krill <tor@excito.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef SATA_SIL3114_H +#define SATA_SIL3114_H + +struct sata_ioports { + unsigned long cmd_addr; + unsigned long data_addr; + unsigned long error_addr; + unsigned long feature_addr; + unsigned long nsect_addr; + unsigned long lbal_addr; + unsigned long lbam_addr; + unsigned long lbah_addr; + unsigned long device_addr; + unsigned long status_addr; + unsigned long command_addr; + unsigned long altstatus_addr; + unsigned long ctl_addr; + unsigned long bmdma_addr; + unsigned long scr_addr; +}; + +struct sata_port { + unsigned char port_no; /* primary=0, secondary=1 */ + struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ + unsigned char ctl_reg; + unsigned char last_ctl; + unsigned char port_state; /* 1-port is available and */ + /* 0-port is not available */ + unsigned char dev_mask; +}; + +/* Missing ata defines */ +#define ATA_CMD_STANDBY 0xE2 +#define ATA_CMD_STANDBYNOW1 0xE0 +#define ATA_CMD_IDLE 0xE3 +#define ATA_CMD_IDLEIMMEDIATE 0xE1 + +/* Defines for SIL3114 chip */ + +/* PCI defines */ +#define SIL_VEND_ID 0x1095 +#define SIL3114_DEVICE_ID 0x3114 + +/* some vendor specific registers */ +#define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */ +#define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22) +#define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23) +#define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24) +#define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25) + +/* internal registers mapped by BAR5 */ +/* SATA Control*/ +#define VND_SCONTROL_CH0 0x100 +#define VND_SCONTROL_CH1 0x180 +#define VND_SCONTROL_CH2 0x300 +#define VND_SCONTROL_CH3 0x380 + +#define SATA_SC_IPM_T2P (1<<16) +#define SATA_SC_IPM_T2S (2<<16) +#define SATA_SC_SPD_1_5 (1<<4) +#define SATA_SC_SPD_3_0 (2<<4) +#define SATA_SC_DET_RST (1) /* ATA Reset sequence */ +#define SATA_SC_DET_PDIS (4) /* PHY Disable */ + +/* SATA Status */ +#define VND_SSTATUS_CH0 0x104 +#define VND_SSTATUS_CH1 0x184 +#define VND_SSTATUS_CH2 0x304 +#define VND_SSTATUS_CH3 0x384 + +#define SATA_SS_IPM_ACTIVE (1<<8) +#define SATA_SS_IPM_PARTIAL (2<<8) +#define SATA_SS_IPM_SLUMBER (6<<8) +#define SATA_SS_SPD_1_5 (1<<4) +#define SATA_SS_SPD_3_0 (2<<4) +#define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */ +#define SATA_DET_PRES (3) /* Device presence and active PHY */ +#define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */ + +/* Task file registers in BAR5 mapping */ +#define VND_TF0_CH0 0x80 +#define VND_TF0_CH1 0xc0 +#define VND_TF0_CH2 0x280 +#define VND_TF0_CH3 0x2c0 +#define VND_TF1_CH0 0x88 +#define VND_TF1_CH1 0xc8 +#define VND_TF1_CH2 0x288 +#define VND_TF1_CH3 0x2c8 +#define VND_TF2_CH0 0x88 +#define VND_TF2_CH1 0xc8 +#define VND_TF2_CH2 0x288 +#define VND_TF2_CH3 0x2c8 + +#define VND_BMDMA_CH0 0x00 +#define VND_BMDMA_CH1 0x08 +#define VND_BMDMA_CH2 0x200 +#define VND_BMDMA_CH3 0x208 +#define VND_BMDMA2_CH0 0x10 +#define VND_BMDMA2_CH1 0x18 +#define VND_BMDMA2_CH2 0x210 +#define VND_BMDMA2_CH3 0x218 + +/* FIFO control */ +#define VND_FIFOCFG_CH0 0x40 +#define VND_FIFOCFG_CH1 0x44 +#define VND_FIFOCFG_CH2 0x240 +#define VND_FIFOCFG_CH3 0x244 + +/* Task File configuration and status */ +#define VND_TF_CNST_CH0 0xa0 +#define VND_TF_CNST_CH1 0xe0 +#define VND_TF_CNST_CH2 0x2a0 +#define VND_TF_CNST_CH3 0x2e0 + +#define VND_TF_CNST_BFCMD (1<<1) +#define VND_TF_CNST_CHNRST (1<<2) +#define VND_TF_CNST_VDMA (1<<10) +#define VND_TF_CNST_INTST (1<<11) +#define VND_TF_CNST_WDTO (1<<12) +#define VND_TF_CNST_WDEN (1<<13) +#define VND_TF_CNST_WDIEN (1<<14) + +/* for testing */ +#define VND_SSDR 0x04c /* System Software Data Register */ +#define VND_FMACS 0x050 /* Flash Memory Address control and status */ + +#endif diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c index e29b29440f..c34851725e 100644 --- a/drivers/hwmon/lm75.c +++ b/drivers/hwmon/lm75.c @@ -47,6 +47,19 @@ int dtt_read(int sensor, int reg) int dlen; uchar data[2]; +#ifdef CONFIG_DTT_AD7414 + /* + * On AD7414 the first value upon bootup is not read correctly. + * This is most likely because of the 800ms update time of the + * temp register in normal update mode. To get current values + * each time we issue the "dtt" command including upon powerup + * we switch into one-short mode. + * + * Issue one-shot mode command + */ + dtt_write(sensor, DTT_CONFIG, 0x64); +#endif + /* * Validate 'reg' param */ diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index 4e304f7407..c1741eac67 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PS2SERIAL must be in 1 ... 6 #endif -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) #if CONFIG_PS2SERIAL == 1 #define COM_BASE (CFG_CCSRBAR+0x4500) @@ -65,7 +66,9 @@ static int ps2ser_getc_hw(void); static void ps2ser_interrupt(void *dev_id); extern struct serial_state rs_table[]; /* in serial.c */ -#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555) +#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \ + !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \ + !defined(CONFIG_MPC8555) static struct serial_state *state; #endif @@ -120,7 +123,8 @@ int ps2ser_init(void) return (0); } -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) int ps2ser_init(void) { NS16550_t com_port = (NS16550_t)COM_BASE; @@ -186,7 +190,8 @@ void ps2ser_putc(int chr) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif #ifdef DEBUG @@ -197,7 +202,8 @@ void ps2ser_putc(int chr) while (!(psc->psc_status & PSC_SR_TXRDY)); psc->psc_buffer_8 = chr; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) while ((com_port->lsr & LSR_THRE) == 0); com_port->thr = chr; #else @@ -211,7 +217,8 @@ static int ps2ser_getc_hw(void) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif int res = -1; @@ -220,7 +227,8 @@ static int ps2ser_getc_hw(void) if (psc->psc_status & PSC_SR_RXRDY) { res = (psc->psc_buffer_8); } -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) if (com_port->lsr & LSR_DR) { res = com_port->rbr; } @@ -279,7 +287,8 @@ static void ps2ser_interrupt(void *dev_id) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif int chr; @@ -289,7 +298,8 @@ static void ps2ser_interrupt(void *dev_id) chr = ps2ser_getc_hw(); #ifdef CONFIG_MPC5xxx status = psc->psc_status; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) status = com_port->lsr; #else status = ps2ser_in(UART_IIR); @@ -305,7 +315,8 @@ static void ps2ser_interrupt(void *dev_id) } #ifdef CONFIG_MPC5xxx } while (status & PSC_SR_RXRDY); -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) } while (status & LSR_DR); #else } while (status & UART_IIR_RDI); diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index dca6a4da4a..48ece4f090 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -27,8 +27,22 @@ #include <asm/fsl_law.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + #define LAWAR_EN 0x80000000 -#define FSL_HW_NUM_LAWS 10 /* number of LAWs in the hw implementation */ +/* number of LAWs in the hw implementation */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) +#define FSL_HW_NUM_LAWS 8 +#elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ + defined(CONFIG_MPC8568) || \ + defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) +#define FSL_HW_NUM_LAWS 10 +#elif defined(CONFIG_MPC8572) +#define FSL_HW_NUM_LAWS 12 +#else +#error FSL_HW_NUM_LAWS not defined for this platform +#endif void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { @@ -36,18 +50,53 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2; + gd->used_laws |= (1 << idx); + out_be32(lawbar, addr >> 12); out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); return ; } +int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + u32 idx = ffz(gd->used_laws); + + if (idx >= FSL_HW_NUM_LAWS) + return -1; + + set_law(idx, addr, sz, id); + + return idx; +} + +int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + u32 idx; + + /* we have no LAWs free */ + if (gd->used_laws == -1) + return -1; + + /* grab the last free law */ + idx = __ilog2(~(gd->used_laws)); + + if (idx >= FSL_HW_NUM_LAWS) + return -1; + + set_law(idx, addr, sz, id); + + return idx; +} + void disable_law(u8 idx) { volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2; + gd->used_laws &= ~(1 << idx); + out_be32(lawar, 0); out_be32(lawbar, 0); @@ -75,14 +124,16 @@ void print_laws(void) void init_laws(void) { int i; - u8 law_idx = 0; - for (i = 0; i < num_law_entries; i++) { - if (law_table[i].index != -1) - law_idx = law_table[i].index; + gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); - set_law(law_idx++, law_table[i].addr, - law_table[i].size, law_table[i].trgt_id); + for (i = 0; i < num_law_entries; i++) { + if (law_table[i].index == -1) + set_next_law(law_table[i].addr, law_table[i].size, + law_table[i].trgt_id); + else + set_law(law_table[i].index, law_table[i].addr, + law_table[i].size, law_table[i].trgt_id); } return ; diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile new file mode 100644 index 0000000000..3dc031b438 --- /dev/null +++ b/drivers/mmc/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libmmc.a + +COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/at32ap/atmel_mci.c b/drivers/mmc/atmel_mci.c index f59dfb5995..61aa1849c2 100644 --- a/cpu/at32ap/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -21,8 +21,6 @@ */ #include <common.h> -#ifdef CONFIG_MMC - #include <part.h> #include <mmc.h> @@ -139,7 +137,7 @@ mmc_cmd(unsigned long cmd, unsigned long arg, pr_debug("mmc: status 0x%08lx\n", status); - if (status & ERROR_FLAGS) { + if (status & error_flags) { printf("mmc: command %lu failed (status: 0x%08lx)\n", cmd, status); return -EIO; @@ -182,12 +180,13 @@ static int mmc_acmd(unsigned long cmd, unsigned long arg, static unsigned long mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, - unsigned long *buffer) + void *buffer) { int ret, i = 0; unsigned long resp[4]; unsigned long card_status, data; unsigned long wordcount; + u32 *p = buffer; u32 status; if (blkcnt == 0) @@ -225,7 +224,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, if (status & MMCI_BIT(RXRDY)) { data = mmci_readl(RDR); /* pr_debug("%x\n", data); */ - *buffer++ = data; + *p++ = data; wordcount++; } } while(wordcount < (mmc_blkdev.blksz / 4)); @@ -350,7 +349,7 @@ static int sd_init_card(struct mmc_cid *cid, int verbose) mmc_idle_cards(); for (i = 0; i < 1000; i++) { - ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND, + ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CFG_MMC_OP_COND, resp, R3 | NID); if (ret || (resp[0] & 0x80000000)) break; @@ -368,7 +367,7 @@ static int sd_init_card(struct mmc_cid *cid, int verbose) mmc_dump_cid(cid); /* Get RCA of the card that responded */ - ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); + ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); if (ret) return ret; @@ -443,6 +442,7 @@ static void mci_set_data_timeout(struct mmc_csd *csd) dtocyc = timeout_clks; dtomul = 0; + shift = 0; while (dtocyc > 15 && dtomul < 8) { dtomul++; shift = dtomul_to_shift[dtomul]; @@ -546,5 +546,3 @@ int mmc2info(ulong addr) { return 0; } - -#endif /* CONFIG_MMC */ diff --git a/cpu/at32ap/atmel_mci.h b/drivers/mmc/atmel_mci.h index 5b4f5c99b6..5b4f5c99b6 100644 --- a/cpu/at32ap/atmel_mci.h +++ b/drivers/mmc/atmel_mci.h diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 68ab55f8a5..c0ea97be70 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -76,7 +76,9 @@ #define FLASH_CMD_PROTECT_SET 0x01 #define FLASH_CMD_PROTECT_CLEAR 0xD0 #define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_READ_STATUS 0x70 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 #define FLASH_STATUS_DONE 0x80 @@ -136,6 +138,7 @@ #define CFI_CMDSET_MITSU_STANDARD 256 #define CFI_CMDSET_MITSU_EXTENDED 257 #define CFI_CMDSET_SST 258 +#define CFI_CMDSET_INTEL_PROG_REGIONS 512 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET @@ -298,17 +301,25 @@ static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, /*----------------------------------------------------------------------- * make a proper sized command based on the port and chip widths */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf) { int i; + int cword_offset; + int cp_offset; + uchar val; uchar *cp = (uchar *) cmdbuf; + for (i = info->portwidth; i > 0; i--){ + cword_offset = (info->portwidth-i)%info->chipwidth; #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) - for (i = info->portwidth; i > 0; i--) + cp_offset = info->portwidth - i; + val = *((uchar*)&cmd + cword_offset); #else - for (i = 1; i <= info->portwidth; i++) + cp_offset = i - 1; + val = *((uchar*)&cmd + sizeof(ulong) - cword_offset - 1); #endif - *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; + cp[cp_offset] = (cword_offset >= sizeof(ulong)) ? 0x00 : val; + } } #ifdef DEBUG @@ -422,7 +433,7 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, * Write a proper sized command to the correct address */ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, - uint offset, uchar cmd) + uint offset, ulong cmd) { void *addr; @@ -570,20 +581,16 @@ static int flash_toggle (flash_info_t * info, flash_sect_t sect, flash_make_cmd (info, cmd, &cword); switch (info->portwidth) { case FLASH_CFI_8BIT: - retval = ((flash_read8(addr) & cword.c) != - (flash_read8(addr) & cword.c)); + retval = flash_read8(addr) != flash_read8(addr); break; case FLASH_CFI_16BIT: - retval = ((flash_read16(addr) & cword.w) != - (flash_read16(addr) & cword.w)); + retval = flash_read16(addr) != flash_read16(addr); break; case FLASH_CFI_32BIT: - retval = ((flash_read32(addr) & cword.l) != - (flash_read32(addr) & cword.l)); + retval = flash_read32(addr) != flash_read32(addr); break; case FLASH_CFI_64BIT: - retval = ((flash_read64(addr) & cword.ll) != - (flash_read64(addr) & cword.ll)); + retval = flash_read64(addr) != flash_read64(addr); break; default: retval = 0; @@ -605,6 +612,7 @@ static int flash_is_busy (flash_info_t * info, flash_sect_t sect) int retval; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); @@ -664,6 +672,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, retcode = flash_status_check (info, sector, tout, prompt); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode == ERR_OK) @@ -792,6 +801,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, flag = disable_interrupts (); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); @@ -846,6 +856,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int flag = 0; uint offset = 0; unsigned int shift; + uchar write_cmd; switch (info->portwidth) { case FLASH_CFI_8BIT: @@ -900,10 +911,14 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, sector = find_sector (info, dest); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: + write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? + FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS); + flash_write_cmd (info, sector, 0, write_cmd); retcode = flash_status_check (info, sector, info->buffer_write_tout, "write to buffer"); @@ -911,7 +926,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, /* reduce the number of loops by the width of * the port */ cnt = len >> shift; - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + flash_write_cmd (info, sector, 0, cnt - 1); while (cnt-- > 0) { switch (info->portwidth) { case FLASH_CFI_8BIT: @@ -1038,6 +1053,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd (info, sect, 0, @@ -1106,6 +1122,9 @@ void flash_print_info (flash_info_t * info) info->size >> 20, info->sector_count); printf (" "); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: + printf ("Intel Prog Regions"); + break; case CFI_CMDSET_INTEL_STANDARD: printf ("Intel Standard"); break; @@ -1496,6 +1515,7 @@ static void flash_read_jedec_ids (flash_info_t * info) info->device_id2 = 0; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: cmdset_intel_read_jedec_ids(info); @@ -1550,6 +1570,7 @@ static int flash_detect_legacy(ulong base, int banknum) } switch(info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: info->cmd_reset = FLASH_CMD_RESET; @@ -1720,6 +1741,8 @@ ulong flash_get_size (ulong base, int banknum) int erase_region_count; struct cfi_qry qry; + memset(&qry, 0, sizeof(qry)); + info->ext_addr = 0; info->cfi_version = 0; #ifdef CFG_FLASH_PROTECTION @@ -1745,6 +1768,7 @@ ulong flash_get_size (ulong base, int banknum) #endif switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: cmdset_intel_init(info, &qry); @@ -1822,6 +1846,7 @@ ulong flash_get_size (ulong base, int banknum) * supported devices (intel...) */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: info->protect[sect_cnt] = diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index b958d1723a..9845e9364e 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -42,7 +42,7 @@ #define MANUFACTURER_SST 0x00BF /* AMD */ -#define AM29DL800BB 0x22C8 +#define AM29DL800BB 0x22CB #define AM29DL800BT 0x224A #define AM29F800BB 0x2258 diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 5cc410a5e2..67ae9c8d5b 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -20,112 +20,83 @@ #include <linux/mtd/fsl_upm.h> #include <nand.h> -#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */ -#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */ -#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */ -#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */ +static int fsl_upm_in_pattern; static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) { - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset); + clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); } static void fsl_upm_end_pattern(struct fsl_upm *upm) { - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); - while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) + clrbits_be32(upm->mxmr, MxMR_OP_RUNP); + + while (in_be32(upm->mxmr) & MxMR_OP_RUNP) eieio(); } static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd) { - out_be32(upm->mar, cmd << (32 - width * 8)); - out_8(upm->io_addr, 0x0); -} - -static void fsl_upm_setup(struct fsl_upm *upm) -{ - int i; - - /* write upm array */ - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA); - - for (i = 0; i < 64; i++) { - out_be32(upm->mdr, upm->array[i]); + out_be32(upm->mar, cmd << (32 - width)); + switch (width) { + case 8: out_8(upm->io_addr, 0x0); + break; + case 16: + out_be16(upm->io_addr, 0x0); + break; + case 32: + out_be32(upm->io_addr, 0x0); + break; } - - /* normal operation */ - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); - while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) - eieio(); } -static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column, - int page_addr) +static void nand_hwcontrol (struct mtd_info *mtd, int cmd) { struct nand_chip *chip = mtd->priv; struct fsl_upm_nand *fun = chip->priv; - fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); - - if (command == NAND_CMD_SEQIN) { - int readcmd; - - if (column >= mtd->oobblock) { - /* OOB area */ - column -= mtd->oobblock; - readcmd = NAND_CMD_READOOB; - } else if (column < 256) { - /* First 256 bytes --> READ0 */ - readcmd = NAND_CMD_READ0; - } else { - column -= 256; - readcmd = NAND_CMD_READ1; - } - fsl_upm_run_pattern(&fun->upm, fun->width, readcmd); + switch (cmd) { + case NAND_CTL_SETCLE: + fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); + fsl_upm_in_pattern++; + break; + case NAND_CTL_SETALE: + fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); + fsl_upm_in_pattern++; + break; + case NAND_CTL_CLRCLE: + case NAND_CTL_CLRALE: + fsl_upm_end_pattern(&fun->upm); + fsl_upm_in_pattern--; + break; } +} - fsl_upm_run_pattern(&fun->upm, fun->width, command); - - fsl_upm_end_pattern(&fun->upm); - - fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); - - if (column != -1) - fsl_upm_run_pattern(&fun->upm, fun->width, column); +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *chip = mtd->priv; - if (page_addr != -1) { - fsl_upm_run_pattern(&fun->upm, fun->width, page_addr); - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 8) & 0xFF); - if (chip->chipsize > (32 << 20)) { - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 16) & 0x0f); - } - } + if (fsl_upm_in_pattern) { + struct fsl_upm_nand *fun = chip->priv; - fsl_upm_end_pattern(&fun->upm); + fsl_upm_run_pattern(&fun->upm, fun->width, byte); - if (fun->wait_pattern) { /* * Some boards/chips needs this. At least on MPC8360E-RDK we * need it. Probably weird chip, because I don't see any need * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are * 0-2 unexpected busy states per block read. */ - while (!fun->dev_ready()) - debug("unexpected busy state\n"); + if (fun->wait_pattern) { + while (!fun->dev_ready()) + debug("unexpected busy state\n"); + } + } else { + out_8(chip->IO_ADDR_W, byte); } } -static void nand_write_byte(struct mtd_info *mtd, u_char byte) -{ - struct nand_chip *chip = mtd->priv; - - out_8(chip->IO_ADDR_W, byte); -} - static u8 nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -164,10 +135,6 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) return 0; } -static void nand_hwcontrol(struct mtd_info *mtd, int cmd) -{ -} - static int nand_dev_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -178,23 +145,20 @@ static int nand_dev_ready(struct mtd_info *mtd) int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) { - /* yet only 8 bit accessors implemented */ - if (fun->width != 1) + if (fun->width != 8 && fun->width != 16 && fun->width != 32) return -ENOSYS; - fsl_upm_setup(&fun->upm); - chip->priv = fun; chip->chip_delay = fun->chip_delay; chip->eccmode = NAND_ECC_SOFT; - chip->cmdfunc = fun_cmdfunc; chip->hwcontrol = nand_hwcontrol; chip->read_byte = nand_read_byte; chip->read_buf = nand_read_buf; chip->write_byte = nand_write_byte; chip->write_buf = nand_write_buf; chip->verify_buf = nand_verify_buf; - chip->dev_ready = nand_dev_ready; + if (fun->dev_ready) + chip->dev_ready = nand_dev_ready; return 0; } diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 5aef31cd18..6416d1529e 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -113,18 +113,22 @@ static struct nand_oobinfo nand_oob_64 = { .oobfree = { {2, 38} } }; -/* This is used for padding purposes in nand_write_oob */ -static u_char ffchars[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +static struct nand_oobinfo nand_oob_128 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 48, + .eccpos = { + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127}, + .oobfree = { {2, 78} } }; +/* This is used for padding purposes in nand_write_oob */ +static u_char *ffchars; + /* * NAND low-level MTD interface functions */ @@ -193,6 +197,10 @@ static void nand_release_device (struct mtd_info *mtd) { struct nand_chip *this = mtd->priv; this->select_chip(mtd, -1); /* De-select the NAND device */ + if (ffchars) { + kfree(ffchars); + ffchars = NULL; + } } #endif @@ -891,7 +899,7 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa u_char *oob_buf, struct nand_oobinfo *oobsel, int cached) { int i, status; - u_char ecc_code[32]; + u_char ecc_code[NAND_MAX_OOBSIZE]; int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE; uint *oob_config = oobsel->eccpos; int datidx = 0, eccidx = 0, eccsteps = this->eccsteps; @@ -954,7 +962,9 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa status = this->waitfunc (mtd, this, FL_WRITING); /* See if device thinks it succeeded */ if (status & 0x01) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "%s: Failed write, page 0x%08x, ", + __FUNCTION__, page); return -EIO; } } else { @@ -1002,7 +1012,9 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int for (j = 0; j < eccsteps; j++) { /* Loop through and verify the data */ if (this->verify_buf(mtd, &this->data_poi[datidx], mtd->eccsize)) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: " + "Failed write verify, page 0x%08x ", + __FUNCTION__, page); goto out; } datidx += mtd->eccsize; @@ -1010,7 +1022,9 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int if (!hweccbytes) continue; if (this->verify_buf(mtd, &this->oob_buf[oobofs], hweccbytes)) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: " + "Failed write verify, page 0x%08x ", + __FUNCTION__, page); goto out; } oobofs += hweccbytes; @@ -1021,7 +1035,9 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int */ if (oobmode) { if (this->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: " + "Failed write verify, page 0x%08x ", + __FUNCTION__, page); goto out; } } else { @@ -1034,9 +1050,11 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int for (i = 0; i < ecccnt; i++) { int idx = oobsel->eccpos[i]; if (oobdata[idx] != oob_buf[oobofs + idx] ) { - DEBUG (MTD_DEBUG_LEVEL0, + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: Failed ECC write " - "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i); + "verify, page 0x%08x, " + "%6i bytes were succesful\n", + __FUNCTION__, page, i); goto out; } } @@ -1112,8 +1130,8 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0; struct nand_chip *this = mtd->priv; u_char *data_poi, *oob_data = oob_buf; - u_char ecc_calc[32]; - u_char ecc_code[32]; + u_char ecc_calc[NAND_MAX_OOBSIZE]; + u_char ecc_code[NAND_MAX_OOBSIZE]; int eccmode, eccsteps; unsigned *oob_config; int datidx; @@ -1123,11 +1141,13 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, int oobreadlen; - DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", + (unsigned int) from, (int) len); /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_read_ecc: Attempt read beyond end of device\n"); *retlen = 0; return -EINVAL; } @@ -1244,7 +1264,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, * generator for an error, reads back the syndrome and * does the error correction on the fly */ if (this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]) == -1) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr); ecc_failed++; } @@ -1283,7 +1303,9 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, } if (ecc_status == -1) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " + "Failed ECC read, page 0x%08x\n", + page); ecc_failed++; } } @@ -1380,7 +1402,8 @@ static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t struct nand_chip *this = mtd->priv; int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; - DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", + (unsigned int) from, (int) len); /* Shift to get page */ page = (int)(from >> this->page_shift); @@ -1394,7 +1417,8 @@ static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_read_oob: Attempt read beyond end of device\n"); *retlen = 0; return -EINVAL; } @@ -1480,7 +1504,8 @@ int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_read_raw: Attempt read beyond end of device\n"); return -EINVAL; } @@ -1618,14 +1643,16 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, u_char *oobbuf, *bufstart; int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); - DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", + (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ *retlen = 0; /* Do not allow write past end of device */ if ((to + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_write_ecc: Attempt to write past end of page\n"); return -EINVAL; } @@ -1687,7 +1714,8 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, */ ret = nand_write_page (mtd, this, page, &oobbuf[oob], oobsel, (--numpages > 0)); if (ret) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: write_page failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_write_ecc: write_page failed %d\n", ret); goto out; } /* Next oob page */ @@ -1711,7 +1739,8 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, page - startpage, oobbuf, oobsel, chipnr, (eccbuf != NULL)); if (ret) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: " + "verify_pages failed %d\n", ret); goto out; } *retlen = written; @@ -1744,7 +1773,8 @@ cmp: if (!ret) *retlen = written; else - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_write_ecc: verify_pages failed %d\n", ret); out: /* Deselect and wake up anyone waiting on the device */ @@ -1769,7 +1799,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * int column, page, status, ret = -EIO, chipnr; struct nand_chip *this = mtd->priv; - DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", + (unsigned int) to, (int) len); /* Shift to get page */ page = (int) (to >> this->page_shift); @@ -1783,7 +1814,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * /* Do not allow write past end of page */ if ((column + len) > mtd->oobsize) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "Attempt to write past end of page\n"); return -EINVAL; } @@ -1811,6 +1843,16 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * if (NAND_MUST_PAD(this)) { /* Write out desired data */ this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask); + if (!ffchars) { + if (!(ffchars = kmalloc (mtd->oobsize, GFP_KERNEL))) { + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "No memory for padding array, " + "need %d bytes", mtd->oobsize); + ret = -ENOMEM; + goto out; + } + memset(ffchars, 0xff, mtd->oobsize); + } /* prepad 0xff for partial programming */ this->write_buf(mtd, ffchars, column); /* write data */ @@ -1830,7 +1872,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * /* See if device thinks it succeeded */ if (status & 0x01) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "Failed write, page 0x%08x\n", page); ret = -EIO; goto out; } @@ -1842,7 +1885,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * this->cmdfunc (mtd, NAND_CMD_READOOB, column, page & this->pagemask); if (this->verify_buf(mtd, buf, len)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "Failed write verify, page 0x%08x\n", page); ret = -EIO; goto out; } @@ -1902,12 +1946,14 @@ static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsig for (i = 0; i < count; i++) total_len += (int) vecs[i].iov_len; - DEBUG (MTD_DEBUG_LEVEL3, - "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count); + MTDDEBUG (MTD_DEBUG_LEVEL3, + "nand_writev: to = 0x%08x, len = %i, count = %ld\n", + (unsigned int) to, (unsigned int) total_len, count); /* Do not allow write past end of page */ if ((to + total_len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_writev: Attempted write past end of device\n"); return -EINVAL; } @@ -2100,24 +2146,26 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb int page, len, status, pages_per_block, ret, chipnr; struct nand_chip *this = mtd->priv; - DEBUG (MTD_DEBUG_LEVEL3, - "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", + (unsigned int) instr->addr, (unsigned int) instr->len); /* Start address must align on block boundary */ if (instr->addr & ((1 << this->phys_erase_shift) - 1)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); return -EINVAL; } /* Length must align on block boundary */ if (instr->len & ((1 << this->phys_erase_shift) - 1)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_erase: Length not block aligned\n"); return -EINVAL; } /* Do not allow erase past end of device */ if ((instr->len + instr->addr) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_erase: Erase past end of device\n"); return -EINVAL; } @@ -2139,7 +2187,8 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb /* Check the WP bit */ /* Check, if it is write protected */ if (nand_check_wp(mtd)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_erase: Device is write protected!!!\n"); instr->state = MTD_ERASE_FAILED; goto erase_exit; } @@ -2169,7 +2218,8 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb /* See if block erase succeeded */ if (status & 0x01) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " + "Failed erase, page 0x%08x\n", page); instr->state = MTD_ERASE_FAILED; instr->fail_addr = (page << this->page_shift); goto erase_exit; @@ -2212,7 +2262,7 @@ static void nand_sync (struct mtd_info *mtd) { struct nand_chip *this = mtd->priv; - DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n"); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n"); /* Grab the lock and see if the device is available */ nand_get_device (this, mtd, FL_SYNCING); @@ -2479,6 +2529,9 @@ int nand_scan (struct mtd_info *mtd, int maxchips) case 64: this->autooob = &nand_oob_64; break; + case 128: + this->autooob = &nand_oob_128; + break; default: printk (KERN_WARNING "No oob scheme defined for oobsize %d\n", mtd->oobsize); diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index eff76d717c..a97743b45e 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -1038,8 +1038,8 @@ int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt) block = (int) (offs >> (this->bbt_erase_shift - 1)); res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; - DEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n", - (unsigned int)offs, res, block >> 1); + MTDDEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: " + "(block %d) 0x%02x\n", (unsigned int)offs, res, block >> 1); switch ((int)res) { case 0x00: return 0; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 6c5624a49a..c82f77b555 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -153,6 +153,13 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) priv_nand->bbt = NULL; } + if (erase_length < meminfo->erasesize) { + printf("Warning: Erase size 0x%08x smaller than one " \ + "erase block 0x%08x\n",erase_length, meminfo->erasesize); + printf(" Erasing 0x%08x instead\n", meminfo->erasesize); + erase_length = meminfo->erasesize; + } + for (; erase.addr < opts->offset + erase_length; erase.addr += meminfo->erasesize) { diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index d1b9f8f546..d32e382558 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -293,22 +293,22 @@ static int onenand_wait(struct mtd_info *mtd, int state) ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); if (ctrl & ONENAND_CTRL_ERROR) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_wait: controller error = 0x%04x\n", ctrl); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_wait: controller error = 0x%04x\n", ctrl); return -EAGAIN; } if (ctrl & ONENAND_CTRL_LOCK) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_wait: it's locked error = 0x%04x\n", ctrl); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_wait: it's locked error = 0x%04x\n", ctrl); return -EIO; } if (interrupt & ONENAND_INT_READ) { ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); if (ecc & ONENAND_ECC_2BIT_ALL) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_wait: ECC error = 0x%04x\n", ecc); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_wait: ECC error = 0x%04x\n", ecc); return -EBADMSG; } } @@ -524,13 +524,14 @@ static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, int thislen; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", - (unsigned int)from, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_read_ecc: " + "from = 0x%08x, len = %i\n", + (unsigned int)from, (int)len); /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_ecc: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_read_ecc: " + "Attempt read beyond end of device\n"); *retlen = 0; return -EINVAL; } @@ -561,8 +562,8 @@ static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, break; if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_ecc: read failed = %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_read_ecc: read failed = %d\n", ret); break; } @@ -615,16 +616,17 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, int read = 0, thislen, column; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", - (unsigned int)from, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_read_oob: " + "from = 0x%08x, len = %i\n", + (unsigned int)from, (int)len); /* Initialize return length value */ *retlen = 0; /* Do not allow reads past end of device */ if (unlikely((from + len) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_oob: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_read_oob: " + "Attempt read beyond end of device\n"); return -EINVAL; } @@ -652,8 +654,8 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, break; if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_oob: read failed = %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_read_oob: read failed = %d\n", ret); break; } @@ -733,23 +735,24 @@ static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, int written = 0; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n", - (unsigned int)to, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_write_ecc: " + "to = 0x%08x, len = %i\n", + (unsigned int)to, (int)len); /* Initialize retlen, in case of early exit */ *retlen = 0; /* Do not allow writes past end of device */ if (unlikely((to + len) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: Attempt write to past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_ecc: " + "Attempt write to past end of device\n"); return -EINVAL; } /* Reject writes, which are not page aligned */ if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: Attempt to write not page aligned data\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_ecc: " + "Attempt to write not page aligned data\n"); return -EINVAL; } @@ -772,8 +775,8 @@ static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, ret = this->wait(mtd, FL_WRITING); if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: write filaed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_write_ecc: write filaed %d\n", ret); break; } @@ -782,8 +785,8 @@ static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, /* Only check verify write turn on */ ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page); if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: verify failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_write_ecc: verify failed %d\n", ret); break; } @@ -836,16 +839,17 @@ int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, int column, status; int written = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", - (unsigned int)to, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_write_oob: " + "to = 0x%08x, len = %i\n", + (unsigned int)to, (int)len); /* Initialize retlen, in case of early exit */ *retlen = 0; /* Do not allow writes past end of device */ if (unlikely((to + len) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_oob: Attempt write to past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_oob: " + "Attempt write to past end of device\n"); return -EINVAL; } @@ -904,28 +908,29 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) int len; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", - (unsigned int)instr->addr, (unsigned int)instr->len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", + (unsigned int)instr->addr, (unsigned int)instr->len); block_size = (1 << this->erase_shift); /* Start address must align on block boundary */ if (unlikely(instr->addr & (block_size - 1))) { - DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_erase: Unaligned address\n"); return -EINVAL; } /* Length must align on block boundary */ if (unlikely(instr->len & (block_size - 1))) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Length not block aligned\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_erase: Length not block aligned\n"); return -EINVAL; } /* Do not allow erase past end of device */ if (unlikely((instr->len + instr->addr) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Erase past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_erase: Erase past end of device\n"); return -EINVAL; } @@ -950,12 +955,12 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) /* Check, if it is write protected */ if (ret) { if (ret == -EPERM) - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Device is write protected!!!\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " + "Device is write protected!!!\n"); else - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Failed erase, block %d\n", - (unsigned)(addr >> this->erase_shift)); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " + "Failed erase, block %d\n", + (unsigned)(addr >> this->erase_shift)); instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; goto erase_exit; @@ -988,7 +993,7 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) */ void onenand_sync(struct mtd_info *mtd) { - DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); /* Grab the lock and see if the device is available */ onenand_get_device(mtd, FL_SYNCING); diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index 5a610ee5ea..87344ab65f 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -156,9 +156,9 @@ static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) block = (int)(offs >> (bbm->bbt_erase_shift - 1)); res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; - DEBUG(MTD_DEBUG_LEVEL2, - "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", - (unsigned int)offs, block >> 1, res); + MTDDEBUG (MTD_DEBUG_LEVEL2, + "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, block >> 1, res); switch ((int)res) { case 0x00: diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile new file mode 100644 index 0000000000..af6af97d11 --- /dev/null +++ b/drivers/mtd/spi/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libspi_flash.a + +COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o +COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c new file mode 100644 index 0000000000..fb7a4a939b --- /dev/null +++ b/drivers/mtd/spi/atmel.c @@ -0,0 +1,362 @@ +/* + * Atmel SPI DataFlash support + * + * Copyright (C) 2008 Atmel Corporation + */ +#define DEBUG +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +/* AT45-specific commands */ +#define CMD_AT45_READ_STATUS 0xd7 +#define CMD_AT45_ERASE_PAGE 0x81 +#define CMD_AT45_LOAD_PROG_BUF1 0x82 +#define CMD_AT45_LOAD_BUF1 0x84 +#define CMD_AT45_LOAD_PROG_BUF2 0x85 +#define CMD_AT45_LOAD_BUF2 0x87 +#define CMD_AT45_PROG_BUF1 0x88 +#define CMD_AT45_PROG_BUF2 0x89 + +/* AT45 status register bits */ +#define AT45_STATUS_P2_PAGE_SIZE (1 << 0) +#define AT45_STATUS_READY (1 << 7) + +/* DataFlash family IDs, as obtained from the second idcode byte */ +#define DF_FAMILY_AT26F 0 +#define DF_FAMILY_AT45 1 +#define DF_FAMILY_AT26DF 2 /* AT25DF and AT26DF */ + +struct atmel_spi_flash_params { + u8 idcode1; + /* Log2 of page size in power-of-two mode */ + u8 l2_page_size; + u8 pages_per_block; + u8 blocks_per_sector; + u8 nr_sectors; + const char *name; +}; + +struct atmel_spi_flash { + const struct atmel_spi_flash_params *params; + struct spi_flash flash; +}; + +static inline struct atmel_spi_flash * +to_atmel_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct atmel_spi_flash, flash); +} + +static const struct atmel_spi_flash_params atmel_spi_flash_table[] = { + { + .idcode1 = 0x28, + .l2_page_size = 10, + .pages_per_block = 8, + .blocks_per_sector = 32, + .nr_sectors = 32, + .name = "AT45DB642D", + }, +}; + +static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 cmd = CMD_AT45_READ_STATUS; + u8 status; + + timebase = get_timer(0); + + ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); + if (ret) + return -1; + + do { + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) + return -1; + + if (status & AT45_STATUS_READY) + break; + } while (get_timer(timebase) < timeout); + + /* Deactivate CS */ + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if (status & AT45_STATUS_READY) + return 0; + + /* Timed out */ + return -1; +} + +/* + * Assemble the address part of a command for AT45 devices in + * non-power-of-two page size mode. + */ +static void at45_build_address(struct atmel_spi_flash *asf, u8 *cmd, u32 offset) +{ + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + + /* + * The "extra" space per page is the power-of-two page size + * divided by 32. + */ + page_shift = asf->params->l2_page_size; + page_size = (1 << page_shift) + (1 << (page_shift - 5)); + page_shift++; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = page_addr >> (16 - page_shift); + cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[2] = byte_addr; +} + +static int dataflash_read_fast_p2(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int dataflash_read_fast_at45(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + at45_build_address(asf, cmd + 1, offset); + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int dataflash_write_at45(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_shift = asf->params->l2_page_size; + page_size = (1 << page_shift) + (1 << (page_shift - 5)); + page_shift++; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + /* Use the same address bits for both commands */ + cmd[0] = CMD_AT45_LOAD_BUF1; + cmd[1] = page_addr >> (16 - page_shift); + cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[3] = byte_addr; + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: Loading AT45 buffer failed\n"); + goto out; + } + + cmd[0] = CMD_AT45_PROG_BUF1; + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: AT45 page programming failed\n"); + goto out; + } + + ret = at45_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: AT45 page programming timed out\n"); + goto out; + } + + page_addr++; + byte_addr = 0; + } + + debug("SF: AT45: Successfully programmed %u bytes @ 0x%x\n", + len, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len) +{ + struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); + unsigned long page_addr; + unsigned long page_size; + unsigned int page_shift; + size_t actual; + int ret; + u8 cmd[4]; + + /* + * TODO: This function currently uses page erase only. We can + * probably speed things up by using block and/or sector erase + * when possible. + */ + + page_shift = asf->params->l2_page_size; + page_size = (1 << page_shift) + (1 << (page_shift - 5)); + page_shift++; + page_addr = offset / page_size; + + if (offset % page_size || len % page_size) { + debug("SF: Erase offset/length not multiple of page size\n"); + return -1; + } + + cmd[0] = CMD_AT45_ERASE_PAGE; + cmd[3] = 0x00; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += page_size) { + cmd[1] = page_addr >> (16 - page_shift); + cmd[2] = page_addr << (page_shift - 8); + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: AT45 page erase failed\n"); + goto out; + } + + ret = at45_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); + if (ret < 0) { + debug("SF: AT45 page erase timed out\n"); + goto out; + } + + page_addr++; + } + + debug("SF: AT45: Successfully erased %u bytes @ 0x%x\n", + len, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) +{ + const struct atmel_spi_flash_params *params; + unsigned long page_size; + unsigned int family; + struct atmel_spi_flash *asf; + unsigned int i; + int ret; + u8 status; + + for (i = 0; i < ARRAY_SIZE(atmel_spi_flash_table); i++) { + params = &atmel_spi_flash_table[i]; + if (params->idcode1 == idcode[1]) + break; + } + + if (i == ARRAY_SIZE(atmel_spi_flash_table)) { + debug("SF: Unsupported DataFlash ID %02x\n", + idcode[1]); + return NULL; + } + + asf = malloc(sizeof(struct atmel_spi_flash)); + if (!asf) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + asf->params = params; + asf->flash.spi = spi; + asf->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + family = idcode[1] >> 5; + + switch (family) { + case DF_FAMILY_AT45: + /* + * AT45 chips have configurable page size. The status + * register indicates which configuration is active. + */ + ret = spi_flash_cmd(spi, CMD_AT45_READ_STATUS, &status, 1); + if (ret) + goto err; + + debug("SF: AT45 status register: %02x\n", status); + + if (!(status & AT45_STATUS_P2_PAGE_SIZE)) { + asf->flash.read = dataflash_read_fast_at45; + asf->flash.write = dataflash_write_at45; + asf->flash.erase = dataflash_erase_at45; + page_size += 1 << (params->l2_page_size - 5); + } else { + asf->flash.read = dataflash_read_fast_p2; + } + + break; + + case DF_FAMILY_AT26F: + case DF_FAMILY_AT26DF: + asf->flash.read = dataflash_read_fast_p2; + break; + + default: + debug("SF: Unsupported DataFlash family %u\n", family); + goto err; + } + + asf->flash.size = page_size * params->pages_per_block + * params->blocks_per_sector + * params->nr_sectors; + + debug("SF: Detected %s with page size %u, total %u bytes\n", + params->name, page_size, asf->flash.size); + + return &asf->flash; + +err: + free(asf); + return NULL; +} diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c new file mode 100644 index 0000000000..d581cb3e89 --- /dev/null +++ b/drivers/mtd/spi/spi_flash.c @@ -0,0 +1,162 @@ +/* + * SPI flash interface + * + * Copyright (C) 2008 Atmel Corporation + */ +#define DEBUG +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + + if (len == 0) + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, 8, &cmd, NULL, flags); + if (ret) { + debug("SF: Failed to send command %02x: %d\n", cmd, ret); + return ret; + } + + if (len) { + ret = spi_xfer(spi, len * 8, NULL, response, SPI_XFER_END); + if (ret) + debug("SF: Failed to read response (%zu bytes): %d\n", + len, ret); + } + + return ret; +} + +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + + if (data_len == 0) + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("SF: Failed to send read command (%zu bytes): %d\n", + cmd_len, ret); + } else if (data_len != 0) { + ret = spi_xfer(spi, data_len * 8, NULL, data, SPI_XFER_END); + if (ret) + debug("SF: Failed to read %zu bytes of data: %d\n", + data_len, ret); + } + + return ret; +} + +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + + if (data_len == 0) + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("SF: Failed to send read command (%zu bytes): %d\n", + cmd_len, ret); + } else if (data_len != 0) { + ret = spi_xfer(spi, data_len * 8, data, NULL, SPI_XFER_END); + if (ret) + debug("SF: Failed to read %zu bytes of data: %d\n", + data_len, ret); + } + + return ret; +} + + +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + struct spi_slave *spi = flash->spi; + int ret; + + spi_claim_bus(spi); + ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); + spi_release_bus(spi); + + return ret; +} + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + struct spi_flash *flash; + int ret; + u8 idcode[3]; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + debug("SF: Failed to set up slave\n"); + return NULL; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("SF: Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + /* Read the ID codes */ + ret = spi_flash_cmd(spi, CMD_READ_ID, &idcode, sizeof(idcode)); + if (ret) + goto err_read_id; + + debug("SF: Got idcode %02x %02x %02x\n", idcode[0], + idcode[1], idcode[2]); + + switch (idcode[0]) { +#ifdef CONFIG_SPI_FLASH_SPANSION + case 0x01: + flash = spi_flash_probe_spansion(spi, idcode); + break; +#endif +#ifdef CONFIG_SPI_FLASH_ATMEL + case 0x1F: + flash = spi_flash_probe_atmel(spi, idcode); + break; +#endif + default: + debug("SF: Unsupported manufacturer %02X\n", idcode[0]); + flash = NULL; + break; + } + + if (!flash) + goto err_manufacturer_probe; + + spi_release_bus(spi); + + return flash; + +err_manufacturer_probe: +err_read_id: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return NULL; +} + +void spi_flash_free(struct spi_flash *flash) +{ + spi_free_slave(flash->spi); + free(flash); +} diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h new file mode 100644 index 0000000000..14380500aa --- /dev/null +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -0,0 +1,45 @@ +/* + * SPI flash internal definitions + * + * Copyright (C) 2008 Atmel Corporation + */ + +/* Common parameters */ +#define SPI_FLASH_PROG_TIMEOUT ((10 * CFG_HZ) / 1000) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT ((50 * CFG_HZ) / 1000) +#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CFG_HZ) + +/* Common commands */ +#define CMD_READ_ID 0x9f + +#define CMD_READ_ARRAY_SLOW 0x03 +#define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_ARRAY_LEGACY 0xe8 + +/* Send a single-byte command to the device and read the response */ +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); + +/* + * Send a multi-byte command to the device and read the response. Used + * for flash array reads, etc. + */ +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +/* + * Send a multi-byte command to the device followed by (optional) + * data. Used for programming the flash array, etc. + */ +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len); + +/* + * Same as spi_flash_cmd_read() except it also claims/releases the SPI + * bus. Used as common part of the ->read() operation. + */ +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +/* Manufacturer-specific probe functions */ +struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/net/3c589.c b/drivers/net/3c589.c index 3f1e770efe..0cf8dff689 100644 --- a/drivers/net/3c589.c +++ b/drivers/net/3c589.c @@ -26,8 +26,6 @@ #include <command.h> #include <net.h> -#ifdef CONFIG_DRIVER_3C589 - #include "3c589.h" @@ -514,6 +512,3 @@ int eth_send(volatile void *packet, int length) { return length; } - - -#endif /* CONFIG_DRIVER_3C589 */ diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5b031c9af1..bcf31cbe27 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -25,47 +25,48 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnet.a -COBJS-y += 3c589.o -COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o +COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o +COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o -COBJS-y += cs8900.o -COBJS-y += dc2114x.o -COBJS-y += dm9000x.o -COBJS-y += e1000.o -COBJS-y += eepro100.o -COBJS-y += enc28j60.o -COBJS-y += fsl_mcdmafec.o +COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o +COBJS-$(CONFIG_TULIP) += dc2114x.o +COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o +COBJS-$(CONFIG_E1000) += e1000.o +COBJS-$(CONFIG_EEPRO100) += eepro100.o +COBJS-$(CONFIG_ENC28J60) += enc28j60.o +COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o COBJS-$(CONFIG_GRETH) += greth.o -COBJS-y += inca-ip_sw.o -COBJS-y += ks8695eth.o -COBJS-y += lan91c96.o -COBJS-y += macb.o -COBJS-y += mcffec.o -COBJS-y += natsemi.o +COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o +COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o +COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o +COBJS-$(CONFIG_MACB) += macb.o +COBJS-$(CONFIG_MCFFEC) += mcffec.o +COBJS-$(CONFIG_NATSEMI) += natsemi.o ifeq ($(CONFIG_DRIVER_NE2000),y) COBJS-y += ne2000.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o endif -COBJS-y += netarm_eth.o -COBJS-y += netconsole.o -COBJS-y += ns7520_eth.o -COBJS-y += ns8382x.o -COBJS-y += ns9750_eth.o -COBJS-y += pcnet.o -COBJS-y += plb2800_eth.o -COBJS-y += rtl8019.o -COBJS-y += rtl8139.o -COBJS-y += rtl8169.o -COBJS-y += s3c4510b_eth.o -COBJS-y += smc91111.o -COBJS-y += smc911x.o -COBJS-y += tigon3.o -COBJS-y += tsec.o -COBJS-y += tsi108_eth.o -COBJS-y += uli526x.o -COBJS-y += vsc7385.o +COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o +COBJS-$(CONFIG_NETCONSOLE) += netconsole.o +COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o +COBJS-$(CONFIG_NS8382X) += ns8382x.o +COBJS-$(CONFIG_DRIVER_NS9750_ETHERNET) += ns9750_eth.o +COBJS-$(CONFIG_PCNET) += pcnet.o +COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o +COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o +COBJS-$(CONFIG_RTL8139) += rtl8139.o +COBJS-$(CONFIG_RTL8169) += rtl8169.o +COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o +COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o +COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o +COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o +COBJS-$(CONFIG_TSEC_ENET) += tsec.o +COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o +COBJS-$(CONFIG_ULI526X) += uli526x.o +COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_SH_ETHER) += sh_eth.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c index 5ad31d1fdb..6b28b95ebc 100644 --- a/drivers/net/bcm570x.c +++ b/drivers/net/bcm570x.c @@ -6,9 +6,6 @@ #include <common.h> -#if defined(CONFIG_CMD_NET) \ - && (!defined(CONFIG_NET_MULTI)) && defined(CONFIG_BCM570x) - #ifdef CONFIG_BMW #include <mpc824x.h> #endif @@ -1599,5 +1596,3 @@ PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx) return pQueue->Array[Idx]; } - -#endif diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index 458b517d1f..ae1983ac0b 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -41,10 +41,6 @@ #include "cs8900.h" #include <net.h> -#ifdef CONFIG_DRIVER_CS8900 - -#if defined(CONFIG_CMD_NET) - #undef DEBUG /* packet page register access functions */ @@ -315,7 +311,3 @@ int cs8900_e2prom_write(unsigned char addr, unsigned short value) return 0; } - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_CS8900 */ diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 1d728d8b30..811723904d 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -19,10 +19,6 @@ */ #include <common.h> - -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_TULIP) - #include <malloc.h> #include <net.h> #include <pci.h> @@ -766,5 +762,3 @@ static void update_srom(struct eth_device *dev, bd_t *bis) } } #endif /* UPDATE_SROM */ - -#endif diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 01e2f14a9d..844fb766d8 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -36,7 +36,24 @@ v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: -------------------------------------- - 12/15/2003 Initial port to u-boot by Sascha Hauer <saschahauer@web.de> + 12/15/2003 Initial port to u-boot by + Sascha Hauer <saschahauer@web.de> + + 06/03/2008 Remy Bohmer <linux@bohmer.net> + - Fixed the driver to work with DM9000A. + (check on ISR receive status bit before reading the + FIFO as described in DM9000 programming guide and + application notes) + - Added autodetect of databus width. + - Made debug code compile again. + - Adapt eth_send such that it matches the DM9000* + application notes. Needed to make it work properly + for DM9000A. + - Adapted reset procedure to match DM9000 application + notes (i.e. double reset) + - some minor code cleanups + These changes are tested with DM9000{A,EP,E} together + with a 200MHz Atmel AT91SAM92161 core TODO: Homerun NIC and longrun NIC are not functional, only internal at the moment. @@ -47,8 +64,6 @@ TODO: Homerun NIC and longrun NIC are not functional, only internal at the #include <net.h> #include <asm/io.h> -#ifdef CONFIG_DRIVER_DM9000 - #include "dm9000x.h" /* Board/System/Debug information/definition ---------------- */ @@ -59,10 +74,22 @@ TODO: Homerun NIC and longrun NIC are not functional, only internal at the /* #define CONFIG_DM9000_DEBUG */ #ifdef CONFIG_DM9000_DEBUG -#define DM9000_DBG(fmt,args...) printf(fmt ,##args) -#else /* */ +#define DM9000_DBG(fmt,args...) printf(fmt, ##args) +#define DM9000_DMP_PACKET(func,packet,length) \ + do { \ + int i; \ + printf(func ": length: %d\n", length); \ + for (i = 0; i < length; i++) { \ + if (i % 8 == 0) \ + printf("\n%s: %02x: ", func, i); \ + printf("%02x ", ((unsigned char *) packet)[i]); \ + } printf("\n"); \ + } while(0) +#else #define DM9000_DBG(fmt,args...) -#endif /* */ +#define DM9000_DMP_PACKET(func,packet,length) +#endif + enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD = 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO = 8, DM9000_1M_HPNA = 0x10 @@ -84,8 +111,11 @@ typedef struct board_info { u8 device_wait_reset; /* device state */ u8 nic_type; /* NIC type */ unsigned char srom[128]; + void (*outblk)(volatile void *data_ptr, int count); + void (*inblk)(void *data_ptr, int count); + void (*rx_status)(u16 *RxStatus, u16 *RxLen); } board_info_t; -board_info_t dmfe_info; +static board_info_t dm9000_info; /* For module input parameter */ static int media_mode = DM9000_AUTO; @@ -124,10 +154,85 @@ dump_regs(void) DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); - DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR)); + DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR)); DM9000_DBG("\n"); } -#endif /* */ +#endif + +static void dm9000_outblk_8bit(volatile void *data_ptr, int count) +{ + int i; + for (i = 0; i < count; i++) + DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); +} + +static void dm9000_outblk_16bit(volatile void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 1) / 2; + + for (i = 0; i < tmplen; i++) + DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); +} +static void dm9000_outblk_32bit(volatile void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 3) / 4; + + for (i = 0; i < tmplen; i++) + DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); +} + +static void dm9000_inblk_8bit(void *data_ptr, int count) +{ + int i; + for (i = 0; i < count; i++) + ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA); +} + +static void dm9000_inblk_16bit(void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 1) / 2; + + for (i = 0; i < tmplen; i++) + ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA); +} +static void dm9000_inblk_32bit(void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 3) / 4; + + for (i = 0; i < tmplen; i++) + ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA); +} + +static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen) +{ + u32 tmpdata; + + DM9000_outb(DM9000_MRCMD, DM9000_IO); + + tmpdata = DM9000_inl(DM9000_DATA); + *RxStatus = tmpdata; + *RxLen = tmpdata >> 16; +} + +static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen) +{ + DM9000_outb(DM9000_MRCMD, DM9000_IO); + + *RxStatus = DM9000_inw(DM9000_DATA); + *RxLen = DM9000_inw(DM9000_DATA); +} + +static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen) +{ + DM9000_outb(DM9000_MRCMD, DM9000_IO); + + *RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); + *RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); +} /* Search DM9000 board, allocate space and register it @@ -236,7 +341,7 @@ program_dm9802(void) static void identify_nic(void) { - struct board_info *db = &dmfe_info; /* Point a board information structure */ + struct board_info *db = &dm9000_info; u16 phy_reg3; DM9000_iow(DM9000_NCR, NCR_EXT_PHY); phy_reg3 = phy_read(3); @@ -263,9 +368,35 @@ identify_nic(void) static void dm9000_reset(void) { - DM9000_DBG("resetting\n"); - DM9000_iow(DM9000_NCR, NCR_RST); - udelay(1000); /* delay 1ms */ + DM9000_DBG("resetting DM9000\n"); + + /* Reset DM9000, + see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */ + + /* DEBUG: Make all GPIO pins outputs */ + DM9000_iow(DM9000_GPCR, 0x0F); + /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ + DM9000_iow(DM9000_GPR, 0); + /* Step 2: Software reset */ + DM9000_iow(DM9000_NCR, 3); + + do { + DM9000_DBG("resetting the DM9000, 1st reset\n"); + udelay(25); /* Wait at least 20 us */ + } while (DM9000_ior(DM9000_NCR) & 1); + + DM9000_iow(DM9000_NCR, 0); + DM9000_iow(DM9000_NCR, 3); /* Issue a second reset */ + + do { + DM9000_DBG("resetting the DM9000, 2nd reset\n"); + udelay(25); /* Wait at least 20 us */ + } while (DM9000_ior(DM9000_NCR) & 1); + + /* Check whether the ethernet controller is present */ + if ((DM9000_ior(DM9000_PIDL) != 0x0) || + (DM9000_ior(DM9000_PIDH) != 0x90)) + printf("ERROR: resetting DM9000 -> not responding\n"); } /* Initilize dm9000 board @@ -274,12 +405,46 @@ int eth_init(bd_t * bd) { int i, oft, lnk; + u8 io_mode; + struct board_info *db = &dm9000_info; + DM9000_DBG("eth_init()\n"); /* RESET device */ dm9000_reset(); dm9000_probe(); + /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ + io_mode = DM9000_ior(DM9000_ISR) >> 6; + + switch (io_mode) { + case 0x0: /* 16-bit mode */ + printf("DM9000: running in 16 bit mode\n"); + db->outblk = dm9000_outblk_16bit; + db->inblk = dm9000_inblk_16bit; + db->rx_status = dm9000_rx_status_16bit; + break; + case 0x01: /* 32-bit mode */ + printf("DM9000: running in 32 bit mode\n"); + db->outblk = dm9000_outblk_32bit; + db->inblk = dm9000_inblk_32bit; + db->rx_status = dm9000_rx_status_32bit; + break; + case 0x02: /* 8 bit mode */ + printf("DM9000: running in 8 bit mode\n"); + db->outblk = dm9000_outblk_8bit; + db->inblk = dm9000_inblk_8bit; + db->rx_status = dm9000_rx_status_8bit; + break; + default: + /* Assume 8 bit mode, will probably not work anyway */ + printf("DM9000: Undefined IO-mode:0x%x\n", io_mode); + db->outblk = dm9000_outblk_8bit; + db->inblk = dm9000_inblk_8bit; + db->rx_status = dm9000_rx_status_8bit; + break; + } + /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ identify_nic(); @@ -289,19 +454,28 @@ eth_init(bd_t * bd) /* Set PHY */ set_PHY_mode(); - /* Program operating register */ - DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ - DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ - DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ - DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ - DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ - DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ - DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ - DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ + /* Program operating register, only intern phy supported by now */ + DM9000_iow(DM9000_NCR, 0x0); + /* TX Polling clear */ + DM9000_iow(DM9000_TCR, 0); + /* Less 3Kb, 200us */ + DM9000_iow(DM9000_BPTR, 0x3f); + /* Flow Control : High/Low Water */ + DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); + /* SH FIXME: This looks strange! Flow Control */ + DM9000_iow(DM9000_FCR, 0x0); + /* Special Mode */ + DM9000_iow(DM9000_SMCR, 0); + /* clear TX status */ + DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); + /* Clear interrupt status */ + DM9000_iow(DM9000_ISR, 0x0f); /* Set Node address */ +#ifndef CONFIG_AT91SAM9261EK for (i = 0; i < 6; i++) ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); +#endif if (is_zero_ether_addr(bd->bi_enetaddr) || is_multicast_ether_addr(bd->bi_enetaddr)) { @@ -331,8 +505,11 @@ eth_init(bd_t * bd) DM9000_DBG("\n"); /* Activate DM9000 */ - DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ - DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ + /* RX enable */ + DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); + /* Enable TX/RX interrupt mask */ + DM9000_iow(DM9000_IMR, IMR_PAR); + i = 0; while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ udelay(1000); @@ -374,54 +551,37 @@ eth_init(bd_t * bd) int eth_send(volatile void *packet, int length) { - char *data_ptr; - u32 tmplen, i; int tmo; - DM9000_DBG("eth_send: length: %d\n", length); - for (i = 0; i < length; i++) { - if (i % 8 == 0) - DM9000_DBG("\nSend: 02x: ", i); - DM9000_DBG("%02x ", ((unsigned char *) packet)[i]); - } DM9000_DBG("\n"); - - /* Move data to DM9000 TX RAM */ - data_ptr = (char *) packet; - DM9000_outb(DM9000_MWCMD, DM9000_IO); + struct board_info *db = &dm9000_info; -#ifdef CONFIG_DM9000_USE_8BIT - /* Byte mode */ - for (i = 0; i < length; i++) - DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA); + DM9000_DMP_PACKET("eth_send", packet, length); -#endif /* */ -#ifdef CONFIG_DM9000_USE_16BIT - tmplen = (length + 1) / 2; - for (i = 0; i < tmplen; i++) - DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); + DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ -#endif /* */ -#ifdef CONFIG_DM9000_USE_32BIT - tmplen = (length + 3) / 4; - for (i = 0; i < tmplen; i++) - DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); + /* Move data to DM9000 TX RAM */ + DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ -#endif /* */ + /* push the data to the TX-fifo */ + (db->outblk)(packet, length); /* Set TX length to DM9000 */ DM9000_iow(DM9000_TXPLL, length & 0xff); DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); /* Issue TX polling command */ - DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ + DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ /* wait for end of transmission */ tmo = get_timer(0) + 5 * CFG_HZ; - while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { + while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || + !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) { if (get_timer(0) >= tmo) { printf("transmission timeout\n"); break; } } + DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ + DM9000_DBG("transmit done\n\n"); return 0; } @@ -450,86 +610,67 @@ eth_rx(void) { u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; u16 RxStatus, RxLen = 0; - u32 tmplen, i; -#ifdef CONFIG_DM9000_USE_32BIT - u32 tmpdata; -#endif + struct board_info *db = &dm9000_info; - /* Check packet ready or not */ - DM9000_ior(DM9000_MRCMDX); /* Dummy read */ - rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ - if (rxbyte == 0) + /* Check packet ready or not, we must check + the ISR status first for DM9000A */ + if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ return 0; - /* Status check: this byte must be 0 or 1 */ - if (rxbyte > 1) { - DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ - DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ - DM9000_DBG("rx status check: %d\n", rxbyte); - } - DM9000_DBG("receiving packet\n"); - - /* A packet ready now & Get status/length */ - DM9000_outb(DM9000_MRCMD, DM9000_IO); + DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ -#ifdef CONFIG_DM9000_USE_8BIT - RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); - RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); - -#endif /* */ -#ifdef CONFIG_DM9000_USE_16BIT - RxStatus = DM9000_inw(DM9000_DATA); - RxLen = DM9000_inw(DM9000_DATA); - -#endif /* */ -#ifdef CONFIG_DM9000_USE_32BIT - tmpdata = DM9000_inl(DM9000_DATA); - RxStatus = tmpdata; - RxLen = tmpdata >> 16; + /* There is _at least_ 1 package in the fifo, read them all */ + for (;;) { + DM9000_ior(DM9000_MRCMDX); /* Dummy read */ -#endif /* */ - DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); + /* Get most updated data, + only look at bits 0:1, See application notes DM9000 */ + rxbyte = DM9000_inb(DM9000_DATA) & 0x03; - /* Move data from DM9000 */ - /* Read received packet from RX SRAM */ -#ifdef CONFIG_DM9000_USE_8BIT - for (i = 0; i < RxLen; i++) - rdptr[i] = DM9000_inb(DM9000_DATA); - -#endif /* */ -#ifdef CONFIG_DM9000_USE_16BIT - tmplen = (RxLen + 1) / 2; - for (i = 0; i < tmplen; i++) - ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA); + /* Status check: this byte must be 0 or 1 */ + if (rxbyte > DM9000_PKT_RDY) { + DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ + DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ + printf("DM9000 error: status check fail: 0x%x\n", + rxbyte); + return 0; + } -#endif /* */ -#ifdef CONFIG_DM9000_USE_32BIT - tmplen = (RxLen + 3) / 4; - for (i = 0; i < tmplen; i++) - ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA); + if (rxbyte != DM9000_PKT_RDY) + return 0; /* No packet received, ignore */ + + DM9000_DBG("receiving packet\n"); + + /* A packet ready now & Get status/length */ + (db->rx_status)(&RxStatus, &RxLen); + + DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); + + /* Move data from DM9000 */ + /* Read received packet from RX SRAM */ + (db->inblk)(rdptr, RxLen); + + if ((RxStatus & 0xbf00) || (RxLen < 0x40) + || (RxLen > DM9000_PKT_MAX)) { + if (RxStatus & 0x100) { + printf("rx fifo error\n"); + } + if (RxStatus & 0x200) { + printf("rx crc error\n"); + } + if (RxStatus & 0x8000) { + printf("rx length error\n"); + } + if (RxLen > DM9000_PKT_MAX) { + printf("rx length too big\n"); + dm9000_reset(); + } + } else { + DM9000_DMP_PACKET("eth_rx", rdptr, RxLen); -#endif /* */ - if ((RxStatus & 0xbf00) || (RxLen < 0x40) - || (RxLen > DM9000_PKT_MAX)) { - if (RxStatus & 0x100) { - printf("rx fifo error\n"); + DM9000_DBG("passing packet to upper layer\n"); + NetReceive(NetRxPackets[0], RxLen); } - if (RxStatus & 0x200) { - printf("rx crc error\n"); - } - if (RxStatus & 0x8000) { - printf("rx length error\n"); - } - if (RxLen > DM9000_PKT_MAX) { - printf("rx length too big\n"); - dm9000_reset(); - } - } else { - - /* Pass to upper layer */ - DM9000_DBG("passing packet to upper layer\n"); - NetReceive(NetRxPackets[0], RxLen); - return RxLen; } return 0; } @@ -590,12 +731,12 @@ phy_read(int reg) /* Fill the phyxcer register into REG_0C */ DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ - udelay(100); /* Wait read complete */ + udelay(100); /* Wait read complete */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); /* The read data keeps on REG_0D & REG_0E */ - DM9000_DBG("phy_read(%d): %d\n", reg, val); + DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val); return val; } @@ -613,8 +754,7 @@ phy_write(int reg, u16 value) DM9000_iow(DM9000_EPDRL, (value & 0xff)); DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ - udelay(500); /* Wait write complete */ + udelay(500); /* Wait write complete */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ - DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value); + DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value); } -#endif /* CONFIG_DRIVER_DM9000 */ diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index c53c226d28..060b518996 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -44,9 +44,6 @@ tested on both gig copper and gig fiber boards #include "e1000.h" -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_E1000) - #define TOUT_LOOP 100000 #undef virt_to_bus @@ -78,11 +75,13 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, }; /* Function forward declarations */ @@ -638,6 +637,7 @@ e1000_set_mac_type(struct e1000_hw *hw) hw->mac_type = e1000_82540; break; case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545GM_COPPER: case E1000_DEV_ID_82545EM_FIBER: hw->mac_type = e1000_82545; break; @@ -646,6 +646,7 @@ e1000_set_mac_type(struct e1000_hw *hw) hw->mac_type = e1000_82546; break; case E1000_DEV_ID_82541ER: + case E1000_DEV_ID_82541GI_LF: hw->mac_type = e1000_82541_rev_2; break; default: @@ -3059,5 +3060,3 @@ e1000_initialize(bd_t * bis) } return 1; } - -#endif diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 851467d81c..c258bc2383 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -217,12 +217,14 @@ struct e1000_phy_stats { #define E1000_DEV_ID_82544GC_LOM 0x100D #define E1000_DEV_ID_82540EM 0x100E #define E1000_DEV_ID_82540EM_LOM 0x1015 +#define E1000_DEV_ID_82545GM_COPPER 0x1026 #define E1000_DEV_ID_82545EM_COPPER 0x100F #define E1000_DEV_ID_82545EM_FIBER 0x1011 #define E1000_DEV_ID_82546EB_COPPER 0x1010 #define E1000_DEV_ID_82546EB_FIBER 0x1012 #define E1000_DEV_ID_82541ER 0x1078 -#define NUM_DEV_IDS 14 +#define E1000_DEV_ID_82541GI_LF 0x107C +#define NUM_DEV_IDS 16 #define NODE_ADDRESS_SIZE 6 #define ETH_LENGTH_OF_ADDRESS 6 diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 96ed2710c2..9de0fb5e46 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -30,9 +30,6 @@ #undef DEBUG -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_EEPRO100) - /* Ethernet chip registers. */ #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ @@ -944,5 +941,3 @@ static void read_hw_addr (struct eth_device *dev, bd_t * bis) #endif } } - -#endif diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 98303aceee..5c24b0d9f9 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -17,7 +17,6 @@ #include <config.h> #include <common.h> -#ifdef CONFIG_ENC28J60 #include <net.h> #include <asm/arch/hardware.h> #include <asm/arch/spi.h> @@ -979,5 +978,3 @@ static void phyWrite(unsigned char addr, unsigned short data) } } } - -#endif /* CONFIG_ENC28J60 */ diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 2ef91f2d22..f2bdba6184 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -31,7 +31,6 @@ #include <net.h> #include <miiphy.h> -#ifdef CONFIG_FSLDMAFEC #undef ET_DEBUG #undef MII_DEBUG @@ -49,7 +48,6 @@ #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ BD_ENET_RX_OV | BD_ENET_RX_TR) -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) #include <asm/immap.h> #include <asm/fsl_mcdmafec.h> @@ -586,6 +584,3 @@ int mcdmafec_initialize(bd_t * bis) return 1; } - -#endif /* CONFIG_CMD_NET && CONFIG_NET_MULTI */ -#endif /* CONFIG_FSLDMAFEC */ diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c index e4aaed6afb..d852a150fa 100644 --- a/drivers/net/inca-ip_sw.c +++ b/drivers/net/inca-ip_sw.c @@ -26,9 +26,6 @@ #include <common.h> -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_INCA_IP_SWITCH) - #include <malloc.h> #include <net.h> #include <asm/inca-ip.h> @@ -234,7 +231,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) /* Initialize the descriptor rings. */ for (i = 0; i < NUM_RX_DESC; i++) { - inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]); + inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]); memset(rx_desc, 0, sizeof(rx_ring[i])); /* Set maximum size of receive buffer. @@ -252,14 +249,14 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) /* Let the last descriptor point to the first * one. */ - rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring); + rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring); } else { /* Set the address of the next descriptor. */ - rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]); + rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]); } - rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]); + rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]); } #if 0 @@ -268,7 +265,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) #endif for (i = 0; i < NUM_TX_DESC; i++) { - inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]); + inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]); memset(tx_desc, 0, sizeof(tx_ring[i])); @@ -282,11 +279,11 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) /* Let the last descriptor point to the * first one. */ - tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring); + tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring); } else { /* Set the address of the next descriptor. */ - tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]); + tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]); } } @@ -346,7 +343,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l int res = -1; u32 command; u32 regValue; - inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]); + inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]); #if 0 printf("Entered inca_switch_send()\n"); @@ -365,7 +362,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l } if (tx_old_hold >= 0) { - KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1; + ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1; } tx_old_hold = tx_hold; @@ -376,7 +373,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l tx_desc->TxDataPtr = (u32)packet; tx_desc->params.field.NBA = length; - KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0; + ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0; tx_hold = tx_new; tx_new = (tx_new + 1) % NUM_TX_DESC; @@ -397,7 +394,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); #if 1 - for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) { + for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) { if (i >= TOUT_LOOP) { printf("%s: tx buffer not ready\n", dev->name); goto Done; @@ -423,7 +420,7 @@ static int inca_switch_recv(struct eth_device *dev) #endif for (;;) { - rx_desc = KSEG1ADDR(&rx_ring[rx_new]); + rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]); if (rx_desc->status.field.C == 0) { break; @@ -456,7 +453,7 @@ static int inca_switch_recv(struct eth_device *dev) #if 0 printf("Received %d bytes\n", length); #endif - NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4); + NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4); } else { #if 1 printf("Zero length!!!\n"); @@ -464,7 +461,7 @@ static int inca_switch_recv(struct eth_device *dev) } - KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0; + ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0; rx_hold = rx_new; @@ -813,5 +810,3 @@ Fail: return -1; } #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ - -#endif diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c index b598dd7f23..7f3e0c2e49 100644 --- a/drivers/net/ks8695eth.c +++ b/drivers/net/ks8695eth.c @@ -21,8 +21,6 @@ /****************************************************************************/ #include <common.h> - -#ifdef CONFIG_DRIVER_KS8695ETH #include <malloc.h> #include <net.h> #include <asm/io.h> @@ -234,5 +232,3 @@ int eth_send(volatile void *packet, int len) return len; } - -#endif /* CONFIG_DRIVER_KS8695ETH */ diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 51cfb7e3e2..c23a4000a2 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -63,10 +63,6 @@ #include "lan91c96.h" #include <net.h> -#ifdef CONFIG_DRIVER_LAN91C96 - -#if defined(CONFIG_CMD_NET) - /*------------------------------------------------------------------------ * * Configuration options, for the experienced user to change. @@ -865,9 +861,6 @@ static int smc_hw_init () } #endif /* 0 */ -#endif /* CONFIG_CMD_NET */ - - /* smc_get_ethaddr (bd_t * bd) * * This checks both the environment and the ROM for an ethernet address. If @@ -963,5 +956,3 @@ int get_rom_mac (unsigned char *v_rom_mac) return (1); #endif } - -#endif /* CONFIG_DRIVER_LAN91C96 */ diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 703784ee0d..aa39284d1d 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -17,9 +17,6 @@ */ #include <common.h> -#if defined(CONFIG_MACB) \ - && (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII)) - /* * The u-boot networking stack is a little weird. It seems like the * networking core allocates receive buffers up front without any @@ -417,13 +414,15 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) +#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ + defined(CONFIG_AT91SAM9263) macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else macb_writel(macb, USRIO, 0); #endif #else -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) +#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ + defined(CONFIG_AT91SAM9263) macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #else macb_writel(macb, USRIO, MACB_BIT(MII)); @@ -591,5 +590,3 @@ int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) } #endif - -#endif /* CONFIG_MACB */ diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 5ab4726ff5..58ed5e32c6 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -27,8 +27,6 @@ #include <common.h> #include <malloc.h> -#ifdef CONFIG_MCFFEC - #include <asm/fec.h> #include <asm/immap.h> @@ -51,8 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) - struct fec_info_s fec_info[] = { #ifdef CFG_FEC0_IOBASE { @@ -125,11 +121,17 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) } if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef CONFIG_MCF5445x + fecp->rcr &= ~0x200; /* disabled 10T base */ +#endif #ifdef MII_DEBUG printf("100Mbps\n"); #endif bd->bi_ethspeed = 100; } else { +#ifdef CONFIG_MCF5445x + fecp->rcr |= 0x200; /* enabled 10T base */ +#endif #ifdef MII_DEBUG printf("10Mbps\n"); #endif @@ -599,6 +601,3 @@ int mcffec_initialize(bd_t * bis) return 1; } - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ -#endif /* CONFIG_MCFFEC */ diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index a523959812..4aee0481db 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -56,9 +56,6 @@ #include <asm/io.h> #include <pci.h> -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_NATSEMI) - /* defines */ #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/ @@ -878,5 +875,3 @@ natsemi_disable(struct eth_device *dev) /* Restore PME enable bit */ OUTL(dev, SavedClkRun, ClkRun); } - -#endif diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index 2da57b68bc..ec92485cbe 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -758,8 +758,6 @@ static hw_info_t hw_info[] = { #define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t)) -u8 dev_addr[6]; - #define PCNET_CMD 0x00 #define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */ #define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ @@ -769,14 +767,14 @@ static void pcnet_reset_8390(void) { int i, r; - PRINTK("nic base is %lx\n", nic_base); + PRINTK("nic base is %lx\n", nic.base); n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); @@ -852,8 +850,6 @@ int __get_prom(u8* mac_addr) return 0; } -u32 nic_base; - /* U-boot specific routines */ static u8 *pbuf = NULL; @@ -879,6 +875,7 @@ void uboot_push_tx_done(int key, int val) { int eth_init(bd_t *bd) { int r; + u8 dev_addr[6]; char ethaddr[20]; PRINTK("### eth_init\n"); @@ -901,7 +898,6 @@ int eth_init(bd_t *bd) { } #endif - nic_base = CONFIG_DRIVER_NE2000_BASE; nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE; r = get_prom(dev_addr); diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c index ecf45dc92f..c011809b6f 100644 --- a/drivers/net/netarm_eth.c +++ b/drivers/net/netarm_eth.c @@ -22,15 +22,11 @@ #include <common.h> - -#ifdef CONFIG_DRIVER_NETARMETH #include <command.h> #include <net.h> #include "netarm_eth.h" #include <asm/arch/netarm_registers.h> -#if defined(CONFIG_CMD_NET) - static int na_mii_poll_busy (void); static void na_get_mac_addr (void) @@ -352,7 +348,3 @@ extern int eth_send (volatile void *packet, int length) printf ("eth_send timeout\n"); return 1; } - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 69089f92ce..b2ee5eaba4 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -22,9 +22,6 @@ */ #include <common.h> - -#ifdef CONFIG_NETCONSOLE - #include <command.h> #include <devices.h> #include <net.h> @@ -263,5 +260,3 @@ int drv_nc_init (void) return (rc == 0) ? 1 : rc; } - -#endif /* CONFIG_NETCONSOLE */ diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c index a5a20dfd72..e19c223255 100644 --- a/drivers/net/ns7520_eth.c +++ b/drivers/net/ns7520_eth.c @@ -15,8 +15,6 @@ #include <common.h> -#if defined(CONFIG_DRIVER_NS7520_ETHERNET) - #include <net.h> /* NetSendPacket */ #include <asm/arch/netarm_registers.h> #include <asm/arch/netarm_dma_module.h> @@ -389,8 +387,8 @@ static int ns7520_eth_reset(void) ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); /* reset PHY */ - ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); - ns7520_mii_write(PHY_COMMON_CTRL, 0); + ns7520_mii_write(PHY_BMCR, PHY_BMCR_RESET); + ns7520_mii_write(PHY_BMCR, 0); udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */ @@ -440,26 +438,23 @@ static void ns7520_link_auto_negotiate(void) /* run auto-negotation */ /* define what we are capable of */ - ns7520_mii_write(PHY_COMMON_AUTO_ADV, - PHY_COMMON_AUTO_ADV_100BTXFD | - PHY_COMMON_AUTO_ADV_100BTX | - PHY_COMMON_AUTO_ADV_10BTFD | - PHY_COMMON_AUTO_ADV_10BT | - PHY_COMMON_AUTO_ADV_802_3); + ns7520_mii_write(PHY_ANAR, + PHY_ANLPAR_TXFD | + PHY_ANLPAR_TX | + PHY_ANLPAR_10FD | + PHY_ANLPAR_10 | + PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns7520_mii_write(PHY_COMMON_CTRL, - PHY_COMMON_CTRL_AUTO_NEG | - PHY_COMMON_CTRL_RES_AUTO); + ns7520_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* wait for completion */ ulStartJiffies = get_timer(0); while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) { - uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + uiStatus = ns7520_mii_read(PHY_BMSR); if ((uiStatus & - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) - == - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { /* lucky we are, auto-negotiation succeeded */ ns7520_link_print_changed(); ns7520_link_update_egcr(); @@ -520,14 +515,13 @@ static void ns7520_link_print_changed(void) DEBUG_FN(DEBUG_LINK); - uiControl = ns7520_mii_read(PHY_COMMON_CTRL); + uiControl = ns7520_mii_read(PHY_BMCR); - if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == - PHY_COMMON_CTRL_AUTO_NEG) { - /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ - uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { + /* PHY_BMSR_LS is only set on autonegotiation */ + uiStatus = ns7520_mii_read(PHY_BMSR); - if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + if (!(uiStatus & PHY_BMSR_LS)) { printk(KERN_WARNING NS7520_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -588,12 +582,12 @@ static char ns7520_mii_identify_phy(void) DEBUG_FN(DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1); + phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_PHYIDR1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns7520_mii_read(PHY_COMMON_ID2); + uiID2 = ns7520_mii_read(PHY_PHYIDR2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; @@ -846,14 +840,11 @@ extern int ns7520_miiphy_write(char *devname, unsigned char const addr, return (ret); } #endif /* defined(CONFIG_MII) */ -#endif /* CONFIG_DRIVER_NS7520_ETHERNET */ int ns7520_miiphy_initialize(bd_t *bis) { -#if defined(CONFIG_DRIVER_NS7520_ETHERNET) #if defined(CONFIG_MII) miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write); #endif -#endif return 0; } diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index c807dd4c7b..0b9a3ae66d 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -56,9 +56,6 @@ #include <asm/io.h> #include <pci.h> -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_NS8382X) - /* defines */ #define DSIZE 0x00000FFF #define ETH_ALEN 6 @@ -859,5 +856,3 @@ ns8382x_disable(struct eth_device *dev) /* Restore PME enable bit */ OUTL(dev, SavedClkRun, ClkRun); } - -#endif diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c index 067ff8efab..cade831ac9 100644 --- a/drivers/net/ns9750_eth.c +++ b/drivers/net/ns9750_eth.c @@ -37,9 +37,7 @@ #include "ns9750_eth.h" /* for Ethernet and PHY */ -#ifdef CONFIG_DRIVER_NS9750_ETHERNET - -/* some definition to make transistion to linux easier */ +/* some definition to make transition to linux easier */ #define NS9750_DRIVER_NAME "eth" #define KERN_WARNING "Warning:" @@ -401,8 +399,8 @@ static int ns9750_eth_reset (void) ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); /* reset PHY */ - ns9750_mii_write (PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); - ns9750_mii_write (PHY_COMMON_CTRL, 0); + ns9750_mii_write(PHY_BMCR, PHY_BMCR_RESET); + ns9750_mii_write(PHY_BMCR, 0); /* @TODO check time */ udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But @@ -457,26 +455,26 @@ static void ns9750_link_force (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read (PHY_COMMON_CTRL); - uiControl &= ~(PHY_COMMON_CTRL_SPD_MA | - PHY_COMMON_CTRL_AUTO_NEG | PHY_COMMON_CTRL_DUPLEX); + uiControl = ns9750_mii_read(PHY_BMCR); + uiControl &= ~(PHY_BMCR_SPEED_MASK | + PHY_BMCR_AUTON | PHY_BMCR_DPLX); uiLastLinkStatus = 0; if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) == FS_EEPROM_AUTONEG_SPEED_100) { - uiControl |= PHY_COMMON_CTRL_SPD_100; + uiControl |= PHY_BMCR_100MB; uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX; } else - uiControl |= PHY_COMMON_CTRL_SPD_10; + uiControl |= PHY_BMCR_10_MBPS; if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) == FS_EEPROM_AUTONEG_DUPLEX_FULL) { - uiControl |= PHY_COMMON_CTRL_DUPLEX; + uiControl |= PHY_BMCR_DPLX; uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE; } - ns9750_mii_write (PHY_COMMON_CTRL, uiControl); + ns9750_mii_write(PHY_BMCR, uiControl); ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -497,25 +495,23 @@ static void ns9750_link_auto_negotiate (void) /* run auto-negotation */ /* define what we are capable of */ - ns9750_mii_write (PHY_COMMON_AUTO_ADV, - PHY_COMMON_AUTO_ADV_100BTXFD | - PHY_COMMON_AUTO_ADV_100BTX | - PHY_COMMON_AUTO_ADV_10BTFD | - PHY_COMMON_AUTO_ADV_10BT | - PHY_COMMON_AUTO_ADV_802_3); + ns9750_mii_write(PHY_ANAR, + PHY_ANLPAR_TXFD | + PHY_ANLPAR_TX | + PHY_ANLPAR_10FD | + PHY_ANLPAR_10 | + PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns9750_mii_write (PHY_COMMON_CTRL, - PHY_COMMON_CTRL_AUTO_NEG | - PHY_COMMON_CTRL_RES_AUTO); + ns9750_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* wait for completion */ ulStartJiffies = get_ticks (); while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) { - uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + uiStatus = ns9750_mii_read(PHY_BMSR); if ((uiStatus & - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) == - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { /* lucky we are, auto-negotiation succeeded */ ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -573,14 +569,13 @@ static void ns9750_link_print_changed (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read (PHY_COMMON_CTRL); + uiControl = ns9750_mii_read(PHY_BMCR); - if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == - PHY_COMMON_CTRL_AUTO_NEG) { - /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ - uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { + /* PHY_BMSR_LS is only set on autonegotiation */ + uiStatus = ns9750_mii_read(PHY_BMSR); - if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + if (!(uiStatus & PHY_BMSR_LS)) { printk (KERN_WARNING NS9750_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -594,7 +589,7 @@ static void ns9750_link_print_changed (void) /* mask out all uninteresting parts */ } - /* other PHYs must store there link information in + /* other PHYs must store their link information in uiStatus as PHY_LXT971 */ } } else { @@ -639,12 +634,12 @@ static char ns9750_mii_identify_phy (void) DEBUG_FN (DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns9750_mii_read (PHY_COMMON_ID1); + phyDetected = (PhyType) uiID1 = ns9750_mii_read(PHY_PHYIDR1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns9750_mii_read (PHY_COMMON_ID2); + uiID2 = ns9750_mii_read(PHY_PHYIDR2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; @@ -793,5 +788,3 @@ static unsigned int ns9750_mii_poll_busy (void) return unTimeout; } - -#endif /* CONFIG_DRIVER_NS9750_ETHERNET */ diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index aa04e8f185..a4f0214106 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -45,9 +45,6 @@ #define PCNET_DEBUG2(fmt,args...) #endif -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET) - #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) #error "Macro for PCnet chip version is not defined!" #endif @@ -537,4 +534,3 @@ static void pcnet_halt (struct eth_device *dev) printf ("%s: TIMEOUT: controller reset failed\n", dev->name); } } -#endif diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c index b8cc57aa78..dad842c728 100644 --- a/drivers/net/plb2800_eth.c +++ b/drivers/net/plb2800_eth.c @@ -24,10 +24,6 @@ */ #include <common.h> - -#if defined(CONFIG_CMD_NET) \ - && defined(CONFIG_NET_MULTI) && defined(CONFIG_PLB2800_ETHER) - #include <malloc.h> #include <net.h> #include <asm/addrspace.h> @@ -392,5 +388,3 @@ static unsigned char * plb2800_get_mac_addr(void) return addr; } - -#endif /* CONFIG_PLB2800_ETHER */ diff --git a/drivers/net/rtl8019.c b/drivers/net/rtl8019.c index 9d62cab346..3ddf91793c 100644 --- a/drivers/net/rtl8019.c +++ b/drivers/net/rtl8019.c @@ -32,10 +32,6 @@ #include "rtl8019.h" #include <net.h> -#ifdef CONFIG_DRIVER_RTL8019 - -#if defined(CONFIG_CMD_NET) - /* packet page register access functions */ static unsigned char get_reg (unsigned int regno) @@ -271,7 +267,3 @@ extern int eth_send (volatile void *packet, int length) return 0; } - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_RTL8019 */ diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 097f6841ae..4fd20ac4fe 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -77,9 +77,6 @@ #include <asm/io.h> #include <pci.h> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_RTL8139) - #define RTL_TIMEOUT 100000 #define ETH_FRAME_LEN 1514 @@ -545,4 +542,3 @@ static void rtl_disable(struct eth_device *dev) udelay (100); /* wait 100us */ } } -#endif diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 6c4c9ff63e..7423bc0eb8 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -58,9 +58,6 @@ #include <asm/io.h> #include <pci.h> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_RTL8169) - #undef DEBUG_RTL8169 #undef DEBUG_RTL8169_TX #undef DEBUG_RTL8169_RX @@ -887,5 +884,3 @@ int rtl8169_initialize(bd_t *bis) } return card_number; } - -#endif diff --git a/drivers/net/s3c4510b_eth.c b/drivers/net/s3c4510b_eth.c index 3d9066abea..6dcb244861 100644 --- a/drivers/net/s3c4510b_eth.c +++ b/drivers/net/s3c4510b_eth.c @@ -25,9 +25,6 @@ */ #include <common.h> - -#ifdef CONFIG_DRIVER_S3C4510_ETH - #include <command.h> #include <net.h> #include <asm/hardware.h> @@ -242,5 +239,3 @@ void eth_halt(void) /* disable MAC */ PUT_REG( REG_MACCON, ETH_HaltReg); } - -#endif diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c new file mode 100644 index 0000000000..9e3cf98b3b --- /dev/null +++ b/drivers/net/sh_eth.c @@ -0,0 +1,603 @@ +/* + * sh_eth.c - Driver for Renesas SH7763's ethernet controler. + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (c) 2008 Nobuhiro Iwamatsu + * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/errno.h> +#include <asm/io.h> + +#include "sh_eth.h" + +#ifndef CONFIG_SH_ETHER_USE_PORT +# error "Please define CONFIG_SH_ETHER_USE_PORT" +#endif +#ifndef CONFIG_SH_ETHER_PHY_ADDR +# error "Please define CONFIG_SH_ETHER_PHY_ADDR" +#endif + +extern int eth_init(bd_t *bd); +extern void eth_halt(void); +extern int eth_rx(void); +extern int eth_send(volatile void *packet, int length); + +static struct dev_info_s *dev; + +/* + * Bits are written to the PHY serially using the + * PIR register, just like a bit banger. + */ +static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) +{ + int i; + u32 pir; + + /* Bit positions is 1 less than the number of bits */ + for (i = len - 1; i >= 0; i--) { + /* Write direction, bit to write, clock is low */ + pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); + outl(pir, PIR(port)); + udelay(1); + /* Write direction, bit to write, clock is high */ + pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); + outl(pir, PIR(port)); + udelay(1); + /* Write direction, bit to write, clock is low */ + pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); + outl(pir, PIR(port)); + udelay(1); + } +} + +static void sh_eth_mii_bus_release(int port) +{ + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); + /* Read direction, clock is high */ + outl(1, PIR(port)); + udelay(1); + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); +} + +static void sh_eth_mii_ind_bus_release(int port) +{ + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); +} + +static int sh_eth_mii_read_phy_bits(int port, u32 * val, int len) +{ + int i; + u32 pir; + + *val = 0; + for (i = len - 1; i >= 0; i--) { + /* Read direction, clock is high */ + outl(1, PIR(port)); + udelay(1); + /* Read bit */ + pir = inl(PIR(port)); + *val |= (pir & 8) ? 1 << i : 0; + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); + } + + return 0; +} + +#define PHY_INIT 0xFFFFFFFF +#define PHY_READ 0x02 +#define PHY_WRITE 0x01 +/* + * To read a phy register, mii managements frames are sent to the phy. + * The frames look like this: + * pre (32 bits): 0xffff ffff + * st (2 bits): 01 + * op (2bits): 10: read 01: write + * phyad (5 bits): xxxxx + * regad (5 bits): xxxxx + * ta (Bus release): + * data (16 bits): read data + */ +static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) +{ + u32 val; + + /* Sent mii management frame */ + /* pre */ + sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); + /* st (start of frame) */ + sh_eth_mii_write_phy_bits(port, 0x1, 2); + /* op (code) */ + sh_eth_mii_write_phy_bits(port, PHY_READ, 2); + /* phy address */ + sh_eth_mii_write_phy_bits(port, phy_addr, 5); + /* Register to read */ + sh_eth_mii_write_phy_bits(port, reg, 5); + + /* Bus release */ + sh_eth_mii_bus_release(port); + + /* Read register */ + sh_eth_mii_read_phy_bits(port, &val, 16); + + return val; +} + +/* + * To write a phy register, mii managements frames are sent to the phy. + * The frames look like this: + * pre (32 bits): 0xffff ffff + * st (2 bits): 01 + * op (2bits): 10: read 01: write + * phyad (5 bits): xxxxx + * regad (5 bits): xxxxx + * ta (2 bits): 10 + * data (16 bits): write data + * idle (Independent bus release) + */ +static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) +{ + /* Sent mii management frame */ + /* pre */ + sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); + /* st (start of frame) */ + sh_eth_mii_write_phy_bits(port, 0x1, 2); + /* op (code) */ + sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); + /* phy address */ + sh_eth_mii_write_phy_bits(port, phy_addr, 5); + /* Register to read */ + sh_eth_mii_write_phy_bits(port, reg, 5); + /* ta */ + sh_eth_mii_write_phy_bits(port, PHY_READ, 2); + /* Write register data */ + sh_eth_mii_write_phy_bits(port, val, 16); + + /* Independent bus release */ + sh_eth_mii_ind_bus_release(port); +} + +void eth_halt(void) +{ +} + +int eth_send(volatile void *packet, int len) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + int timeout; + int rc = 0; + + if (!packet || len > 0xffff) { + printf("eth_send: Invalid argument\n"); + return -EINVAL; + } + + /* packet must be a 4 byte boundary */ + if ((int)packet & (4 - 1)) { + printf("eth_send: packet not 4 byte alligned\n"); + return -EFAULT; + } + + /* Update tx descriptor */ + port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); + port_info->tx_desc_cur->td1 = len << 16; + /* Must preserve the end of descriptor list indication */ + if (port_info->tx_desc_cur->td0 & TD_TDLE) + port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; + else + port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; + + /* Restart the transmitter if disabled */ + if (!(inl(EDTRR(port)) & EDTRR_TRNS)) + outl(EDTRR_TRNS, EDTRR(port)); + + /* Wait until packet is transmitted */ + timeout = 1000; + while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) + udelay(100); + + if (timeout < 0) { + printf("eth_send: transmit timeout\n"); + rc = -1; + goto err; + } + +err: + port_info->tx_desc_cur++; + if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) + port_info->tx_desc_cur = port_info->tx_desc_base; + + return rc; +} + +int eth_rx(void) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + int len = 0; + volatile u8 *packet; + + /* Check if the rx descriptor is ready */ + if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { + /* Check for errors */ + if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { + len = port_info->rx_desc_cur->rd1 & 0xffff; + packet = (volatile u8 *) + ADDR_TO_P2(port_info->rx_desc_cur->rd2); + NetReceive(packet, len); + } + + /* Make current descriptor available again */ + if (port_info->rx_desc_cur->rd0 & RD_RDLE) + port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; + else + port_info->rx_desc_cur->rd0 = RD_RACT; + + /* Point to the next descriptor */ + port_info->rx_desc_cur++; + if (port_info->rx_desc_cur >= + port_info->rx_desc_base + NUM_RX_DESC) + port_info->rx_desc_cur = port_info->rx_desc_base; + } + + /* Restart the receiver if disabled */ + if (!(inl(EDRRR(port)) & EDRRR_R)) + outl(EDRRR_R, EDRRR(port)); + + return len; +} + +#define EDMR_INIT_CNT 1000 +static int sh_eth_reset(struct dev_info_s *dev) +{ + int port = dev->port; + int i; + + /* Start e-dmac transmitter and receiver */ + outl(EDSR_ENALL, EDSR(port)); + + /* Perform a software reset and wait for it to complete */ + outl(EDMR_SRST, EDMR(port)); + for (i = 0; i < EDMR_INIT_CNT; i++) { + if (!(inl(EDMR(port)) & EDMR_SRST)) + break; + udelay(1000); + } + + if (i == EDMR_INIT_CNT) { + printf("Error: Software reset timeout\n"); + return -1; + } + return 0; +} + +static int sh_eth_tx_desc_init(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + u32 tmp_addr; + struct tx_desc_s *cur_tx_desc; + int i; + + /* Allocate tx descriptors. They must be TX_DESC_SIZE bytes + aligned */ + if (!(port_info->tx_desc_malloc = malloc(NUM_TX_DESC * + sizeof(struct tx_desc_s) + + TX_DESC_SIZE - 1))) { + printf("Error: malloc failed\n"); + return -ENOMEM; + } + tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & + ~(TX_DESC_SIZE - 1)); + /* Make sure we use a P2 address (non-cacheable) */ + port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); + + port_info->tx_desc_cur = port_info->tx_desc_base; + + /* Initialize all descriptors */ + for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; + cur_tx_desc++, i++) { + cur_tx_desc->td0 = 0x00; + cur_tx_desc->td1 = 0x00; + cur_tx_desc->td2 = 0x00; + } + + /* Mark the end of the descriptors */ + cur_tx_desc--; + cur_tx_desc->td0 |= TD_TDLE; + + /* Point the controller to the tx descriptor list. Must use physical + addresses */ + outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); + outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); + outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); + outl(0x01, TDFFR(port));/* Last discriptor bit */ + + return 0; +} + +static int sh_eth_rx_desc_init(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + u32 tmp_addr; + struct rx_desc_s *cur_rx_desc; + u8 *rx_buf; + int i; + + /* Allocate rx descriptors. They must be RX_DESC_SIZE bytes + aligned */ + if (!(port_info->rx_desc_malloc = malloc(NUM_RX_DESC * + sizeof(struct rx_desc_s) + + RX_DESC_SIZE - 1))) { + printf("Error: malloc failed\n"); + return -ENOMEM; + } + tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & + ~(RX_DESC_SIZE - 1)); + /* Make sure we use a P2 address (non-cacheable) */ + port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); + + port_info->rx_desc_cur = port_info->rx_desc_base; + + /* Allocate rx data buffers. They must be 32 bytes aligned and in + P2 area */ + if (!(port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + + 31))) { + printf("Error: malloc failed\n"); + free(port_info->rx_desc_malloc); + port_info->rx_desc_malloc = NULL; + return -ENOMEM; + } + tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & + ~(32 - 1)); + port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); + + /* Initialize all descriptors */ + for (cur_rx_desc = port_info->rx_desc_base, + rx_buf = port_info->rx_buf_base, i = 0; + i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { + cur_rx_desc->rd0 = RD_RACT; + cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; + cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); + } + + /* Mark the end of the descriptors */ + cur_rx_desc--; + cur_rx_desc->rd0 |= RD_RDLE; + + /* Point the controller to the rx descriptor list */ + outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); + outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); + outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); + outl(RDFFR_RDLF, RDFFR(port)); + + return 0; +} + +static void sh_eth_desc_free(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + + if (port_info->tx_desc_malloc) { + free(port_info->tx_desc_malloc); + port_info->tx_desc_malloc = NULL; + } + + if (port_info->rx_desc_malloc) { + free(port_info->rx_desc_malloc); + port_info->rx_desc_malloc = NULL; + } + + if (port_info->rx_buf_malloc) { + free(port_info->rx_buf_malloc); + port_info->rx_buf_malloc = NULL; + } +} + +static int sh_eth_desc_init(struct dev_info_s *dev) +{ + int rc; + + if ((rc = sh_eth_tx_desc_init(dev)) || (rc = sh_eth_rx_desc_init(dev))) { + sh_eth_desc_free(dev); + return rc; + } + + return 0; +} + +static int sh_eth_phy_config(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + int timeout; + u32 val; + /* Reset phy */ + sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); + timeout = 10; + while (timeout--) { + val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, PHY_CTRL); + if (!(val & PHY_C_RESET)) + break; + udelay(50000); + } + if (timeout < 0) { + printf("%s phy reset timeout\n", __func__); + return -1; + } + + /* Advertise 100/10 baseT full/half duplex */ + sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, + (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); + /* Autonegotiation, normal operation, full duplex, enable tx */ + sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, + (PHY_C_ANEGEN|PHY_C_RANEG)); + /* Wait for autonegotiation to complete */ + timeout = 100; + while (timeout--) { + val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); + if (val & PHY_S_ANEGC) + break; + udelay(50000); + } + if (timeout < 0) { + printf("sh_eth_phy_config() phy auto-negotiation failed\n"); + return -1; + } + + return 0; +} + +static int sh_eth_config(struct dev_info_s *dev, bd_t * bd) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + u32 val; + u32 phy_status; + int rc; + + /* Configure e-dmac registers */ + outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); + outl(0, EESIPR(port)); + outl(0, TRSCER(port)); + outl(0, TFTR(port)); + outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); + outl(RMCR_RST, RMCR(port)); + outl(0, RPADIR(port)); + outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); + + /* Configure e-mac registers */ + outl(0, ECSIPR(port)); + + /* Set Mac address */ + val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 | + bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3]; + outl(val, MAHR(port)); + + val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5]; + outl(val, MALR(port)); + + outl(RFLR_RFL_MIN, RFLR(port)); + outl(0, PIPR(port)); + outl(APR_AP, APR(port)); + outl(MPR_MP, MPR(port)); + outl(TPAUSER_TPAUSE, TPAUSER(port)); + + /* Configure phy */ + if ((rc = sh_eth_phy_config(dev))) + return rc; + + /* Read phy status to finish configuring the e-mac */ + phy_status = sh_eth_mii_read_phy_reg(dev->port, + dev->port_info[dev->port].phy_addr, + 1); + + /* Set the transfer speed */ + if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { + printf("100Base/"); + outl(GECMR_100B, GECMR(port)); + } else { + printf("10Base/"); + outl(GECMR_10B, GECMR(port)); + } + + /* Check if full duplex mode is supported by the phy */ + if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { + printf("Full\n"); + outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); + } else { + printf("Half\n"); + outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); + } + return 0; +} + +static int sh_eth_start(struct dev_info_s *dev) +{ + /* + * Enable the e-dmac receiver only. The transmitter will be enabled when + * we have something to transmit + */ + outl(EDRRR_R, EDRRR(dev->port)); + + return 0; +} + +static int sh_eth_get_mac(bd_t *bd) +{ + char *s, *e; + int i; + + s = getenv("ethaddr"); + if (s != NULL) { + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } else { + puts("Please set MAC address\n"); + } + return 0; +} + +int eth_init(bd_t *bd) +{ + int rc; + /* Allocate main device information structure */ + if (!(dev = malloc(sizeof(*dev)))) { + printf("eth_init: malloc failed\n"); + return -ENOMEM; + } + + memset(dev, 0, sizeof(*dev)); + + dev->port = CONFIG_SH_ETHER_USE_PORT; + dev->port_info[dev->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; + + sh_eth_get_mac(bd); + + if ((rc = sh_eth_reset(dev)) || (rc = sh_eth_desc_init(dev))) + goto err; + + if ((rc = sh_eth_config(dev, bd)) || (rc = sh_eth_start(dev))) + goto err_desc; + + return 0; + +err_desc: + sh_eth_desc_free(dev); +err: + free(dev); + printf("eth_init: Failed\n"); + return rc; +} diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h new file mode 100644 index 0000000000..9cf0ea0b9e --- /dev/null +++ b/drivers/net/sh_eth.h @@ -0,0 +1,446 @@ +/* + * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler. + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (c) 2008 Nobuhiro Iwamatsu + * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <asm/types.h> + +#define SHETHER_NAME "sh_eth" + +/* Malloc returns addresses in the P1 area (cacheable). However we need to + use area P2 (non-cacheable) */ +#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) + +/* The ethernet controller needs to use physical addresses */ +#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) + +/* Number of supported ports */ +#define MAX_PORT_NUM 2 + +/* Buffers must be big enough to hold the largest ethernet frame. Also, rx + buffers must be a multiple of 32 bytes */ +#define MAX_BUF_SIZE (48 * 32) + +/* The number of tx descriptors must be large enough to point to 5 or more + frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. + We use one descriptor per frame */ +#define NUM_TX_DESC 8 + +/* The size of the tx descriptor is determined by how much padding is used. + 4, 20, or 52 bytes of padding can be used */ +#define TX_DESC_PADDING 4 +#define TX_DESC_SIZE (12 + TX_DESC_PADDING) + +/* Tx descriptor. We always use 4 bytes of padding */ +struct tx_desc_s { + volatile u32 td0; + u32 td1; + u32 td2; /* Buffer start */ + u32 padding; +}; + +/* There is no limitation in the number of rx descriptors */ +#define NUM_RX_DESC 8 + +/* The size of the rx descriptor is determined by how much padding is used. + 4, 20, or 52 bytes of padding can be used */ +#define RX_DESC_PADDING 4 +#define RX_DESC_SIZE (12 + RX_DESC_PADDING) + +/* Rx descriptor. We always use 4 bytes of padding */ +struct rx_desc_s { + volatile u32 rd0; + volatile u32 rd1; + u32 rd2; /* Buffer start */ + u32 padding; +}; + +struct port_info_s { + struct tx_desc_s *tx_desc_malloc; + struct tx_desc_s *tx_desc_base; + struct tx_desc_s *tx_desc_cur; + struct rx_desc_s *rx_desc_malloc; + struct rx_desc_s *rx_desc_base; + struct rx_desc_s *rx_desc_cur; + u8 *rx_buf_malloc; + u8 *rx_buf_base; + u8 mac_addr[6]; + u8 phy_addr; +}; + +struct dev_info_s { + int port; + struct port_info_s port_info[MAX_PORT_NUM]; +}; + +/* Register Address */ +#define BASE_IO_ADDR 0xfee00000 + +#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) + +#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) +#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) +#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) +#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) + +#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) +#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) +#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) +#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) + +#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) +#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) +#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) +#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) +#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) +#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) +#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) +#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) +#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) +#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) +#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) +#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) +#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) +#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) +#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) +#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) +#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) +#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) +#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) +#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) +#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) +#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) + +/* + * Register's bits + * Copy from Linux driver source code + */ +#ifdef CONFIG_CPU_SH7763 +/* EDSR */ +enum EDSR_BIT { + EDSR_ENT = 0x01, EDSR_ENR = 0x02, +}; +#define EDSR_ENALL (EDSR_ENT|EDSR_ENR) +#endif + +/* EDMR */ +enum DMAC_M_BIT { + EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, +#ifdef CONFIG_CPU_SH7763 + EDMR_SRST = 0x03, + EMDR_DESC_R = 0x30, /* Descriptor reserve size */ + EDMR_EL = 0x40, /* Litte endian */ +#else /* CONFIG_CPU_SH7763 */ + EDMR_SRST = 0x01, +#endif +}; + +/* RFLR */ +#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ + +/* EDTRR */ +enum DMAC_T_BIT { +#ifdef CONFIG_CPU_SH7763 + EDTRR_TRNS = 0x03, +#else + EDTRR_TRNS = 0x01, +#endif +}; + +/* GECMR */ +enum GECMR_BIT { + GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00, +}; + +/* EDRRR*/ +enum EDRRR_R_BIT { + EDRRR_R = 0x01, +}; + +/* TPAUSER */ +enum TPAUSER_BIT { + TPAUSER_TPAUSE = 0x0000ffff, + TPAUSER_UNLIMITED = 0, +}; + +/* BCFR */ +enum BCFR_BIT { + BCFR_RPAUSE = 0x0000ffff, + BCFR_UNLIMITED = 0, +}; + +/* PIR */ +enum PIR_BIT { + PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, +}; + +/* PSR */ +enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; + +/* EESR */ +enum EESR_BIT { +#ifndef CONFIG_CPU_SH7763 + EESR_TWB = 0x40000000, +#else + EESR_TWB = 0xC0000000, + EESR_TC1 = 0x20000000, + EESR_TUC = 0x10000000, + EESR_ROC = 0x80000000, +#endif + EESR_TABT = 0x04000000, + EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, +#ifndef CONFIG_CPU_SH7763 + EESR_ADE = 0x00800000, +#endif + EESR_ECI = 0x00400000, + EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, + EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, + EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, +#ifndef CONFIG_CPU_SH7763 + EESR_CND = 0x00000800, +#endif + EESR_DLC = 0x00000400, + EESR_CD = 0x00000200, EESR_RTO = 0x00000100, + EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, + EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, + rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, + EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, +}; + + +#ifdef CONFIG_CPU_SH7763 +# define TX_CHECK (EESR_TC1 | EESR_FTC) +# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ + | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) +# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) + +#else +# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) +# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ + | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) +# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) +#endif + +/* EESIPR */ +enum DMAC_IM_BIT { + DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, + DMAC_M_RABT = 0x02000000, + DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, + DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, + DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, + DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, + DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, + DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, + DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, + DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, + DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, + DMAC_M_RINT1 = 0x00000001, +}; + +/* Receive descriptor bit */ +enum RD_STS_BIT { + RD_RACT = 0x80000000, RD_RDLE = 0x40000000, + RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, + RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, + RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, + RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, + RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, + RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, + RD_RFS1 = 0x00000001, +}; +#define RDF1ST RD_RFP1 +#define RDFEND RD_RFP0 +#define RD_RFP (RD_RFP1|RD_RFP0) + +/* RDFFR*/ +enum RDFFR_BIT { + RDFFR_RDLF = 0x01, +}; + +/* FCFTR */ +enum FCFTR_BIT { + FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, + FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, + FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, +}; +#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) +#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) + +/* Transfer descriptor bit */ +enum TD_STS_BIT { +#ifdef CONFIG_CPU_SH7763 + TD_TACT = 0x80000000, +#else + TD_TACT = 0x7fffffff, +#endif + TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, + TD_TFP0 = 0x10000000, +}; +#define TDF1ST TD_TFP1 +#define TDFEND TD_TFP0 +#define TD_TFP (TD_TFP1|TD_TFP0) + +/* RMCR */ +enum RECV_RST_BIT { RMCR_RST = 0x01, }; +/* ECMR */ +enum FELIC_MODE_BIT { +#ifdef CONFIG_CPU_SH7763 + ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, + ECMR_RZPF = 0x00100000, +#endif + ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, + ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, + ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, + ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, + ECMR_PRM = 0x00000001, +}; + +#ifdef CONFIG_CPU_SH7763 +#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ + ECMR_TXF | ECMR_MCT) +#else +#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT) +#endif + +/* ECSR */ +enum ECSR_STATUS_BIT { +#ifndef CONFIG_CPU_SH7763 + ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, +#endif + ECSR_LCHNG = 0x04, + ECSR_MPD = 0x02, ECSR_ICD = 0x01, +}; + +#ifdef CONFIG_CPU_SH7763 +# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) +#else +# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ + ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) +#endif + +/* ECSIPR */ +enum ECSIPR_STATUS_MASK_BIT { +#ifndef CONFIG_CPU_SH7763 + ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, +#endif + ECSIPR_LCHNGIP = 0x04, + ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, +}; + +#ifdef CONFIG_CPU_SH7763 +# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) +#else +# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ + ECSIPR_ICDIP | ECSIPR_MPDIP) +#endif + +/* APR */ +enum APR_BIT { + APR_AP = 0x00000004, +}; + +/* MPR */ +enum MPR_BIT { + MPR_MP = 0x00000006, +}; + +/* TRSCER */ +enum DESC_I_BIT { + DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, + DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, + DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, + DESC_I_RINT1 = 0x0001, +}; + +/* RPADIR */ +enum RPADIR_BIT { + RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, + RPADIR_PADR = 0x0003f, +}; + +#ifdef CONFIG_CPU_SH7763 +# define RPADIR_INIT (0x00) +#else +# define RPADIR_INIT (RPADIR_PADS1) +#endif + +/* FDR */ +enum FIFO_SIZE_BIT { + FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, +}; + +enum PHY_OFFSETS { + PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, + PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6, + PHY_16 = 16, +}; + +/* PHY_CTRL */ +enum PHY_CTRL_BIT { + PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000, + PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400, + PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080, +}; +#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */ + +/* PHY_STAT */ +enum PHY_STAT_BIT { + PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000, + PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020, + PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004, + PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001, +}; + +/* PHY_ANA */ +enum PHY_ANA_BIT { + PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, + PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, + PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, + PHY_A_SEL = 0x001e, + PHY_A_EXT = 0x0001, +}; + +/* PHY_ANL */ +enum PHY_ANL_BIT { + PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000, + PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100, + PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020, + PHY_L_SEL = 0x001f, +}; + +/* PHY_ANE */ +enum PHY_ANE_BIT { + PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004, + PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001, +}; + +/* DM9161 */ +enum PHY_16_BIT { + PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000, + PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800, + PHY_16_TXselect = 0x0400, + PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100, + PHY_16_Force100LNK = 0x0080, + PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020, + PHY_16_RPDCTR_EN = 0x0010, + PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004, + PHY_16_Sleepmode = 0x0002, + PHY_16_RemoteLoopOut = 0x0001, +}; diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 8061f12979..e8b235b4ab 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -65,8 +65,6 @@ #include "smc91111.h" #include <net.h> -#ifdef CONFIG_DRIVER_SMC91111 - /* Use power-down feature of the chip */ #define POWER_DOWN 0 @@ -1620,4 +1618,3 @@ int get_rom_mac (uchar *v_rom_mac) return (valid_mac ? 1 : 0); #endif } -#endif /* CONFIG_DRIVER_SMC91111 */ diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 5302cb5223..1484b0b696 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -23,14 +23,17 @@ */ #include <common.h> - -#ifdef CONFIG_DRIVER_SMC911X - #include <command.h> #include <net.h> #include <miiphy.h> -#ifdef CONFIG_DRIVER_SMC911X_32_BIT +#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \ + defined (CONFIG_DRIVER_SMC911X_16_BIT) +#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \ + CONFIG_DRIVER_SMC911X_16_BIT shall be set" +#endif + +#if defined (CONFIG_DRIVER_SMC911X_32_BIT) static inline u32 reg_read(u32 addr) { return *(volatile u32*)addr; @@ -39,9 +42,20 @@ static inline void reg_write(u32 addr, u32 val) { *(volatile u32*)addr = val; } +#elif defined (CONFIG_DRIVER_SMC911X_16_BIT) +static inline u32 reg_read(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); +} +static inline void reg_write(u32 addr, u32 val) +{ + *(volatile u16*)addr = (u16)val; + *(volatile u16*)(addr + 2) = (u16)(val >> 16); +} #else -#error "SMC911X: Only 32-bit bus is supported" -#endif +#error "SMC911X: undefined bus width" +#endif /* CONFIG_DRIVER_SMC911X_16_BIT */ #define mdelay(n) udelay((n)*1000) @@ -583,7 +597,7 @@ int eth_init(bd_t *bd) val = reg_read(BYTE_TEST); if (val != 0x87654321) { - printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val); + printf(DRIVERNAME ": Invalid chip endian 0x%08x\n", val); goto err_out; } @@ -682,5 +696,3 @@ int eth_rx(void) return 0; } - -#endif /* CONFIG_DRIVER_SMC911X */ diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c index 5f6a4ecd0a..ab448b0f81 100644 --- a/drivers/net/tigon3.c +++ b/drivers/net/tigon3.c @@ -12,8 +12,7 @@ /******************************************************************************/ #include <common.h> #include <asm/types.h> -#if defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_TIGON3) + #ifdef CONFIG_BMW #include <mpc824x.h> #endif @@ -5695,5 +5694,3 @@ LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, } return LM_STATUS_SUCCESS; } - -#endif diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index c7af930b6b..6e0f2c6fd0 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -17,7 +17,6 @@ #include <net.h> #include <command.h> -#if defined(CONFIG_TSEC_ENET) #include "tsec.h" #include "miiphy.h" @@ -1128,6 +1127,36 @@ struct phy_info phy_info_M88E1111S = { }, }; +struct phy_info phy_info_M88E1118 = { + 0x01410e1, + "Marvell 88E1118", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x16, 0x0002, NULL}, /* Change Page Number */ + {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + {0x16, 0x0000, NULL}, /* Change Page Number */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, +}; + static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) { uint mii_data = read_phy_reg(priv, mii_reg); @@ -1492,6 +1521,7 @@ struct phy_info *phy_info[] = { &phy_info_BCM5464S, &phy_info_M88E1011S, &phy_info_M88E1111S, + &phy_info_M88E1118, &phy_info_M88E1145, &phy_info_M88E1149S, &phy_info_dm9161, @@ -1710,5 +1740,3 @@ tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) return 0; } #endif /* Multicast TFTP ? */ - -#endif /* CONFIG_TSEC_ENET */ diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c index a09115e6dd..57c0dc3cea 100644 --- a/drivers/net/tsi108_eth.c +++ b/drivers/net/tsi108_eth.c @@ -27,9 +27,6 @@ #include <config.h> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_TSI108_ETH) - #if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) #error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2" #endif @@ -1032,5 +1029,3 @@ static void tsi108_eth_halt (struct eth_device *dev) /* Put MAC into reset state. */ reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET; } - -#endif diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 79d29ae822..7145b72264 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -22,9 +22,6 @@ /* some kernel function compatible define */ -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_ULI526X) - #undef DEBUG /* Board/System/Debug information/definition */ @@ -993,4 +990,3 @@ static void set_mac_addr(struct eth_device *dev) udelay(10); return; } -#endif diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index 4095bce5bf..4e7259fd96 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -13,9 +13,6 @@ */ #include <config.h> - -#ifdef CONFIG_VSC7385_ENET - #include <common.h> #include <asm/io.h> #include <asm/errno.h> @@ -97,5 +94,3 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size) return 0; } - -#endif diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c index d5f11e42f0..4f02cb85e8 100644 --- a/drivers/pci/tsi108_pci.c +++ b/drivers/pci/tsi108_pci.c @@ -33,8 +33,9 @@ #include <pci.h> #include <asm/io.h> #include <tsi108.h> -#ifdef CONFIG_OF_FLAT_TREE -#include <ft_build.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <fdt_support.h> #endif struct pci_controller local_hose; @@ -162,20 +163,24 @@ void pci_init_board (void) return; } -#ifdef CONFIG_OF_FLAT_TREE -void -ft_pci_setup (void *blob, bd_t *bd) +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) { - u32 *p; - int len; - - p = (u32 *)ft_get_prop (blob, "/" OF_TSI "/pci@1000/bus-range", &len); - if (p != NULL) { - p[0] = local_hose.first_busno; - p[1] = local_hose.last_busno; + int nodeoffset; + int tmp[2]; + const char *path; + + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { + path = fdt_getprop(blob, nodeoffset, "pci", NULL); + if (path) { + tmp[0] = cpu_to_be32(local_hose.first_busno); + tmp[1] = cpu_to_be32(local_hose.last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + } } - } -#endif +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_TSI108_PCI */ diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index ac4378a0bd..ba251d0984 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -27,11 +27,11 @@ LIB := $(obj)libpcmcia.a COBJS-$(CONFIG_I82365) += i82365.o COBJS-y += mpc8xx_pcmcia.o -COBJS-y += pxa_pcmcia.o +COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o COBJS-y += rpx_pcmcia.o -COBJS-y += ti_pci1410a.o +COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o COBJS-y += tqm8xx_pcmcia.o -COBJS-y += marubun_pcmcia.o +COBJS-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c index a213092334..d075ba37cd 100644 --- a/drivers/pcmcia/marubun_pcmcia.c +++ b/drivers/pcmcia/marubun_pcmcia.c @@ -31,12 +31,11 @@ #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_CMD_IDE) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_MARUBUN_PCCARD)) +#if defined(CONFIG_PCMCIA) /* MR-SHPC-01 register */ #define MRSHPC_MODE (CFG_MARUBUN_MRSHPC + 4) @@ -112,4 +111,4 @@ int pcmcia_off (void) return 0; } -#endif /* CONFIG_MARUBUN_PCCARD */ +#endif /* CONFIG_PCMCIA */ diff --git a/drivers/pcmcia/pxa_pcmcia.c b/drivers/pcmcia/pxa_pcmcia.c index 65427efdbd..11d8590d7b 100644 --- a/drivers/pcmcia/pxa_pcmcia.c +++ b/drivers/pcmcia/pxa_pcmcia.c @@ -1,8 +1,6 @@ #include <common.h> #include <config.h> -#ifdef CONFIG_PXA_PCMCIA - #include <pcmcia.h> #include <asm/arch/pxa-regs.h> #include <asm/io.h> @@ -93,5 +91,3 @@ int pcmcia_off (void) return 0; } #endif - -#endif /* CONFIG_PXA_PCMCIA */ diff --git a/drivers/pcmcia/ti_pci1410a.c b/drivers/pcmcia/ti_pci1410a.c index 208ca50a74..c876d0c402 100644 --- a/drivers/pcmcia/ti_pci1410a.c +++ b/drivers/pcmcia/ti_pci1410a.c @@ -64,7 +64,7 @@ #include <pcmcia.h> -#if defined(CONFIG_CMD_PCMCIA) && defined(CONFIG_IDE_TI_CARDBUS) +#if defined(CONFIG_CMD_PCMCIA) int pcmcia_on(int ide_base_bus); @@ -662,4 +662,4 @@ static int identify(volatile uchar *p) return 0; /* don't know */ } -#endif /* CONFIG_IDE_TI_CARDBUS */ +#endif /* CONFIG_CMD_PCMCIA */ diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c index 1c8ac7f292..29854fc7c4 100644 --- a/drivers/rtc/ds1306.c +++ b/drivers/rtc/ds1306.c @@ -62,13 +62,6 @@ #define RTC_USER_RAM_BASE 0x20 -/* - * External table of chip select functions (see the appropriate board - * support for the actual definition of the table). - */ -extern spi_chipsel_type spi_chipsel[]; -extern int spi_chipsel_cnt; - static unsigned int bin2bcd (unsigned int n); static unsigned char bcd2bin (unsigned char c); @@ -305,11 +298,29 @@ void rtc_reset (void) static unsigned char rtc_read (unsigned char reg); static void rtc_write (unsigned char reg, unsigned char val); +static struct spi_slave *slave; + /* read clock time from DS1306 and return it in *tmp */ int rtc_get (struct rtc_time *tmp) { unsigned char sec, min, hour, mday, wday, mon, year; + /* + * Assuming Vcc = 2.0V (lowest speed) + * + * REVISIT: If we add an rtc_init() function we can do this + * step just once. + */ + if (!slave) { + slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, + SPI_MODE_3 | SPI_CS_HIGH); + if (!slave) + return; + } + + if (spi_claim_bus(slave)) + return; + sec = rtc_read (RTC_SECONDS); min = rtc_read (RTC_MINUTES); hour = rtc_read (RTC_HOURS); @@ -318,6 +329,8 @@ int rtc_get (struct rtc_time *tmp) mon = rtc_read (RTC_MONTH); year = rtc_read (RTC_YEAR); + spi_release_bus(slave); + debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " "hr: %02x min: %02x sec: %02x\n", year, mon, mday, wday, hour, min, sec); @@ -360,6 +373,17 @@ int rtc_get (struct rtc_time *tmp) /* set clock time from *tmp in DS1306 RTC */ void rtc_set (struct rtc_time *tmp) { + /* Assuming Vcc = 2.0V (lowest speed) */ + if (!slave) { + slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, + SPI_MODE_3 | SPI_CS_HIGH); + if (!slave) + return; + } + + if (spi_claim_bus(slave)) + return; + debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); @@ -371,6 +395,8 @@ void rtc_set (struct rtc_time *tmp) rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); + + spi_release_bus(slave); } /* ------------------------------------------------------------------------- */ @@ -378,6 +404,17 @@ void rtc_set (struct rtc_time *tmp) /* reset the DS1306 */ void rtc_reset (void) { + /* Assuming Vcc = 2.0V (lowest speed) */ + if (!slave) { + slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, + SPI_MODE_3 | SPI_CS_HIGH); + if (!slave) + return; + } + + if (spi_claim_bus(slave)) + return; + /* clear the control register */ rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ @@ -391,22 +428,18 @@ void rtc_reset (void) rtc_write (RTC_HOURS_ALARM1, 0x00); rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); + + spi_release_bus(slave); } /* ------------------------------------------------------------------------- */ static unsigned char rtc_read (unsigned char reg) { - unsigned char dout[2]; /* SPI Output Data Bytes */ - unsigned char din[2]; /* SPI Input Data Bytes */ - - dout[0] = reg; + int ret; - if (spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din) != 0) { - return 0; - } else { - return din[1]; - } + ret = spi_w8r8(slave, reg); + return ret < 0 ? 0 : ret; } /* ------------------------------------------------------------------------- */ @@ -419,7 +452,7 @@ static void rtc_write (unsigned char reg, unsigned char val) dout[0] = 0x80 | reg; dout[1] = val; - spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din); + spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); } #endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c index 35b1b8b254..b6e15014bb 100644 --- a/drivers/rtc/mc13783-rtc.c +++ b/drivers/rtc/mc13783-rtc.c @@ -24,34 +24,50 @@ #include <rtc.h> #include <spi.h> +static struct spi_slave *slave; + int rtc_get(struct rtc_time *rtc) { u32 day1, day2, time; u32 reg; int err, tim, i = 0; - spi_select(1, 0, SPI_MODE_2 | SPI_CS_HIGH); + if (!slave) { + /* FIXME: Verify the max SCK rate */ + slave = spi_setup_slave(1, 0, 1000000, + SPI_MODE_2 | SPI_CS_HIGH); + if (!slave) + return -1; + } + + if (spi_claim_bus(slave)) + return -1; do { reg = 0x2c000000; - err = spi_xfer(0, 32, (uchar *)®, (uchar *)&day1); + err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1, + SPI_XFER_BEGIN | SPI_XFER_END); if (err) return err; reg = 0x28000000; - err = spi_xfer(0, 32, (uchar *)®, (uchar *)&time); + err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time, + SPI_XFER_BEGIN | SPI_XFER_END); if (err) return err; reg = 0x2c000000; - err = spi_xfer(0, 32, (uchar *)®, (uchar *)&day2); + err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2, + SPI_XFER_BEGIN | SPI_XFER_END); if (err) return err; } while (day1 != day2 && i++ < 3); + spi_release_bus(slave); + tim = day1 * 86400 + time; to_tm(tim, rtc); @@ -65,16 +81,31 @@ void rtc_set(struct rtc_time *rtc) { u32 time, day, reg; + if (!slave) { + /* FIXME: Verify the max SCK rate */ + slave = spi_setup_slave(1, 0, 1000000, + SPI_MODE_2 | SPI_CS_HIGH); + if (!slave) + return; + } + time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday, rtc->tm_hour, rtc->tm_min, rtc->tm_sec); day = time / 86400; time %= 86400; + if (spi_claim_bus(slave)) + return; + reg = 0x2c000000 | day | 0x80000000; - spi_xfer(0, 32, (uchar *)®, (uchar *)&day); + spi_xfer(slave, 32, (uchar *)®, (uchar *)&day, + SPI_XFER_BEGIN | SPI_XFER_END); reg = 0x28000000 | time | 0x80000000; - spi_xfer(0, 32, (uchar *)®, (uchar *)&time); + spi_xfer(slave, 32, (uchar *)®, (uchar *)&time, + SPI_XFER_BEGIN | SPI_XFER_END); + + spi_release_bus(slave); } void rtc_reset(void) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 76425d8790..182ca2d149 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -144,8 +144,13 @@ static int calc_divisor (NS16550_t port) #else #define MODE_X_DIV 16 #endif - return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate); + /* Compute divisor value. Normally, we should simply return: + * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate + * but we need to round that value by adding 0.5 or 8/16. + * Rounding is especially important at high baud rates. + */ + return (((16 * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate) + 8) / 16; } #if !defined(CONFIG_SERIAL_MULTI) diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c index 417b6aeda6..134ed0967f 100644 --- a/drivers/serial/serial_pl010.c +++ b/drivers/serial/serial_pl010.c @@ -29,6 +29,7 @@ /* Should be fairly simple to make it work with the PL010 as well */ #include <common.h> +#include <watchdog.h> #ifdef CFG_PL010_SERIAL @@ -137,7 +138,8 @@ void serial_setbrg (void) static void pl010_putc (int portnum, char c) { /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) + WATCHDOG_RESET(); /* Send the character */ IO_WRITE (port[portnum] + UART_PL01x_DR, c); @@ -148,7 +150,8 @@ static int pl010_getc (int portnum) unsigned int data; /* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) + WATCHDOG_RESET(); data = IO_READ (port[portnum] + UART_PL01x_DR); @@ -164,6 +167,7 @@ static int pl010_getc (int portnum) static int pl010_tstc (int portnum) { + WATCHDOG_RESET(); return !(IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); } diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index aa4ff35333..0801ac4a8c 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -26,6 +26,8 @@ #define SCIF_BASE SCIF0_BASE #elif defined (CONFIG_CONS_SCIF1) #define SCIF_BASE SCIF1_BASE +#elif defined (CONFIG_CONS_SCIF2) +#define SCIF_BASE SCIF2_BASE #else #error "Default SCIF doesn't set....." #endif @@ -36,17 +38,17 @@ #define SCSCR (vu_short *)(SCIF_BASE + 0x8) #define SCFCR (vu_short *)(SCIF_BASE + 0x18) #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) -#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ -# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ +#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ +# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ # define SCFTDR (vu_char *)(SCIF_BASE + 0x20) # define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else # define SCFTDR (vu_char *)(SCIF_BASE + 0xC) -# define SCFSR (vu_short *)(SCIF_BASE + 0x10) +# define SCFSR (vu_short *)(SCIF_BASE + 0x10) # define SCFRDR (vu_char *)(SCIF_BASE + 0x14) #endif -#if defined(CONFIG_CPU_SH7780) || \ +#if defined(CONFIG_CPU_SH7780) || \ defined(CONFIG_CPU_SH7785) # define SCRFDR (vu_short *)(SCIF_BASE + 0x20) # define SCSPTR (vu_short *)(SCIF_BASE + 0x24) @@ -54,20 +56,34 @@ # define SCRER (vu_short *)(SCIF_BASE + 0x2C) # define LSR_ORER 1 # define FIFOLEVEL_MASK 0xFF +#elif defined(CONFIG_CPU_SH7763) +# if defined (CONFIG_CONS_SCIF2) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F +# else +# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x28) +# define SCRER (vu_short *)(SCIF_BASE + 0x2C) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0xFF +# endif #elif defined(CONFIG_CPU_SH7750) || \ defined(CONFIG_CPU_SH7751) || \ defined(CONFIG_CPU_SH7722) # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define LSR_ORER 1 # define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7720) -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define LSR_ORER 0x0200 # define FIFOLEVEL_MASK 0x1F -#elif defined(CONFIG_CPU_SH7710) +#elif defined(CONFIG_CPU_SH7710) || \ defined(CONFIG_CPU_SH7712) -# define SCLSR SCFSR /* SCSSR */ +# define SCLSR SCFSR /* SCSSR */ # define LSR_ORER 1 # define FIFOLEVEL_MASK 0x1F #endif @@ -75,34 +91,34 @@ /* SCBRR register value setting */ #if defined(CONFIG_CPU_SH7720) # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) -#else /* Generic SuperH */ +#else /* Generic SuperH */ # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif -#define SCR_RE (1 << 4) -#define SCR_TE (1 << 5) -#define FCR_RFRST (1 << 1) /* RFCL */ -#define FCR_TFRST (1 << 2) /* TFCL */ -#define FSR_DR (1 << 0) -#define FSR_RDF (1 << 1) -#define FSR_FER (1 << 3) -#define FSR_BRK (1 << 4) -#define FSR_FER (1 << 3) -#define FSR_TEND (1 << 6) -#define FSR_ER (1 << 7) +#define SCR_RE (1 << 4) +#define SCR_TE (1 << 5) +#define FCR_RFRST (1 << 1) /* RFCL */ +#define FCR_TFRST (1 << 2) /* TFCL */ +#define FSR_DR (1 << 0) +#define FSR_RDF (1 << 1) +#define FSR_FER (1 << 3) +#define FSR_BRK (1 << 4) +#define FSR_FER (1 << 3) +#define FSR_TEND (1 << 6) +#define FSR_ER (1 << 7) /*----------------------------------------------------------------------*/ -void serial_setbrg (void) +void serial_setbrg(void) { DECLARE_GLOBAL_DATA_PTR; - *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ); + *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ); } -int serial_init (void) +int serial_init(void) { *SCSCR = (SCR_RE | SCR_TE); - *SCSMR = 0 ; + *SCSMR = 0; *SCSMR = 0; *SCFCR = (FCR_RFRST | FCR_TFRST); *SCFCR; @@ -112,21 +128,21 @@ int serial_init (void) return 0; } -static int serial_rx_fifo_level (void) +static int serial_rx_fifo_level(void) { -#if defined(CONFIG_SH4A) +#if defined(SCRFDR) return (*SCRFDR >> 0) & FIFOLEVEL_MASK; #else return (*SCFDR >> 0) & FIFOLEVEL_MASK; #endif } -void serial_raw_putc (const char c) +void serial_raw_putc(const char c) { unsigned int fsr_bits_to_clear; while (1) { - if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ + if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ fsr_bits_to_clear = FSR_TEND; break; } @@ -137,65 +153,67 @@ void serial_raw_putc (const char c) *SCFSR &= ~fsr_bits_to_clear; } -void serial_putc (const char c) +void serial_putc(const char c) { if (c == '\n') - serial_raw_putc ('\r'); - serial_raw_putc (c); + serial_raw_putc('\r'); + serial_raw_putc(c); } -void serial_puts (const char *s) +void serial_puts(const char *s) { char c; while ((c = *s++) != 0) - serial_putc (c); + serial_putc(c); } -int serial_tstc (void) +int serial_tstc(void) { - return serial_rx_fifo_level() ? 1 : 0; + return serial_rx_fifo_level()? 1 : 0; } -#define FSR_ERR_CLEAR 0x0063 -#define RDRF_CLEAR 0x00fc -void handle_error( void ){ +#define FSR_ERR_CLEAR 0x0063 +#define RDRF_CLEAR 0x00fc +void handle_error(void) +{ - (void)*SCFSR ; - *SCFSR = FSR_ERR_CLEAR ; - (void)*SCLSR ; - *SCLSR = 0x00 ; + (void)*SCFSR; + *SCFSR = FSR_ERR_CLEAR; + (void)*SCLSR; + *SCLSR = 0x00; } -int serial_getc_check( void ){ +int serial_getc_check(void) +{ unsigned short status; - status = *SCFSR ; + status = *SCFSR; - if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) + if (status & (FSR_FER | FSR_ER | FSR_BRK)) handle_error(); - if( *SCLSR & LSR_ORER ) + if (*SCLSR & LSR_ORER) handle_error(); - return (status & ( FSR_DR | FSR_RDF )); + return (status & (FSR_DR | FSR_RDF)); } -int serial_getc (void) +int serial_getc(void) { - unsigned short status ; + unsigned short status; char ch; - while(!serial_getc_check()); + while (!serial_getc_check()) ; ch = *SCFRDR; - status = *SCFSR ; + status = *SCFSR; - *SCFSR = RDRF_CLEAR ; + *SCFSR = RDRF_CLEAR; if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) handle_error(); - if( *SCLSR & LSR_ORER ) + if (*SCLSR & LSR_ORER) handle_error(); - return ch ; + return ch; } -#endif /* CFG_SCIF_CONSOLE */ +#endif /* CFG_SCIF_CONSOLE */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index bc8a104121..4f7b679eeb 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a -COBJS-y += mpc8xxx_spi.o +COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS := $(COBJS-y) diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c new file mode 100644 index 0000000000..317c0b41b6 --- /dev/null +++ b/drivers/spi/atmel_spi.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <spi.h> +#include <malloc.h> + +#include <asm/io.h> + +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> + +#include "atmel_spi.h" + +void spi_init() +{ + +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct atmel_spi_slave *as; + unsigned int scbr; + u32 csrx; + void *regs; + + if (cs > 3 || !spi_cs_is_valid(bus, cs)) + return NULL; + + switch (bus) { + case 0: + regs = (void *)SPI0_BASE; + break; +#ifdef SPI1_BASE + case 1: + regs = (void *)SPI1_BASE; + break; +#endif +#ifdef SPI2_BASE + case 2: + regs = (void *)SPI2_BASE; + break; +#endif +#ifdef SPI3_BASE + case 3: + regs = (void *)SPI3_BASE; + break; +#endif + default: + return NULL; + } + + + scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; + if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) + /* Too low max SCK rate */ + return NULL; + if (scbr < 1) + scbr = 1; + + csrx = ATMEL_SPI_CSRx_SCBR(scbr); + csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); + if (!(mode & SPI_CPHA)) + csrx |= ATMEL_SPI_CSRx_NCPHA; + if (mode & SPI_CPOL) + csrx |= ATMEL_SPI_CSRx_CPOL; + + as = malloc(sizeof(struct atmel_spi_slave)); + if (!as) + return NULL; + + as->slave.bus = bus; + as->slave.cs = cs; + as->regs = regs; + as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS + | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); + spi_writel(as, CSR(cs), csrx); + + return &as->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct atmel_spi_slave *as = to_atmel_spi(slave); + + free(as); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct atmel_spi_slave *as = to_atmel_spi(slave); + + /* Enable the SPI hardware */ + spi_writel(as, CR, ATMEL_SPI_CR_SPIEN); + + /* + * Select the slave. This should set SCK to the correct + * initial state, etc. + */ + spi_writel(as, MR, as->mr); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct atmel_spi_slave *as = to_atmel_spi(slave); + + /* Disable the SPI hardware */ + spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct atmel_spi_slave *as = to_atmel_spi(slave); + unsigned int len_tx; + unsigned int len_rx; + unsigned int len; + int ret; + u32 status; + const u8 *txp = dout; + u8 *rxp = din; + u8 value; + + ret = 0; + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + /* + * The controller can do automatic CS control, but it is + * somewhat quirky, and it doesn't really buy us much anyway + * in the context of U-Boot. + */ + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + for (len_tx = 0, len_rx = 0; len_rx < len; ) { + status = spi_readl(as, SR); + + if (status & ATMEL_SPI_SR_OVRES) + return -1; + + if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) { + if (txp) + value = *txp++; + else + value = 0; + spi_writel(as, TDR, value); + len_tx++; + } + if (status & ATMEL_SPI_SR_RDRF) { + value = spi_readl(as, RDR); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) { + /* + * Wait until the transfer is completely done before + * we deactivate CS. + */ + do { + status = spi_readl(as, SR); + } while (!(status & ATMEL_SPI_SR_TXEMPTY)); + + spi_cs_deactivate(slave); + } + + return 0; +} diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h new file mode 100644 index 0000000000..8b69a6d215 --- /dev/null +++ b/drivers/spi/atmel_spi.h @@ -0,0 +1,95 @@ +/* + * Register definitions for the Atmel AT32/AT91 SPI Controller + */ + +/* Register offsets */ +#define ATMEL_SPI_CR 0x0000 +#define ATMEL_SPI_MR 0x0004 +#define ATMEL_SPI_RDR 0x0008 +#define ATMEL_SPI_TDR 0x000c +#define ATMEL_SPI_SR 0x0010 +#define ATMEL_SPI_IER 0x0014 +#define ATMEL_SPI_IDR 0x0018 +#define ATMEL_SPI_IMR 0x001c +#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x)) +#define ATMEL_SPI_VERSION 0x00fc + +/* Bits in CR */ +#define ATMEL_SPI_CR_SPIEN (1 << 0) +#define ATMEL_SPI_CR_SPIDIS (1 << 1) +#define ATMEL_SPI_CR_SWRST (1 << 7) +#define ATMEL_SPI_CR_LASTXFER (1 << 24) + +/* Bits in MR */ +#define ATMEL_SPI_MR_MSTR (1 << 0) +#define ATMEL_SPI_MR_PS (1 << 1) +#define ATMEL_SPI_MR_PCSDEC (1 << 2) +#define ATMEL_SPI_MR_FDIV (1 << 3) +#define ATMEL_SPI_MR_MODFDIS (1 << 4) +#define ATMEL_SPI_MR_LLB (1 << 7) +#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) +#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) + +/* Bits in RDR */ +#define ATMEL_SPI_RDR_RD(x) (x) +#define ATMEL_SPI_RDR_PCS(x) ((x) << 16) + +/* Bits in TDR */ +#define ATMEL_SPI_TDR_TD(x) (x) +#define ATMEL_SPI_TDR_PCS(x) ((x) << 16) +#define ATMEL_SPI_TDR_LASTXFER (1 << 24) + +/* Bits in SR/IER/IDR/IMR */ +#define ATMEL_SPI_SR_RDRF (1 << 0) +#define ATMEL_SPI_SR_TDRE (1 << 1) +#define ATMEL_SPI_SR_MODF (1 << 2) +#define ATMEL_SPI_SR_OVRES (1 << 3) +#define ATMEL_SPI_SR_ENDRX (1 << 4) +#define ATMEL_SPI_SR_ENDTX (1 << 5) +#define ATMEL_SPI_SR_RXBUFF (1 << 6) +#define ATMEL_SPI_SR_TXBUFE (1 << 7) +#define ATMEL_SPI_SR_NSSR (1 << 8) +#define ATMEL_SPI_SR_TXEMPTY (1 << 9) +#define ATMEL_SPI_SR_SPIENS (1 << 16) + +/* Bits in CSRx */ +#define ATMEL_SPI_CSRx_CPOL (1 << 0) +#define ATMEL_SPI_CSRx_NCPHA (1 << 1) +#define ATMEL_SPI_CSRx_CSAAT (1 << 3) +#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) +#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) +#define ATMEL_SPI_CSRx_SCBR_MAX 0xff +#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) +#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24) + +/* Bits in VERSION */ +#define ATMEL_SPI_VERSION_REV(x) ((x) << 0) +#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16) + +/* Constants for CSRx:BITS */ +#define ATMEL_SPI_BITS_8 0 +#define ATMEL_SPI_BITS_9 1 +#define ATMEL_SPI_BITS_10 2 +#define ATMEL_SPI_BITS_11 3 +#define ATMEL_SPI_BITS_12 4 +#define ATMEL_SPI_BITS_13 5 +#define ATMEL_SPI_BITS_14 6 +#define ATMEL_SPI_BITS_15 7 +#define ATMEL_SPI_BITS_16 8 + +struct atmel_spi_slave { + struct spi_slave slave; + void *regs; + u32 mr; +}; + +static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) +{ + return container_of(slave, struct atmel_spi_slave, slave); +} + +/* Register access macros */ +#define spi_readl(as, reg) \ + readl(as->regs + ATMEL_SPI_##reg) +#define spi_writel(as, reg, value) \ + writel(value, as->regs + ATMEL_SPI_##reg) diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 2fe838c45d..9eaf9860b4 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -22,8 +22,8 @@ */ #include <common.h> -#if defined(CONFIG_MPC8XXX_SPI) && defined(CONFIG_HARD_SPI) +#include <malloc.h> #include <spi.h> #include <asm/mpc8xxx_spi.h> @@ -37,6 +37,34 @@ #define SPI_TIMEOUT 1000 +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* + * TODO: Some of the code in spi_init() should probably move + * here, or into spi_claim_bus() below. + */ + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + void spi_init(void) { volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi; @@ -53,7 +81,18 @@ void spi_init(void) spi->com = 0; /* LST bit doesn't do anything, so disregard */ } -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) { volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi; unsigned int tmpdout, tmpdin, event; @@ -61,11 +100,11 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) int tm, isRead = 0; unsigned char charSize = 32; - debug("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", - (int)chipsel, *(uint *) dout, *(uint *) din, bitlen); + debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen); - if (chipsel != NULL) - (*chipsel) (1); /* select the target chip */ + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); spi->event = 0xffffffff; /* Clear all SPI events */ @@ -135,9 +174,8 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin); } - if (chipsel != NULL) - (*chipsel) (0); /* deselect the target chip */ + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); return 0; } -#endif /* CONFIG_HARD_SPI */ diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index c166ec5023..5957ada3a4 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -19,6 +19,7 @@ */ #include <common.h> +#include <malloc.h> #include <spi.h> #include <asm/io.h> @@ -61,17 +62,18 @@ static unsigned long spi_bases[] = { 0x53f84000, }; -static unsigned long spi_base; - #endif -spi_chipsel_type spi_chipsel[] = { - (spi_chipsel_type)0, - (spi_chipsel_type)1, - (spi_chipsel_type)2, - (spi_chipsel_type)3, +struct mxc_spi_slave { + struct spi_slave slave; + unsigned long base; + u32 ctrl_reg; }; -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct mxc_spi_slave, slave); +} static inline u32 reg_read(unsigned long addr) { @@ -83,30 +85,31 @@ static inline void reg_write(unsigned long addr, u32 val) *(volatile unsigned long*)addr = val; } -static u32 spi_xchg_single(u32 data, int bitlen) +static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen) { - - unsigned int cfg_reg = reg_read(spi_base + MXC_CSPICTRL); + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL); if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) { cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | MXC_CSPICTRL_BITCOUNT(bitlen - 1); - reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg); } - reg_write(spi_base + MXC_CSPITXDATA, data); + reg_write(mxcs->base + MXC_CSPITXDATA, data); cfg_reg |= MXC_CSPICTRL_XCH; - reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg); - while (reg_read(spi_base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) + while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) ; - return reg_read(spi_base + MXC_CSPIRXDATA); + return reg_read(mxcs->base + MXC_CSPIRXDATA); } -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) { int n_blks = (bitlen + 31) / 32; u32 *out_l, *in_l; @@ -117,13 +120,10 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) return 1; } - if (!spi_base) - spi_select(CONFIG_MXC_SPI_IFACE, (int)chipsel, SPI_MODE_2 | SPI_CS_HIGH); - for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; i < n_blks; i++, in_l++, out_l++, bitlen -= 32) - *in_l = spi_xchg_single(*out_l, bitlen); + *in_l = spi_xchg_single(slave, *out_l, bitlen); return 0; } @@ -132,17 +132,17 @@ void spi_init(void) { } -int spi_select(unsigned int bus, unsigned int dev, unsigned long mode) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { unsigned int ctrl_reg; + struct mxc_spi_slave *mxcs; if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) || - dev > 3) - return 1; - - spi_base = spi_bases[bus]; + cs > 3) + return NULL; - ctrl_reg = MXC_CSPICTRL_CHIPSELECT(dev) | + ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | MXC_CSPICTRL_BITCOUNT(31) | MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ MXC_CSPICTRL_EN | @@ -155,12 +155,38 @@ int spi_select(unsigned int bus, unsigned int dev, unsigned long mode) if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; - reg_write(spi_base + MXC_CSPIRESET, 1); + mxcs = malloc(sizeof(struct mxc_spi_slave)); + if (!mxcs) + return NULL; + + mxcs->slave.bus = bus; + mxcs->slave.cs = cs; + mxcs->base = spi_bases[bus]; + mxcs->ctrl_reg = ctrl_reg; + + return &mxcs->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + + reg_write(mxcs->base + MXC_CSPIRESET, 1); udelay(1); - reg_write(spi_base + MXC_CSPICTRL, ctrl_reg); - reg_write(spi_base + MXC_CSPIPERIOD, + reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); + reg_write(mxcs->base + MXC_CSPIPERIOD, MXC_CSPIPERIOD_32KHZ); - reg_write(spi_base + MXC_CSPIINT, 0); + reg_write(mxcs->base + MXC_CSPIINT, 0); return 0; } + +void spi_release_bus(struct spi_slave *slave) +{ + /* TODO: Shut the controller down */ +} diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 9d2f65b7f8..20a54c54df 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libvideo.a COBJS-y += ati_radeon_fb.o +COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-y += cfb_console.o COBJS-y += ct69000.o COBJS-y += mb862xx.o diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c new file mode 100644 index 0000000000..27df449660 --- /dev/null +++ b/drivers/video/atmel_lcdfb.c @@ -0,0 +1,160 @@ +/* + * Driver for AT91/AT32 LCD Controller + * + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <lcd.h> +#include <atmel_lcdc.h> + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + +/* configurable parameters */ +#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 +#define ATMEL_LCDC_DMA_BURST_LEN 8 + +#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9) +#define ATMEL_LCDC_FIFO_SIZE 2048 +#else +#define ATMEL_LCDC_FIFO_SIZE 512 +#endif + +#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg)) +#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg)) + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +#if defined(CONFIG_ATMEL_LCD_BGR555) + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), + (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7)); +#else + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), + (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8)); +#endif +} + +void lcd_ctrl_init(void *lcdbase) +{ + unsigned long value; + + /* Turn off the LCD controller and the DMA controller */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, + 1 << ATMEL_LCDC_GUARDT_OFFSET); + + /* Wait for the LCDC core to become idle */ + while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) + udelay(10); + + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0); + + /* Reset LCDC DMA */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST); + + /* ...set frame size and burst length = 8 words (?) */ + value = (panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 32; + value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value); + + /* Set pixel clock */ + value = get_lcdc_clk_rate(0) / panel_info.vl_clk; + if (get_lcdc_clk_rate(0) % panel_info.vl_clk) + value++; + value = (value / 2) - 1; + + if (!value) { + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); + } else + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, + value << ATMEL_LCDC_CLKVAL_OFFSET); + + /* Initialize control register 2 */ + value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; + if (panel_info.vl_tft) + value |= ATMEL_LCDC_DISTYPE_TFT; + + if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED)) + value |= ATMEL_LCDC_INVLINE_INVERTED; + if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED)) + value |= ATMEL_LCDC_INVFRAME_INVERTED; + value |= (panel_info.vl_bpix << 5); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value); + + /* Vertical timing */ + value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET; + value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET; + value |= panel_info.vl_lower_margin; + lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value); + + /* Horizontal timing */ + value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET; + value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET; + value |= (panel_info.vl_left_margin - 1); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value); + + /* Display size */ + value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET; + value |= panel_info.vl_row - 1; + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value); + + /* FIFO Threshold: Use formula from data sheet */ + value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value); + + /* Toggle LCD_MODE every frame */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0); + + /* Disable all interrupts */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL); + + /* Set contrast */ + value = ATMEL_LCDC_PS_DIV8 | + ATMEL_LCDC_POL_POSITIVE | + ATMEL_LCDC_ENA_PWMENABLE; + lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); + + /* Set framebuffer DMA base address and pixel offset */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase); + + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, + (1 << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); +} + +ulong calc_fbsize(void) +{ + return ((panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; +} diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 1993dc2359..d1423c1cda 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -116,6 +116,7 @@ #include <malloc.h> #include <linux/stat.h> #include <linux/time.h> +#include <watchdog.h> #if defined(CONFIG_CMD_JFFS2) @@ -164,9 +165,6 @@ static struct part_info *current_part; /* this one defined in nand_legacy.c */ int read_jffs2_nand(size_t start, size_t len, size_t * retlen, u_char * buf, int nanddev); -#else -/* info for NAND chips, defined in drivers/mtd/nand/nand.c */ -extern nand_info_t nand_info[]; #endif #define NAND_PAGE_SIZE 512 @@ -1188,6 +1186,8 @@ jffs2_1pass_build_lists(struct part_info * part) oldoffset = offset; } + WATCHDOG_RESET(); + node = (struct jffs2_unknown_node *) get_node_mem((u32)part->offset + offset); if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) { /* if its a fragment add it */ diff --git a/include/ACEX1K.h b/include/ACEX1K.h index 6ea0eed952..354e0f0e47 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -77,6 +77,8 @@ typedef struct { #endif #define Altera_EP1K100_SIZE (166965*8) +#define Altera_EP2C8_SIZE 247942 +#define Altera_EP2C20_SIZE 586562 #define Altera_EP2C35_SIZE 883905 /* Descriptor Macros diff --git a/include/asm-arm/arch-at91sam9/at91_pmc.h b/include/asm-arm/arch-at91sam9/at91_pmc.h index 103be86999..b57875d798 100644 --- a/include/asm-arm/arch-at91sam9/at91_pmc.h +++ b/include/asm-arm/arch-at91sam9/at91_pmc.h @@ -96,4 +96,9 @@ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ +#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ + +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ + #endif diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91sam9/at91cap9.h index d1b33a069a..0b52228138 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9.h +++ b/include/asm-arm/arch-at91sam9/at91cap9.h @@ -101,13 +101,25 @@ #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS) #define AT91_USART0 AT91CAP9_BASE_US0 #define AT91_USART1 AT91CAP9_BASE_US1 #define AT91_USART2 AT91CAP9_BASE_US2 /* + * SCKCR flags + */ +#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ +#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ +#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ +#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ +#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) +#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) + +/* * Internal Memory. */ #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ diff --git a/include/asm-arm/arch-at91sam9/at91sam9261.h b/include/asm-arm/arch-at91sam9/at91sam9261.h new file mode 100644 index 0000000000..752d81dfe3 --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9261.h @@ -0,0 +1,105 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] + * + * Copyright (C) SAN People + * + * Common definitions. + * Based on AT91SAM9261 datasheet revision E. (Preliminary) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9261_H +#define AT91SAM9261_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9261_ID_US0 6 /* USART 0 */ +#define AT91SAM9261_ID_US1 7 /* USART 1 */ +#define AT91SAM9261_ID_US2 8 /* USART 2 */ +#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9261_ID_UHP 20 /* USB Host port */ +#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ +#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9261_BASE_TCB0 0xfffa0000 +#define AT91SAM9261_BASE_TC0 0xfffa0000 +#define AT91SAM9261_BASE_TC1 0xfffa0040 +#define AT91SAM9261_BASE_TC2 0xfffa0080 +#define AT91SAM9261_BASE_UDP 0xfffa4000 +#define AT91SAM9261_BASE_MCI 0xfffa8000 +#define AT91SAM9261_BASE_TWI 0xfffac000 +#define AT91SAM9261_BASE_US0 0xfffb0000 +#define AT91SAM9261_BASE_US1 0xfffb4000 +#define AT91SAM9261_BASE_US2 0xfffb8000 +#define AT91SAM9261_BASE_SSC0 0xfffbc000 +#define AT91SAM9261_BASE_SSC1 0xfffc0000 +#define AT91SAM9261_BASE_SSC2 0xfffc4000 +#define AT91SAM9261_BASE_SPI0 0xfffc8000 +#define AT91SAM9261_BASE_SPI1 0xfffcc000 +#define AT91_BASE_SYS 0xffffea00 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9261_BASE_US0 +#define AT91_USART1 AT91SAM9261_BASE_US1 +#define AT91_USART2 AT91SAM9261_BASE_US2 + + +/* + * Internal Memory. + */ +#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ + +#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ +#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ + + +#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h new file mode 100644 index 0000000000..e2bfc4b0c9 --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h @@ -0,0 +1,64 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] + * + * Copyright (C) 2007 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9261_MATRIX_H +#define AT91SAM9261_MATRIX_H + +#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ + +#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_ITCM_64 (7 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_DTCM_64 (7 << 4) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ + +#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ +#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ + +#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam9263.h b/include/asm-arm/arch-at91sam9/at91sam9263.h new file mode 100644 index 0000000000..98251cbeee --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9263.h @@ -0,0 +1,127 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] + * + * (C) 2007 Atmel Corporation. + * + * Common definitions. + * Based on AT91SAM9263 datasheet revision B (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9263_H +#define AT91SAM9263_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ +#define AT91SAM9263_ID_US0 7 /* USART 0 */ +#define AT91SAM9263_ID_US1 8 /* USART 1 */ +#define AT91SAM9263_ID_US2 9 /* USART 2 */ +#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ +#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ +#define AT91SAM9263_ID_CAN 12 /* CAN */ +#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ +#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ +#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ +#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ +#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ +#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ +#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ +#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ +#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ +#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ +#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ +#define AT91SAM9263_ID_UHP 29 /* USB Host port */ +#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9263_BASE_UDP 0xfff78000 +#define AT91SAM9263_BASE_TCB0 0xfff7c000 +#define AT91SAM9263_BASE_TC0 0xfff7c000 +#define AT91SAM9263_BASE_TC1 0xfff7c040 +#define AT91SAM9263_BASE_TC2 0xfff7c080 +#define AT91SAM9263_BASE_MCI0 0xfff80000 +#define AT91SAM9263_BASE_MCI1 0xfff84000 +#define AT91SAM9263_BASE_TWI 0xfff88000 +#define AT91SAM9263_BASE_US0 0xfff8c000 +#define AT91SAM9263_BASE_US1 0xfff90000 +#define AT91SAM9263_BASE_US2 0xfff94000 +#define AT91SAM9263_BASE_SSC0 0xfff98000 +#define AT91SAM9263_BASE_SSC1 0xfff9c000 +#define AT91SAM9263_BASE_AC97C 0xfffa0000 +#define AT91SAM9263_BASE_SPI0 0xfffa4000 +#define AT91SAM9263_BASE_SPI1 0xfffa8000 +#define AT91SAM9263_BASE_CAN 0xfffac000 +#define AT91SAM9263_BASE_PWMC 0xfffb8000 +#define AT91SAM9263_BASE_EMAC 0xfffbc000 +#define AT91SAM9263_BASE_ISI 0xfffc4000 +#define AT91SAM9263_BASE_2DGE 0xfffc8000 +#define AT91_BASE_SYS 0xffffe000 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) +#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) +#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) +#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) +#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) +#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9263_BASE_US0 +#define AT91_USART1 AT91SAM9263_BASE_US1 +#define AT91_USART2 AT91SAM9263_BASE_US2 + +#define AT91_SMC AT91_SMC0 + +/* + * Internal Memory. + */ +#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ +#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ + +#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ + +#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ +#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ + +#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ +#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ +#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ + + +#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h new file mode 100644 index 0000000000..83aaaab773 --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h @@ -0,0 +1,129 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] + * + * Copyright (C) 2006 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9263 datasheet revision B (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9263_MATRIX_H +#define AT91SAM9263_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ +#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ +#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ +#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ +#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ +#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ +#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ +#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ +#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ +#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ +#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) + +#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ +#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) +#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) +#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) + +#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ +#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) +#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) + +#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam9rl.h b/include/asm-arm/arch-at91sam9/at91sam9rl.h new file mode 100644 index 0000000000..215bbc8d6a --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9rl.h @@ -0,0 +1,115 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h] + * + * Copyright (C) 2007 Atmel Corporation + * + * Common definitions. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_H +#define AT91SAM9RL_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Controller */ +#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91SAM9RL_ID_US0 6 /* USART 0 */ +#define AT91SAM9RL_ID_US1 7 /* USART 1 */ +#define AT91SAM9RL_ID_US2 8 /* USART 2 */ +#define AT91SAM9RL_ID_US3 9 /* USART 3 */ +#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ +#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ +#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ +#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ +#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ +#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ +#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ +#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ +#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ +#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ +#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9RL_BASE_TCB0 0xfffa0000 +#define AT91SAM9RL_BASE_TC0 0xfffa0000 +#define AT91SAM9RL_BASE_TC1 0xfffa0040 +#define AT91SAM9RL_BASE_TC2 0xfffa0080 +#define AT91SAM9RL_BASE_MCI 0xfffa4000 +#define AT91SAM9RL_BASE_TWI0 0xfffa8000 +#define AT91SAM9RL_BASE_TWI1 0xfffac000 +#define AT91SAM9RL_BASE_US0 0xfffb0000 +#define AT91SAM9RL_BASE_US1 0xfffb4000 +#define AT91SAM9RL_BASE_US2 0xfffb8000 +#define AT91SAM9RL_BASE_US3 0xfffbc000 +#define AT91SAM9RL_BASE_SSC0 0xfffc0000 +#define AT91SAM9RL_BASE_SSC1 0xfffc4000 +#define AT91SAM9RL_BASE_PWMC 0xfffc8000 +#define AT91SAM9RL_BASE_SPI 0xfffcc000 +#define AT91SAM9RL_BASE_TSC 0xfffd0000 +#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 +#define AT91SAM9RL_BASE_AC97C 0xfffd8000 +#define AT91_BASE_SYS 0xffffc000 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9RL_BASE_US0 +#define AT91_USART1 AT91SAM9RL_BASE_US1 +#define AT91_USART2 AT91SAM9RL_BASE_US2 +#define AT91_USART3 AT91SAM9RL_BASE_US3 + + +/* + * Internal Memory. + */ +#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ + +#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ + +#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ +#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ + +#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h new file mode 100644 index 0000000000..af8d914acc --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h @@ -0,0 +1,96 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h] + * + * Copyright (C) 2007 Atmel Corporation + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_MATRIX_H +#define AT91SAM9RL_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) + + +#endif diff --git a/include/asm-arm/arch-at91sam9/clk.h b/include/asm-arm/arch-at91sam9/clk.h index f67b4356d9..1b502c822c 100644 --- a/include/asm-arm/arch-at91sam9/clk.h +++ b/include/asm-arm/arch-at91sam9/clk.h @@ -36,4 +36,10 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id) return AT91_MASTER_CLOCK; } +static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) +{ + return AT91_MASTER_CLOCK; +} + + #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91sam9/hardware.h b/include/asm-arm/arch-at91sam9/hardware.h index d2fe45388b..f31241901a 100644 --- a/include/asm-arm/arch-at91sam9/hardware.h +++ b/include/asm-arm/arch-at91sam9/hardware.h @@ -26,10 +26,19 @@ #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9261) #include <asm/arch/at91sam9261.h> +#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 +#define AT91_ID_UHP AT91SAM9261_ID_UHP +#define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9263) #include <asm/arch/at91sam9263.h> +#define AT91_BASE_EMAC AT91SAM9263_BASE_EMAC +#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 +#define AT91_ID_UHP AT91SAM9263_ID_UHP +#define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9RL) #include <asm/arch/at91sam9rl.h> +#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI +#define AT91_ID_UHP AT91SAM9RL_ID_UHP #elif defined(CONFIG_AT91CAP9) #include <asm/arch/at91cap9.h> #define AT91_BASE_EMAC AT91CAP9_BASE_EMAC @@ -42,15 +51,4 @@ #error "Unsupported AT91 processor" #endif -/* - * container_of - cast a member of a structure out to the containing structure - * - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - */ -#define container_of(ptr, type, member) ({ \ - const typeof(((type *)0)->member) *__mptr = (ptr); \ - (type *)((char *)__mptr - offsetof(type, member)); }) - #endif diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index 9440d80b50..85e144b682 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -110,23 +110,6 @@ #define MMC_DEFAULT_RCA 1 #define MMC_BLOCK_SIZE 512 -#define MMC_CMD_RESET 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RCA 3 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_BLOCK 17 -#define MMC_CMD_RD_BLK_MULTI 18 -#define MMC_CMD_WRITE_BLOCK 24 -#define MMC_CMD_APP_CMD 55 - -#define SD_CMD_APP_SET_BUS_WIDTH 6 -#define SD_CMD_APP_OP_COND 41 - #define MMC_MAX_BLOCK_SIZE 512 #define MMC_R1_IDLE_STATE 0x01 diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index 7564ff1469..7e2a53adb0 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -48,7 +48,7 @@ typedef struct global_data { #if 0 unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ #endif void **jt; /* jump table */ diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index aaf2ea20c9..b347857c9f 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_P300 1602 #define MACH_TYPE_XDACOMET 1603 #define MACH_TYPE_DEXFLEX2 1604 +#define MACH_TYPE_SFFSDR 1657 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -16500,6 +16501,18 @@ extern unsigned int __machine_arch_type; # define machine_is_schmoogie() (0) #endif +#ifdef CONFIG_MACH_SFFSDR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFFSDR +# endif +# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) +#else +# define machine_is_sffsdr() (0) +#endif + #ifdef CONFIG_MACH_AZTOOL # ifdef machine_arch_type # undef machine_arch_type diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h index 41e7a8f7d3..4ee5a327e5 100644 --- a/include/asm-arm/u-boot-arm.h +++ b/include/asm-arm/u-boot-arm.h @@ -52,7 +52,7 @@ void setup_revision_tag (struct tag **params); /* To be fixed! */ /* ------------------------------------------------------------ */ /* common/cmd_nvedit.c */ -void setenv (char *, char *); +int setenv (char *, char *); /* cpu/.../interrupt.c */ void reset_timer_masked (void); diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h index 29b1fd663d..c47107e2a6 100644 --- a/include/asm-avr32/arch-at32ap700x/chip-features.h +++ b/include/asm-avr32/arch-at32ap700x/chip-features.h @@ -25,6 +25,7 @@ /* Currently, all the AP700x chips have these */ #define AT32AP700x_CHIP_HAS_USART #define AT32AP700x_CHIP_HAS_MMCI +#define AT32AP700x_CHIP_HAS_SPI /* Only AP7000 has ethernet interface */ #ifdef CONFIG_AT32AP7000 diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index 385319aac7..a9d8431a66 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -58,7 +58,7 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id) return get_pba_clk_rate(); } #endif -#ifdef AT32AP700x_CHIP_HAS_USART +#ifdef AT32AP700x_CHIP_HAS_MACB static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { return get_pbb_clk_rate(); @@ -74,6 +74,14 @@ static inline unsigned long get_mci_clk_rate(void) return get_pbb_clk_rate(); } #endif +#ifdef AT32AP700x_CHIP_HAS_SPI +static inline unsigned long get_spi_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +#endif + +extern void clk_init(void); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h index b10a3e4f86..8c922c7c65 100644 --- a/include/asm-avr32/arch-at32ap700x/gpio.h +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -180,6 +180,11 @@ #define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) #define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) +#define GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */ +#define GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */ +#define GPIOF_DEGLITCH 0x00000004 /* (IN) Filter glitches */ +#define GPIOF_MULTIDRV 0x00000008 /* Enable multidriver option */ + static inline void *gpio_pin_to_addr(unsigned int pin) { switch (pin >> 5) { @@ -200,6 +205,9 @@ static inline void *gpio_pin_to_addr(unsigned int pin) void gpio_select_periph_A(unsigned int pin, int use_pullup); void gpio_select_periph_B(unsigned int pin, int use_pullup); +void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags); +void gpio_set_value(unsigned int pin, int value); +int gpio_get_value(unsigned int pin); void gpio_enable_ebi(void); @@ -216,5 +224,9 @@ void gpio_enable_macb1(void); #ifdef AT32AP700x_CHIP_HAS_MMCI void gpio_enable_mmci(void); #endif +#ifdef AT32AP700x_CHIP_HAS_SPI +void gpio_enable_spi0(unsigned long cs_mask); +void gpio_enable_spi1(unsigned long cs_mask); +#endif #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix.h b/include/asm-avr32/arch-at32ap700x/hmatrix.h new file mode 100644 index 0000000000..d6b626328d --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/hmatrix.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_HMATRIX_H__ +#define __ASM_AVR32_ARCH_HMATRIX_H__ + +#include <asm/hmatrix-common.h> + +/* Bitfields in SFR4 (EBI) */ +#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1 +#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1 +#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3 +#define HMATRIX_EBI_NAND_ENABLE_SIZE 1 +#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4 +#define HMATRIX_EBI_CF0_ENABLE_SIZE 1 +#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5 +#define HMATRIX_EBI_CF1_ENABLE_SIZE 1 +#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8 +#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1 + +/* HSB masters */ +#define HMATRIX_MASTER_CPU_DCACHE 0 +#define HMATRIX_MASTER_CPU_ICACHE 1 +#define HMATRIX_MASTER_PDC 2 +#define HMATRIX_MASTER_ISI 3 +#define HMATRIX_MASTER_USBA 4 +#define HMATRIX_MASTER_LCDC 5 +#define HMATRIX_MASTER_MACB0 6 +#define HMATRIX_MASTER_MACB1 7 +#define HMATRIX_MASTER_DMACA_M0 8 +#define HMATRIX_MASTER_DMACA_M1 9 + +/* HSB slaves */ +#define HMATRIX_SLAVE_SRAM0 0 +#define HMATRIX_SLAVE_SRAM1 1 +#define HMATRIX_SLAVE_PBA 2 +#define HMATRIX_SLAVE_PBB 3 +#define HMATRIX_SLAVE_EBI 4 +#define HMATRIX_SLAVE_USBA 5 +#define HMATRIX_SLAVE_LCDC 6 +#define HMATRIX_SLAVE_DMACA 7 + +#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h deleted file mode 100644 index b0e787a92f..0000000000 --- a/include/asm-avr32/arch-at32ap700x/hmatrix2.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Register definition for the High-speed Bus Matrix - */ -#ifndef __ASM_AVR32_HMATRIX2_H__ -#define __ASM_AVR32_HMATRIX2_H__ - -/* HMATRIX2 register offsets */ -#define HMATRIX2_MCFG0 0x0000 -#define HMATRIX2_MCFG1 0x0004 -#define HMATRIX2_MCFG2 0x0008 -#define HMATRIX2_MCFG3 0x000c -#define HMATRIX2_MCFG4 0x0010 -#define HMATRIX2_MCFG5 0x0014 -#define HMATRIX2_MCFG6 0x0018 -#define HMATRIX2_MCFG7 0x001c -#define HMATRIX2_MCFG8 0x0020 -#define HMATRIX2_MCFG9 0x0024 -#define HMATRIX2_MCFG10 0x0028 -#define HMATRIX2_MCFG11 0x002c -#define HMATRIX2_MCFG12 0x0030 -#define HMATRIX2_MCFG13 0x0034 -#define HMATRIX2_MCFG14 0x0038 -#define HMATRIX2_MCFG15 0x003c -#define HMATRIX2_SCFG0 0x0040 -#define HMATRIX2_SCFG1 0x0044 -#define HMATRIX2_SCFG2 0x0048 -#define HMATRIX2_SCFG3 0x004c -#define HMATRIX2_SCFG4 0x0050 -#define HMATRIX2_SCFG5 0x0054 -#define HMATRIX2_SCFG6 0x0058 -#define HMATRIX2_SCFG7 0x005c -#define HMATRIX2_SCFG8 0x0060 -#define HMATRIX2_SCFG9 0x0064 -#define HMATRIX2_SCFG10 0x0068 -#define HMATRIX2_SCFG11 0x006c -#define HMATRIX2_SCFG12 0x0070 -#define HMATRIX2_SCFG13 0x0074 -#define HMATRIX2_SCFG14 0x0078 -#define HMATRIX2_SCFG15 0x007c -#define HMATRIX2_PRAS0 0x0080 -#define HMATRIX2_PRBS0 0x0084 -#define HMATRIX2_PRAS1 0x0088 -#define HMATRIX2_PRBS1 0x008c -#define HMATRIX2_PRAS2 0x0090 -#define HMATRIX2_PRBS2 0x0094 -#define HMATRIX2_PRAS3 0x0098 -#define HMATRIX2_PRBS3 0x009c -#define HMATRIX2_PRAS4 0x00a0 -#define HMATRIX2_PRBS4 0x00a4 -#define HMATRIX2_PRAS5 0x00a8 -#define HMATRIX2_PRBS5 0x00ac -#define HMATRIX2_PRAS6 0x00b0 -#define HMATRIX2_PRBS6 0x00b4 -#define HMATRIX2_PRAS7 0x00b8 -#define HMATRIX2_PRBS7 0x00bc -#define HMATRIX2_PRAS8 0x00c0 -#define HMATRIX2_PRBS8 0x00c4 -#define HMATRIX2_PRAS9 0x00c8 -#define HMATRIX2_PRBS9 0x00cc -#define HMATRIX2_PRAS10 0x00d0 -#define HMATRIX2_PRBS10 0x00d4 -#define HMATRIX2_PRAS11 0x00d8 -#define HMATRIX2_PRBS11 0x00dc -#define HMATRIX2_PRAS12 0x00e0 -#define HMATRIX2_PRBS12 0x00e4 -#define HMATRIX2_PRAS13 0x00e8 -#define HMATRIX2_PRBS13 0x00ec -#define HMATRIX2_PRAS14 0x00f0 -#define HMATRIX2_PRBS14 0x00f4 -#define HMATRIX2_PRAS15 0x00f8 -#define HMATRIX2_PRBS15 0x00fc -#define HMATRIX2_MRCR 0x0100 -#define HMATRIX2_SFR0 0x0110 -#define HMATRIX2_SFR1 0x0114 -#define HMATRIX2_SFR2 0x0118 -#define HMATRIX2_SFR3 0x011c -#define HMATRIX2_SFR4 0x0120 -#define HMATRIX2_SFR5 0x0124 -#define HMATRIX2_SFR6 0x0128 -#define HMATRIX2_SFR7 0x012c -#define HMATRIX2_SFR8 0x0130 -#define HMATRIX2_SFR9 0x0134 -#define HMATRIX2_SFR10 0x0138 -#define HMATRIX2_SFR11 0x013c -#define HMATRIX2_SFR12 0x0140 -#define HMATRIX2_SFR13 0x0144 -#define HMATRIX2_SFR14 0x0148 -#define HMATRIX2_SFR15 0x014c -#define HMATRIX2_VERSION 0x01fc - -/* Bitfields in MCFG0 */ -#define HMATRIX2_ULBT_OFFSET 0 -#define HMATRIX2_ULBT_SIZE 3 - -/* Bitfields in SCFG0 */ -#define HMATRIX2_SLOT_CYCLE_OFFSET 0 -#define HMATRIX2_SLOT_CYCLE_SIZE 8 -#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 -#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 -#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 -#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 -#define HMATRIX2_ARBT_OFFSET 24 -#define HMATRIX2_ARBT_SIZE 2 - -/* Bitfields in PRAS0 */ -#define HMATRIX2_M0PR_OFFSET 0 -#define HMATRIX2_M0PR_SIZE 4 -#define HMATRIX2_M1PR_OFFSET 4 -#define HMATRIX2_M1PR_SIZE 4 -#define HMATRIX2_M2PR_OFFSET 8 -#define HMATRIX2_M2PR_SIZE 4 -#define HMATRIX2_M3PR_OFFSET 12 -#define HMATRIX2_M3PR_SIZE 4 -#define HMATRIX2_M4PR_OFFSET 16 -#define HMATRIX2_M4PR_SIZE 4 -#define HMATRIX2_M5PR_OFFSET 20 -#define HMATRIX2_M5PR_SIZE 4 -#define HMATRIX2_M6PR_OFFSET 24 -#define HMATRIX2_M6PR_SIZE 4 -#define HMATRIX2_M7PR_OFFSET 28 -#define HMATRIX2_M7PR_SIZE 4 - -/* Bitfields in PRBS0 */ -#define HMATRIX2_M8PR_OFFSET 0 -#define HMATRIX2_M8PR_SIZE 4 -#define HMATRIX2_M9PR_OFFSET 4 -#define HMATRIX2_M9PR_SIZE 4 -#define HMATRIX2_M10PR_OFFSET 8 -#define HMATRIX2_M10PR_SIZE 4 -#define HMATRIX2_M11PR_OFFSET 12 -#define HMATRIX2_M11PR_SIZE 4 -#define HMATRIX2_M12PR_OFFSET 16 -#define HMATRIX2_M12PR_SIZE 4 -#define HMATRIX2_M13PR_OFFSET 20 -#define HMATRIX2_M13PR_SIZE 4 -#define HMATRIX2_M14PR_OFFSET 24 -#define HMATRIX2_M14PR_SIZE 4 -#define HMATRIX2_M15PR_OFFSET 28 -#define HMATRIX2_M15PR_SIZE 4 - -/* Bitfields in MRCR */ -#define HMATRIX2_RBC0_OFFSET 0 -#define HMATRIX2_RBC0_SIZE 1 -#define HMATRIX2_RBC1_OFFSET 1 -#define HMATRIX2_RBC1_SIZE 1 -#define HMATRIX2_RBC2_OFFSET 2 -#define HMATRIX2_RBC2_SIZE 1 -#define HMATRIX2_RBC3_OFFSET 3 -#define HMATRIX2_RBC3_SIZE 1 -#define HMATRIX2_RBC4_OFFSET 4 -#define HMATRIX2_RBC4_SIZE 1 -#define HMATRIX2_RBC5_OFFSET 5 -#define HMATRIX2_RBC5_SIZE 1 -#define HMATRIX2_RBC6_OFFSET 6 -#define HMATRIX2_RBC6_SIZE 1 -#define HMATRIX2_RBC7_OFFSET 7 -#define HMATRIX2_RBC7_SIZE 1 -#define HMATRIX2_RBC8_OFFSET 8 -#define HMATRIX2_RBC8_SIZE 1 -#define HMATRIX2_RBC9_OFFSET 9 -#define HMATRIX2_RBC9_SIZE 1 -#define HMATRIX2_RBC10_OFFSET 10 -#define HMATRIX2_RBC10_SIZE 1 -#define HMATRIX2_RBC11_OFFSET 11 -#define HMATRIX2_RBC11_SIZE 1 -#define HMATRIX2_RBC12_OFFSET 12 -#define HMATRIX2_RBC12_SIZE 1 -#define HMATRIX2_RBC13_OFFSET 13 -#define HMATRIX2_RBC13_SIZE 1 -#define HMATRIX2_RBC14_OFFSET 14 -#define HMATRIX2_RBC14_SIZE 1 -#define HMATRIX2_RBC15_OFFSET 15 -#define HMATRIX2_RBC15_SIZE 1 - -/* Bitfields in SFR0 */ -#define HMATRIX2_SFR_OFFSET 0 -#define HMATRIX2_SFR_SIZE 32 - -/* Bitfields in SFR4 */ -#define HMATRIX2_CS1A_OFFSET 1 -#define HMATRIX2_CS1A_SIZE 1 -#define HMATRIX2_CS3A_OFFSET 3 -#define HMATRIX2_CS3A_SIZE 1 -#define HMATRIX2_CS4A_OFFSET 4 -#define HMATRIX2_CS4A_SIZE 1 -#define HMATRIX2_CS5A_OFFSET 5 -#define HMATRIX2_CS5A_SIZE 1 -#define HMATRIX2_DBPUC_OFFSET 8 -#define HMATRIX2_DBPUC_SIZE 1 - -/* Bitfields in VERSION */ -#define HMATRIX2_VERSION_OFFSET 0 -#define HMATRIX2_VERSION_SIZE 12 -#define HMATRIX2_MFN_OFFSET 16 -#define HMATRIX2_MFN_SIZE 3 - -/* Constants for ULBT */ -#define HMATRIX2_ULBT_INFINITE 0 -#define HMATRIX2_ULBT_SINGLE 1 -#define HMATRIX2_ULBT_FOUR_BEAT 2 -#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 - -/* Constants for DEFMSTR_TYPE */ -#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 -#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 -#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 - -/* Constants for ARBT */ -#define HMATRIX2_ARBT_ROUND_ROBIN 0 -#define HMATRIX2_ARBT_FIXED_PRIORITY 1 - -/* Bit manipulation macros */ -#define HMATRIX2_BIT(name) \ - (1 << HMATRIX2_##name##_OFFSET) -#define HMATRIX2_BF(name,value) \ - (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \ - << HMATRIX2_##name##_OFFSET) -#define HMATRIX2_BFEXT(name,value) \ - (((value) >> HMATRIX2_##name##_OFFSET) \ - & ((1 << HMATRIX2_##name##_SIZE) - 1)) -#define HMATRIX2_BFINS(name,value,old) \ - (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \ - << HMATRIX2_##name##_OFFSET)) \ - | HMATRIX2_BF(name,value)) - -/* Register access macros */ -#define hmatrix2_readl(reg) \ - readl((void *)HMATRIX_BASE + HMATRIX2_##reg) -#define hmatrix2_writel(reg,value) \ - writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) - -#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h index 5513e88e7b..6592c039fa 100644 --- a/include/asm-avr32/arch-at32ap700x/memory-map.h +++ b/include/asm-avr32/arch-at32ap700x/memory-map.h @@ -22,6 +22,26 @@ #ifndef __AT32AP7000_MEMORY_MAP_H__ #define __AT32AP7000_MEMORY_MAP_H__ +/* Internal and external memories */ +#define EBI_SRAM_CS0_BASE 0x00000000 +#define EBI_SRAM_CS0_SIZE 0x04000000 +#define EBI_SRAM_CS4_BASE 0x04000000 +#define EBI_SRAM_CS4_SIZE 0x04000000 +#define EBI_SRAM_CS2_BASE 0x08000000 +#define EBI_SRAM_CS2_SIZE 0x04000000 +#define EBI_SRAM_CS3_BASE 0x0c000000 +#define EBI_SRAM_CS3_SIZE 0x04000000 +#define EBI_SRAM_CS1_BASE 0x10000000 +#define EBI_SRAM_CS1_SIZE 0x10000000 +#define EBI_SRAM_CS5_BASE 0x20000000 +#define EBI_SRAM_CS5_SIZE 0x04000000 + +#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE +#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE + +#define INTERNAL_SRAM_BASE 0x24000000 +#define INTERNAL_SRAM_SIZE 0x00008000 + /* Devices on the High Speed Bus (HSB) */ #define LCDC_BASE 0xFF000000 #define DMAC_BASE 0xFF200000 diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h index 6a33fef5a8..9caba9168e 100644 --- a/include/asm-avr32/arch-at32ap700x/mmc.h +++ b/include/asm-avr32/arch-at32ap700x/mmc.h @@ -71,25 +71,6 @@ struct mmc_csd u8 one:1; }; -/* MMC Command numbers */ -#define MMC_CMD_GO_IDLE_STATE 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RELATIVE_ADDR 3 -#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 -#define MMC_CMD_SET_DSR 4 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_SINGLE_BLOCK 17 -#define MMC_CMD_READ_MULTIPLE_BLOCK 18 -#define MMC_CMD_WRITE_BLOCK 24 -#define MMC_CMD_APP_CMD 55 - -#define MMC_ACMD_SD_SEND_OP_COND 41 - #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) diff --git a/include/asm-avr32/hmatrix-common.h b/include/asm-avr32/hmatrix-common.h new file mode 100644 index 0000000000..4b7e6105dd --- /dev/null +++ b/include/asm-avr32/hmatrix-common.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_HMATRIX_COMMON_H__ +#define __ASM_AVR32_HMATRIX_COMMON_H__ + +/* HMATRIX register offsets */ +struct hmatrix_regs { + u32 MCFG[16]; + u32 SCFG[16]; + struct { + u32 A; + u32 B; + } PRS[16]; + u32 MRCR; + u32 __reserved[3]; + u32 SFR[16]; +}; + +/* Bitfields in MCFG */ +#define HMATRIX_ULBT_OFFSET 0 +#define HMATRIX_ULBT_SIZE 3 + +/* Bitfields in SCFG */ +#define HMATRIX_SLOT_CYCLE_OFFSET 0 +#define HMATRIX_SLOT_CYCLE_SIZE 8 +#define HMATRIX_DEFMSTR_TYPE_OFFSET 16 +#define HMATRIX_DEFMSTR_TYPE_SIZE 2 +#define HMATRIX_FIXED_DEFMSTR_OFFSET 18 +#define HMATRIX_FIXED_DEFMSTR_SIZE 4 +#define HMATRIX_ARBT_OFFSET 24 +#define HMATRIX_ARBT_SIZE 1 + +/* Bitfields in PRS.A */ +#define HMATRIX_M0PR_OFFSET 0 +#define HMATRIX_M0PR_SIZE 4 +#define HMATRIX_M1PR_OFFSET 4 +#define HMATRIX_M1PR_SIZE 4 +#define HMATRIX_M2PR_OFFSET 8 +#define HMATRIX_M2PR_SIZE 4 +#define HMATRIX_M3PR_OFFSET 12 +#define HMATRIX_M3PR_SIZE 4 +#define HMATRIX_M4PR_OFFSET 16 +#define HMATRIX_M4PR_SIZE 4 +#define HMATRIX_M5PR_OFFSET 20 +#define HMATRIX_M5PR_SIZE 4 +#define HMATRIX_M6PR_OFFSET 24 +#define HMATRIX_M6PR_SIZE 4 +#define HMATRIX_M7PR_OFFSET 28 +#define HMATRIX_M7PR_SIZE 4 + +/* Bitfields in PRS.B */ +#define HMATRIX_M8PR_OFFSET 0 +#define HMATRIX_M8PR_SIZE 4 +#define HMATRIX_M9PR_OFFSET 4 +#define HMATRIX_M9PR_SIZE 4 +#define HMATRIX_M10PR_OFFSET 8 +#define HMATRIX_M10PR_SIZE 4 +#define HMATRIX_M11PR_OFFSET 12 +#define HMATRIX_M11PR_SIZE 4 +#define HMATRIX_M12PR_OFFSET 16 +#define HMATRIX_M12PR_SIZE 4 +#define HMATRIX_M13PR_OFFSET 20 +#define HMATRIX_M13PR_SIZE 4 +#define HMATRIX_M14PR_OFFSET 24 +#define HMATRIX_M14PR_SIZE 4 +#define HMATRIX_M15PR_OFFSET 28 +#define HMATRIX_M15PR_SIZE 4 + +/* Constants for ULBT */ +#define HMATRIX_ULBT_INFINITE 0 +#define HMATRIX_ULBT_SINGLE 1 +#define HMATRIX_ULBT_FOUR_BEAT 2 +#define HMATRIX_ULBT_EIGHT_BEAT 3 +#define HMATRIX_ULBT_SIXTEEN_BEAT 4 + +/* Constants for DEFMSTR_TYPE */ +#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0 +#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1 +#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2 + +/* Constants for ARBT */ +#define HMATRIX_ARBT_ROUND_ROBIN 0 +#define HMATRIX_ARBT_FIXED_PRIORITY 1 + +/* Bit manipulation macros */ +#define HMATRIX_BIT(name) \ + (1 << HMATRIX_##name##_OFFSET) +#define HMATRIX_BF(name,value) \ + (((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \ + << HMATRIX_##name##_OFFSET) +#define HMATRIX_BFEXT(name,value) \ + (((value) >> HMATRIX_##name##_OFFSET) \ + & ((1 << HMATRIX_##name##_SIZE) - 1)) +#define HMATRIX_BFINS(name,value,old) \ + (((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \ + << HMATRIX_##name##_OFFSET)) \ + | HMATRIX_BF(name,value)) + +/* Register access macros */ +#define __hmatrix_reg(reg) \ + (((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg) +#define hmatrix_read(reg) \ + (__hmatrix_reg(reg)) +#define hmatrix_write(reg, value) \ + do { __hmatrix_reg(reg) = (value); } while (0) + +#define hmatrix_slave_read(slave, reg) \ + hmatrix_read(reg[HMATRIX_SLAVE_##slave]) +#define hmatrix_slave_write(slave, reg, value) \ + hmatrix_write(reg[HMATRIX_SLAVE_##slave], value) + +#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */ diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h index 833af6e6ad..7bdefc1fd2 100644 --- a/include/asm-avr32/sdram.h +++ b/include/asm-avr32/sdram.h @@ -22,15 +22,32 @@ #ifndef __ASM_AVR32_SDRAM_H #define __ASM_AVR32_SDRAM_H -struct sdram_info { - unsigned long phys_addr; - unsigned int row_bits, col_bits, bank_bits; - unsigned int cas, twr, trc, trp, trcd, tras, txsr; +struct sdram_config { + /* Number of data bits. */ + enum { + SDRAM_DATA_16BIT, + SDRAM_DATA_32BIT, + } data_bits; + + /* Number of address bits */ + uint8_t row_bits, col_bits, bank_bits; + + /* SDRAM timings in cycles */ + uint8_t cas, twr, trc, trp, trcd, tras, txsr; /* SDRAM refresh period in cycles */ unsigned long refresh_period; }; -extern unsigned long sdram_init(const struct sdram_info *info); +/* + * Attempt to initialize the SDRAM controller using the specified + * parameters. Return the expected size of the memory area based on + * the number of address and data bits. + * + * The caller should verify that the configuration is correct by + * running a memory test, e.g. get_ram_size(). + */ +extern unsigned long sdram_init(void *sdram_base, + const struct sdram_config *config); #endif /* __ASM_AVR32_SDRAM_H */ diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h index 75373abde7..fe819b2db6 100644 --- a/include/asm-avr32/sections.h +++ b/include/asm-avr32/sections.h @@ -25,15 +25,8 @@ /* References to section boundaries */ extern char _text[], _etext[]; -extern char __flashprog_start[], __flashprog_end[]; extern char _data[], __data_lma[], _edata[], __edata_lma[]; extern char __got_start[], __got_lma[], __got_end[]; extern char _end[]; -/* - * Everything in .flashprog will be locked in the icache so it doesn't - * get disturbed when executing flash commands. - */ -#define __flashprog __attribute__((section(".flashprog"), __noinline__)) - #endif /* __ASM_AVR32_SECTIONS_H */ diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h index 71dfcaf284..85ef008b72 100644 --- a/include/asm-avr32/u-boot.h +++ b/include/asm-avr32/u-boot.h @@ -42,15 +42,4 @@ typedef struct bd_info { #define bi_memstart bi_dram[0].start #define bi_memsize bi_dram[0].size -/** - * container_of - cast a member of a structure out to the containing structure - * - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - */ -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - #endif /* __ASM_U_BOOT_H__ */ diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 4c88639623..b0b01e4856 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -43,7 +43,7 @@ typedef struct global_data { unsigned long board_type; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h index 84f1553e0a..9d2903be9a 100644 --- a/include/asm-blackfin/u-boot.h +++ b/include/asm-blackfin/u-boot.h @@ -34,7 +34,7 @@ typedef struct bd_info { unsigned char bi_enetaddr[6]; /* Ethernet adress */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h index 3235063995..5dfb595109 100644 --- a/include/asm-i386/global_data.h +++ b/include/asm-i386/global_data.h @@ -43,7 +43,7 @@ typedef struct { unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ void **jt; /* jump table */ } gd_t; diff --git a/include/asm-i386/u-boot.h b/include/asm-i386/u-boot.h index 1e19f8f3d2..fc5a2ae591 100644 --- a/include/asm-i386/u-boot.h +++ b/include/asm-i386/u-boot.h @@ -38,7 +38,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index 7377d313db..10c6931534 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -51,7 +51,7 @@ typedef struct global_data { unsigned long i2c1_clk; unsigned long i2c2_clk; #endif - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ unsigned long env_addr; /* Address of Environment struct */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h index 93a6959ff1..5a0d5fe487 100644 --- a/include/asm-m68k/u-boot.h +++ b/include/asm-m68k/u-boot.h @@ -38,7 +38,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-microblaze/u-boot.h b/include/asm-microblaze/u-boot.h index e2035bd79c..9db491ec99 100644 --- a/include/asm-microblaze/u-boot.h +++ b/include/asm-microblaze/u-boot.h @@ -34,7 +34,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 0e6abd7d0f..3a1e6d615f 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -3,16 +3,94 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996 by Ralf Baechle - * Copyright (C) 2000 by Maciej W. Rozycki - * - * Defitions for the address spaces of the MIPS CPUs. + * Copyright (C) 1996, 99 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + */ +#ifndef _ASM_ADDRSPACE_H +#define _ASM_ADDRSPACE_H + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ATYPE_ +#define _ATYPE32_ +#define _ATYPE64_ +#define _CONST64_(x) x +#else +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int +#define _ATYPE64_ __s64 +#ifdef CONFIG_64BIT +#define _CONST64_(x) x ## L +#else +#define _CONST64_(x) x ## LL +#endif +#endif + +/* + * 32-bit MIPS address spaces + */ +#ifdef __ASSEMBLY__ +#define _ACAST32_ +#define _ACAST64_ +#else +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ +#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ +#endif + +/* + * Returns the kernel segment base of a given address + */ +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) + +/* + * Returns the physical address of a CKSEGx / XKPHYS address + */ +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _CONST64_(0x000000ffffffffff)) + +#ifdef CONFIG_64BIT + +/* + * Memory segments (64bit kernel mode addresses) + * The compatibility segments use the full 64-bit sign extended value. Note + * the R8000 doesn't have them so don't reference these in generic MIPS code. + */ +#define XKUSEG _CONST64_(0x0000000000000000) +#define XKSSEG _CONST64_(0x4000000000000000) +#define XKPHYS _CONST64_(0x8000000000000000) +#define XKSEG _CONST64_(0xc000000000000000) +#define CKSEG0 _CONST64_(0xffffffff80000000) +#define CKSEG1 _CONST64_(0xffffffffa0000000) +#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG3 _CONST64_(0xffffffffe0000000) + +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) + +#else + +#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) + +/* + * Map an address to a certain kernel segment */ -#ifndef __ASM_MIPS_ADDRSPACE_H -#define __ASM_MIPS_ADDRSPACE_H +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) +#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) +#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) /* * Memory segments (32bit kernel mode addresses) + * These are the traditional names used in the 32-bit universe. */ #define KUSEG 0x00000000 #define KSEG0 0x80000000 @@ -20,63 +98,68 @@ #define KSEG2 0xc0000000 #define KSEG3 0xe0000000 -#define K0BASE KSEG0 +#define CKUSEG 0x00000000 +#define CKSEG0 0x80000000 +#define CKSEG1 0xa0000000 +#define CKSEG2 0xc0000000 +#define CKSEG3 0xe0000000 + +#endif /* - * Returns the kernel segment base of a given address + * Cache modes for XKPHYS address conversion macros */ -#ifndef __ASSEMBLY__ -#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) -#else -#define KSEGX(a) ((a) & 0xe0000000) -#endif +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 /* - * Returns the physical address of a KSEG0/KSEG1 address + * 64-bit address conversions */ -#ifndef __ASSEMBLY__ -#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) -#else -#define PHYSADDR(a) ((a) & 0x1fffffff) -#endif +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ + (_CONST64_(cm) << 59) | (a)) /* * Returns the uncached address of a sdram address */ #ifndef __ASSEMBLY__ -#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229) +#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) /* We use a 36 bit physical address map here and cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_AU1X00 */ +#else /* !CONFIG_SOC_AU1X00 */ #define UNCACHED_SDRAM(a) KSEG1ADDR(a) -#endif /* CONFIG_AU1X00 */ +#endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */ + /* - * Map an address to a certain kernel segment + * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * R8000 implements most with its 48-bit physical address space. */ -#ifndef __ASSEMBLY__ -#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) -#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) -#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) -#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) -#else -#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) -#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) -#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) -#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) -#endif +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ + +#ifndef CONFIG_CPU_R8000 /* - * Memory segments (64bit kernel mode addresses) + * The R8000 doesn't have the 32-bit compat spaces so we don't define them + * in order to catch bugs in the source code. */ -#define XKUSEG 0x0000000000000000 -#define XKSSEG 0x4000000000000000 -#define XKPHYS 0x8000000000000000 -#define XKSEG 0xc000000000000000 -#define CKSEG0 0xffffffff80000000 -#define CKSEG1 0xffffffffa0000000 -#define CKSSEG 0xffffffffc0000000 -#define CKSEG3 0xffffffffe0000000 - -#endif /* __ASM_MIPS_ADDRSPACE_H */ + +#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) +#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ + +#endif + +#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) + +#endif /* _ASM_ADDRSPACE_H */ diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h index 6a33197f6c..2a948e8fe7 100644 --- a/include/asm-mips/au1x00.h +++ b/include/asm-mips/au1x00.h @@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x) #define CP0_DEBUG $23 /* SDRAM Controller */ -#ifdef CONFIG_AU1550 +#ifdef CONFIG_SOC_AU1550 #define MEM_SDMODE0 0xB4000800 #define MEM_SDMODE1 0xB4000808 @@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x) #define MEM_SDWRMD1 0xB4000888 #define MEM_SDWRMD2 0xB4000890 -#else /* CONFIG_AU1550 */ +#else /* CONFIG_SOC_AU1550 */ #define MEM_SDMODE0 0xB4000000 #define MEM_SDMODE1 0xB4000004 @@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x) #define MEM_SDWRMD1 0xB4000028 #define MEM_SDWRMD2 0xB400002C -#endif /* CONFIG_AU1550 */ +#endif /* CONFIG_SOC_AU1550 */ #define MEM_SDSLEEP 0xB4000030 #define MEM_SDSMCKE 0xB4000034 diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h new file mode 100644 index 0000000000..1665a63a81 --- /dev/null +++ b/include/asm-mips/errno.h @@ -0,0 +1,143 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle + */ +#ifndef _ASM_MIPS_ERRNO_H +#define _ASM_MIPS_ERRNO_H + +/* + * These first 34 error codes are from Linux 2.6, <asm-generic/errno-base.h> + */ +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +/* + * These error numbers are intended to be MIPS ABI compatible + */ +#define ENOMSG 35 /* No message of desired type */ +#define EIDRM 36 /* Identifier removed */ +#define ECHRNG 37 /* Channel number out of range */ +#define EL2NSYNC 38 /* Level 2 not synchronized */ +#define EL3HLT 39 /* Level 3 halted */ +#define EL3RST 40 /* Level 3 reset */ +#define ELNRNG 41 /* Link number out of range */ +#define EUNATCH 42 /* Protocol driver not attached */ +#define ENOCSI 43 /* No CSI structure available */ +#define EL2HLT 44 /* Level 2 halted */ +#define EDEADLK 45 /* Resource deadlock would occur */ +#define ENOLCK 46 /* No record locks available */ +#define EBADE 50 /* Invalid exchange */ +#define EBADR 51 /* Invalid request descriptor */ +#define EXFULL 52 /* Exchange full */ +#define ENOANO 53 /* No anode */ +#define EBADRQC 54 /* Invalid request code */ +#define EBADSLT 55 /* Invalid slot */ +#define EDEADLOCK 56 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EDOTDOT 73 /* RFS specific error */ +#define EMULTIHOP 74 /* Multihop attempted */ +#define EBADMSG 77 /* Not a data message */ +#define ENAMETOOLONG 78 /* File name too long */ +#define EOVERFLOW 79 /* Value too large for defined data type */ +#define ENOTUNIQ 80 /* Name not unique on network */ +#define EBADFD 81 /* File descriptor in bad state */ +#define EREMCHG 82 /* Remote address changed */ +#define ELIBACC 83 /* Can not access a needed shared library */ +#define ELIBBAD 84 /* Accessing a corrupted shared library */ +#define ELIBSCN 85 /* .lib section in a.out corrupted */ +#define ELIBMAX 86 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 87 /* Cannot exec a shared library directly */ +#define EILSEQ 88 /* Illegal byte sequence */ +#define ENOSYS 89 /* Function not implemented */ +#define ELOOP 90 /* Too many symbolic links encountered */ +#define ERESTART 91 /* Interrupted system call should be restarted */ +#define ESTRPIPE 92 /* Streams pipe error */ +#define ENOTEMPTY 93 /* Directory not empty */ +#define EUSERS 94 /* Too many users */ +#define ENOTSOCK 95 /* Socket operation on non-socket */ +#define EDESTADDRREQ 96 /* Destination address required */ +#define EMSGSIZE 97 /* Message too long */ +#define EPROTOTYPE 98 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 99 /* Protocol not available */ +#define EPROTONOSUPPORT 120 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 121 /* Socket type not supported */ +#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 123 /* Protocol family not supported */ +#define EAFNOSUPPORT 124 /* Address family not supported by protocol */ +#define EADDRINUSE 125 /* Address already in use */ +#define EADDRNOTAVAIL 126 /* Cannot assign requested address */ +#define ENETDOWN 127 /* Network is down */ +#define ENETUNREACH 128 /* Network is unreachable */ +#define ENETRESET 129 /* Network dropped connection because of reset */ +#define ECONNABORTED 130 /* Software caused connection abort */ +#define ECONNRESET 131 /* Connection reset by peer */ +#define ENOBUFS 132 /* No buffer space available */ +#define EISCONN 133 /* Transport endpoint is already connected */ +#define ENOTCONN 134 /* Transport endpoint is not connected */ +#define EUCLEAN 135 /* Structure needs cleaning */ +#define ENOTNAM 137 /* Not a XENIX named type file */ +#define ENAVAIL 138 /* No XENIX semaphores available */ +#define EISNAM 139 /* Is a named type file */ +#define EREMOTEIO 140 /* Remote I/O error */ +#define EINIT 141 /* Reserved */ +#define EREMDEV 142 /* Error 142 */ +#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 144 /* Too many references: cannot splice */ +#define ETIMEDOUT 145 /* Connection timed out */ +#define ECONNREFUSED 146 /* Connection refused */ +#define EHOSTDOWN 147 /* Host is down */ +#define EHOSTUNREACH 148 /* No route to host */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define EALREADY 149 /* Operation already in progress */ +#define EINPROGRESS 150 /* Operation now in progress */ +#define ESTALE 151 /* Stale NFS file handle */ +#define ECANCELED 158 /* AIO operation canceled */ + +#endif /* _ASM_MIPS_ERRNO_H */ diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h index 0c0ba50f42..ecee6dea6a 100644 --- a/include/asm-mips/global_data.h +++ b/include/asm-mips/global_data.h @@ -41,7 +41,7 @@ typedef struct global_data { unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 7137072ce4..3a0f33f204 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -120,7 +120,7 @@ static inline void set_io_port_base(unsigned long base) */ extern inline unsigned long virt_to_phys(volatile void * address) { - return PHYSADDR(address); + return CPHYSADDR(address); } extern inline void * phys_to_virt(unsigned long address) @@ -133,7 +133,7 @@ extern inline void * phys_to_virt(unsigned long address) */ extern inline unsigned long virt_to_bus(volatile void * address) { - return PHYSADDR(address); + return CPHYSADDR(address); } extern inline void * bus_to_virt(unsigned long address) diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 61a0dac1ce..be7e5c65ec 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -7,8 +7,8 @@ * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 Maciej W. Rozycki + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * Copyright (C) 2003, 2004 Maciej W. Rozycki */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H @@ -29,6 +29,15 @@ #endif /* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* * Coprocessor 0 register names */ #define CP0_INDEX $0 @@ -55,12 +64,15 @@ #define CP0_XCONTEXT $20 #define CP0_FRAMEMASK $21 #define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 #define CP0_PERFORMANCE $25 #define CP0_ECC $26 #define CP0_CACHEERR $27 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 +#define CP0_DESAVE $31 /* * R4640/R4650 cp0 register names. These registers are listed @@ -82,11 +94,27 @@ #define CP0_S1_DERRADDR0 $26 #define CP0_S1_DERRADDR1 $27 #define CP0_S1_INTCONTROL $20 + +/* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + /* * Coprocessor 1 (FPU) register names */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 +#define CP1_REVISION $0 +#define CP1_STATUS $31 /* * FPU Status Register Values @@ -95,230 +123,113 @@ * Status Register Values */ -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ /* * X the exception cause indicator * E the exception enable * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 + */ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* rounding mode */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ /* * Values for PageMask register */ -#include <linux/config.h> #ifdef CONFIG_CPU_VR41XX -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 -#else -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#endif -/* - * Values used for computation of new tlb entries - */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 +/* Why doesn't stupidity hurt ... */ -/* - * Macros to access the system control coprocessor - */ -#define read_32bit_cp0_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 -#define read_32bit_cp0_set1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#else -/* - * For now use this only with interrupts disabled! - */ -#define read_64bit_cp0_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0,"STR(source)"\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res;}) +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 -#define write_32bit_cp0_register(register,value) \ - __asm__ __volatile__( \ - "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ - : : "r" (value)); - -#define write_32bit_cp0_set1_register(register,value) \ - __asm__ __volatile__( \ - "ctc0\t%0,"STR(register)"\n\t" \ - "nop" \ - : : "r" (value)); - -#define write_64bit_cp0_register(register,value) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%0,"STR(register)"\n\t" \ - ".set\tmips0" \ - : : "r" (value)) - -/* - * This should be changed when we get a compiler that support the MIPS32 ISA. - */ -#define read_mips32_cp0_config1() \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - ".word\t0x40018001\n\t" \ - "move\t%0,$1\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - :"=r" (__res)); \ - __res;}) +#endif -#define tlb_write_indexed() \ - __asm__ __volatile__( \ - ".set noreorder\n\t" \ - "tlbwi\n\t" \ -".set reorder") +/* + * Values used for computation of new tlb entries + */ +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 /* * R4x00 interrupt enable / cause bits */ -#define IE_SW0 (1<< 8) -#define IE_SW1 (1<< 9) -#define IE_IRQ0 (1<<10) -#define IE_IRQ1 (1<<11) -#define IE_IRQ2 (1<<12) -#define IE_IRQ3 (1<<13) -#define IE_IRQ4 (1<<14) -#define IE_IRQ5 (1<<15) +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) /* * R4x00 interrupt cause bits */ -#define C_SW0 (1<< 8) -#define C_SW1 (1<< 9) -#define C_IRQ0 (1<<10) -#define C_IRQ1 (1<<11) -#define C_IRQ2 (1<<12) -#define C_IRQ3 (1<<13) -#define C_IRQ4 (1<<14) -#define C_IRQ5 (1<<15) - -#ifndef _LANGUAGE_ASSEMBLY -/* - * Manipulate the status register. - * Mostly used to access the interrupt bits. - */ -#define __BUILD_SET_CP0(name,register) \ -extern __inline__ unsigned int \ -set_cp0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_32bit_cp0_register(register); \ - res |= set; \ - write_32bit_cp0_register(register, res); \ - \ - return res; \ -} \ - \ -extern __inline__ unsigned int \ -clear_cp0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_32bit_cp0_register(register); \ - res &= ~clear; \ - write_32bit_cp0_register(register, res); \ - \ - return res; \ -} \ - \ -extern __inline__ unsigned int \ -change_cp0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_32bit_cp0_register(register); \ - res &= ~change; \ - res |= (new & change); \ - if(change) \ - write_32bit_cp0_register(register, res); \ - \ - return res; \ -} - -__BUILD_SET_CP0(status,CP0_STATUS) -__BUILD_SET_CP0(cause,CP0_CAUSE) -__BUILD_SET_CP0(config,CP0_CONFIG) - -#endif /* defined (_LANGUAGE_ASSEMBLY) */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) /* * Bitfields in the R4xx0 cp0 status register @@ -337,9 +248,16 @@ __BUILD_SET_CP0(config,CP0_CONFIG) #define ST0_CE 0x00020000 /* + * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate + * cacheops in userspace. This bit exists only on RM7000 and RM9000 + * processors. + */ +#define ST0_CO 0x08000000 + +/* * Bitfields in the R[23]000 cp0 status register. */ -#define ST0_IEC 0x00000001 +#define ST0_IEC 0x00000001 #define ST0_KUC 0x00000002 #define ST0_IEP 0x00000004 #define ST0_KUP 0x00000008 @@ -353,9 +271,14 @@ __BUILD_SET_CP0(config,CP0_CONFIG) /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (1 << 4) -#define ST0_IL (1 << 23) -#define ST0_DL (1 << 24) +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Enable the MIPS MDMX and DSP ASEs + */ +#define ST0_MX 0x01000000 /* * Bitfields in the TX39 family CP0 Configuration Register 3 @@ -395,39 +318,40 @@ __BUILD_SET_CP0(config,CP0_CONFIG) */ #define ST0_IM 0x0000ff00 #define STATUSB_IP0 8 -#define STATUSF_IP0 (1 << 8) +#define STATUSF_IP0 (_ULCAST_(1) << 8) #define STATUSB_IP1 9 -#define STATUSF_IP1 (1 << 9) +#define STATUSF_IP1 (_ULCAST_(1) << 9) #define STATUSB_IP2 10 -#define STATUSF_IP2 (1 << 10) +#define STATUSF_IP2 (_ULCAST_(1) << 10) #define STATUSB_IP3 11 -#define STATUSF_IP3 (1 << 11) +#define STATUSF_IP3 (_ULCAST_(1) << 11) #define STATUSB_IP4 12 -#define STATUSF_IP4 (1 << 12) +#define STATUSF_IP4 (_ULCAST_(1) << 12) #define STATUSB_IP5 13 -#define STATUSF_IP5 (1 << 13) +#define STATUSF_IP5 (_ULCAST_(1) << 13) #define STATUSB_IP6 14 -#define STATUSF_IP6 (1 << 14) +#define STATUSF_IP6 (_ULCAST_(1) << 14) #define STATUSB_IP7 15 -#define STATUSF_IP7 (1 << 15) +#define STATUSF_IP7 (_ULCAST_(1) << 15) #define STATUSB_IP8 0 -#define STATUSF_IP8 (1 << 0) +#define STATUSF_IP8 (_ULCAST_(1) << 0) #define STATUSB_IP9 1 -#define STATUSF_IP9 (1 << 1) +#define STATUSF_IP9 (_ULCAST_(1) << 1) #define STATUSB_IP10 2 -#define STATUSF_IP10 (1 << 2) +#define STATUSF_IP10 (_ULCAST_(1) << 2) #define STATUSB_IP11 3 -#define STATUSF_IP11 (1 << 3) +#define STATUSF_IP11 (_ULCAST_(1) << 3) #define STATUSB_IP12 4 -#define STATUSF_IP12 (1 << 4) +#define STATUSF_IP12 (_ULCAST_(1) << 4) #define STATUSB_IP13 5 -#define STATUSF_IP13 (1 << 5) +#define STATUSF_IP13 (_ULCAST_(1) << 5) #define STATUSB_IP14 6 -#define STATUSF_IP14 (1 << 6) +#define STATUSF_IP14 (_ULCAST_(1) << 6) #define STATUSB_IP15 7 -#define STATUSF_IP15 (1 << 7) +#define STATUSF_IP15 (_ULCAST_(1) << 7) #define ST0_CH 0x00040000 #define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 #define ST0_BEV 0x00400000 #define ST0_RE 0x02000000 #define ST0_FR 0x04000000 @@ -444,35 +368,36 @@ __BUILD_SET_CP0(config,CP0_CONFIG) * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ #define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (31 << 2) +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) #define CAUSEB_IP 8 -#define CAUSEF_IP (255 << 8) +#define CAUSEF_IP (_ULCAST_(255) << 8) #define CAUSEB_IP0 8 -#define CAUSEF_IP0 (1 << 8) +#define CAUSEF_IP0 (_ULCAST_(1) << 8) #define CAUSEB_IP1 9 -#define CAUSEF_IP1 (1 << 9) +#define CAUSEF_IP1 (_ULCAST_(1) << 9) #define CAUSEB_IP2 10 -#define CAUSEF_IP2 (1 << 10) +#define CAUSEF_IP2 (_ULCAST_(1) << 10) #define CAUSEB_IP3 11 -#define CAUSEF_IP3 (1 << 11) +#define CAUSEF_IP3 (_ULCAST_(1) << 11) #define CAUSEB_IP4 12 -#define CAUSEF_IP4 (1 << 12) +#define CAUSEF_IP4 (_ULCAST_(1) << 12) #define CAUSEB_IP5 13 -#define CAUSEF_IP5 (1 << 13) +#define CAUSEF_IP5 (_ULCAST_(1) << 13) #define CAUSEB_IP6 14 -#define CAUSEF_IP6 (1 << 14) +#define CAUSEF_IP6 (_ULCAST_(1) << 14) #define CAUSEB_IP7 15 -#define CAUSEF_IP7 (1 << 15) +#define CAUSEF_IP7 (_ULCAST_(1) << 15) #define CAUSEB_IV 23 -#define CAUSEF_IV (1 << 23) +#define CAUSEF_IV (_ULCAST_(1) << 23) #define CAUSEB_CE 28 -#define CAUSEF_CE (3 << 28) +#define CAUSEF_CE (_ULCAST_(3) << 28) #define CAUSEB_BD 31 -#define CAUSEF_BD (1 << 31) +#define CAUSEF_BD (_ULCAST_(1) << 31) /* - * Bits in the coprozessor 0 config register. + * Bits in the coprocessor 0 config register. */ +/* Generic bits. */ #define CONF_CM_CACHABLE_NO_WA 0 #define CONF_CM_CACHABLE_WA 1 #define CONF_CM_UNCACHED 2 @@ -482,66 +407,958 @@ __BUILD_SET_CP0(config,CP0_CONFIG) #define CONF_CM_CACHABLE_CUW 6 #define CONF_CM_CACHABLE_ACCELERATED 7 #define CONF_CM_CMASK 7 -#define CONF_DB (1 << 4) -#define CONF_IB (1 << 5) -#define CONF_SC (1 << 17) -#define CONF_AC (1 << 23) -#define CONF_HALT (1 << 25) +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_TE (_ULCAST_(1) << 12) +#define RM7K_CONF_CLK (_ULCAST_(1) << 16) +#define RM7K_CONF_TC (_ULCAST_(1) << 17) +#define RM7K_CONF_SI (_ULCAST_(3) << 20) +#define RM7K_CONF_SC (_ULCAST_(1) << 31) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_P4K (_ULCAST_(1) << 13) +#define VR41_CONF_BP (_ULCAST_(1) << 16) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. + */ +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS (_ULCAST_(7) << 22) +#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) + +#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) +#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) +#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) +#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) +#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) +#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) +#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF2_TU (_ULCAST_(7) << 28) + +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) + +#define MIPS_CONF7_WII (_ULCAST_(1) << 31) + +#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. + */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) + +#ifndef __ASSEMBLY__ + +/* + * Functions to access the R10000 performance counters. These are basically + * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit + * performance counter number encoded into bits 1 ... 5 of the instruction. + * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware + * disassembler these will look like an access to sel 0 or 1. + */ +#define read_r10k_perf_cntr(counter) \ +({ \ + unsigned int __res; \ + __asm__ __volatile__( \ + "mfpc\t%0, %1" \ + : "=r" (__res) \ + : "i" (counter)); \ + \ + __res; \ +}) + +#define write_r10k_perf_cntr(counter,val) \ +do { \ + __asm__ __volatile__( \ + "mtpc\t%0, %1" \ + : \ + : "r" (val), "i" (counter)); \ +} while (0) + +#define read_r10k_perf_event(counter) \ +({ \ + unsigned int __res; \ + __asm__ __volatile__( \ + "mfps\t%0, %1" \ + : "=r" (__res) \ + : "i" (counter)); \ + \ + __res; \ +}) + +#define write_r10k_perf_cntl(counter,val) \ +do { \ + __asm__ __volatile__( \ + "mtps\t%0, %1" \ + : \ + : "r" (val), "i" (counter)); \ +} while (0) + +/* + * Macros to access the system control coprocessor + */ + +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long long __res; \ + if (sizeof(unsigned long) == 4) \ + __res = __read_64bit_c0_split(source, sel); \ + else if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_64bit_c0_split(register, sel, value); \ + else if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ +} while (0) + +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + (unsigned long) __read_32bit_c0_register(reg, sel) : \ + (unsigned long) __read_64bit_c0_register(reg, sel)) + +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ +} while (0) + +/* + * On RM7000/RM9000 these are uses to access cop0 set 1 registers + */ +#define __read_32bit_c0_ctrl_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + "cfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_ctrl_register(register, value) \ +do { \ + __asm__ __volatile__( \ + "ctc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +/* + * These versions are only needed for systems with more than 38 bits of + * physical address space running the 32-bit kernel. That's none atm :-) + */ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long __val; \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (__val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (__val)); \ + local_irq_restore(__flags); \ + \ + __val; \ +}) + +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(__flags); \ +} while (0) + +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) + +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) + +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) + +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) + +#define read_c0_userlocal() __read_ulong_c0_register($4, 2) +#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) + +#define read_c0_info() __read_32bit_c0_register($7, 0) + +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) +#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) + +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) + +#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ +#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) + +#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ +#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) + +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) + +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) + +#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ +#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) + +#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ +#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) + +#define read_c0_status() __read_32bit_c0_register($12, 0) +#ifdef CONFIG_MIPS_MT_SMTC +#define write_c0_status(val) \ +do { \ + __write_32bit_c0_register($12, 0, val); \ + __ehb(); \ +} while (0) +#else +/* + * Legacy non-SMTC code, which may be hazardous + * but which might not support EHB + */ +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) +#endif /* CONFIG_MIPS_MT_SMTC */ + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) + +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define read_c0_config4() __read_32bit_c0_register($16, 4) +#define read_c0_config5() __read_32bit_c0_register($16, 5) +#define read_c0_config6() __read_32bit_c0_register($16, 6) +#define read_c0_config7() __read_32bit_c0_register($16, 7) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) + +/* + * The WatchLo register. There may be upto 8 of them. + */ +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) + +/* + * The WatchHi register. There may be upto 8 of them. + */ +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) + +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) + +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) + +#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) +#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) + +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) + +/* RM9000 PerfControl performance counter control register */ +#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) +#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_diag() __read_32bit_c0_register($22, 0) +#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_diag1() __read_32bit_c0_register($22, 1) +#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) + +#define read_c0_diag2() __read_32bit_c0_register($22, 2) +#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) + +#define read_c0_diag3() __read_32bit_c0_register($22, 3) +#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) + +#define read_c0_diag4() __read_32bit_c0_register($22, 4) +#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) + +#define read_c0_diag5() __read_32bit_c0_register($22, 5) +#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) + +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) + +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) + +/* + * MIPS32 / MIPS64 performance counters + */ +#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) +#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) +#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) +#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) +#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) +#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) +#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) +#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) +#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) +#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) +#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) +#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) +#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) + +/* RM9000 PerfCount performance counter register */ +#define read_c0_perfcount() __read_64bit_c0_register($25, 0) +#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) + +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) + +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) + +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) + +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) + +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) + +#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) +#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) + +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) + +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) + +/* MIPSR2 */ +#define read_c0_hwrena() __read_32bit_c0_register($7, 0) +#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_intctl() __read_32bit_c0_register($12, 1) +#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) + +#define read_c0_srsctl() __read_32bit_c0_register($12, 2) +#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) + +#define read_c0_srsmap() __read_32bit_c0_register($12, 3) +#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) + +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) /* - * R10000 performance counter definitions. + * Macros to access the floating point coprocessor control registers + */ +#define read_32bit_cp1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc1\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (mask)); \ +} while (0) + +#define mfhi0() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac0 \n" \ + " .word 0x00000810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi1() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac1 \n" \ + " .word 0x00200810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi2() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac2 \n" \ + " .word 0x00400810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi3() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac3 \n" \ + " .word 0x00600810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo0() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac0 \n" \ + " .word 0x00000812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo1() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac1 \n" \ + " .word 0x00200812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo2() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac2 \n" \ + " .word 0x00400812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo3() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac3 \n" \ + " .word 0x00600812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mthi0(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac0 \n" \ + " .word 0x00200011 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi1(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac1 \n" \ + " .word 0x00200811 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi2(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac2 \n" \ + " .word 0x00201011 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi3(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac3 \n" \ + " .word 0x00201811 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo0(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac0 \n" \ + " .word 0x00200013 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo1(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac1 \n" \ + " .word 0x00200813 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo2(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac2 \n" \ + " .word 0x00201013 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo3(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac3 \n" \ + " .word 0x00201813 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +/* + * TLB operations. * - * FIXME: The R10000 performance counter opens a nice way to implement CPU - * time accounting with a precission of one cycle. I don't have - * R10000 silicon but just a manual, so ... - */ - -/* - * Events counted by counter #0 - */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 - -/* - * Events counted by counter #1 - */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 - -/* - * These flags define in which priviledge mode the counters count events - */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + * It is responsibility of the caller to take care of any TLB hazards. + */ +static inline void tlb_probe(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); +} + +static inline void tlb_read(void) +{ +#if MIPS34K_MISSED_ITLB_WAR + int res = 0; + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41610001 # dvpe $1 \n" + " move %0, $1 \n" + " ehb \n" + " .set pop \n" + : "=r" (res)); + + instruction_hazard(); +#endif + + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); + +#if MIPS34K_MISSED_ITLB_WAR + if ((res & _ULCAST_(1))) + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41600021 # evpe \n" + " ehb \n" + " .set pop \n"); +#endif +} + +static inline void tlb_write_indexed(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); +} + +static inline void tlb_write_random(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); +} + +/* + * Manipulate bits in a c0 register. + */ +#define __BUILD_SET_C0(name) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ + \ + return res; \ +} + +__BUILD_SET_C0(status) +__BUILD_SET_C0(cause) +__BUILD_SET_C0(config) +__BUILD_SET_C0(intcontrol) +__BUILD_SET_C0(intctl) +__BUILD_SET_C0(srsmap) + +#endif /* !__ASSEMBLY__ */ #endif /* _ASM_MIPSREGS_H */ diff --git a/include/asm-mips/u-boot.h b/include/asm-mips/u-boot.h index d1273a4535..9ecb9ac327 100644 --- a/include/asm-mips/u-boot.h +++ b/include/asm-mips/u-boot.h @@ -38,7 +38,7 @@ typedef struct bd_info { unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h index a8cc987893..a56f939df3 100644 --- a/include/asm-nios/global_data.h +++ b/include/asm-nios/global_data.h @@ -30,7 +30,7 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ diff --git a/include/asm-nios/u-boot.h b/include/asm-nios/u-boot.h index aae4be13c4..3436185a8f 100644 --- a/include/asm-nios/u-boot.h +++ b/include/asm-nios/u-boot.h @@ -34,7 +34,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h index 729048917b..cd17e0894f 100644 --- a/include/asm-nios2/global_data.h +++ b/include/asm-nios2/global_data.h @@ -29,7 +29,7 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ diff --git a/include/asm-nios2/u-boot.h b/include/asm-nios2/u-boot.h index 3f299624ab..de8c4052f1 100644 --- a/include/asm-nios2/u-boot.h +++ b/include/asm-nios2/u-boot.h @@ -33,7 +33,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index 3264915d89..daa66cf918 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -152,6 +152,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr) } /* Return the bit position of the most significant 1 bit in a word */ +/* - the result is undefined when x == 0 */ extern __inline__ int __ilog2(unsigned int x) { int lz; @@ -167,6 +168,57 @@ extern __inline__ int ffz(unsigned int x) return __ilog2(x & -x); } +/* + * fls: find last (most-significant) bit set. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + * + * On powerpc, __ilog2(0) returns -1, but this is not safe in general + */ +static __inline__ int fls(unsigned int x) +{ + return __ilog2(x) + 1; +} + +/** + * fls64 - find last set bit in a 64-bit word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffsll, but returns the position of the most significant set bit. + * + * fls64(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 64. + */ +#if BITS_PER_LONG == 32 +static inline int fls64(__u64 x) +{ + __u32 h = x >> 32; + if (h) + return fls(h) + 32; + return fls(x); +} +#elif BITS_PER_LONG == 64 +static inline int fls64(__u64 x) +{ + if (x == 0) + return 0; + return __ilog2(x) + 1; +} +#else +#error BITS_PER_LONG not 32 or 64 +#endif + +static inline int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} + +static inline int ffs64(u64 x) +{ + return __ilog2_u64(x & -x) + 1ull; +} + #ifdef __KERNEL__ /* @@ -287,7 +339,7 @@ extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) #define ext2_find_first_zero_bit(addr, size) \ ext2_find_next_zero_bit((addr), (size), 0) -extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, +static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) { unsigned int *p = ((unsigned int *) addr) + (offset >> 5); diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index e955c756e8..227bf8326c 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -6,6 +6,9 @@ #define SET_LAW_ENTRY(idx, a, sz, trgt) \ { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } +#define SET_LAW(a, sz, trgt) \ + { .index = -1, .addr = a, .size = sz, .trgt_id = trgt } + enum law_size { LAW_SIZE_4K = 0xb, LAW_SIZE_8K, @@ -70,6 +73,8 @@ struct law_entry { }; extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); +extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); +extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern void disable_law(u8 idx); extern void init_laws(void); extern void print_laws(void); diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h new file mode 100644 index 0000000000..c4af7971b1 --- /dev/null +++ b/include/asm-ppc/fsl_lbc.h @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __ASM_PPC_FSL_LBC_H +#define __ASM_PPC_FSL_LBC_H + +#include <config.h> + +/* BR - Base Registers + */ +#define BR0 0x5000 /* Register offset to immr */ +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_DECC_OFF 0x00000000 +#define BR_DECC_CHK 0x00000200 +#define BR_DECC_CHK_GEN 0x00000400 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_FCM 0x00000020 /* FCM */ +#ifdef CONFIG_MPC83xx +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#elif defined(CONFIG_MPC85xx) +#define BR_MS_SDRAM 0x00000000 /* SDRAM */ +#endif +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#if !defined(CONFIG_MPC834X) +#define BR_ATOM 0x0000000C +#define BR_ATOM_SHIFT 2 +#endif +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 + +#define UPMA 0 +#define UPMB 1 +#define UPMC 2 + +#if defined(CONFIG_MPC834X) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) +#else +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) +#endif + +/* OR - Option Registers + */ +#define OR0 0x5004 /* Register offset to immr */ +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 +#define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD_SHIFT 12 +#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT_SHIFT 11 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_DIV2 0x00000600 +#define OR_GPCM_ACS_DIV4 0x00000400 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 + +/* helpers to convert values into an OR address mask (GPCM mode) */ +#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ +#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) + +#define OR_FCM_AM 0xFFFF8000 +#define OR_FCM_AM_SHIFT 15 +#define OR_FCM_BCTLD 0x00001000 +#define OR_FCM_BCTLD_SHIFT 12 +#define OR_FCM_PGS 0x00000400 +#define OR_FCM_PGS_SHIFT 10 +#define OR_FCM_CSCT 0x00000200 +#define OR_FCM_CSCT_SHIFT 9 +#define OR_FCM_CST 0x00000100 +#define OR_FCM_CST_SHIFT 8 +#define OR_FCM_CHT 0x00000080 +#define OR_FCM_CHT_SHIFT 7 +#define OR_FCM_SCY 0x00000070 +#define OR_FCM_SCY_SHIFT 4 +#define OR_FCM_SCY_1 0x00000010 +#define OR_FCM_SCY_2 0x00000020 +#define OR_FCM_SCY_3 0x00000030 +#define OR_FCM_SCY_4 0x00000040 +#define OR_FCM_SCY_5 0x00000050 +#define OR_FCM_SCY_6 0x00000060 +#define OR_FCM_SCY_7 0x00000070 +#define OR_FCM_RST 0x00000008 +#define OR_FCM_RST_SHIFT 3 +#define OR_FCM_TRLX 0x00000004 +#define OR_FCM_TRLX_SHIFT 2 +#define OR_FCM_EHTR 0x00000002 +#define OR_FCM_EHTR_SHIFT 1 + +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 + +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 + +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + +/* MxMR - UPM Machine A/B/C Mode Registers + */ +#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ +#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */ +#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */ +#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */ +#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */ +#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */ +#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */ +#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */ +#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */ +#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */ +#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */ +#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */ +#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */ +#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */ +#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */ +#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */ +#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */ +#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */ +#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */ +#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */ +#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ +#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */ +#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */ +#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ +#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ +#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ +#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ +#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ +#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ +#define MxMR_OP_WARR 0x10000000 /* Write to Array */ +#define MxMR_OP_RARR 0x20000000 /* Read from Array */ +#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */ +#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */ +#define MxMR_RFEN 0x40000000 /* Refresh Enable */ +#define MxMR_BSEL 0x80000000 /* Bus Select */ + +#define LBLAWAR_EN 0x80000000 +#define LBLAWAR_4KB 0x0000000B +#define LBLAWAR_8KB 0x0000000C +#define LBLAWAR_16KB 0x0000000D +#define LBLAWAR_32KB 0x0000000E +#define LBLAWAR_64KB 0x0000000F +#define LBLAWAR_128KB 0x00000010 +#define LBLAWAR_256KB 0x00000011 +#define LBLAWAR_512KB 0x00000012 +#define LBLAWAR_1MB 0x00000013 +#define LBLAWAR_2MB 0x00000014 +#define LBLAWAR_4MB 0x00000015 +#define LBLAWAR_8MB 0x00000016 +#define LBLAWAR_16MB 0x00000017 +#define LBLAWAR_32MB 0x00000018 +#define LBLAWAR_64MB 0x00000019 +#define LBLAWAR_128MB 0x0000001A +#define LBLAWAR_256MB 0x0000001B +#define LBLAWAR_512MB 0x0000001C +#define LBLAWAR_1GB 0x0000001D +#define LBLAWAR_2GB 0x0000001E + +/* LBCR - Local Bus Configuration Register + */ +#define LBCR_LDIS 0x80000000 +#define LBCR_LDIS_SHIFT 31 +#define LBCR_BCTLC 0x00C00000 +#define LBCR_BCTLC_SHIFT 22 +#define LBCR_LPBSE 0x00020000 +#define LBCR_LPBSE_SHIFT 17 +#define LBCR_EPAR 0x00010000 +#define LBCR_EPAR_SHIFT 16 +#define LBCR_BMT 0x0000FF00 +#define LBCR_BMT_SHIFT 8 + +/* LCRR - Clock Ratio Register + */ +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_BUFCMDC_1 0x10000000 +#define LCRR_BUFCMDC_2 0x20000000 +#define LCRR_BUFCMDC_3 0x30000000 +#define LCRR_BUFCMDC_4 0x00000000 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_ECL_4 0x00000000 +#define LCRR_ECL_5 0x01000000 +#define LCRR_ECL_6 0x02000000 +#define LCRR_ECL_7 0x03000000 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_EADC_1 0x00010000 +#define LCRR_EADC_2 0x00020000 +#define LCRR_EADC_3 0x00030000 +#define LCRR_EADC_4 0x00000000 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_SHIFT 0 +#define LCRR_CLKDIV_2 0x00000002 +#define LCRR_CLKDIV_4 0x00000004 +#define LCRR_CLKDIV_8 0x00000008 + +#endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index ea702662f8..c5ac6584ac 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -96,6 +96,9 @@ typedef struct global_data { uint mp_alloc_base; uint mp_alloc_top; #endif /* CONFIG_QE */ +#if defined(CONFIG_FSL_LAW) + u32 used_laws; +#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; @@ -113,7 +116,7 @@ typedef struct global_data { unsigned long pev_clk; unsigned long flb_clk; #endif - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ unsigned long env_addr; /* Address of Environment struct */ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 7cc28bfe3a..c3496818f0 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -238,6 +238,42 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + /* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 4f78ca7a94..050a7b6472 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -140,11 +140,16 @@ extern void _tlbia(void); /* invalidate all TLB entries */ typedef enum { IBAT0 = 0, IBAT1, IBAT2, IBAT3, - DBAT0, DBAT1, DBAT2, DBAT3 + DBAT0, DBAT1, DBAT2, DBAT3, +#ifdef CONFIG_HIGH_BATS + IBAT4, IBAT5, IBAT6, IBAT7, + DBAT4, DBAT5, DBAT6, DBAT7 +#endif } ppc_bat_t; extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); +extern void print_bats(void); #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h new file mode 100644 index 0000000000..83931f17f5 --- /dev/null +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -0,0 +1,1156 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_SDRAM_H_ +#define _PPC4xx_SDRAM_H_ + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM) + +/* + * SDRAM Controller + */ +/* + * XXX - ToDo: Revisit file to change all these lower case defines into + * upper case. Also needs to be done in the controller setup code too + * of course. sr, 2008-06-02 + */ +#ifndef CONFIG_405EP +#define mem_besra 0x00 /* bus error syndrome reg a */ +#define mem_besrsa 0x04 /* bus error syndrome reg set a */ +#define mem_besrb 0x08 /* bus error syndrome reg b */ +#define mem_besrsb 0x0c /* bus error syndrome reg set b */ +#define mem_bear 0x10 /* bus error address reg */ +#endif +#define mem_mcopt1 0x20 /* memory controller options 1 */ +#define mem_status 0x24 /* memory status */ +#define mem_rtr 0x30 /* refresh timer reg */ +#define mem_pmit 0x34 /* power management idle timer */ +#define mem_mb0cf 0x40 /* memory bank 0 configuration */ +#define mem_mb1cf 0x44 /* memory bank 1 configuration */ +#ifndef CONFIG_405EP +#define mem_mb2cf 0x48 /* memory bank 2 configuration */ +#define mem_mb3cf 0x4c /* memory bank 3 configuration */ +#endif +#define mem_sdtr1 0x80 /* timing reg 1 */ +#ifndef CONFIG_405EP +#define mem_ecccf 0x94 /* ECC configuration */ +#define mem_eccerr 0x98 /* ECC error status */ +#endif + +#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */ + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) + +/* + * Memory controller registers + */ +#define SDRAM_CFG0 0x20 /* memory controller options 0 */ +#define SDRAM_CFG1 0x21 /* memory controller options 1 */ + +/* + * XXX - ToDo: Revisit file to change all these lower case defines into + * upper case. Also needs to be done in the controller setup code too + * of course. sr, 2008-06-02 + */ +#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ +#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ +#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ +#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ +#define mem_bear 0x0010 /* bus error address reg */ +#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ +#define mem_mirq_set 0x0012 /* bus master interrupt (set) */ +#define mem_slio 0x0018 /* ddr sdram slave interface options */ +#define mem_cfg0 0x0020 /* ddr sdram options 0 */ +#define mem_cfg1 0x0021 /* ddr sdram options 1 */ +#define mem_devopt 0x0022 /* ddr sdram device options */ +#define mem_mcsts 0x0024 /* memory controller status */ +#define mem_rtr 0x0030 /* refresh timer register */ +#define mem_pmit 0x0034 /* power management idle timer */ +#define mem_uabba 0x0038 /* plb UABus base address */ +#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ +#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ +#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ +#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ +#define mem_tr0 0x0080 /* sdram timing register 0 */ +#define mem_tr1 0x0081 /* sdram timing register 1 */ +#define mem_clktr 0x0082 /* ddr clock timing register */ +#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ +#define mem_dlycal 0x0084 /* delay line calibration register */ +#define mem_eccesr 0x0098 /* ECC error status */ + +/* + * Memory Controller Options 0 + */ +#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ +#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ +#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ +#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ +#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ +#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ +#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ + +/* + * Memory Controller Options 1 + */ +#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ +#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ + +/* + * SDRAM DEVPOT Options + */ +#define SDRAM_DEVOPT_DLL 0x80000000 +#define SDRAM_DEVOPT_DS 0x40000000 + +/* + * SDRAM MCSTS Options + */ +#define SDRAM_MCSTS_MRSC 0x80000000 +#define SDRAM_MCSTS_SRMS 0x40000000 +#define SDRAM_MCSTS_CIS 0x20000000 + +/* + * SDRAM Refresh Timer Register + */ +#define SDRAM_RTR_RINT_MASK 0xFFFF0000 +#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) + +/* + * SDRAM UABus Base Address Reg + */ +#define SDRAM_UABBA_UBBA_MASK 0x0000000F + +/* + * Memory Bank 0-7 configuration + */ +#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ +#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ +#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ +#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ +#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ +#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ +#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ +#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ +#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ +#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ +#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ +#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ +#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ +#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ +#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ + +/* + * SDRAM TR0 Options + */ +#define SDRAM_TR0_SDWR_MASK 0x80000000 +#define SDRAM_TR0_SDWR_2_CLK 0x00000000 +#define SDRAM_TR0_SDWR_3_CLK 0x80000000 +#define SDRAM_TR0_SDWD_MASK 0x40000000 +#define SDRAM_TR0_SDWD_0_CLK 0x00000000 +#define SDRAM_TR0_SDWD_1_CLK 0x40000000 +#define SDRAM_TR0_SDCL_MASK 0x01800000 +#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 +#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 +#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 +#define SDRAM_TR0_SDPA_MASK 0x000C0000 +#define SDRAM_TR0_SDPA_2_CLK 0x00040000 +#define SDRAM_TR0_SDPA_3_CLK 0x00080000 +#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 +#define SDRAM_TR0_SDCP_MASK 0x00030000 +#define SDRAM_TR0_SDCP_2_CLK 0x00000000 +#define SDRAM_TR0_SDCP_3_CLK 0x00010000 +#define SDRAM_TR0_SDCP_4_CLK 0x00020000 +#define SDRAM_TR0_SDCP_5_CLK 0x00030000 +#define SDRAM_TR0_SDLD_MASK 0x0000C000 +#define SDRAM_TR0_SDLD_1_CLK 0x00000000 +#define SDRAM_TR0_SDLD_2_CLK 0x00004000 +#define SDRAM_TR0_SDRA_MASK 0x0000001C +#define SDRAM_TR0_SDRA_6_CLK 0x00000000 +#define SDRAM_TR0_SDRA_7_CLK 0x00000004 +#define SDRAM_TR0_SDRA_8_CLK 0x00000008 +#define SDRAM_TR0_SDRA_9_CLK 0x0000000C +#define SDRAM_TR0_SDRA_10_CLK 0x00000010 +#define SDRAM_TR0_SDRA_11_CLK 0x00000014 +#define SDRAM_TR0_SDRA_12_CLK 0x00000018 +#define SDRAM_TR0_SDRA_13_CLK 0x0000001C +#define SDRAM_TR0_SDRD_MASK 0x00000003 +#define SDRAM_TR0_SDRD_2_CLK 0x00000001 +#define SDRAM_TR0_SDRD_3_CLK 0x00000002 +#define SDRAM_TR0_SDRD_4_CLK 0x00000003 + +/* + * SDRAM TR1 Options + */ +#define SDRAM_TR1_RDSS_MASK 0xC0000000 +#define SDRAM_TR1_RDSS_TR0 0x00000000 +#define SDRAM_TR1_RDSS_TR1 0x40000000 +#define SDRAM_TR1_RDSS_TR2 0x80000000 +#define SDRAM_TR1_RDSS_TR3 0xC0000000 +#define SDRAM_TR1_RDSL_MASK 0x00C00000 +#define SDRAM_TR1_RDSL_STAGE1 0x00000000 +#define SDRAM_TR1_RDSL_STAGE2 0x00400000 +#define SDRAM_TR1_RDSL_STAGE3 0x00800000 +#define SDRAM_TR1_RDCD_MASK 0x00000800 +#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 +#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 +#define SDRAM_TR1_RDCT_MASK 0x000001FF +#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) +#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) +#define SDRAM_TR1_RDCT_MIN 0x00000000 +#define SDRAM_TR1_RDCT_MAX 0x000001FF + +/* + * SDRAM WDDCTR Options + */ +#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 +#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 +#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 +#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 +#define SDRAM_WDDCTR_DCD_MASK 0x000001FF + +/* + * SDRAM CLKTR Options + */ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 +#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 +#define SDRAM_CLKTR_DCDT_MASK 0x000001FF + +/* + * SDRAM DLYCAL Options + */ +#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC +#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) +#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) + +#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */ + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) + +#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC +#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) +#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) + +/* + * Memory queue defines + */ +#define SDRAMQ_DCR_BASE 0x040 + +#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ +#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ +#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ +#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ +#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ +#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ +#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ +#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ +#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ +#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ +#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ +#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ +#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ +#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ +#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ + +#if !defined(CONFIG_405EX) +/* + * Memory Bank 0-7 configuration + */ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ +#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFFE00000)>>2) +#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFFE00000)<<2) +#endif /* CONFIG_440SPE */ +#if defined(CONFIG_440SP) +#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ +#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000)) +#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000)) +#endif /* CONFIG_440SP */ +#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ +#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6) +#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF) +#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */ +#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */ +#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */ +#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */ +#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */ +#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */ +#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */ +#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */ +#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */ +#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */ +#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */ +#else /* CONFIG_405EX */ +/* + * XXX - ToDo: + * Revisit this file to check if all these 405EX defines are correct and + * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02 + */ +#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF) +#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0) +#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1) +#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2) +#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3) +#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4) +#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5) +#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6) +#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7) +#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8) +#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9) +#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA) +#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB) +#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB +#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB +#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB +#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB +#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB +#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB +#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB +#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB +#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB +#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB +#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB +#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0) +#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1) +#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2) +#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3) +#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4) +#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5) +#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6) +#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7) +#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8) +#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9) +#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0) +#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1) +#endif /* CONFIG_405EX */ + +/* + * Memory controller registers + */ +#define SDRAM_MCSTAT 0x14 /* memory controller status */ +#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ +#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ +#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ +#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ +#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ +#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ +#define SDRAM_CODT 0x26 /* on die termination for controller */ +#define SDRAM_VVPR 0x27 /* variable VRef programmming */ +#define SDRAM_OPARS 0x28 /* on chip driver control setup */ +#define SDRAM_OPART 0x29 /* on chip driver control trigger */ +#define SDRAM_RTR 0x30 /* refresh timer */ +#define SDRAM_PMIT 0x34 /* power management idle timer */ +#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ +#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ +#define SDRAM_MB2CF 0x48 +#define SDRAM_MB3CF 0x4C +#define SDRAM_INITPLR0 0x50 /* manual initialization control */ +#define SDRAM_INITPLR1 0x51 /* manual initialization control */ +#define SDRAM_INITPLR2 0x52 /* manual initialization control */ +#define SDRAM_INITPLR3 0x53 /* manual initialization control */ +#define SDRAM_INITPLR4 0x54 /* manual initialization control */ +#define SDRAM_INITPLR5 0x55 /* manual initialization control */ +#define SDRAM_INITPLR6 0x56 /* manual initialization control */ +#define SDRAM_INITPLR7 0x57 /* manual initialization control */ +#define SDRAM_INITPLR8 0x58 /* manual initialization control */ +#define SDRAM_INITPLR9 0x59 /* manual initialization control */ +#define SDRAM_INITPLR10 0x5a /* manual initialization control */ +#define SDRAM_INITPLR11 0x5b /* manual initialization control */ +#define SDRAM_INITPLR12 0x5c /* manual initialization control */ +#define SDRAM_INITPLR13 0x5d /* manual initialization control */ +#define SDRAM_INITPLR14 0x5e /* manual initialization control */ +#define SDRAM_INITPLR15 0x5f /* manual initialization control */ +#define SDRAM_RQDC 0x70 /* read DQS delay control */ +#define SDRAM_RFDC 0x74 /* read feedback delay control */ +#define SDRAM_RDCC 0x78 /* read data capture control */ +#define SDRAM_DLCR 0x7A /* delay line calibration */ +#define SDRAM_CLKTR 0x80 /* DDR clock timing */ +#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ +#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ +#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ +#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ +#define SDRAM_MMODE 0x88 /* memory mode */ +#define SDRAM_MEMODE 0x89 /* memory extended mode */ +#define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_CID 0xA4 /* core ID */ +#define SDRAM_RID 0xA8 /* revision ID */ +#define SDRAM_RTSR 0xB1 /* run time status tracking */ + +/* + * Memory Controller Status + */ +#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ +#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ +#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ +#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */ +#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */ +#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */ + +/* + * Memory Controller Options 1 + */ +#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/ +#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ +#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ +#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3) +#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ +#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ +#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ +#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ +#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ +#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ +#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ +#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ +#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ +#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ +#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ +#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ +#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ +#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ +#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ +#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ +#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ +#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ +#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ +#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ +#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ +#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ +#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ +#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ + +/* + * Memory Controller Options 2 + */ +#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ +#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ +#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ +#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ +#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ +#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ +#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ +#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ +#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ +#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ +#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ +#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ +#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ + +/* + * SDRAM Refresh Timer Register + */ +#define SDRAM_RTR_RINT_MASK 0xFFF80000 +#define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16) +#define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8) + +/* + * SDRAM Read DQS Delay Control Register + */ +#define SDRAM_RQDC_RQDE_MASK 0x80000000 +#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 +#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 +#define SDRAM_RQDC_RQFD_MASK 0x000001FF +#define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0) + +#define SDRAM_RQDC_RQFD_MAX 0x1FF + +/* + * SDRAM Read Data Capture Control Register + */ +#define SDRAM_RDCC_RDSS_MASK 0xC0000000 +#define SDRAM_RDCC_RDSS_T1 0x00000000 +#define SDRAM_RDCC_RDSS_T2 0x40000000 +#define SDRAM_RDCC_RDSS_T3 0x80000000 +#define SDRAM_RDCC_RDSS_T4 0xC0000000 +#define SDRAM_RDCC_RSAE_MASK 0x00000001 +#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 +#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 + +/* + * SDRAM Read Feedback Delay Control Register + */ +#define SDRAM_RFDC_ARSE_MASK 0x80000000 +#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 +#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 +#define SDRAM_RFDC_RFOS_MASK 0x007F0000 +#define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16) +#define SDRAM_RFDC_RFFD_MASK 0x000007FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0) + +#define SDRAM_RFDC_RFFD_MAX 0x7FF + +/* + * SDRAM Delay Line Calibration Register + */ +#define SDRAM_DLCR_DCLM_MASK 0x80000000 +#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_AUTO 0x00000000 +#define SDRAM_DLCR_DLCR_MASK 0x08000000 +#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 +#define SDRAM_DLCR_DLCR_IDLE 0x00000000 +#define SDRAM_DLCR_DLCS_MASK 0x07000000 +#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 +#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 +#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 +#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 +#define SDRAM_DLCR_DLCS_ERROR 0x04000000 +#define SDRAM_DLCR_DLCV_MASK 0x000001FF +#define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0) +#define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF) + +/* + * SDRAM Controller On Die Termination Register + */ +#define SDRAM_CODT_ODT_ON 0x80000000 +#define SDRAM_CODT_ODT_OFF 0x00000000 +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 +#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 +#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 +#define SDRAM_CODT_DQS_MASK 0x00000010 +#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 +#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 + +/* + * SDRAM Mode Register + */ +#define SDRAM_MMODE_WR_MASK 0x00000E00 +#define SDRAM_MMODE_WR_DDR1 0x00000000 +#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 +#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 +#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 +#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 +#define SDRAM_MMODE_DCL_MASK 0x00000070 +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 + +/* + * SDRAM Extended Mode Register + */ +#define SDRAM_MEMODE_DIC_MASK 0x00000002 +#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 +#define SDRAM_MEMODE_DIC_WEAK 0x00000002 +#define SDRAM_MEMODE_DLL_MASK 0x00000001 +#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 +#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 +#define SDRAM_MEMODE_RTT_MASK 0x00000044 +#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 +#define SDRAM_MEMODE_RTT_75OHM 0x00000004 +#define SDRAM_MEMODE_RTT_150OHM 0x00000040 +#define SDRAM_MEMODE_DQS_MASK 0x00000400 +#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 +#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 + +/* + * SDRAM Clock Timing Register + */ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 +#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000 +#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000 + +/* + * SDRAM Write Timing Register + */ +#define SDRAM_WRDTR_LLWP_MASK 0x10000000 +#define SDRAM_WRDTR_LLWP_DIS 0x10000000 +#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 +#define SDRAM_WRDTR_WTR_MASK 0x0E000000 +#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000 +#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 +#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 + +/* + * SDRAM SDTR1 Options + */ +#define SDRAM_SDTR1_LDOF_MASK 0x80000000 +#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 +#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 +#define SDRAM_SDTR1_RTW_MASK 0x00F00000 +#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 +#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 +#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 +#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 +#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 +#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 +#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000 +#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 + +/* + * SDRAM SDTR2 Options + */ +#define SDRAM_SDTR2_RCD_MASK 0xF0000000 +#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 +#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 +#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 +#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 +#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 +#define SDRAM_SDTR2_WTR_MASK 0x0F000000 +#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 +#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 +#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 +#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 +#define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24) +#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 +#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 +#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 +#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 +#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 +#define SDRAM_SDTR2_WPC_MASK 0x0000F000 +#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 +#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 +#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 +#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 +#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 +#define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12) +#define SDRAM_SDTR2_RPC_MASK 0x00000F00 +#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 +#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 +#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 +#define SDRAM_SDTR2_RP_MASK 0x000000F0 +#define SDRAM_SDTR2_RP_3_CLK 0x00000030 +#define SDRAM_SDTR2_RP_4_CLK 0x00000040 +#define SDRAM_SDTR2_RP_5_CLK 0x00000050 +#define SDRAM_SDTR2_RP_6_CLK 0x00000060 +#define SDRAM_SDTR2_RP_7_CLK 0x00000070 +#define SDRAM_SDTR2_RRD_MASK 0x0000000F +#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 +#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 + +/* + * SDRAM SDTR3 Options + */ +#define SDRAM_SDTR3_RAS_MASK 0x1F000000 +#define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24) +#define SDRAM_SDTR3_RC_MASK 0x001F0000 +#define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16) +#define SDRAM_SDTR3_XCS_MASK 0x00001F00 +#define SDRAM_SDTR3_XCS 0x00000D00 +#define SDRAM_SDTR3_RFC_MASK 0x0000003F +#define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0) + +/* + * Memory Bank 0-1 configuration + */ +#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ +#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ +#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ +#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ +#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ +#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ +#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ +#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ +#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ +#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ +#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ +#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ + +#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/ +#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */ +#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */ +#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */ +#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */ + +#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ + +#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */ + +#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2) +/* + * SDRAM Controller + */ +#define DDR0_00 0x00 +#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24) +#define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F) +/* Status */ +#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ +/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT0 0x00010000 +/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT1 0x00020000 +/* Bit2. Single correctable ECC event detected */ +#define DDR0_00_INT_STATUS_BIT2 0x00040000 +/* Bit3. Multiple correctable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT3 0x00080000 +/* Bit4. Single uncorrectable ECC event detected. */ +#define DDR0_00_INT_STATUS_BIT4 0x00100000 +/* Bit5. Multiple uncorrectable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT5 0x00200000 +/* Bit6. DRAM initialization complete. */ +#define DDR0_00_INT_STATUS_BIT6 0x00400000 +/* Bit7. Logical OR of all lower bits. */ +#define DDR0_00_INT_STATUS_BIT7 0x00800000 + +#define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16) +#define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF) +#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 +#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F) +#define DDR0_00_DLL_START_POINT_MASK 0x0000007F +#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_01 0x01 +#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 +#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24) +#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F) +#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 +#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16) +#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F) +#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ +#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8) +#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7) +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0) +#define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF) +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_02 0x02 +#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ +#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24) +#define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2) +#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ +#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16) +#define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF) +#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ +#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8) +#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF) +#define DDR0_02_START_MASK 0x00000001 +#define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1) +#define DDR0_02_START_OFF 0x00000000 +#define DDR0_02_START_ON 0x00000001 + +#define DDR0_03 0x03 +#define DDR0_03_BSTLEN_MASK 0x07000000 +#define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24) +#define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7) +#define DDR0_03_CASLAT_MASK 0x00070000 +#define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16) +#define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7) +#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 +#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8) +#define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF) +#define DDR0_03_INITAREF_MASK 0x0000000F +#define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0) +#define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF) + +#define DDR0_04 0x04 +#define DDR0_04_TRC_MASK 0x1F000000 +#define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24) +#define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F) +#define DDR0_04_TRRD_MASK 0x00070000 +#define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16) +#define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7) +#define DDR0_04_TRTP_MASK 0x00000700 +#define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8) +#define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7) + +#define DDR0_05 0x05 +#define DDR0_05_TMRD_MASK 0x1F000000 +#define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24) +#define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F) +#define DDR0_05_TEMRS_MASK 0x00070000 +#define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16) +#define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7) +#define DDR0_05_TRP_MASK 0x00000F00 +#define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8) +#define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF) +#define DDR0_05_TRAS_MIN_MASK 0x000000FF +#define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0) +#define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF) + +#define DDR0_06 0x06 +#define DDR0_06_WRITEINTERP_MASK 0x01000000 +#define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24) +#define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1) +#define DDR0_06_TWTR_MASK 0x00070000 +#define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16) +#define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7) +#define DDR0_06_TDLL_MASK 0x0000FF00 +#define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8) +#define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF) +#define DDR0_06_TRFC_MASK 0x0000007F +#define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_07 0x07 +#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 +#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24) +#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1) +#define DDR0_07_TFAW_MASK 0x001F0000 +#define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16) +#define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F) +#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 +#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8) +#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1) +#define DDR0_07_AREFRESH_MASK 0x00000001 +#define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1) + +#define DDR0_08 0x08 +#define DDR0_08_WRLAT_MASK 0x07000000 +#define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24) +#define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7) +#define DDR0_08_TCPD_MASK 0x00FF0000 +#define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16) +#define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF) +#define DDR0_08_DQS_N_EN_MASK 0x00000100 +#define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8) +#define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1) +#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 +#define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1) + +#define DDR0_09 0x09 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24) +#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F) +#define DDR0_09_RTT_0_MASK 0x00030000 +#define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16) +#define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 +#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F) +#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F +#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_10 0x0A +#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ +#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16) +#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1) +#define DDR0_10_CS_MAP_MASK 0x00000300 +#define DDR0_10_CS_MAP_NO_MEM 0x00000000 +#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 +#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 +#define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8) +#define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F +#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F) + +#define DDR0_11 0x0B +#define DDR0_11_SREFRESH_MASK 0x01000000 +#define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24) +#define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F) +#define DDR0_11_TXSNR_MASK 0x00FF0000 +#define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16) +#define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF) +#define DDR0_11_TXSR_MASK 0x0000FF00 +#define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8) +#define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF) + +#define DDR0_12 0x0C +#define DDR0_12_TCKE_MASK 0x0000007 +#define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0) +#define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7) + +#define DDR0_14 0x0E +#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 +#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24) +#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1) +#define DDR0_14_REDUC_MASK 0x00010000 +#define DDR0_14_REDUC_64BITS 0x00000000 +#define DDR0_14_REDUC_32BITS 0x00010000 +#define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16) +#define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1) +#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 +#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8) +#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1) + +#define DDR0_17 0x11 +#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 +#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24) +#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F) +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16) +#define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1) +#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ +#define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F) + +#define DDR0_18 0x12 +#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 +#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24) +#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 +#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16) +#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 +#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F +#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_19 0x13 +#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 +#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24) +#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 +#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16) +#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 +#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F +#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_20 0x14 +#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 +#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24) +#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 +#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16) +#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 +#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F +#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_21 0x15 +#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 +#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24) +#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 +#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16) +#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 +#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F +#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_22 0x16 +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 +#define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24) +#define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F) +#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 +#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8) +#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F) +#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F +#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0) +#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F) + +#define DDR0_23 0x17 +#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 +#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24) +#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3) +#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ +#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16) +#define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF) +#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ +#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8) +#define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF) +#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ +#define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1) + +#define DDR0_24 0x18 +#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 +#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24) +#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3) +#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 +#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16) +#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3) +#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 +#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8) +#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3) +#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 +#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0) +#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3) + +#define DDR0_25 0x19 +#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ +#define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16) +#define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF) +#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ +#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0) +#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF) + +#define DDR0_26 0x1A +#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 +#define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16) +#define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF) +#define DDR0_26_TREF_MASK 0x00003FFF +#define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF) + +#define DDR0_27 0x1B +#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 +#define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16) +#define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF) +#define DDR0_27_TINIT_MASK 0x0000FFFF +#define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0) +#define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF) + +#define DDR0_28 0x1C +#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 +#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16) +#define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF) +#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF +#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0) +#define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF) + +#define DDR0_31 0x1F +#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF +#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0) +#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF) + +#define DDR0_32 0x20 +#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) +#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) + +#define DDR0_33 0x21 +#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1) + +#define DDR0_34 0x22 +#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) +#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) + +#define DDR0_35 0x23 +#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1) + +#define DDR0_36 0x24 +#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) +#define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) + +#define DDR0_37 0x25 +#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) +#define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) + +#define DDR0_38 0x26 +#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) +#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) + +#define DDR0_39 0x27 +#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1) + +#define DDR0_40 0x28 +#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) +#define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) + +#define DDR0_41 0x29 +#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) +#define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) + +#define DDR0_42 0x2A +#define DDR0_42_ADDR_PINS_MASK 0x07000000 +#define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24) +#define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7) +#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F +#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0) +#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF) + +#define DDR0_43 0x2B +#define DDR0_43_TWR_MASK 0x07000000 +#define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24) +#define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7) +#define DDR0_43_APREBIT_MASK 0x000F0000 +#define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16) +#define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF) +#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 +#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8) +#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7) +#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 +#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0) +#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1) + +#define DDR0_44 0x2C +#define DDR0_44_TRCD_MASK 0x000000FF +#define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0) +#define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF) + +#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */ + +#endif /* _PPC4xx_SDRAM_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 8bdfb9ddf3..10fd478bab 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -460,17 +460,19 @@ #define SPRN_PID2 0x27a /* Process ID Register 2 */ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define SPRN_MCAR 0x23d /* Machine Check Address register */ -#ifdef CONFIG_440 #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#if defined(CONFIG_440) #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#else +#define MCSR_DB 0x20000000 /* Data PLB Error */ +#endif /* defined(CONFIG_440) */ #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#endif #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) @@ -960,6 +962,24 @@ n: #define SR15 15 #ifndef __ASSEMBLY__ + +struct cpu_type { + char name[15]; + u32 soc_ver; +}; + +struct cpu_type *identify_cpu(u32 ver); + +#if defined(CONFIG_MPC85xx) +#define CPU_TYPE_ENTRY(n, v) \ + { .name = #n, .soc_ver = SVR_##v, } +#else +#if defined(CONFIG_MPC83XX) +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} +#endif +#endif + + #ifndef CONFIG_MACH_SPECIFIC extern int _machine; extern int have_of; diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 83af2f584e..54ac01d362 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -38,7 +38,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index c200ba5a46..5a8a5a149c 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -35,6 +35,8 @@ # include <asm/cpu_sh7750.h> #elif defined (CONFIG_CPU_SH7722) # include <asm/cpu_sh7722.h> +#elif defined (CONFIG_CPU_SH7763) +# include <asm/cpu_sh7763.h> #elif defined (CONFIG_CPU_SH7780) # include <asm/cpu_sh7780.h> #else diff --git a/include/asm-sh/cpu_sh7763.h b/include/asm-sh/cpu_sh7763.h new file mode 100644 index 0000000000..78b456b4b2 --- /dev/null +++ b/include/asm-sh/cpu_sh7763.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_CPU_SH7763_H_ +#define _ASM_CPU_SH7763_H_ + +/* CACHE */ +#define CACHE_OC_NUM_WAYS 1 +#define CCR 0xFF00001C +#define CCR_CACHE_INIT 0x0000090b + +/* SCIF */ +/* SCIF0 */ +#define SCIF0_BASE SCSMR0 +#define SCSMR0 0xFFE00000 + +/* SCIF1 */ +#define SCIF1_BASE SCSMR1 +#define SCSMR1 0xFFE08000 + +/* SCIF2 */ +#define SCIF2_BASE SCSMR2 +#define SCSMR2 0xFFE10000 + +/* Watchdog Timer */ +#define WTCNT WDTST +#define WDTST 0xFFCC0000 + +/* TMU */ +#define TSTR 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 + +#endif /* _ASM_CPU_SH7763_H_ */ diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h index 69af24a770..d61421b687 100644 --- a/include/asm-sh/global_data.h +++ b/include/asm-sh/global_data.h @@ -34,7 +34,7 @@ typedef struct global_data unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h index b79644cfd2..e89c1936ff 100644 --- a/include/asm-sh/u-boot.h +++ b/include/asm-sh/u-boot.h @@ -27,7 +27,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-sparc/global_data.h b/include/asm-sparc/global_data.h index de2c84b22b..a8d85f1b5c 100644 --- a/include/asm-sparc/global_data.h +++ b/include/asm-sparc/global_data.h @@ -46,7 +46,7 @@ typedef struct global_data { unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; - unsigned long ram_size; /* RAM size */ + phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ unsigned long env_addr; /* Address of Environment struct */ diff --git a/include/asm-sparc/io.h b/include/asm-sparc/io.h index 2a27d06798..ede0b1a8db 100644 --- a/include/asm-sparc/io.h +++ b/include/asm-sparc/io.h @@ -70,7 +70,6 @@ * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h index 69f93d60b8..2cf974a7a9 100644 --- a/include/asm-sparc/types.h +++ b/include/asm-sparc/types.h @@ -65,6 +65,9 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-sparc/u-boot.h b/include/asm-sparc/u-boot.h index 9c594e1f8c..c42e93cbef 100644 --- a/include/asm-sparc/u-boot.h +++ b/include/asm-sparc/u-boot.h @@ -44,7 +44,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/atmel_lcdc.h b/include/atmel_lcdc.h new file mode 100644 index 0000000000..73dd8f7693 --- /dev/null +++ b/include/atmel_lcdc.h @@ -0,0 +1,177 @@ +/* + * Header file for AT91/AT32 LCD Controller + * + * Data structure and register user interface + * + * Copyright (C) 2007 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ATMEL_LCDC_H__ +#define __ATMEL_LCDC_H__ + +#define ATMEL_LCDC_DMABADDR1 0x00 +#define ATMEL_LCDC_DMABADDR2 0x04 +#define ATMEL_LCDC_DMAFRMPT1 0x08 +#define ATMEL_LCDC_DMAFRMPT2 0x0c +#define ATMEL_LCDC_DMAFRMADD1 0x10 +#define ATMEL_LCDC_DMAFRMADD2 0x14 + +#define ATMEL_LCDC_DMAFRMCFG 0x18 +#define ATMEL_LCDC_FRSIZE (0x7fffff << 0) +#define ATMEL_LCDC_BLENGTH_OFFSET 24 +#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) + +#define ATMEL_LCDC_DMACON 0x1c +#define ATMEL_LCDC_DMAEN (0x1 << 0) +#define ATMEL_LCDC_DMARST (0x1 << 1) +#define ATMEL_LCDC_DMABUSY (0x1 << 2) +#define ATMEL_LCDC_DMAUPDT (0x1 << 3) +#define ATMEL_LCDC_DMA2DEN (0x1 << 4) + +#define ATMEL_LCDC_DMA2DCFG 0x20 +#define ATMEL_LCDC_ADDRINC_OFFSET 0 +#define ATMEL_LCDC_ADDRINC (0xffff) +#define ATMEL_LCDC_PIXELOFF_OFFSET 24 +#define ATMEL_LCDC_PIXELOFF (0x1f << 24) + +#define ATMEL_LCDC_LCDCON1 0x0800 +#define ATMEL_LCDC_BYPASS (1 << 0) +#define ATMEL_LCDC_CLKVAL_OFFSET 12 +#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) +#define ATMEL_LCDC_LINCNT (0x7ff << 21) + +#define ATMEL_LCDC_LCDCON2 0x0804 +#define ATMEL_LCDC_DISTYPE (3 << 0) +#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) +#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) +#define ATMEL_LCDC_DISTYPE_TFT (2 << 0) +#define ATMEL_LCDC_SCANMOD (1 << 2) +#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) +#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) +#define ATMEL_LCDC_IFWIDTH (3 << 3) +#define ATMEL_LCDC_IFWIDTH_4 (0 << 3) +#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) +#define ATMEL_LCDC_IFWIDTH_16 (2 << 3) +#define ATMEL_LCDC_PIXELSIZE (7 << 5) +#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) +#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) +#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) +#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) +#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) +#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) +#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) +#define ATMEL_LCDC_INVVD (1 << 8) +#define ATMEL_LCDC_INVVD_NORMAL (0 << 8) +#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) +#define ATMEL_LCDC_INVFRAME (1 << 9 ) +#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) +#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) +#define ATMEL_LCDC_INVLINE (1 << 10) +#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) +#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) +#define ATMEL_LCDC_INVCLK (1 << 11) +#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) +#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) +#define ATMEL_LCDC_INVDVAL (1 << 12) +#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) +#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) +#define ATMEL_LCDC_CLKMOD (1 << 15) +#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) +#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) +#define ATMEL_LCDC_MEMOR (1 << 31) +#define ATMEL_LCDC_MEMOR_BIG (0 << 31) +#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) + +#define ATMEL_LCDC_TIM1 0x0808 +#define ATMEL_LCDC_VFP (0xffU << 0) +#define ATMEL_LCDC_VBP_OFFSET 8 +#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET) +#define ATMEL_LCDC_VPW_OFFSET 16 +#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET) +#define ATMEL_LCDC_VHDLY_OFFSET 24 +#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET) + +#define ATMEL_LCDC_TIM2 0x080c +#define ATMEL_LCDC_HBP (0xffU << 0) +#define ATMEL_LCDC_HPW_OFFSET 8 +#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET) +#define ATMEL_LCDC_HFP_OFFSET 21 +#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET) + +#define ATMEL_LCDC_LCDFRMCFG 0x0810 +#define ATMEL_LCDC_LINEVAL (0x7ff << 0) +#define ATMEL_LCDC_HOZVAL_OFFSET 21 +#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) + +#define ATMEL_LCDC_FIFO 0x0814 +#define ATMEL_LCDC_FIFOTH (0xffff) + +#define ATMEL_LCDC_MVAL 0x0818 + +#define ATMEL_LCDC_DP1_2 0x081c +#define ATMEL_LCDC_DP4_7 0x0820 +#define ATMEL_LCDC_DP3_5 0x0824 +#define ATMEL_LCDC_DP2_3 0x0828 +#define ATMEL_LCDC_DP5_7 0x082c +#define ATMEL_LCDC_DP3_4 0x0830 +#define ATMEL_LCDC_DP4_5 0x0834 +#define ATMEL_LCDC_DP6_7 0x0838 +#define ATMEL_LCDC_DP1_2_VAL (0xff) +#define ATMEL_LCDC_DP4_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_5_VAL (0xfffff) +#define ATMEL_LCDC_DP2_3_VAL (0xfff) +#define ATMEL_LCDC_DP5_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_4_VAL (0xffff) +#define ATMEL_LCDC_DP4_5_VAL (0xfffff) +#define ATMEL_LCDC_DP6_7_VAL (0xfffffff) + +#define ATMEL_LCDC_PWRCON 0x083c +#define ATMEL_LCDC_PWR (1 << 0) +#define ATMEL_LCDC_GUARDT_OFFSET 1 +#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) +#define ATMEL_LCDC_BUSY (1 << 31) + +#define ATMEL_LCDC_CONTRAST_CTR 0x0840 +#define ATMEL_LCDC_PS (3 << 0) +#define ATMEL_LCDC_PS_DIV1 (0 << 0) +#define ATMEL_LCDC_PS_DIV2 (1 << 0) +#define ATMEL_LCDC_PS_DIV4 (2 << 0) +#define ATMEL_LCDC_PS_DIV8 (3 << 0) +#define ATMEL_LCDC_POL (1 << 2) +#define ATMEL_LCDC_POL_NEGATIVE (0 << 2) +#define ATMEL_LCDC_POL_POSITIVE (1 << 2) +#define ATMEL_LCDC_ENA (1 << 3) +#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) +#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) + +#define ATMEL_LCDC_CONTRAST_VAL 0x0844 +#define ATMEL_LCDC_CVAL (0xff) + +#define ATMEL_LCDC_IER 0x0848 +#define ATMEL_LCDC_IDR 0x084c +#define ATMEL_LCDC_IMR 0x0850 +#define ATMEL_LCDC_ISR 0x0854 +#define ATMEL_LCDC_ICR 0x0858 +#define ATMEL_LCDC_LNI (1 << 0) +#define ATMEL_LCDC_LSTLNI (1 << 1) +#define ATMEL_LCDC_EOFI (1 << 2) +#define ATMEL_LCDC_UFLWI (1 << 4) +#define ATMEL_LCDC_OWRI (1 << 5) +#define ATMEL_LCDC_MERI (1 << 6) + +#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) + +#endif /* __ATMEL_LCDC_H__ */ diff --git a/include/common.h b/include/common.h index d0f57040ee..2fcb1fd379 100644 --- a/include/common.h +++ b/include/common.h @@ -176,6 +176,17 @@ typedef void (interrupt_handler_t)(void *); (__x > __y) ? __x : __y; }) +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + /* * Function Prototypes */ @@ -191,9 +202,9 @@ int serial_buffered_tstc (void); void hang (void) __attribute__ ((noreturn)); /* */ -long int initdram (int); +phys_size_t initdram (int); int display_options (void); -void print_size (ulong, const char *); +void print_size (phys_size_t, const char *); int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen); /* common/main.c */ @@ -232,9 +243,9 @@ char *getenv (char *); int getenv_r (char *name, char *buf, unsigned len); int saveenv (void); #ifdef CONFIG_PPC /* ARM version to be fixed! */ -void inline setenv (char *, char *); +int inline setenv (char *, char *); #else -void setenv (char *, char *); +int setenv (char *, char *); #ifdef CONFIG_HAS_UID void forceenv (char *, char *); #endif @@ -596,8 +607,10 @@ ulong simple_strtoul(const char *cp,char **endp,unsigned int base); unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); #endif long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...); -int sprintf(char * buf, const char *fmt, ...); +void panic(const char *fmt, ...) + __attribute__ ((format (__printf__, 1, 2))); +int sprintf(char * buf, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); int vsprintf(char *buf, const char *fmt, va_list args); /* lib_generic/crc32.c */ @@ -619,7 +632,8 @@ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ */ /* serial stuff */ -void serial_printf (const char *fmt, ...); +void serial_printf (const char *fmt, ...) + __attribute__ ((format (__printf__, 1, 2))); /* stdin */ int getc(void); @@ -628,7 +642,8 @@ int tstc(void); /* stdout */ void putc(const char c); void puts(const char *s); -void printf(const char *fmt, ...); +void printf(const char *fmt, ...) + __attribute__ ((format (__printf__, 1, 2))); void vprintf(const char *fmt, va_list args); /* stderr */ @@ -645,7 +660,8 @@ void vprintf(const char *fmt, va_list args); #define stderr 2 #define MAX_FILES 3 -void fprintf(int file, const char *fmt, ...); +void fprintf(int file, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); void fputs(int file, const char *s); void fputc(int file, const char c); int ftstc(int file); @@ -671,6 +687,9 @@ void __attribute__((weak)) show_boot_progress (int val); #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) + /* Multicore arch functions */ #ifdef CONFIG_MP int cpu_status(int nr); diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 3f2f6140f6..38b962f823 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_ALASKA8220 1 /* ... on Alaska board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 706c13efad..b7574bf149 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -61,6 +61,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index b248639fd0..fd49f569ae 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -88,32 +88,17 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -#if 0 /* test-only */ -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -256,29 +241,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition, use whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci4052-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)" -*/ - #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 1e9597dc61..55dd6296de 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -88,7 +88,6 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING @@ -238,27 +237,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405ab-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)" -*/ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC32) for environment */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index a8029eae9d..6b585bed5f 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -87,23 +87,12 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -260,27 +249,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405dt-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)" -*/ - #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization @@ -416,7 +384,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - /* * Internal Definitions * diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 48e29a2087..89edbde1de 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -61,6 +61,8 @@ #undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* which initialization functions to call for this board */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index f85cff7abf..3a347eac55 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 23508f9f5a..59d0bdbeb2 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -197,6 +197,13 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#if defined(CONFIG_OF_LIBFDT) +#define OF_CPU "cpu@0" +#define OF_TBCLK (bd->bi_busfreq / 4) +#endif + /* * BOOTP options */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 610151f586..d547681c3d 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -469,6 +469,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index e0a887c7e6..095f6658c1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -203,7 +203,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ @@ -453,6 +453,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 32f57ac7da..977c041dca 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -468,6 +468,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 1276a124c9..9ca2a2be04 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -483,6 +483,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 119e7ac7c6..870583845d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -157,7 +157,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ @@ -355,7 +355,6 @@ /* SPI */ #define CONFIG_MPC8XXX_SPI -#define CONFIG_HARD_SPI /* SPI with hardware support */ #undef CONFIG_SOFT_SPI /* SPI bit-banged */ /* GPIOs. Used as SPI chip selects */ @@ -626,6 +625,7 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index c72de03c01..82d06867be 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) @@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ OR_GPCM_EHTR | OR_GPCM_EAD) @@ -555,6 +555,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 983575eb0c..b4bff9a2be 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -203,7 +203,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ @@ -515,6 +515,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 7b7d6f50c0..ca8d53cf25 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -195,7 +195,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) @@ -419,6 +419,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e92493ae4d..0dd02795a6 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -239,7 +239,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ @@ -502,6 +502,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f7e6fd2c52..29c2490e6b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -524,6 +524,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5719759808..d1d3cc3606 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -87,9 +87,6 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 5b3ea05e63..a64565db93 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -73,9 +73,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index ffe9e0089d..669f4d7c8b 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -77,19 +77,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 -#define CFG_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* @@ -171,6 +166,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index fc8ad8813f..acf6f0dce6 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -87,9 +87,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index e8383455c4..1948c0d276 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -73,9 +73,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 9c95cc6567..edf8525179 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -40,6 +40,7 @@ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ +#define CONFIG_MPC8560 1 #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -80,11 +81,8 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a7c69d293c..9e6bb44ff9 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -80,7 +80,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 15ff0eacf2..fc168909e7 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -55,6 +55,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ #define CONFIG_ALTIVEC 1 /* @@ -71,10 +72,8 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_R 1 -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 -#define CFG_ALT_MEMTEST /* * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 9acc3da54a..455e154222 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -67,6 +67,7 @@ #define BANK_INTERLEAVING 0x22000000 #define SUPER_BANK_INTERLEAVING 0x23000000 +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1 @@ -86,7 +87,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h new file mode 100644 index 0000000000..b412655b6d --- /dev/null +++ b/include/configs/MVBLM7.h @@ -0,0 +1,480 @@ +/* + * Copyright (C) Matrix Vision GmbH 2008 + * + * Matrix Vision mvBlueLYNX-M7 configuration file + * based on Freescale's MPC8349ITX. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <version.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC834X 1 +#define CONFIG_MPC8343 1 + +#define CFG_IMMR 0xE0000000 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI +#define CONFIG_PCI_SKIP_HOST_BRIDGE +#define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET +#define CONFIG_MPC8XXX_SPI +#define CONFIG_HARD_SPI +#define MVBLM7_MMC_CS 0x04000000 + +/* I2C */ +#undef CONFIG_SOFT_I2C + +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 0x7F + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_83XX_DDR_USES_CS0 1 +#define CFG_MEMTEST_START (60<<20) +#define CFG_MEMTEST_END (70<<20) + +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + +#define CFG_DDR_SIZE 256 + +/* HC, 75Ohm, DDR-II, DRQ */ +#define CFG_DDRCDR 0x80000001 +/* EN, ODT_WR, 3BA, 14row, 10col */ +#define CFG_DDR_CS0_CONFIG 0x80014102 +#define CFG_DDR_CS1_CONFIG 0x0 +#define CFG_DDR_CS2_CONFIG 0x0 +#define CFG_DDR_CS3_CONFIG 0x0 + +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS1_BNDS 0x0 +#define CFG_DDR_CS2_BNDS 0x0 +#define CFG_DDR_CS3_BNDS 0x0 + +#define CFG_DDR_CLK_CNTL 0x02000000 + +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x2625b221 +#define CFG_DDR_TIMING_2 0x1f9820c7 +#define CFG_DDR_TIMING_3 0x00000000 + +/* ~MEM_EN, SREN, DDR-II, 32_BE */ +#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#define CFG_DDR_INTERVAL 0x04060100 + +#define CFG_DDR_MODE 0x078e0232 + +/* Flash */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CFG_FLASH_BASE 0xFF800000 +#define CFG_FLASH_SIZE 8 +#define CFG_FLASH_SIZE_SHIFT 3 +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_ERASE_TOUT 60000 +#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\ + OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \ + OR_GPCM_EAD) +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) + +/* + * U-Boot memory configuration + */ +#define CFG_MONITOR_BASE TEXT_BASE +#undef CFG_RAMBOOT + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +#define CFG_MONITOR_LEN (512 * 1024) +#define CFG_MALLOC_LEN (512 * 1024) + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +/* LB sdram refresh timer, about 6us */ +#define CFG_LBC_LSRT 0x32000000 +/* LB refresh timer prescal, 266MHz/32*/ +#define CFG_LBC_MRTPR 0x20000000 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_CONSOLE ttyS0 +#define CONFIG_BAUDRATE 115200 + +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define MV_DTB_NAME "mvblm7.dtb" + +/* + * PCI + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 +#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x01000000 + +#define _IO_BASE 0x00000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 3 + +#define PCI_66M +#define CONFIG_83XX_CLKIN 66666667 +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +/* TSEC */ +#define CONFIG_GMII +#define CFG_VSC8601_SKEWFIX +#define CFG_VSC8601_SKEW_TX 3 +#define CFG_VSC8601_SKEW_RX 3 + +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 + +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_FEC1_PHY_NORXERR +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define TSEC1_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) + +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_FEC2_PHY_NORXERR +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define TSEC2_PHY_ADDR 0x11 +#define TSEC2_PHYIDX 0 +#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) + +#define CONFIG_ETHPRIME "TSEC0" + +#define CONFIG_BOOTP_VENDOREX +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* USB */ +#define CONFIG_HAS_FSL_DR_USB + +/* + * Environment + */ +#undef CFG_FLASH_PROTECTION +#define CONFIG_ENV_OVERWRITE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFF800000 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +#define CONFIG_LOADS_ECHO +#define CFG_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_FPGA + +#undef CONFIG_WATCHDOG + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* default load address */ +#define CFG_LOAD_ADDR 0x2000000 +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x200000 + +#define CFG_PROMPT "mvBL-M7> " +#define CFG_CBSIZE 256 + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE CFG_CBSIZE +#define CFG_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CFG_HRCW_LOW 0x0 +#define CFG_HRCW_HIGH 0x0 + +/* + * System performance + */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ + +/* clocking */ +#define CFG_SCCR_ENCCM 0 +#define CFG_SCCR_USBMPHCM 0 +#define CFG_SCCR_USBDRCM 2 +#define CFG_SCCR_TSEC1CM 1 +#define CFG_SCCR_TSEC2CM 1 + +#define CFG_SICRH 0x1fff8003 +#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT + +#define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 + +/* DDR */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI */ +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* no PCI2 */ +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_IBAT4L 0 +#define CFG_IBAT4U 0 + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT7L 0 +#define CFG_IBAT7U 0 + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV eth0 + +/* Default path and filenames */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "s" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 1000 + +#define MV_CI "mvBL-M7" +#define MV_VCI "mvBL-M7" +#define MV_FPGA_DATA "0xfff80000" +#define MV_FPGA_SIZE "0x76ca2" +#define MV_KERNEL_ADDR "0xff810000" +#define MV_INITRD_ADDR "0xffc00000" +#define MV_AUTOSCR_ADDR "0xff804000" +#define MV_AUTOSCR_ADDR2 "0xff806000" +#define MV_DTB_ADDR "0xff808000" +#define MV_INITRD_LENGTH "0x00300000" + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM "0x00100000" +#define MV_DTB_ADDR_RAM "0x00600000" +#define MV_INITRD_ADDR_RAM "0x01000000" + +#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ + then autoscr ${autoscr_addr}; \ + else autoscr ${autoscr_addr2}; \ + fi;" +#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "fpga=0\0" \ + "fpgadata=" MV_FPGA_DATA "\0" \ + "fpgadatasize=" MV_FPGA_SIZE "\0" \ + "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \ + "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \ + "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \ + "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \ + "mv_initrd_addr=" MV_INITRD_ADDR "\0" \ + "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \ + "mv_initrd_length=" MV_INITRD_LENGTH "\0" \ + "mv_dtb_addr=" MV_DTB_ADDR "\0" \ + "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \ + "dtb_name=" MV_DTB_NAME "\0" \ + "mv_version=" U_BOOT_VERSION "\0" \ + "dhcp_client_id=" MV_CI "\0" \ + "dhcp_vendor-class-identifier=" MV_VCI "\0" \ + "netretry=no\0" \ + "use_static_ipaddr=no\0" \ + "static_ipaddr=192.168.90.10\0" \ + "static_netmask=255.255.255.0\0" \ + "static_gateway=0.0.0.0\0" \ + "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "zcip=no\0" \ + "netboot=yes\0" \ + "mvtest=Ff\0" \ + "tried_bootfromflash=no\0" \ + "tried_bootfromnet=no\0" \ + "bootfile=mvblm72625.boot\0" \ + "use_dhcp=yes\0" \ + "gev_start=yes\0" \ + "mvbcdma_debug=0\0" \ + "mvbcia_debug=0\0" \ + "propdev_debug=0\0" \ + "gevss_debug=0\0" \ + "watchdog=0\0" \ + "usb_dr_mode=host\0" \ + "" + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 + +#endif diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 99e1179e68..fa0e5db021 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -45,10 +45,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.10.100 -#define CONFIG_SERVERIP 192.168.10.77 -#define CONFIG_GATEWAYIP 192.168.10.77 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 6eb6444925..259178f857 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index ff64378f20..8a53fdd0cb 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -49,6 +49,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ +#define CONFIG_MPC8540 1 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 6cb3022b93..d21783b838 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 71fa36baae..4c447356a4 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index bff2edf769..bfb478a868 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -47,6 +47,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index a86939e097..0d2ca7225b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks; BR_MS_GPCM | BR_PS_32 | BR_V) /* FLASH timing (0x0000_0c54) */ -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_5 | OR_GPCM_TRLX) #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ @@ -423,6 +423,8 @@ extern int tqm834x_num_flash_banks; #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index fca5f74df7..d18f2346c6 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2007 + * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. + * * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -27,7 +30,7 @@ */ /* - * TQM85xx (8560/40/55/41) board configuration file + * TQM85xx (8560/40/55/41/48) board configuration file */ #ifndef __CONFIG_H @@ -39,25 +42,53 @@ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_PCI +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ +#ifdef CONFIG_TQM8548 +#define CONFIG_PCI1 +#define CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + /* + * Configuration for big NOR Flashes + * + * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash. + * Please be aware, that this changes the whole memory map (new CCSRBAR + * address, etc). You have to use an adapted Linux kernel or FDT blob + * if this option is set. + */ +#undef CONFIG_TQM_BIGFLASH + +/* + * NAND flash support (disabled by default) + * + * Warning: NAND support will likely increase the U-Boot image size + * to more than 256 KB. Please adjust TEXT_BASE if necessary. + */ +#undef CONFIG_NAND + /* - * Only MPC8540 doesn't have CPM module + * MPC8540 and MPC8548 don't have CPM module */ -#ifndef CONFIG_MPC8540 +#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548) #define CONFIG_CPM2 1 /* has CPM2 */ #endif -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support */ /* * sysclk for MPC85xx * * Two valid values are: - * 33000000 - * 66000000 + * 33333333 + * 66666666 * * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz * is likely the desired value here, so that is now the default. @@ -88,10 +119,18 @@ * actual resources get mapped (not physical addresses) */ #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_CCSRBAR 0xA0000000 /* relocated CCSRBAR */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR + 0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR + 0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR + 0xa000) + /* * DDR Setup */ @@ -102,65 +141,116 @@ /* TQM8540 & 8560 need DLL-override */ #define CONFIG_DDR_DLL /* DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ -#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ +#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */ -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \ + defined(CONFIG_TQM8548) #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ +#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */ + +/* + * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM + * series while new boards have 'N' type Flashes from the S29GLxxxN + * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB. + */ +#ifdef CONFIG_TQM8548 +#define CONFIG_TQM_FLASH_N_TYPE +#endif /* CONFIG_TQM8548 */ /* * Flash on the Local Bus */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_FLASH0 0xE0000000 +#define CFG_FLASH1 0xC0000000 +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_FLASH0 0xFC000000 #define CFG_FLASH1 0xF8000000 +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +/* Default ORx timings are for <= 41.7 MHz Local Bus Clock. + * + * Note: According to timing specifications external addr latch delay + * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz. + * + * For other Local Bus Clocks see following table: + * + * Clock/MHz CFG_ORx_PRELIM + * 166 0x.....CA5 + * 133 0x.....C85 + * 100 0x.....C65 + * 83 0x.....FA2 + * 66 0x.....C82 + * 50 0x.....C60 + * 42 0x.....040 + * 33 0x.....030 + * 25 0x.....020 + * + */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_BR0_PRELIM 0xE0001801 /* port size 32bit */ +#define CFG_OR0_PRELIM 0xE0000040 /* 512MB Flash */ +#define CFG_BR1_PRELIM 0xC0001801 /* port size 32bit */ +#define CFG_OR1_PRELIM 0xE0000040 /* 512MB Flash */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ +#endif /* CONFIG_TQM_BIGFLASH */ -#define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */ -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +/* + * Note: when changing the Local Bus clock divider you have to + * change the timing values in CFG_ORx_PRELIM. + * + * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8. + * LCRR[16:17] EADC : External address delay cycles. It should be set to 2 + * for Local Bus Clock > 83.3 MHz. + */ +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_ADDR (CFG_CCSRBAR \ + + 0x04010000) /* Initial RAM address */ #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */ +#define CFG_MALLOC_LEN (384 * 1024) /* Reserved for malloc */ /* Serial Port */ #if defined(CONFIG_TQM8560) -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#else /* ! TQM8560 */ +#else /* !CONFIG_TQM8560 */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -173,20 +263,18 @@ #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* PS/2 Keyboard */ -#if !defined(CONFIG_TQM8560) #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ #define CONFIG_BOARD_EARLY_INIT_R 1 -#endif /* !CONFIG_TQM8560 */ #endif /* CONFIG_TQM8560 */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -194,11 +282,25 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* CAN */ +#define CFG_CAN_BASE (CFG_CCSRBAR \ + + 0x03000000) /* CAN base address */ +#ifdef CONFIG_CAN_DRIVER +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ +#define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI) +#define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \ + BR_PS_8 | BR_MS_UPMC | BR_V) +#endif /* CONFIG_CAN_DRIVER */ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ @@ -219,7 +321,7 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ /* I2C SYSMON (LM75) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ @@ -228,10 +330,64 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 +#ifndef CONFIG_PCIE1 /* RapidIO MMU */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_RIO_MEM_BASE 0xb0000000 /* base address */ +#define CFG_RIO_MEM_SIZE 0x10000000 /* 256M */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ +#endif /* CONFIG_PCIE1 */ + +/* NAND FLASH */ +#ifdef CONFIG_NAND + +#undef CFG_NAND_LEGACY + +#define CONFIG_NAND_FSL_UPM 1 + +#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */ + +/* address distance between chip selects */ +#define CFG_NAND_SELECT_DEVICE 1 +#define CFG_NAND_CS_DIST 0x200 + +#define CFG_NAND_SIZE 0x8000 +#define CFG_NAND0_BASE (CFG_CCSRBAR + 0x03010000) +#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) + +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 + +#if (CFG_MAX_NAND_DEVICE == 1) +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#elif (CFG_MAX_NAND_DEVICE == 2) +#define CFG_NAND_QUIET_TEST 1 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ + CFG_NAND1_BASE, \ +} +#elif (CFG_MAX_NAND_DEVICE == 4) +#define CFG_NAND_QUIET_TEST 1 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ + CFG_NAND1_BASE, \ + CFG_NAND2_BASE, \ + CFG_NAND3_BASE, \ +} +#endif + +/* CS3 for NAND Flash */ +#define CFG_BR3_PRELIM ((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \ + BR_MS_UPMB | BR_V) +#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI) + +#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ + +#endif /* CONFIG_NAND */ /* * General PCI @@ -240,9 +396,33 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_BASE (CFG_CCSRBAR + 0x02000000) #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#ifdef CONFIG_PCIE1 +/* + * General PCI express + * Addresses are mapped 1-1. + */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_PCIE1_MEM_BASE 0xb0000000 +#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0xaf000000 +#else /* !CONFIG_TQM_BIGFLASH */ +#define CFG_PCIE1_MEM_BASE 0xc0000000 +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0xef000000 +#endif /* CONFIG_TQM_BIGFLASH */ +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE +#define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */ +#endif /* CONFIG_PCIE1 */ #if defined(CONFIG_PCI) @@ -254,8 +434,7 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ -#endif /* CONFIG_PCI */ - +#endif /* CONFIG_PCI */ #define CONFIG_NET_MULTI 1 @@ -277,6 +456,27 @@ #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 +#ifdef CONFIG_TQM8548 +/* + * TQM8548 has 4 ethernet ports. 4 ETSEC's. + * + * On the STK85xx Starterkit the ETSEC3/4 ports are on an + * additional adapter (AIO) between module and Starterkit. + */ +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "TSEC2" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "TSEC3" +#define TSEC3_PHY_ADDR 4 +#define TSEC4_PHY_ADDR 5 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define CONFIG_HAS_ETH3 +#define CONFIG_HAS_ETH4 +#endif /* CONFIG_TQM8548 */ + /* Options are TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" @@ -305,7 +505,7 @@ * FCC2: a - c (X50.2 - 1) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ #endif #if defined(CONFIG_TQM8560) @@ -321,12 +521,13 @@ * FCC3: a - d (X50.2 - 3) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ #endif #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) #define CONFIG_ETHER_ON_FCC1 -#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \ + CMXFCR_TF1CS_MSK) #define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -334,7 +535,8 @@ #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) #define CONFIG_ETHER_ON_FCC2 -#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \ + CMXFCR_TF2CS_MSK) #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -342,7 +544,8 @@ #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) #define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \ + CMXFCR_TF3CS_MSK) #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -352,17 +555,21 @@ * Environment */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + +#ifdef CONFIG_TQM_FLASH_N_TYPE +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */ +#else /* !CONFIG_TQM_FLASH_N_TYPE */ +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ +#endif /* CONFIG_TQM_FLASH_N_TYPE */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_TIMESTAMP /* Print image info with ts */ - +#define CONFIG_TIMESTAMP /* Print image info with ts */ /* * BOOTP options @@ -372,6 +579,25 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +#ifdef CONFIG_NAND +/* + * Use NAND-FLash as JFFS2 device + */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 + +#define CONFIG_JFFS2_NAND 1 + +#ifdef CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=TQM85xx-nand" +#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-" +#else +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */ +#endif /* CONFIG_JFFS2_CMDLINE */ + +#endif /* CONFIG_NAND */ /* * Command line configuration. @@ -389,10 +615,9 @@ #define CONFIG_CMD_MII #if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI #endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -403,12 +628,13 @@ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ +#define CFG_PBSIZE (CFG_CBSIZE + \ + sizeof(CFG_PROMPT) + 16) /* Print Buf Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ @@ -433,7 +659,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif - #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ @@ -444,10 +669,26 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +/* + * Setup some board specific values for the default environment variables + */ +#ifdef CONFIG_CPM2 +#define CFG_ENV_CONSDEV "consdev=ttyCPM0\0" +#else +#define CFG_ENV_CONSDEV "consdev=ttyS0\0" +#endif +#define CFG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \ + MK_STR(CONFIG_HOSTNAME)".dtb\0" +#define CFG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0" +#define CFG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \ + "uboot_addr="MK_STR(TEXT_BASE)"\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile="CFG_BOOTFILE_PATH"\0" \ + CFG_ENV_BOOTFILE \ + CFG_ENV_FDT_FILE \ + CFG_ENV_CONSDEV \ "netdev=eth0\0" \ - "consdev=ttyS0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -457,20 +698,27 @@ "addcons=setenv bootargs $bootargs " \ "console=$consdev,$baudrate\0" \ "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ + "bootm $kernel_addr - $fdt_addr\0" \ "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ + "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ + "net_nfs=tftp $kernel_addr_r $bootfile;" \ + "tftp $fdt_addr_r $fdt_file;" \ + "run nfsargs addip addcons;" \ + "bootm $kernel_addr_r - $fdt_addr_r\0" \ "rootpath=/opt/eldk/ppc_85xx\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE180000\0" \ - "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "fdt_addr_r=900000\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr=ffec0000\0" \ + "kernel_addr=ffd00000\0" \ + "ramdisk_addr=ff800000\0" \ + CFG_ENV_UBOOT \ + "load=tftp 100000 $uboot\0" \ + "update=protect off $uboot_addr +$filesize;" \ + "erase $uboot_addr +$filesize;" \ + "cp.b 100000 $uboot_addr $filesize;" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 31f10dd87c..598fe7bf27 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -48,6 +48,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 00c4ff093a..1b4195a08f 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_YUKON8220 1 /* ... on Yukon board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/acadia.h b/include/configs/acadia.h index bbf726dc62..9092a7c096 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -34,6 +34,13 @@ #define CONFIG_ACADIA 1 /* Board is Acadia */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME acadia +#include "amcc-common.h" + /* Detect Acadia PLL input clock automatically via CPLD bit */ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \ 66666666 : 33333000) @@ -59,16 +66,11 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xfe000000 #define CFG_CPLD_BASE 0x80000000 #define CFG_NAND_ADDR 0xd0000000 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) -#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ - /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ @@ -89,12 +91,6 @@ *----------------------------------------------------------------------*/ #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /*----------------------------------------------------------------------- * Environment @@ -202,10 +198,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -222,77 +215,24 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#if 0 /* test-only... */ -/*----------------------------------------------------------------------- - * SPI stuff - Define to include SPI control - *----------------------------------------------------------------------- - */ -#define CONFIG_SPI -#endif - /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define xstr(s) str(s) -#define str(s) #s - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=acadia\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=acadia/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 acadia/u-boot.bin\0" \ - "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "nload=tftp 200000 acadia/u-boot-nand.bin\0" \ - "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ - "setenv filesize;saveenv\0" \ - "nupd=run nload nupdate\0" \ "kozio=bootm ffc60000\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE @@ -305,35 +245,10 @@ #define CONFIG_SUPPORT_VFAT /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_USB /* @@ -344,43 +259,6 @@ #undef CONFIG_CMD_IMLS #endif -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -493,21 +371,4 @@ #define CFG_GPIO1_TSRL 0x00000000 #define CFG_GPIO1_TSRH 0x00000000 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index c975a249c7..4226529eb7 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -372,6 +372,8 @@ #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Internal Definitions * diff --git a/include/configs/aev.h b/include/configs/aev.h index e3f810c5c8..c5e475921c 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -41,6 +41,8 @@ #define CONFIG_AEVFIFO 1 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 3e906c4251..fb6feb5274 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -33,7 +33,6 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_4xx_DCACHE /* Enable i- and d-cache */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h new file mode 100644 index 0000000000..1f27d785b8 --- /dev/null +++ b/include/configs/amcc-common.h @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Common configuration options for all AMCC boards + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __AMCC_COMMON_H +#define __AMCC_COMMON_H + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_MONITOR_BASE TEXT_BASE /* Start of U-Boot */ +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) +#define CFG_MALLOC_LEN (1 << 20) /* Reserved for malloc */ + +/* + * UART + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* + * I2C + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Ethernet/EMAC/PHY + */ +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_NET_MULTI +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#if defined(CONFIG_440) +#define CFG_RX_ETH_BUFFER 32 /* number of eth rx buffers */ +#else +#define CFG_RX_ETH_BUFFER 16 /* number of eth rx buffers */ +#endif + +/* + * Commands + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#if defined(CONFIG_440) +#define CONFIG_CMD_CACHE +#endif +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +/* + * Miscellaneous configurable options + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup*/ + +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Internal Definitions + */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* + * Booting and default environment + */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * Only very few boards have default console not on ttyS0 (like Taishan) + */ +#if !defined(CONFIG_USE_TTY) +#define CONFIG_USE_TTY ttyS0 +#endif + +/* + * Only some 4xx PPC's are equipped with an FPU + */ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" +#else +#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" +#endif + +/* + * Only some boards need to extend the bootargs by some additional + * parameters (like Makalu) + */ +#if !defined(CONFIG_ADDMISC) +#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0" +#endif + +#define xstr(s) str(s) +#define str(s) #s + +/* + * General common environment variables shared on all AMCC eval boards + */ +#define CONFIG_AMCC_DEF_ENV \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \ + CONFIG_ADDMISC \ + "initrd_high=30000000\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=800000\0" \ + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + CONFIG_AMCC_DEF_ENV_ROOTPATH + +/* + * Default environment for arch/powerpc booting + * for boards that are ported to arch/powerpc + */ +#define CONFIG_AMCC_DEF_ENV_POWERPC \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" + +/* + * Default environment for arch/ppc booting, + * for boards that are not ported to arch/powerpc yet + */ +#define CONFIG_AMCC_DEF_ENV_PPC \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r}\0" + +/* + * Default environment for arch/ppc booting (old version), + * for boards that are ported to arch/ppc and arch/powerpc + */ +#define CONFIG_AMCC_DEF_ENV_PPC_OLD \ + "flash_self_old=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs_old=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r}\0" + +#define CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + +#define CONFIG_AMCC_DEF_ENV_NAND_UPD \ + "nload=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ + "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \ + "setenv filesize;saveenv\0" \ + "nupd=run nload nupdate\0" + +#endif /* __AMCC_COMMON_H */ diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index c891fa80ed..342ce2a649 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -28,6 +28,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91CAP9" #define AT91_MAIN_CLOCK 200000000 /* from 12 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ #define CFG_HZ 1000000 /* 1us resolution */ @@ -55,11 +56,19 @@ #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock1 rw rootfstype=jffs2" +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 -/* #define CONFIG_ENV_OVERWRITE 1 */ +#define CONFIG_BOOTDELAY 3 /* * BOOTP options @@ -94,9 +103,9 @@ #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) #define CFG_MAX_DATAFLASH_BANKS 1 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define AT91_SPI_CLK 20000000 -#define DATAFLASH_TCSS (0xFA << 16) -#define DATAFLASH_TCHS (0x8 << 24) +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) /* NOR flash */ #define CFG_FLASH_CFI 1 @@ -110,6 +119,7 @@ #define NAND_MAX_CHIPS 1 #define CFG_MAX_NAND_DEVICE 1 #define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 /* Ethernet */ #define CONFIG_MACB 1 @@ -143,7 +153,12 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=physmap-flash.0:-(nor);" \ + "at91_nand:-(root) " \ + "rw rootfstype=jffs2" #else @@ -154,6 +169,12 @@ #define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4000 #define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock4 " \ + "mtdparts=physmap-flash.0:16k(bootstrap)ro,"\ + "16k(env),224k(uboot)ro,-(linux);" \ + "at91_nand:-(root) " \ + "rw rootfstype=jffs2" #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 41c418f9ab..675224e0ba 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -56,10 +56,6 @@ #define CONFIG_USART3 1 /* USART 3 is DBGU */ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock0 rw rootfstype=jffs2" - -/* #define CONFIG_ENV_OVERWRITE 1 */ /* * BOOTP options @@ -96,7 +92,7 @@ #define CFG_MAX_DATAFLASH_BANKS 2 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ -#define AT91_SPI_CLK 33000000 +#define AT91_SPI_CLK 15000000 #define DATAFLASH_TCSS (0x1a << 16) #define DATAFLASH_TCHS (0x1 << 24) @@ -104,6 +100,7 @@ #define NAND_MAX_CHIPS 1 #define CFG_MAX_NAND_DEVICE 1 #define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 /* NOR flash - no real flash on this board */ #define CFG_NO_FLASH 1 @@ -142,7 +139,11 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" #elif CFG_USE_DATAFLASH_CS1 @@ -152,7 +153,11 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" #else /* CFG_USE_NANDFLASH */ @@ -162,6 +167,12 @@ #define CFG_ENV_OFFSET_REDUND 0x80000 #define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h new file mode 100644 index 0000000000..e53a23f33f --- /dev/null +++ b/include/configs/at91sam9261ek.h @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Configuation settings for the AT91SAM9261EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9261" +#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */ +#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* NOR flash - no real flash on this board */ +#define CFG_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9261" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH_CS0 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h new file mode 100644 index 0000000000..a8194b564d --- /dev/null +++ b/include/configs/at91sam9263ek.h @@ -0,0 +1,206 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Configuation settings for the AT91SAM9263EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9263" +#define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */ +#define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash, if populated */ +#if 1 +#define CFG_NO_FLASH 1 +#else +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_MAX_FLASH_BANKS 1 +#endif + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9263" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h new file mode 100644 index 0000000000..2ad8d05eb0 --- /dev/null +++ b/include/configs/at91sam9rlek.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Configuation settings for the AT91SAM9RLEK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9RL" +#define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */ +#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ +#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_RGB565 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_BOOTDELAY 3 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_USB + +#define CONFIG_CMD_NAND 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash - not present */ +#define CFG_NO_FLASH 1 + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* Ethernet - not present */ + +/* USB - not supported */ + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 5aad043d89..84d235ea9d 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7000 1 @@ -112,8 +114,13 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + +#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 @@ -121,6 +128,11 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 +#define CONFIG_ATMEL_SPI 1 + +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_ATMEL 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 @@ -137,11 +149,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 -#define CFG_SDRAM_16BIT 1 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -150,27 +160,20 @@ #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) #define CFG_MALLOC_LEN (256*1024) -#define CFG_MALLOC_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - CFG_SDRAM_BASE + gd->sdram_size; \ - }) -#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) - #define CFG_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 95aeab6d4e..90910bb98a 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7000 1 @@ -139,9 +141,9 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC -#define CONFIG_CMD_REGINFO #undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_XIMG @@ -151,6 +153,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 @@ -170,10 +173,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -185,17 +187,17 @@ #define CFG_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 -#define CFG_MAXARGS 8 +#define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 194788b18d..03472a8869 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7001 1 @@ -134,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 @@ -153,10 +156,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -167,17 +169,17 @@ #define CFG_MALLOC_LEN (256*1024) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index b81fc21270..07add821a9 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7002 1 @@ -134,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 @@ -153,11 +156,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 -#define CFG_SDRAM_16BIT 1 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -168,17 +169,17 @@ #define CFG_MALLOC_LEN (256*1024) /* Allow 2MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h new file mode 100644 index 0000000000..f9af67540a --- /dev/null +++ b/include/configs/atstk1006.h @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Configuration settings for the ATSTK1002 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/memory-map.h> + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_ATSTK1006 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=mtd3 fbmem=2400k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 2f0df8ad2d..41058f88cf 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -36,6 +36,12 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME bamboo +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ /* @@ -49,10 +55,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -84,14 +86,9 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * NVRAM/RTC * @@ -223,15 +220,11 @@ #define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} #define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ #define CONFIG_PROG_SDRAM_TLB -#undef CFG_DRAM_TEST /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -245,54 +238,20 @@ #define CFG_ENV_OFFSET 0x0 #endif /* CFG_ENV_IS_IN_EEPROM */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=bamboo\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/bamboo/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b 100000 fffa0000 60000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_HAS_ETH0 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 @@ -300,16 +259,6 @@ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #endif /* CONFIG_BAMBOO_NAND */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - #ifdef CONFIG_440EP /* USB */ #define CONFIG_USB_OHCI @@ -319,77 +268,27 @@ #define USB_2_0_DEVICE #endif /*CONFIG_440EP*/ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 #define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB #ifdef CONFIG_BAMBOO_NAND #define CONFIG_CMD_NAND #endif - #define CONFIG_SUPPORT_VFAT -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION /*----------------------------------------------------------------------- * PCI stuff @@ -408,28 +307,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 75dd4e7e67..acce82f621 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -37,6 +37,12 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME bubinga +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -80,118 +86,35 @@ #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=bubinga\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/bubinga/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff90000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ /* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CFG_405_UART_ERRATA_59, then UART divisor is 31. * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. @@ -205,29 +128,11 @@ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ @@ -272,21 +177,9 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_SRAM_BASE 0xFFF00000 #define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization @@ -423,21 +316,4 @@ #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 0f7bb619ce..f097e2c2f0 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 3dd577aae7..ac2e5d99e0 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -30,12 +30,19 @@ /* This config file is used for Canyonlands (460EX) and Glacier (460GT) */ #ifndef CONFIG_CANYONLANDS #define CONFIG_460GT 1 /* Specific PPC460GT */ +#define CONFIG_HOSTNAME glacier #else #define CONFIG_460EX 1 /* Specific PPC460EX */ +#define CONFIG_HOSTNAME canyonlands #endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ @@ -47,8 +54,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ - #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE @@ -86,10 +91,6 @@ #define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/ - /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in OCM) *----------------------------------------------------------------------*/ @@ -102,13 +103,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -242,10 +238,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_SPEED 400000 /* I2C speed */ #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -270,7 +263,6 @@ * Ethernet *----------------------------------------------------------------------*/ #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 #define CONFIG_HAS_ETH0 @@ -282,14 +274,11 @@ #define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH3 #endif -#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_DYNAMIC_ANEG 1 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - /*----------------------------------------------------------------------- * USB-OHCI *----------------------------------------------------------------------*/ @@ -305,104 +294,30 @@ #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #endif -/*----------------------------------------------------------------------- - * Default environment - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -/* Setup some board specific values for the default environment variables */ -#ifdef CONFIG_CANYONLANDS -#define CONFIG_HOSTNAME canyonlands -#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0" -#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" -#else -#define CONFIG_HOSTNAME glacier -#define CFG_BOOTFILE "bootfile=glacier/uImage\0" -#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" -#endif - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - CFG_DTBFILE \ - CFG_ROOTPATH \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 ${hostname}/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b ${fileaddr} fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \ - "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \ - "setenv filesize;saveenv\0" \ - "nupd=run nload nupdate\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP #ifdef CONFIG_460EX #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT @@ -415,41 +330,6 @@ #define CONFIG_ISO_PARTITION /*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ /* General PCI */ @@ -465,21 +345,6 @@ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -671,8 +536,4 @@ } #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index d554348021..ef50c7cabb 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,6 +31,8 @@ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Supported commands */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 1b30e51a3f..fffd1fe1fa 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h new file mode 100644 index 0000000000..0e49e6c159 --- /dev/null +++ b/include/configs/davinci_sffsdr.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* Board */ +#define SFFSDR +#define CFG_NAND_LARGEPAGE +#define CFG_USE_NAND +#define CFG_USE_DSPLINK /* This is to prevent U-Boot from + * powering ON the DSP. */ +/* SoC Configuration */ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/* Memory Info */ +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/* Serial Driver info */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* I2C Configuration */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/* Network & Ethernet Configuration */ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +/* Flash & Environment */ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +/* I2C switch definitions for PCA9543 chip */ +#define CFG_I2C_PCA9543_ADDR 0x70 +#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ +#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ +/* U-Boot general configuration */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE \ + (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel + * load address. */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, + * may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/* Linux Information */ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=56M " \ + "console=ttyS0,115200n8 " \ + "root=/dev/nfs rw noinitrd ip=dhcp " \ + "nfsroot=${serverip}:/nfsroot/sffsdr " \ + "eth0=${ethaddr}" +#define CONFIG_BOOTCOMMAND \ + "nand read 87A00000 100000 300000;" \ + "bootelf 87A00000" +/* U-Boot commands */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_NAND +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +/* KGDB support (if any) */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index b2f606f498..0e10396dfa 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -30,21 +30,21 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_DBAU1100 -#define CONFIG_AU1100 1 +#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_DBAU1500 -#define CONFIG_AU1500 1 +#define CONFIG_SOC_AU1500 1 #else #ifdef CONFIG_DBAU1550 /* Cabernet */ -#define CONFIG_AU1550 1 +#define CONFIG_SOC_AU1550 1 #else #error "No valid board set" #endif @@ -148,7 +148,9 @@ #error "Invalid CPU frequency - must be multiple of 12!" #endif -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index ba68fd4b96..df444d8e96 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -35,10 +35,15 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ /* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME ebony +#include "amcc-common.h" + +/* * Define here the location of the environment variables (FLASH or NVRAM). * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only * supported for backward compatibility. @@ -55,7 +60,6 @@ *----------------------------------------------------------------------*/ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -74,18 +78,11 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} /*----------------------------------------------------------------------- * NVRAM/RTC @@ -141,10 +138,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -153,125 +147,31 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=ebony\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/ebony/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=ff800000\0" \ "ramdisk_addr=ff810000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 8 /* PHY address */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -288,28 +188,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index c2a50c1f47..c2d6ca70a5 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -30,9 +30,9 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_GTH2 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #define CONFIG_MISC_INIT_R 1 @@ -118,7 +118,9 @@ #define CFG_MHZ 500 -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index e5a8897744..ad7cf76869 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 4281d73c90..ec4ed1eeb6 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -65,7 +65,8 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 -#define CONFIG_MXC_SPI_IFACE 1 +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 5ca00b3734..2e4ee66cf6 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -118,7 +118,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (incaip_get_cpuclk() / 2) +#define CFG_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index c89f041ee4..6ec92c38c5 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -40,6 +40,8 @@ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 980e9fe9ce..c9859270c0 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -41,6 +41,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index cce883fd85..d3789bd67a 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -37,8 +37,14 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ -#undef CFG_DRAM_TEST /* Disable-takes long time */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME katmai +#include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ @@ -48,7 +54,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ @@ -78,10 +83,6 @@ #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ - /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/ @@ -98,12 +99,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE #undef CFG_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- * DDR SDRAM @@ -117,10 +114,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE @@ -172,139 +166,36 @@ *----------------------------------------------------------------------*/ #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define xstr(s) str(s) -#define str(s) #s - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=katmai\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "net_nfs_fdt=tftp 200000 ${bootfile};" \ - "tftp ${fdt_addr} ${fdt_file};" \ - "run nfsargs addip addtty;" \ - "bootm 200000 - ${fdt_addr}\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=katmai/uImage\0" \ - "fdt_file=katmai/katmai.dtb\0" \ - "fdt_addr=400000\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 katmai/u-boot.bin\0" \ - "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "kozio=bootm ffc60000\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_HAS_ETH0 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ /*----------------------------------------------------------------------- * FLASH related @@ -436,28 +327,4 @@ #define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) #define CFG_GPIO_ODR 0 -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index a59676870f..9c1a3a4c1e 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -1,4 +1,7 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -36,6 +39,12 @@ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME kilauea +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_BOARD_EMAC_COUNT @@ -44,43 +53,70 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFC000000 #define CFG_NAND_ADDR 0xF8000000 #define CFG_FPGA_BASE 0xF0000000 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ -#define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END (4 << 10) + * Initial RAM & Stack Pointer Configuration Options + * + * There are traditionally three options for the primordial + * (i.e. initial) stack usage on the 405-series: + * + * 1) On-chip Memory (OCM) (i.e. SRAM) + * 2) Data cache + * 3) SDRAM + * + * For the 405EX(r), there is no OCM, so we are left with (2) or (3) + * the latter of which is less than desireable since it requires + * setting up the SDRAM and ECC in assembly code. + * + * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip + * select on the External Bus Controller (EBC) and then select a + * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid, + * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and + * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid, + * physical SDRAM to use (3). + *-----------------------------------------------------------------------*/ + +#define CFG_INIT_DCACHE_CS 4 + +#if defined(CFG_INIT_DCACHE_CS) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ +#else +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */ +#endif /* defined(CFG_INIT_DCACHE_CS) */ + +#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) -/* extra data in init-ram */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) -#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) -#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ +/* + * If the data cache is being used for the primordial stack and global + * data area, the POST word must be placed somewhere else. The General + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves + * its compare and mask register contents across reset, so it is used + * for the POST word. + */ + +#if defined(CFG_INIT_DCACHE_CS) +# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) +#else +# define CFG_INIT_EXTRA_SIZE 16 +# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE) +# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR +#endif /* defined(CFG_INIT_DCACHE_CS) */ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -131,9 +167,9 @@ * This NAND U-Boot (NUB) is a special U-Boot version which can be started * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 + * On 405EX the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from location 0xfffff000...0xffffffff the + * NAND controller cannot be accessed since it is attached to CS0 too. */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ @@ -187,12 +223,54 @@ *----------------------------------------------------------------------*/ #define CFG_MBYTES_SDRAM (256) /* 256MB */ +#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_256MB | \ + SDRAM_RXBAS_SDAM_MODE7 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_CODT 0x0080f837 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xa8380000 +#define CFG_SDRAM0_INITPLR1 0x81900400 +#define CFG_SDRAM0_INITPLR2 0x81020000 +#define CFG_SDRAM0_INITPLR3 0x81030000 +#define CFG_SDRAM0_INITPLR4 0x81010404 +#define CFG_SDRAM0_INITPLR5 0x81000542 +#define CFG_SDRAM0_INITPLR6 0x81900400 +#define CFG_SDRAM0_INITPLR7 0x8D080000 +#define CFG_SDRAM0_INITPLR8 0x8D080000 +#define CFG_SDRAM0_INITPLR9 0x8D080000 +#define CFG_SDRAM0_INITPLR10 0x8D080000 +#define CFG_SDRAM0_INITPLR11 0x81000442 +#define CFG_SDRAM0_INITPLR12 0x81010780 +#define CFG_SDRAM0_INITPLR13 0x81010400 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000209 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x030000a5 +#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_WRDTR 0x00000000 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x32204232 +#define CFG_SDRAM0_SDTR3 0x080b0d1a +#define CFG_SDRAM0_MMODE 0x00000442 +#define CFG_SDRAM0_MEMODE 0x00000404 + /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ #define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ @@ -212,7 +290,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ @@ -220,107 +297,37 @@ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 2 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "logversion=2\0" \ - "netdev=eth0\0" \ - "hostname=kilauea\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_self_old=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs_old=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty;bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=kilauea/uImage\0" \ - "fdt_file=kilauea/kilauea.dtb\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 kilauea/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b ${fileaddr} fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \ - "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ - "setenv filesize;saveenv\0" \ - "nupd=run nload nupdate\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ #define CONFIG_CMD_LOG -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CACHE | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ CFG_POST_ETHER | \ CFG_POST_I2C | \ @@ -335,37 +342,6 @@ #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ @@ -394,13 +370,6 @@ /* base address of inbound PCIe window */ #define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -429,7 +398,7 @@ /* Memory Bank 2 (FPGA) initialization */ #define CFG_EBC_PB2AP 0x9400C800 -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000) #define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ @@ -474,19 +443,6 @@ } \ } -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /*----------------------------------------------------------------------- * Some Kilauea stuff..., mainly fpga registers */ @@ -522,8 +478,4 @@ #define CFG_FPGA_USER_LED0 0x00000200 #define CFG_FPGA_USER_LED1 0x00000100 -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 37151d31fd..805cc59b30 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -37,6 +37,12 @@ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME luan +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -44,11 +50,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */ - #define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ #define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ #define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ @@ -68,7 +69,6 @@ #define CFG_FLASH_BASE CFG_SMALL_FLASH #endif -#undef CFG_DRAM_TEST #if CFG_SRAM_BASE #define CFG_KBYTES_SDRAM 1024*2 #else @@ -88,13 +88,8 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#undef CONFIG_SERIAL_MULTI #undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -139,10 +134,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -151,61 +143,22 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=luan\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/luan/uImage\0" \ +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc100000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_HAS_ETH0 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - #ifdef DEBUG #define CONFIG_PANIC_HANG #else @@ -213,60 +166,11 @@ #endif /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#undef CONFIG_LYNXKDI /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -287,28 +191,4 @@ #endif -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index af066f3a8a..65b240e0f1 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -1,4 +1,7 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -36,6 +39,13 @@ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME makalu +#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -43,42 +53,69 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFC000000 #define CFG_FPGA_BASE 0xF0000000 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ -#define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END (4 << 10) + * Initial RAM & Stack Pointer Configuration Options + * + * There are traditionally three options for the primordial + * (i.e. initial) stack usage on the 405-series: + * + * 1) On-chip Memory (OCM) (i.e. SRAM) + * 2) Data cache + * 3) SDRAM + * + * For the 405EX(r), there is no OCM, so we are left with (2) or (3) + * the latter of which is less than desireable since it requires + * setting up the SDRAM and ECC in assembly code. + * + * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip + * select on the External Bus Controller (EBC) and then select a + * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid, + * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and + * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid, + * physical SDRAM to use (3). + *-----------------------------------------------------------------------*/ + +#define CFG_INIT_DCACHE_CS 4 + +#if defined(CFG_INIT_DCACHE_CS) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ +#else +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */ +#endif /* defined(CFG_INIT_DCACHE_CS) */ + +#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) -/* extra data in init-ram */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) -#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) -#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ +/* + * If the data cache is being used for the primordial stack and global + * data area, the POST word must be placed somewhere else. The General + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves + * its compare and mask register contents across reset, so it is used + * for the POST word. + */ + +#if defined(CFG_INIT_DCACHE_CS) +# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) +#else +# define CFG_INIT_EXTRA_SIZE 16 +# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE) +# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR +#endif /* defined(CFG_INIT_DCACHE_CS) */ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -113,14 +150,60 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM 256 +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) +#define CFG_SDRAM0_MB1CF_BASE ((128 << 20) + CFG_SDRAM_BASE) + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_128MB | \ + SDRAM_RXBAS_SDAM_MODE2 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB1CF ((CFG_SDRAM0_MB1CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_128MB | \ + SDRAM_RXBAS_SDAM_MODE2 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_CODT 0x0080f837 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xa8380000 +#define CFG_SDRAM0_INITPLR1 0x81900400 +#define CFG_SDRAM0_INITPLR2 0x81020000 +#define CFG_SDRAM0_INITPLR3 0x81030000 +#define CFG_SDRAM0_INITPLR4 0x81010404 +#define CFG_SDRAM0_INITPLR5 0x81000542 +#define CFG_SDRAM0_INITPLR6 0x81900400 +#define CFG_SDRAM0_INITPLR7 0x8D080000 +#define CFG_SDRAM0_INITPLR8 0x8D080000 +#define CFG_SDRAM0_INITPLR9 0x8D080000 +#define CFG_SDRAM0_INITPLR10 0x8D080000 +#define CFG_SDRAM0_INITPLR11 0x81000442 +#define CFG_SDRAM0_INITPLR12 0x81010780 +#define CFG_SDRAM0_INITPLR13 0x81010400 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000209 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x030000a5 +#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_WRDTR 0x00000000 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x32204232 +#define CFG_SDRAM0_SDTR3 0x080b0d1a +#define CFG_SDRAM0_MMODE 0x00000442 +#define CFG_SDRAM0_MEMODE 0x00000404 /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ #define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ @@ -140,7 +223,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ @@ -148,104 +230,35 @@ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "logversion=2\0" \ - "netdev=eth0\0" \ - "hostname=makalu\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \ - "flash_self_old=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs_old=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=makalu/uImage\0" \ - "fdt_file=makalu/makalu.dtb\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 makalu/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b ${fileaddr} fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG #define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ #define CONFIG_CMD_LOG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CACHE | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ CFG_POST_ETHER | \ CFG_POST_I2C | \ @@ -260,37 +273,6 @@ #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ @@ -319,13 +301,6 @@ /* base address of inbound PCIe window */ #define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -384,21 +359,4 @@ #define CFG_GPIO_PCIE_CLKREQ 27 #define CFG_GPIO_PCIE_WAKE 28 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index a9c86f9e3f..e4c3f7239b 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration * diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 5218d9ca97..8dfb9aa8a9 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 1945918300..319923ad6e 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -54,6 +54,7 @@ #define CONFIG_405 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_XILINX_405 1 #define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ #define CONFIG_SYSTEMACE 1 diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 1503598166..b6843af3dc 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -35,6 +35,7 @@ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * BOOTP options diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index f614e679f9..2f24967405 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -39,7 +39,7 @@ #define CONFIG_MPC7448HPC2 #define CONFIG_74xx -#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CONFIG_ALTIVEC /* undef to disable */ #define CFG_BOARD_NAME "MPC7448 HPC II" @@ -58,6 +58,7 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_ENV_OVERWRITE @@ -75,7 +76,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " /* Pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,7448@0" diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 8d92a13e1c..7298e55c70 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -40,10 +40,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.22 -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/munices.h b/include/configs/munices.h index 38b27bb3a7..e0046ec2d3 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -35,6 +35,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Command line configuration. diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 2ea48a6da9..37ba872a43 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -62,7 +62,8 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 -#define CONFIG_MXC_SPI_IFACE 1 /* Default SPI interface number */ +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 8dde1ef391..88bdb03e67 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index be2b3ec7ef..407aae7210 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -44,16 +44,19 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME ocotea +#include "amcc-common.h" + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -75,18 +78,11 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- * Environment @@ -156,10 +152,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -168,54 +161,17 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=ocotea\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/ocotea/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 2 #define CONFIG_PHY2_ADDR 0x10 @@ -228,73 +184,15 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -311,28 +209,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 0dac5161ba..0913b14a4c 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -42,6 +42,7 @@ #if defined (CONFIG_P3M750) #define CONFIG_750FX /* 750GL/GX/FX */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CFG_BOARD_NAME "P3M750" #define CFG_BUS_HZ 100000000 #define CFG_BUS_CLK CFG_BUS_HZ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 810e0f0462..2caa64173c 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -30,16 +30,16 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_PB1000 -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_PB1100 -#define CONFIG_AU1100 1 +#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_PB1500 -#define CONFIG_AU1500 1 +#define CONFIG_SOC_AU1500 1 #else #error "No valid board set" #endif @@ -81,7 +81,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ 396000000 + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 2ce39c913c..c065d3328c 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -49,6 +49,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 1be4e055f9..ef92637127 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -114,7 +114,8 @@ #define CFG_PROMPT "PURPLE # " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ (CPU_CLOCK_RATE/2) +#define CFG_MIPS_TIMER_FREQ (CPU_CLOCK_RATE/2) +#define CFG_HZ 1000 #define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_LOAD_ADDR 0x80500000 /* default load address */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index d6bcc8e3b1..3dfd2181f4 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -120,7 +120,9 @@ #define CFG_MHZ 132 -#define CFG_HZ (CFG_MHZ * 1000000) +#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h new file mode 100644 index 0000000000..622a5d4ccc --- /dev/null +++ b/include/configs/quad100hd.h @@ -0,0 +1,298 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * quad100hd.h - configuration for Quad100hd board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EP 1 /* Specifc 405EP support*/ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */ +#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */ + +/* the environment is in the EEPROM by default */ +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_IN_FLASH + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x01 /* PHY address */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_LOG +#undef CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#undef CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * SDRAM + *----------------------------------------------------------------------*/ +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 +#define CFG_SDRAM_SIZE 0x02000000 /* 32 MB */ + +/* FIX! SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/* + * JFFS2 + */ +#define CFG_JFFS2_FIRST_BANK 0 +#ifdef CFG_KERNEL_IN_JFFS2 +#define CFG_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */ +#else /* kernel not in JFFS */ +#define CFG_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */ +#endif +#define CFG_JFFS2_NUM_BANKS 1 + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */ + +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_SIZE 0x2000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (TEXT_BASE) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +/* the environment is located before u-boot */ +#define CFG_ENV_ADDR (TEXT_BASE - CFG_ENV_SECT_SIZE) + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) +#endif + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x400 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x00000000 +#define CFG_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */ +#endif + +/* partly from PPCBoot */ +/* NAND */ +#define CONFIG_NAND +#ifdef CONFIG_NAND +#define CFG_NAND_BASE 0x60000000 +#define CFG_NAND_CS 10 /* our CS is GPIO10 */ +#define CFG_NAND_RDY 23 /* our RDY is GPIO23 */ +#define CFG_NAND_CE 24 /* our CE is GPIO24 */ +#define CFG_NAND_CLE 31 /* our CLE is GPIO31 */ +#define CFG_NAND_ALE 30 /* our ALE is GPIO30 */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +/* see ./cpu/ppc4xx/start.S */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + * Taken from PPCBoot board/icecube/icecube.h + */ + +/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ +#define CFG_EBC_PB0AP 0x04002480 +/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */ +#define CFG_EBC_PB0CR 0xFFC5A000 +#define CFG_EBC_PB1AP 0x04005480 +#define CFG_EBC_PB1CR 0x60018000 +#define CFG_EBC_PB2AP 0x00000000 +#define CFG_EBC_PB2CR 0x00000000 +#define CFG_EBC_PB3AP 0x00000000 +#define CFG_EBC_PB3CR 0x00000000 +#define CFG_EBC_PB4AP 0x00000000 +#define CFG_EBC_PB4CR 0x00000000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * Taken in part from PPCBoot board/icecube/icecube.h + */ +/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ +#define CFG_GPIO0_OSRH 0x55555550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xFFFF8097 +#define CFG_GPIO0_ODR 0x00000000 + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* ENVIRONMENT VARS */ + +#define CONFIG_IPADDR 192.168.1.67 +#define CONFIG_SERVERIP 192.168.1.50 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_LOADADDR 300000 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index c20bacad22..e269336e82 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -35,12 +35,6 @@ #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_ENV_OVERWRITE 1 -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.51 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - /* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (0x04000000) @@ -60,45 +54,27 @@ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1024 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) #define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* - * NOR Flash + * NOR Flash ( Spantion S29GL256P ) */ #define CFG_FLASH_CFI #define CFG_FLASH_CFI_DRIVER - -#if defined(CONFIG_R2DPLUS_OLD) -#define CFG_FLASH_BASE (0xA0000000) -#define CFG_MAX_FLASH_BANKS (1) /* Max number of - * Flash memory banks - */ -#define CFG_MAX_FLASH_SECT 142 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#else /* CONFIG_R2DPLUS_OLD */ - #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */ -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ - CFG_FLASH_BASE + 0x100000,\ - CFG_FLASH_BASE + 0x400000,\ - CFG_FLASH_BASE + 0x700000, } -#endif /* CONFIG_R2DPLUS_OLD */ +#define CFG_MAX_FLASH_BANKS (1) +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_FLASH_ERASE_TOUT 120000 -#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_ENV_SECT_SIZE 0x40000 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) /* * SuperH Clock setting diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 4e895806ae..4c82c5a2fd 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -1,7 +1,7 @@ /* * Configuation settings for the Renesas R7780MP board * - * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> * * See file CREDITS for list of people who contributed to this @@ -31,7 +31,8 @@ #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7780 1 #define CONFIG_R7780MP 1 -#define __LITTLE_ENDIAN 1 +#define CFG_R7780MP_OLD_FLASH 1 +#define __LITTLE_ENDIAN__ 1 /* * Command line configuration. @@ -59,12 +60,6 @@ /* check for keypress on bootdelay==0 */ /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.82 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - #define CFG_SDRAM_BASE (0x08000000) #define CFG_SDRAM_SIZE (128 * 1024 * 1024) @@ -80,22 +75,30 @@ #define CFG_MEMTEST_START (CFG_SDRAM_BASE) #define CFG_MEMTEST_END (TEXT_BASE - 0x100000) -/* NOR Flash (S29PL127J60TFI130) */ +/* Flash board support */ #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ +#ifdef CFG_R7780MP_OLD_FLASH +/* NOR Flash (S29PL127J60TFI130) */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +# define CFG_MAX_FLASH_BANKS (2) +# define CFG_MAX_FLASH_SECT 270 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ CFG_FLASH_BASE + 0x100000,\ CFG_FLASH_BASE + 0x400000,\ CFG_FLASH_BASE + 0x700000, } +#else /* CFG_R7780MP_OLD_FLASH */ +/* NOR Flash (Spantion S29GL256P) */ +# define CFG_MAX_FLASH_BANKS (1) +# define CFG_MAX_FLASH_SECT 256 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif /* CFG_R7780MP_OLD_FLASH */ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (112 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1204 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) @@ -110,7 +113,7 @@ #define CFG_FLASH_EMPTY_INFO #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE (16 * 1024) +#define CFG_ENV_SECT_SIZE (256 * 1024) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_FLASH_ERASE_TOUT 120000 @@ -141,8 +144,10 @@ #endif /* CONFIG_CMD_PCI */ #if defined(CONFIG_CMD_NET) -/* #define CONFIG_NET_MULTI - #define CONFIG_RTL8169 */ +/* +#define CONFIG_NET_MULTI +#define CONFIG_RTL8169 +*/ /* AX88696L Support(NE2000 base chip) */ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_AX88796L diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 4974fb43f7..2a398e8c45 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -272,10 +272,14 @@ #undef SPI_INIT /* no port initialization needed */ #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) -#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ - else immr->im_ioport.iop_pdatd &= ~I2C_MOSI -#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ - else immr->im_ioport.iop_pdatd &= ~I2C_SCLK +#define SPI_SDA(bit) do { \ + if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ + else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \ + } while (0) +#define SPI_SCL(bit) do { \ + if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ + else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \ + } while (0) #define SPI_DELAY /* No delay is needed */ #endif /* CONFIG_SOFT_SPI */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 0ebc674a69..74815567ff 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -570,6 +570,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 81a1e072c6..146eafe9cc 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -42,6 +42,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ +#define CONFIG_MPC8560 1 /* XXX flagging this as something I might want to delete */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index d140241bff..4ae25adde0 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -257,13 +257,9 @@ #define CFG_CS5L_VAL 0x00000D03 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x16000000 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+4) -/* #define CONFIG_DM9000_USE_8BIT */ -#define CONFIG_DM9000_USE_16BIT -/* #define CONFIG_DM9000_USE_32BIT */ /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) f_ref=16,777MHz diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 48251f3948..f4eefae2f4 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -34,11 +34,19 @@ /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ #ifndef CONFIG_RAINIER #define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_HOSTNAME sequoia #else #define CONFIG_440GRX 1 /* Specific PPC440GRx */ +#define CONFIG_HOSTNAME rainier #endif #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + /* Detect Sequoia PLL input clock automatically via CPLD bit */ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ 33333333 : 33000000) @@ -64,19 +72,9 @@ * Base addresses -- Note these are effective addresses where the actual * resources get mapped (not physical addresses). */ -#ifndef CONFIG_VIDEO -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */ -#else -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ -#endif - #define CFG_TLB_FOR_BOOT_FLASH 0x0003 #define CFG_BOOT_BASE_ADDR 0xf0000000 -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ #define CFG_OCM_DATA_ADDR CFG_OCM_BASE @@ -108,14 +106,9 @@ * Serial Port */ #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /* * Environment */ @@ -227,10 +220,7 @@ /* * I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -247,80 +237,27 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -/* Setup some board specific values for the default environment variables */ -#ifndef CONFIG_RAINIER -#define CONFIG_HOSTNAME sequoia -#define CFG_BOOTFILE "bootfile=sequoia/uImage\0" -#define CFG_DTBFILE "fdt_file=sequoia/sequoia.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" -#else -#define CONFIG_HOSTNAME rainier -#define CFG_BOOTFILE "bootfile=rainier/uImage\0" -#define CFG_DTBFILE "fdt_file=rainier/rainier.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" -#endif - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - CFG_ROOTPATH \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs}\0" \ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addtty addmisc;" \ - "bootm\0" \ - "fdt_file=sequoia/sequoia.dtb\0" \ - "fdt_addr=400000\0" \ - "net_nfs_fdt=tftp 200000 ${bootfile};" \ - "tftp ${fdt_addr} ${fdt_file};" \ - "run nfsargs addip addtty addmisc;" \ - "bootm 200000 - ${fdt_addr}\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=FC000000\0" \ "ramdisk_addr=FC180000\0" \ - "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 200000 FFFA0000 60000\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ - /* buffers & descriptors */ -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 1 @@ -347,35 +284,12 @@ #define CONFIG_ISO_PARTITION /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #ifdef CONFIG_440EPX @@ -407,35 +321,6 @@ #define CONFIG_SUPPORT_VFAT /* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* * PCI stuff */ /* General PCI */ @@ -453,13 +338,6 @@ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ /* - * For booting Linux, the board info and command line data have to be in the - * first 8 MB of memory, since this is the maximum mapped by the Linux kernel - * during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* * External Bus Controller (EBC) Setup */ @@ -577,23 +455,6 @@ } \ } -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #ifdef CONFIG_VIDEO #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h new file mode 100644 index 0000000000..7713eaaf59 --- /dev/null +++ b/include/configs/sh7763rdp.h @@ -0,0 +1,116 @@ +/* + * Configuation settings for the Renesas SH7763RDP board + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SH7763RDP_H +#define __SH7763RDP_H + +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7763 1 +#define CONFIG_SH7763RDP 1 +#define __LITTLE_ENDIAN 1 + +/* + * Command line configuration. + */ +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_ENV + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_SCIF2 1 + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments + passed to kernel */ +#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate + settings for this board */ + +/* SDRAM */ +#define CFG_SDRAM_BASE (0x8C000000) +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) +#define CFG_MEMTEST_START (CFG_SDRAM_BASE) +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +/* Flash(NOR) */ +#define CFG_FLASH_BASE (0xA0000000) +#define CFG_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) +#define CFG_MAX_FLASH_BANKS (1) +#define CFG_MAX_FLASH_SECT (520) + +/* U-boot setting */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE) +#define CFG_MONITOR_LEN (128 * 1024) +/* Size of DRAM reserved for malloc() use */ +#define CFG_MALLOC_LEN (1024 * 1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE (256) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +/* Timeout for Flash erase operations (in ms) */ +#define CFG_FLASH_ERASE_TOUT (3 * 1000) +/* Timeout for Flash write operations (in ms) */ +#define CFG_FLASH_WRITE_TOUT (3 * 1000) +/* Timeout for Flash set sector lock bit operations (in ms) */ +#define CFG_FLASH_LOCK_TOUT (3 * 1000) +/* Timeout for Flash clear lock bit operations (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) +/* Use hardware flash sectors protection instead of U-Boot software protection */ +#undef CFG_FLASH_PROTECTION +#undef CFG_DIRECT_FLASH_TFTP +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (128 * 1024) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE)) +/* Offset of env Flash sector relative to CFG_FLASH_BASE */ +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE)) + +/* Clock */ +#define CONFIG_SYS_CLK_FREQ 66666666 +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __SH7763RDP_H */ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 4578cae7d6..3e47eb88a7 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 23ed87f338..16274137dc 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -165,7 +165,7 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -216,18 +216,14 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ #define CFG_EEPROM_PAGE_WRITE_BITS 4 -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - /* * General PCI * Memory space is mapped 1-1. */ #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - +/* PCI is clocked by the external source at 33 MHz */ +#define CONFIG_PCI_CLK_FREQ 33000000 #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ @@ -237,13 +233,7 @@ #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ @@ -389,10 +379,10 @@ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addcons;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fdt_file=$hostname/socrates.dtb\0" \ + "fdt_file=$hostname/socrates.dtb\0" \ "fdt_addr_r=B00000\0" \ "fdt_addr=FC1E0000\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ + "rootpath=/opt/eldk/ppc_85xxDP\0" \ "kernel_addr=FC000000\0" \ "kernel_addr_r=200000\0" \ "ramdisk_addr=FC200000\0" \ @@ -419,4 +409,14 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1 +/* FPGA and NAND */ +#define CFG_FPGA_BASE 0xc0000000 +#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_CMD_NAND + #endif /* __CONFIG_H */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index c62b9775c6..18f5533737 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_SORCERY 1 /* Sorcery board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 49213dc67a..69d2d67ab1 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -44,6 +44,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index ec04a30bec..6e8213d72a 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -41,6 +41,7 @@ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ +#define CONFIG_MPC8560 1 #undef CONFIG_PCI /* pci ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support*/ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index d033c866d7..a1e9789ea0 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -41,6 +41,7 @@ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ +#define CONFIG_MPC8560 1 #define CONFIG_PCI /* PCI ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support*/ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 97a1032af0..fcafba5937 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -590,8 +590,8 @@ typedef unsigned int led_id_t; /*****************************************************************************/ -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +/* pass open firmware flattened device tree */ +#define CONFIG_OF_LIBFDT 1 #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) diff --git a/include/configs/taihu.h b/include/configs/taihu.h index c060b1e340..86f776df20 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -32,6 +32,12 @@ #define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_TAIHU 1 /* on a taihu board */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME taihu +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ @@ -70,87 +76,31 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile=/tftpboot/taihu/uImage\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "netdev=eth0\0" \ - "hostname=taihu\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=FC000000\0" \ "ramdisk_addr=FC180000\0" \ - "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \ - "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \ - "cp.b 200000 FFFC0000 40000\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0x14 /* PHY address */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ #define CONFIG_PHY_RESET 1 /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SPI -#undef CONFIG_WATCHDOG /* watchdog disabled */ - #undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ #define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ #define CFG_SDRAM_BANKS 2 @@ -169,23 +119,6 @@ #define CFG_SDRAM_tRFC 66 /* Auto refresh period */ /* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CFG_405_UART_ERRATA_59, then UART divisor is 31. * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. @@ -198,35 +131,13 @@ #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_UART1_CONSOLE 1 -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ @@ -278,25 +189,12 @@ unsigned char spi_read(void); /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFFE00000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ - #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ @@ -421,21 +319,5 @@ unsigned char spi_read(void); #define CPLD_REG0_ADDR 0x50100000 #define CPLD_REG1_ADDR 0x50100001 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 #endif /* __CONFIG_H */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 1879d38522..ba421925ed 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -32,9 +32,15 @@ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME taishan +#define CONFIG_USE_TTY ttyS1 +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -42,9 +48,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -70,19 +74,11 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ -#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */ #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- * Environment @@ -138,10 +134,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #undef CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR 0x50 @@ -159,65 +152,23 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=taishan\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/taishan/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc180000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ - "$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \ "kozio=bootm 0xffe00000\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /*----------------------------------------------------------------------- * Networking *----------------------------------------------------------------------*/ #define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ #define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ #define CONFIG_PHY2_ADDR 0x1 @@ -230,70 +181,12 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG #define CONFIG_CMD_DTT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * PCI stuff @@ -312,28 +205,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index dadf5d3329..fc2357d406 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -122,7 +122,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (CPU_TCLOCK_RATE/4) +#define CFG_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 25155ad349..f77dd14f1a 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -276,13 +276,9 @@ #define CFG_MCIO1_VAL 0x0000c108 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x08000000 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) -/* #define CONFIG_DM9000_USE_8BIT */ -/* #define CONFIG_DM9000_USE_16BIT */ -#define CONFIG_DM9000_USE_32BIT #define CONFIG_USB_OHCI_NEW 1 #define CFG_USB_OHCI_BOARD_INIT 1 diff --git a/include/configs/uc101.h b/include/configs/uc101.h index dc1d7e1b3d..042750e2fe 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index e24d6f77ae..c203522552 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -46,6 +46,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index adc420b9ad..e19c5f3482 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -38,122 +38,44 @@ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ /* ...and on a SYCAMORE board */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME walnut +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=walnut\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/walnut/uImage\0" \ +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff80000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ /* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CFG_405_UART_ERRATA_59, then UART divisor is 31. * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. @@ -167,29 +89,11 @@ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -224,13 +128,8 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) /* * Define here the location of the environment variables (FLASH or NVRAM). @@ -243,13 +142,6 @@ #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * FLASH organization */ @@ -335,21 +227,4 @@ */ #define SPD_EEPROM_ADDRESS 0x50 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index f22e79824c..891b515d4e 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -42,6 +42,11 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_BOARD_RESET 1 /* call board_reset() */ @@ -50,10 +55,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -84,14 +85,9 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /*define this if you want console on UART1*/ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -142,10 +138,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -167,72 +160,22 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -/* Setup some board specific values for the default environment variables */ -#ifndef CONFIG_YELLOWSTONE -#define CONFIG_HOSTNAME yosemite -#define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" -#else -#define CONFIG_HOSTNAME yellowstone -#define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" -#endif - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - CFG_ROOTPATH \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "bootfile=/tftpboot/${hostname}/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc180000\0" \ - "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 200000 fff80000 80000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 #define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_PHY1_ADDR 3 /* Partitions */ #define CONFIG_MAC_PARTITION @@ -263,36 +206,11 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG #define CONFIG_CMD_DTT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM #ifdef CONFIG_440EP #define CONFIG_CMD_USB @@ -300,36 +218,6 @@ #define CONFIG_CMD_EXT2 #endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -347,13 +235,6 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -370,21 +251,4 @@ #define CFG_BCSR5_PCI66EN 0x80 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 6f9d3e3c6f..026fef67ce 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -38,13 +38,18 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* Disable-takes long time */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define EXTCLK_33_33 33333333 #define EXTCLK_66_66 66666666 #define EXTCLK_50 50000000 #define EXTCLK_83 83333333 +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME yucca +#include "amcc-common.h" + #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS @@ -53,9 +58,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */ #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ @@ -99,24 +102,15 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR -#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CFG_EXT_SERIAL_CLOCK /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ @@ -127,10 +121,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define IIC0_BOOTPROM_ADDR 0x50 #define IIC0_ALT_BOOTPROM_ADDR 0x54 @@ -153,123 +144,32 @@ #undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ #define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=yucca\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=yucca/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=E7F10000\0" \ "ramdisk_addr=E7F20000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 yuca/u-boot.bin\0" \ - "update=protect off 2:4-7;era 2:4-7;" \ - "cp.b ${fileaddr} FFFB0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:EP:EP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM - #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ -#undef CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_HAS_ETH0 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * FLASH related @@ -318,26 +218,6 @@ /* Support for Intel 82557/82559/82559ER chips. */ #define CONFIG_EEPRO100 -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* FB Divisor selection */ #define FPGA_FB_DIV_6 6 #define FPGA_FB_DIV_10 10 @@ -539,10 +419,4 @@ #define PERIOD_33_33MHZ 30000 /* 30ns */ #define PERIOD_25_00MHZ 40000 /* 40ns */ -/*---------------------------------------------------------------------------*/ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/environment.h b/include/environment.h index bf9f669127..481ea733db 100644 --- a/include/environment.h +++ b/include/environment.h @@ -107,8 +107,8 @@ typedef struct environment_s { unsigned char data[ENV_SIZE]; /* Environment data */ } env_t; -/* Pointer to function that returns a character from the environment */ -extern unsigned char (*env_get_char)(int); +/* Function that returns a character from the environment */ +unsigned char env_get_char (int); /* Function that returns a pointer to a value from the environment */ unsigned char *env_get_addr(int); @@ -117,4 +117,7 @@ unsigned char env_get_char_memory (int index); /* Function that updates CRC of the enironment */ void env_crc_update (void); +/* [re]set to the default environment */ +void set_default_env(void); + #endif /* _ENVIRONMENT_H_ */ diff --git a/include/exports.h b/include/exports.h index d6512cb3a4..6377875bc9 100644 --- a/include/exports.h +++ b/include/exports.h @@ -22,7 +22,7 @@ void vprintf(const char *, va_list); void do_reset (void); unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); char *getenv (char *name); -void setenv (char *varname, char *varvalue); +int setenv (char *varname, char *varvalue); long simple_strtol(const char *cp,char **endp,unsigned int base); int strcmp(const char * cs,const char * ct); #ifdef CONFIG_HAS_UID diff --git a/include/ft_build.h b/include/ft_build.h deleted file mode 100644 index 89c689c084..0000000000 --- a/include/ft_build.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * OF Flat tree builder - * - */ - -#ifndef FT_BUILD_H -#define FT_BUILD_H - -#include <linux/types.h> -#include <asm/u-boot.h> - -/* Definitions used by the flattened device tree */ -#define OF_DT_HEADER 0xd00dfeed /* marker */ -#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */ -#define OF_DT_END_NODE 0x2 /* End node */ -#define OF_DT_PROP 0x3 /* Property: name off, size, - * content */ -#define OF_DT_NOP 0x4 /* nop */ -#define OF_DT_END 0x9 - -#define OF_DT_VERSION 0x10 - -struct boot_param_header { - u32 magic; /* magic word OF_DT_HEADER */ - u32 totalsize; /* total size of DT block */ - u32 off_dt_struct; /* offset to structure */ - u32 off_dt_strings; /* offset to strings */ - u32 off_mem_rsvmap; /* offset to memory reserve map */ - u32 version; /* format version */ - u32 last_comp_version; /* last compatible version */ - /* version 2 fields below */ - u32 boot_cpuid_phys; /* Physical CPU id we're booting on */ - /* version 3 fields below */ - u32 dt_strings_size; /* size of the DT strings block */ -}; - -struct ft_cxt { - struct boot_param_header *bph; - u8 *p_rsvmap; - u8 *p_start; /* pointer to beginning of dt_struct */ - u8 *p_end; /* pointer to end of dt_strings */ - u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */ -}; - -void ft_begin_node(struct ft_cxt *cxt, const char *name); -void ft_init_cxt(struct ft_cxt *cxt, void *blob); -void ft_end_node(struct ft_cxt *cxt); - -void ft_end_tree(struct ft_cxt *cxt); -void ft_finalize_tree(struct ft_cxt *cxt); - -void ft_nop(struct ft_cxt *cxt); -void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz); -void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str); -void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); -void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); -void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); - -void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end); - -void ft_dump_blob(const void *bphp); -void ft_merge_blob(struct ft_cxt *cxt, void *blob); -void *ft_get_prop(void *bphp, const char *propname, int *szp); - -#ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd); -void ft_cpu_setup(void *blob, bd_t *bd); -void ft_pci_setup(void *blob, bd_t *bd); -#endif - -#endif diff --git a/include/image.h b/include/image.h index 664e51e490..46138fa788 100644 --- a/include/image.h +++ b/include/image.h @@ -379,7 +379,7 @@ int image_check_dcrc (image_header_t *hdr); #ifndef USE_HOSTCC int getenv_yesno (char *var); ulong getenv_bootm_low(void); -ulong getenv_bootm_size(void); +phys_size_t getenv_bootm_size(void); void memmove_wd (void *to, void *from, size_t len, ulong chunksz); #endif diff --git a/include/lcd.h b/include/lcd.h index 8a4273cce1..44ac8ef8c7 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -155,7 +155,35 @@ typedef struct vidinfo { u_char vl_bpix; /* Bits per pixel, 0 = 1 */ } vidinfo_t; -#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */ + +#elif defined(CONFIG_ATMEL_LCD) + +typedef struct vidinfo { + u_long vl_col; /* Number of columns (i.e. 640) */ + u_long vl_row; /* Number of rows (i.e. 480) */ + u_long vl_clk; /* pixel clock in ps */ + + /* LCD configuration register */ + u_long vl_sync; /* Horizontal / vertical sync */ + u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ + u_long vl_tft; /* 0 = passive, 1 = TFT */ + + /* Horizontal control register. */ + u_long vl_hsync_len; /* Length of horizontal sync */ + u_long vl_left_margin; /* Time from sync to picture */ + u_long vl_right_margin; /* Time from picture to sync */ + + /* Vertical control register. */ + u_long vl_vsync_len; /* Length of vertical sync */ + u_long vl_upper_margin; /* Time from sync to picture */ + u_long vl_lower_margin; /* Time from picture to sync */ + + u_long mmio; /* Memory mapped registers */ +} vidinfo_t; + +extern vidinfo_t panel_info; + +#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */ /* Video functions */ diff --git a/include/libfdt_env.h b/include/libfdt_env.h index ab5c3012db..a7fd2f8d9a 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -31,7 +31,7 @@ #include <stddef.h> #include <asm/byteorder.h> -extern struct fdt_header *fdt; /* Pointer to the working fdt */ +extern struct fdt_header *working_fdt; /* Pointer to the working fdt */ #define fdt32_to_cpu(x) __be32_to_cpu(x) #define cpu_to_fdt32(x) __cpu_to_be32(x) diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h index 634ff0291c..49fd8a60ff 100644 --- a/include/linux/mtd/fsl_upm.h +++ b/include/linux/mtd/fsl_upm.h @@ -16,7 +16,6 @@ #include <linux/mtd/nand.h> struct fsl_upm { - const u32 *array; void __iomem *mdr; void __iomem *mxmr; void __iomem *mar; diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h index 72d7341d75..4cebea9597 100644 --- a/include/linux/mtd/mtd-abi.h +++ b/include/linux/mtd/mtd-abi.h @@ -93,7 +93,7 @@ struct nand_oobinfo { uint32_t useecc; uint32_t eccbytes; uint32_t oobfree[8][2]; - uint32_t eccpos[32]; + uint32_t eccpos[48]; }; #endif /* __MTD_ABI_H__ */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 71cb2d5c3b..05ba375a82 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -201,13 +201,13 @@ static inline void mtd_erase_callback(struct erase_info *instr) #define MTD_DEBUG_LEVEL3 (3) /* Noisy */ #ifdef CONFIG_MTD_DEBUG -#define DEBUG(n, args...) \ +#define MTDDEBUG(n, args...) \ do { \ if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ printk(KERN_INFO args); \ } while(0) #else /* CONFIG_MTD_DEBUG */ -#define DEBUG(n, args...) do { } while(0) +#define MTDDEBUG(n, args...) do { } while(0) #endif /* CONFIG_MTD_DEBUG */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4cc4a7d1bb..e2a25a60d8 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -385,6 +385,10 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; +#ifndef NAND_MAX_CHIPS +#define NAND_MAX_CHIPS 8 +#endif + /** * struct nand_bbt_descr - bad block table descriptor * @options: options for this descriptor diff --git a/include/lmb.h b/include/lmb.h index cc64cbbc73..14e8727f06 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -17,13 +17,13 @@ #define MAX_LMB_REGIONS 8 struct lmb_property { - ulong base; - ulong size; + phys_addr_t base; + phys_size_t size; }; struct lmb_region { unsigned long cnt; - ulong size; + phys_size_t size; struct lmb_property region[MAX_LMB_REGIONS+1]; }; @@ -35,16 +35,19 @@ struct lmb { extern struct lmb lmb; extern void lmb_init(struct lmb *lmb); -extern long lmb_add(struct lmb *lmb, ulong base, ulong size); -extern long lmb_reserve(struct lmb *lmb, ulong base, ulong size); -extern ulong lmb_alloc(struct lmb *lmb, ulong size, ulong align); -extern ulong lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr); -extern ulong __lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr); -extern int lmb_is_reserved(struct lmb *lmb, ulong addr); +extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size); +extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size); +extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align); +extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, + phys_addr_t max_addr); +extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, + phys_addr_t max_addr); +extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); +extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); extern void lmb_dump_all(struct lmb *lmb); -static inline ulong +static inline phys_size_t lmb_size_bytes(struct lmb_region *type, unsigned long region_nr) { return type->region[region_nr].size; diff --git a/include/logbuff.h b/include/logbuff.h index d06d208844..ae7908ca3d 100644 --- a/include/logbuff.h +++ b/include/logbuff.h @@ -58,6 +58,7 @@ int drv_logbuff_init (void); void logbuff_init_ptrs (void); void logbuff_log(char *msg); void logbuff_reset (void); +unsigned long logbuffer_base (void); #endif /* CONFIG_LOGBUFFER */ diff --git a/include/lxt971a.h b/include/lxt971a.h index f76c336879..72145e0aa3 100644 --- a/include/lxt971a.h +++ b/include/lxt971a.h @@ -30,15 +30,6 @@ #define __LXT971A_H__ /* PHY definitions (LXT971A) [2] */ -#define PHY_COMMON_CTRL (0x00) -#define PHY_COMMON_STAT (0x01) -#define PHY_COMMON_ID1 (0x02) -#define PHY_COMMON_ID2 (0x03) -#define PHY_COMMON_AUTO_ADV (0x04) -#define PHY_COMMON_AUTO_LNKB (0x05) -#define PHY_COMMON_AUTO_EXP (0x06) -#define PHY_COMMON_AUTO_NEXT (0x07) -#define PHY_COMMON_AUTO_LNKN (0x08) #define PHY_LXT971_PORT_CFG (0x10) #define PHY_LXT971_STAT2 (0x11) #define PHY_LXT971_INT_ENABLE (0x12) @@ -47,97 +38,6 @@ #define PHY_LXT971_DIG_CFG (0x1A) #define PHY_LXT971_TX_CTRL (0x1E) -/* CTRL PHY Control Register Bit Fields */ -#define PHY_COMMON_CTRL_RESET (0x8000) -#define PHY_COMMON_CTRL_LOOPBACK (0x4000) -#define PHY_COMMON_CTRL_SPD_MA (0x2040) -#define PHY_COMMON_CTRL_SPD_10 (0x0000) -#define PHY_COMMON_CTRL_SPD_100 (0x2000) -#define PHY_COMMON_CTRL_SPD_1000 (0x0040) -#define PHY_COMMON_CTRL_SPD_RES (0x2040) -#define PHY_COMMON_CTRL_AUTO_NEG (0x1000) -#define PHY_COMMON_CTRL_POWER_DN (0x0800) -#define PHY_COMMON_CTRL_ISOLATE (0x0400) -#define PHY_COMMON_CTRL_RES_AUTO (0x0200) -#define PHY_COMMON_CTRL_DUPLEX (0x0100) -#define PHY_COMMON_CTRL_COL_TEST (0x0080) -#define PHY_COMMON_CTRL_RES1 (0x003F) - -/* STAT Status Register Bit Fields */ -#define PHY_COMMON_STAT_100BT4 (0x8000) -#define PHY_COMMON_STAT_100BXFD (0x4000) -#define PHY_COMMON_STAT_100BXHD (0x2000) -#define PHY_COMMON_STAT_10BTFD (0x1000) -#define PHY_COMMON_STAT_10BTHD (0x0800) -#define PHY_COMMON_STAT_100BT2FD (0x0400) -#define PHY_COMMON_STAT_100BT2HD (0x0200) -#define PHY_COMMON_STAT_EXT_STAT (0x0100) -#define PHY_COMMON_STAT_RES1 (0x0080) -#define PHY_COMMON_STAT_MF_PSUP (0x0040) -#define PHY_COMMON_STAT_AN_COMP (0x0020) -#define PHY_COMMON_STAT_RMT_FLT (0x0010) -#define PHY_COMMON_STAT_AN_CAP (0x0008) -#define PHY_COMMON_STAT_LNK_STAT (0x0004) -#define PHY_COMMON_STAT_JAB_DTCT (0x0002) -#define PHY_COMMON_STAT_EXT_CAP (0x0001) - -/* AUTO_ADV Auto-neg Advert Register Bit Fields */ -#define PHY_COMMON_AUTO_ADV_NP (0x8000) -#define PHY_COMMON_AUTO_ADV_RES1 (0x4000) -#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000) -#define PHY_COMMON_AUTO_ADV_RES2 (0x1000) -#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800) -#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400) -#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200) -#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100) -#define PHY_COMMON_AUTO_ADV_100BTX (0x0080) -#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040) -#define PHY_COMMON_AUTO_ADV_10BT (0x0020) -#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F) -#define PHY_COMMON_AUTO_ADV_802_9 (0x0002) -#define PHY_COMMON_AUTO_ADV_802_3 (0x0001) - -/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */ -#define PHY_COMMON_AUTO_LNKB_NP (0x8000) -#define PHY_COMMON_AUTO_LNKB_ACK (0x4000) -#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000) -#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000) -#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800) -#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400) -#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200) -#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100) -#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080) -#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040) -#define PHY_COMMON_AUTO_LNKB_10BT (0x0020) -#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F) -#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002) -#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001) - -/* AUTO_EXP Auto-neg Expansion Register Bit Fields */ -#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0) -#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020) -#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010) -#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008) -#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004) -#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002) -#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001) - -/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */ -#define PHY_COMMON_AUTO_NEXT_NP (0x8000) -#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000) -#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000) -#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000) -#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800) -#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF) - -/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */ -#define PHY_COMMON_AUTO_LNKN_NP (0x8000) -#define PHY_COMMON_AUTO_LNKN_ACK (0x4000) -#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000) -#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000) -#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800) -#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF) - /* PORT_CFG Port Configuration Register Bit Fields */ #define PHY_LXT971_PORT_CFG_RES1 (0x8000) #define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) diff --git a/include/mmc.h b/include/mmc.h index a2716959e2..19c76fe4cd 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -25,6 +25,30 @@ #define _MMC_H_ #include <asm/arch/mmc.h> +/* MMC command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +/* SD Card command numbers */ +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH 6 +#define SD_CMD_SEND_IF_COND 8 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_SEND_OP_COND 41 + int mmc_init(int verbose); int mmc_read(ulong src, uchar *dst, int size); int mmc_write(uchar *src, ulong dst, int size); diff --git a/include/mpc83xx.h b/include/mpc83xx.h index d2e1e2bb6c..939b82541a 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -14,6 +14,7 @@ #define __MPC83XX_H__ #include <config.h> +#include <asm/fsl_lbc.h> #if defined(CONFIG_E300) #include <asm/e300.h> #endif @@ -820,6 +821,7 @@ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 #define CSCONFIG_ODT_WR_ACS 0x00010000 +#define CSCONFIG_BANK_BIT_3 0x00004000 #define CSCONFIG_ROW_BIT 0x00000700 #define CSCONFIG_ROW_BIT_12 0x00000000 #define CSCONFIG_ROW_BIT_13 0x00000100 @@ -1019,239 +1021,6 @@ #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ #define ECC_ERROR_MAN_SBEC_SHIFT 0 -/* BR - Base Registers - */ -#define BR0 0x5000 /* Register offset to immr */ -#define BR1 0x5008 -#define BR2 0x5010 -#define BR3 0x5018 -#define BR4 0x5020 -#define BR5 0x5028 -#define BR6 0x5030 -#define BR7 0x5038 - -#define BR_BA 0xFFFF8000 -#define BR_BA_SHIFT 15 -#define BR_PS 0x00001800 -#define BR_PS_SHIFT 11 -#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -#define BR_DECC 0x00000600 -#define BR_DECC_SHIFT 9 -#define BR_DECC_OFF 0x00000000 -#define BR_DECC_CHK 0x00000200 -#define BR_DECC_CHK_GEN 0x00000400 -#define BR_WP 0x00000100 -#define BR_WP_SHIFT 8 -#define BR_MSEL 0x000000E0 -#define BR_MSEL_SHIFT 5 -#define BR_MS_GPCM 0x00000000 /* GPCM */ -#define BR_MS_FCM 0x00000020 /* FCM */ -#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#define BR_MS_UPMA 0x00000080 /* UPMA */ -#define BR_MS_UPMB 0x000000A0 /* UPMB */ -#define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834X) -#define BR_ATOM 0x0000000C -#define BR_ATOM_SHIFT 2 -#endif -#define BR_V 0x00000001 -#define BR_V_SHIFT 0 - -#if defined(CONFIG_MPC834X) -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) -#else -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) -#endif - -/* OR - Option Registers - */ -#define OR0 0x5004 /* Register offset to immr */ -#define OR1 0x500C -#define OR2 0x5014 -#define OR3 0x501C -#define OR4 0x5024 -#define OR5 0x502C -#define OR6 0x5034 -#define OR7 0x503C - -#define OR_GPCM_AM 0xFFFF8000 -#define OR_GPCM_AM_SHIFT 15 -#define OR_GPCM_BCTLD 0x00001000 -#define OR_GPCM_BCTLD_SHIFT 12 -#define OR_GPCM_CSNT 0x00000800 -#define OR_GPCM_CSNT_SHIFT 11 -#define OR_GPCM_ACS 0x00000600 -#define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_0b10 0x00000400 -#define OR_GPCM_ACS_0b11 0x00000600 -#define OR_GPCM_XACS 0x00000100 -#define OR_GPCM_XACS_SHIFT 8 -#define OR_GPCM_SCY 0x000000F0 -#define OR_GPCM_SCY_SHIFT 4 -#define OR_GPCM_SCY_1 0x00000010 -#define OR_GPCM_SCY_2 0x00000020 -#define OR_GPCM_SCY_3 0x00000030 -#define OR_GPCM_SCY_4 0x00000040 -#define OR_GPCM_SCY_5 0x00000050 -#define OR_GPCM_SCY_6 0x00000060 -#define OR_GPCM_SCY_7 0x00000070 -#define OR_GPCM_SCY_8 0x00000080 -#define OR_GPCM_SCY_9 0x00000090 -#define OR_GPCM_SCY_10 0x000000a0 -#define OR_GPCM_SCY_11 0x000000b0 -#define OR_GPCM_SCY_12 0x000000c0 -#define OR_GPCM_SCY_13 0x000000d0 -#define OR_GPCM_SCY_14 0x000000e0 -#define OR_GPCM_SCY_15 0x000000f0 -#define OR_GPCM_SETA 0x00000008 -#define OR_GPCM_SETA_SHIFT 3 -#define OR_GPCM_TRLX 0x00000004 -#define OR_GPCM_TRLX_SHIFT 2 -#define OR_GPCM_EHTR 0x00000002 -#define OR_GPCM_EHTR_SHIFT 1 -#define OR_GPCM_EAD 0x00000001 -#define OR_GPCM_EAD_SHIFT 0 - -#define OR_FCM_AM 0xFFFF8000 -#define OR_FCM_AM_SHIFT 15 -#define OR_FCM_BCTLD 0x00001000 -#define OR_FCM_BCTLD_SHIFT 12 -#define OR_FCM_PGS 0x00000400 -#define OR_FCM_PGS_SHIFT 10 -#define OR_FCM_CSCT 0x00000200 -#define OR_FCM_CSCT_SHIFT 9 -#define OR_FCM_CST 0x00000100 -#define OR_FCM_CST_SHIFT 8 -#define OR_FCM_CHT 0x00000080 -#define OR_FCM_CHT_SHIFT 7 -#define OR_FCM_SCY 0x00000070 -#define OR_FCM_SCY_SHIFT 4 -#define OR_FCM_SCY_1 0x00000010 -#define OR_FCM_SCY_2 0x00000020 -#define OR_FCM_SCY_3 0x00000030 -#define OR_FCM_SCY_4 0x00000040 -#define OR_FCM_SCY_5 0x00000050 -#define OR_FCM_SCY_6 0x00000060 -#define OR_FCM_SCY_7 0x00000070 -#define OR_FCM_RST 0x00000008 -#define OR_FCM_RST_SHIFT 3 -#define OR_FCM_TRLX 0x00000004 -#define OR_FCM_TRLX_SHIFT 2 -#define OR_FCM_EHTR 0x00000002 -#define OR_FCM_EHTR_SHIFT 1 - -#define OR_UPM_AM 0xFFFF8000 -#define OR_UPM_AM_SHIFT 15 -#define OR_UPM_XAM 0x00006000 -#define OR_UPM_XAM_SHIFT 13 -#define OR_UPM_BCTLD 0x00001000 -#define OR_UPM_BCTLD_SHIFT 12 -#define OR_UPM_BI 0x00000100 -#define OR_UPM_BI_SHIFT 8 -#define OR_UPM_TRLX 0x00000004 -#define OR_UPM_TRLX_SHIFT 2 -#define OR_UPM_EHTR 0x00000002 -#define OR_UPM_EHTR_SHIFT 1 -#define OR_UPM_EAD 0x00000001 -#define OR_UPM_EAD_SHIFT 0 - -#define OR_SDRAM_AM 0xFFFF8000 -#define OR_SDRAM_AM_SHIFT 15 -#define OR_SDRAM_XAM 0x00006000 -#define OR_SDRAM_XAM_SHIFT 13 -#define OR_SDRAM_COLS 0x00001C00 -#define OR_SDRAM_COLS_SHIFT 10 -#define OR_SDRAM_ROWS 0x000001C0 -#define OR_SDRAM_ROWS_SHIFT 6 -#define OR_SDRAM_PMSEL 0x00000020 -#define OR_SDRAM_PMSEL_SHIFT 5 -#define OR_SDRAM_EAD 0x00000001 -#define OR_SDRAM_EAD_SHIFT 0 - -#define OR_AM_32KB 0xFFFF8000 -#define OR_AM_64KB 0xFFFF0000 -#define OR_AM_128KB 0xFFFE0000 -#define OR_AM_256KB 0xFFFC0000 -#define OR_AM_512KB 0xFFF80000 -#define OR_AM_1MB 0xFFF00000 -#define OR_AM_2MB 0xFFE00000 -#define OR_AM_4MB 0xFFC00000 -#define OR_AM_8MB 0xFF800000 -#define OR_AM_16MB 0xFF000000 -#define OR_AM_32MB 0xFE000000 -#define OR_AM_64MB 0xFC000000 -#define OR_AM_128MB 0xF8000000 -#define OR_AM_256MB 0xF0000000 -#define OR_AM_512MB 0xE0000000 -#define OR_AM_1GB 0xC0000000 -#define OR_AM_2GB 0x80000000 -#define OR_AM_4GB 0x00000000 - -#define LBLAWAR_EN 0x80000000 -#define LBLAWAR_4KB 0x0000000B -#define LBLAWAR_8KB 0x0000000C -#define LBLAWAR_16KB 0x0000000D -#define LBLAWAR_32KB 0x0000000E -#define LBLAWAR_64KB 0x0000000F -#define LBLAWAR_128KB 0x00000010 -#define LBLAWAR_256KB 0x00000011 -#define LBLAWAR_512KB 0x00000012 -#define LBLAWAR_1MB 0x00000013 -#define LBLAWAR_2MB 0x00000014 -#define LBLAWAR_4MB 0x00000015 -#define LBLAWAR_8MB 0x00000016 -#define LBLAWAR_16MB 0x00000017 -#define LBLAWAR_32MB 0x00000018 -#define LBLAWAR_64MB 0x00000019 -#define LBLAWAR_128MB 0x0000001A -#define LBLAWAR_256MB 0x0000001B -#define LBLAWAR_512MB 0x0000001C -#define LBLAWAR_1GB 0x0000001D -#define LBLAWAR_2GB 0x0000001E - -/* LBCR - Local Bus Configuration Register - */ -#define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 -#define LBCR_BCTLC 0x00C00000 -#define LBCR_BCTLC_SHIFT 22 -#define LBCR_LPBSE 0x00020000 -#define LBCR_LPBSE_SHIFT 17 -#define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 -#define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 - -/* LCRR - Clock Ratio Register - */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_BUFCMDC_1 0x10000000 -#define LCRR_BUFCMDC_2 0x20000000 -#define LCRR_BUFCMDC_3 0x30000000 -#define LCRR_BUFCMDC_4 0x00000000 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_ECL_4 0x00000000 -#define LCRR_ECL_5 0x01000000 -#define LCRR_ECL_6 0x02000000 -#define LCRR_ECL_7 0x03000000 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_EADC_1 0x00010000 -#define LCRR_EADC_2 0x00020000 -#define LCRR_EADC_3 0x00030000 -#define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_SHIFT 0 -#define LCRR_CLKDIV_2 0x00000002 -#define LCRR_CLKDIV_4 0x00000004 -#define LCRR_CLKDIV_8 0x00000008 - /* DMAMR - DMA Mode Register */ #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 321b24f755..a4d4d65526 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -6,6 +6,8 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ +#include <asm/fsl_lbc.h> + /* define for common ppc_asm.tmpl */ #define EXC_OFF_SYS_RESET 0x100 /* System reset */ #define _START_OFFSET 0 @@ -26,39 +28,4 @@ #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ -/* - * Local Bus Controller - memory controller registers - */ -#define BRx_V 0x00000001 /* Bank Valid */ -#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ -#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */ -#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ -#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ -#define BRx_PS_8 0x00000800 /* 8 bit port size */ -#define BRx_PS_32 0x00001800 /* 32 bit port size */ -#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ - -#define ORxG_EAD 0x00000001 /* External addr latch delay */ -#define ORxG_EHTR 0x00000002 /* Extended hold time on read */ -#define ORxG_TRLX 0x00000004 /* Timing relaxed */ -#define ORxG_SETA 0x00000008 /* External address termination */ -#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ -#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */ -#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ -#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ - -#define ORxU_BI 0x00000100 /* Burst Inhibit */ -#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ - -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ -#define MxMR_OP_WARR 0x10000000 /* Write to Array */ -#define MxMR_BSEL 0x80000000 /* Bus Select */ - -/* helpers to convert values into an OR address mask (GPCM mode) */ -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) - #endif /* __MPC85xx_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fd349af98..ce3d784da0 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -7,6 +7,8 @@ #ifndef __MPC86xx_H__ #define __MPC86xx_H__ +#include <asm/fsl_lbc.h> + #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ #define _START_OFFSET EXC_OFF_SYS_RESET diff --git a/include/nand.h b/include/nand.h index 247d3465db..e1285cdae9 100644 --- a/include/nand.h +++ b/include/nand.h @@ -24,6 +24,9 @@ #ifndef _NAND_H_ #define _NAND_H_ +extern void nand_init(void); + +#ifndef CFG_NAND_LEGACY #include <linux/mtd/compat.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -32,7 +35,6 @@ typedef struct mtd_info nand_info_t; extern int nand_curr_device; extern nand_info_t nand_info[]; -extern void nand_init(void); static inline int nand_read(nand_info_t *info, off_t ofs, size_t *len, u_char *buf) { @@ -122,4 +124,5 @@ int nand_get_lock_status(nand_info_t *meminfo, ulong offset); void board_nand_select_device(struct nand_chip *nand, int chip); #endif +#endif /* !CFG_NAND_LEGACY */ #endif diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h index 123e6f4c2a..b509697c2f 100644 --- a/include/ns7520_eth.h +++ b/include/ns7520_eth.h @@ -24,6 +24,7 @@ #ifdef CONFIG_DRIVER_NS7520_ETHERNET +#include <miiphy.h> #include "lxt971a.h" /* The port addresses */ diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h index a6e5889b7b..80c721b900 100644 --- a/include/ns9750_eth.h +++ b/include/ns9750_eth.h @@ -31,6 +31,7 @@ #ifdef CONFIG_DRIVER_NS9750_ETHERNET +#include <miiphy.h> #include "lxt971a.h" #define NS9750_ETH_MODULE_BASE (0xA0600000) diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index bd1831ea6d..4449f987bf 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -14,6 +14,8 @@ #ifndef __UBOOT_ONENAND_H #define __UBOOT_ONENAND_H +#include <linux/types.h> + struct kvec { void *iov_base; size_t iov_len; @@ -22,6 +24,9 @@ struct kvec { typedef int spinlock_t; typedef int wait_queue_head_t; +struct mtd_info; +struct erase_info; + /* Functions */ extern void onenand_init(void); extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, diff --git a/include/pci_ids.h b/include/pci_ids.h index 61c22031e9..165456bc8c 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1812,7 +1812,8 @@ #define PCI_DEVICE_ID_INTEL_82434 0x04a3 #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 -#define PCI_DEVICE_ID_INTEL_82541ER 0x1078 +#define PCI_DEVICE_ID_INTEL_82541ER 0x1078 +#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000 #define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001 #define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004 @@ -1826,6 +1827,7 @@ #define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011 #define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012 #define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015 +#define PCI_DEVICE_ID_INTEL_82545GM_COPPER 0x1026 #define PCI_DEVICE_ID_INTEL_82559 0x1030 #define PCI_DEVICE_ID_INTEL_82562ET 0x1031 diff --git a/include/ppc405.h b/include/ppc405.h index d953378c73..2231a5fbb4 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,10 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +/* Define bits and masks for real-mode storage attribute control registers */ +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) + #ifndef CONFIG_IOP480 #define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ #else @@ -363,31 +367,118 @@ #endif /* defined(CONFIG_405EZ) */ /****************************************************************************** - * SDRAM Controller - ******************************************************************************/ - /* values for memcfga register - indirect addressing of these regs */ -#ifndef CONFIG_405EP - #define mem_besra 0x00 /* bus error syndrome reg a */ - #define mem_besrsa 0x04 /* bus error syndrome reg set a */ - #define mem_besrb 0x08 /* bus error syndrome reg b */ - #define mem_besrsb 0x0c /* bus error syndrome reg set b */ - #define mem_bear 0x10 /* bus error address reg */ -#endif - #define mem_mcopt1 0x20 /* memory controller options 1 */ - #define mem_status 0x24 /* memory status */ - #define mem_rtr 0x30 /* refresh timer reg */ - #define mem_pmit 0x34 /* power management idle timer */ - #define mem_mb0cf 0x40 /* memory bank 0 configuration */ - #define mem_mb1cf 0x44 /* memory bank 1 configuration */ -#ifndef CONFIG_405EP - #define mem_mb2cf 0x48 /* memory bank 2 configuration */ - #define mem_mb3cf 0x4c /* memory bank 3 configuration */ -#endif - #define mem_sdtr1 0x80 /* timing reg 1 */ -#ifndef CONFIG_405EP - #define mem_ecccf 0x94 /* ECC configuration */ - #define mem_eccerr 0x98 /* ECC error status */ -#endif + * External Bus Controller (EBC) + *****************************************************************************/ + +/* Bank Configuration Register */ +#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) +#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ + EBC_BXCR_BAS_MASK) << 0) +#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) +#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) +#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) +#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) +#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) +#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) +#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) +#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) +#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) +#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) +#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) +#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) +#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) + +/* Bank Access Parameter Register */ +#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) +#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ + (static_cast(unsigned long, n)) \ + & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0x7) +#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) +#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) +#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) +#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) +#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) +#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ + (static_cast(unsigned long, n)) \ + & 0x7) +#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) +#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) +#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) +#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) +#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) +#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) +#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) +#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) + +/* Configuration Register */ +#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) +#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) +#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) +#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) +#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) +#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) +#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) +#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) +#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) +#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) +#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) +#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) +#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) +#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) +#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) +#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) +#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) +#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) +#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) +#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) +#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) +#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0) +#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1) +#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) +#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) +#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) +#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x1F) +#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) +#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) +#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) +#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) +#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) #ifndef CONFIG_405EP /****************************************************************************** @@ -1163,369 +1254,6 @@ #if defined(CONFIG_405EX) #define SDR0_SRST 0x0200 -#define SDRAM_BESR0 0x00 -#define SDRAM_BEARL 0x02 -#define SDRAM_BEARU 0x03 -#define SDRAM_WMIRQ 0x06 /**/ -#define SDRAM_PLBOPT 0x08 /**/ -#define SDRAM_PUABA 0x09 /**/ -#define SDRAM_MCSTAT 0x1F /* memory controller status */ -#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ -#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ -#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ -#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ -#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ -#define SDRAM_CODT 0x26 /* on die termination for controller */ -#define SDRAM_VVPR 0x27 /* variable VRef programmming */ -#define SDRAM_OPARS 0x28 /* on chip driver control setup */ -#define SDRAM_OPART 0x29 /* on chip driver control trigger */ -#define SDRAM_RTR 0x30 /* refresh timer */ -#define SDRAM_PMIT 0x34 /* power management idle timer */ -#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ -#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ -#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */ -#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */ -#define SDRAM_INITPLR0 0x50 /* manual initialization control */ -#define SDRAM_INITPLR1 0x51 /* manual initialization control */ -#define SDRAM_INITPLR2 0x52 /* manual initialization control */ -#define SDRAM_INITPLR3 0x53 /* manual initialization control */ -#define SDRAM_INITPLR4 0x54 /* manual initialization control */ -#define SDRAM_INITPLR5 0x55 /* manual initialization control */ -#define SDRAM_INITPLR6 0x56 /* manual initialization control */ -#define SDRAM_INITPLR7 0x57 /* manual initialization control */ -#define SDRAM_INITPLR8 0x58 /* manual initialization control */ -#define SDRAM_INITPLR9 0x59 /* manual initialization control */ -#define SDRAM_INITPLR10 0x5a /* manual initialization control */ -#define SDRAM_INITPLR11 0x5b /* manual initialization control */ -#define SDRAM_INITPLR12 0x5c /* manual initialization control */ -#define SDRAM_INITPLR13 0x5d /* manual initialization control */ -#define SDRAM_INITPLR14 0x5e /* manual initialization control */ -#define SDRAM_INITPLR15 0x5f /* manual initialization control */ -#define SDRAM_RQDC 0x70 /* read DQS delay control */ -#define SDRAM_RFDC 0x74 /* read feedback delay control */ -#define SDRAM_RDCC 0x78 /* read data capture control */ -#define SDRAM_DLCR 0x7A /* delay line calibration */ -#define SDRAM_CLKTR 0x80 /* DDR clock timing */ -#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ -#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ -#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ -#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ -#define SDRAM_MMODE 0x88 /* memory mode */ -#define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_RID 0xF8 /* revision ID */ - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-7 configuration -+-----------------------------------------------------------------------------*/ -#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ -#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ -#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ -#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ -#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ -#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ -#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ -#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ -#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ -#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ -#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ -#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Status -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ -#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ -#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 1 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */ -#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ -#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ -#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) -#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ -#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ -#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ -#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ -#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ -#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ -#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ -#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ -#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ -#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ -#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ -#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ -#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ -#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ -#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ -#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ -#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ -#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ -#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ -#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ -#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ -#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ -#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ -#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 2 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ -#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ -#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ -#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ -#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ -#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ -#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ -#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ -#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ -#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ -#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ -#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ -#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ - -/*-----------------------------------------------------------------------------+ -| SDRAM Refresh Timer Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFF80000 -#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) -#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) - -/*-----------------------------------------------------------------------------+ -| SDRAM Read DQS Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RQDC_RQDE_MASK 0x80000000 -#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 -#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 -#define SDRAM_RQDC_RQFD_MASK 0x000001FF -#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) - -#define SDRAM_RQDC_RQFD_MAX 0xFF - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Data Capture Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RDCC_RDSS_MASK 0xC0000000 -#define SDRAM_RDCC_RDSS_T1 0x00000000 -#define SDRAM_RDCC_RDSS_T2 0x40000000 -#define SDRAM_RDCC_RDSS_T3 0x80000000 -#define SDRAM_RDCC_RDSS_T4 0xC0000000 -#define SDRAM_RDCC_RSAE_MASK 0x00000001 -#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 -#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Feedback Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RFDC_ARSE_MASK 0x80000000 -#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 -#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 -#define SDRAM_RFDC_RFOS_MASK 0x007F0000 -#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define SDRAM_RFDC_RFFD_MASK 0x000003FF -#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) - -#define SDRAM_RFDC_RFFD_MAX 0x4FF - -/*-----------------------------------------------------------------------------+ -| SDRAM Delay Line Calibration Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 -#define SDRAM_DLCR_DCLM_AUTO 0x00000000 -#define SDRAM_DLCR_DLCR_MASK 0x08000000 -#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 -#define SDRAM_DLCR_DLCR_IDLE 0x00000000 -#define SDRAM_DLCR_DLCS_MASK 0x07000000 -#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 -#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 -#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 -#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 -#define SDRAM_DLCR_DLCS_ERROR 0x04000000 -#define SDRAM_DLCR_DLCV_MASK 0x000001FF -#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) -#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) - -/*-----------------------------------------------------------------------------+ -| SDRAM Controller On Die Termination Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 - -/*-----------------------------------------------------------------------------+ -| SDRAM Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 - -/*-----------------------------------------------------------------------------+ -| SDRAM Extended Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Clock Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Write Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000 -#define SDRAM_WRDTR_LLWP_MASK 0x10000000 -#define SDRAM_WRDTR_LLWP_DIS 0x10000000 -#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 -#define SDRAM_WRDTR_WTR_MASK 0x0E000000 -#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 -#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 -#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR1 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR1_LDOF_MASK 0x80000000 -#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 -#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 -#define SDRAM_SDTR1_RTW_MASK 0x00F00000 -#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 -#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 -#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 -#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 -#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 -#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 -#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000 -#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR2 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR2_RCD_MASK 0xF0000000 -#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 -#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 -#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 -#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 -#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 -#define SDRAM_SDTR2_WTR_MASK 0x0F000000 -#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 -#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 -#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 -#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 -#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 -#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 -#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 -#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 -#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 -#define SDRAM_SDTR2_WPC_MASK 0x0000F000 -#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 -#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 -#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 -#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 -#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 -#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) -#define SDRAM_SDTR2_RPC_MASK 0x00000F00 -#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 -#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 -#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 -#define SDRAM_SDTR2_RP_MASK 0x000000F0 -#define SDRAM_SDTR2_RP_3_CLK 0x00000030 -#define SDRAM_SDTR2_RP_4_CLK 0x00000040 -#define SDRAM_SDTR2_RP_5_CLK 0x00000050 -#define SDRAM_SDTR2_RP_6_CLK 0x00000060 -#define SDRAM_SDTR2_RP_7_CLK 0x00000070 -#define SDRAM_SDTR2_RRD_MASK 0x0000000F -#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 -#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR3 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR3_RAS_MASK 0x1F000000 -#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define SDRAM_SDTR3_RC_MASK 0x001F0000 -#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define SDRAM_SDTR3_XCS_MASK 0x00001F00 -#define SDRAM_SDTR3_XCS 0x00000D00 -#define SDRAM_SDTR3_RFC_MASK 0x0000003F -#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-1 configuration -+-----------------------------------------------------------------------------*/ -#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ -#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ -#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ -#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ -#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ -#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ -#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ -#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ -#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ -#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ -#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ -#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ - #define sdr_uart0 0x0120 /* UART0 Config */ #define sdr_uart1 0x0121 /* UART1 Config */ #define sdr_mfr 0x4300 /* SDR0_MFR reg */ @@ -1612,4 +1340,27 @@ #define SDR0_PFC1_GPT_FREQ 0x0000000f #endif +/* General Purpose Timer (GPT) Register Offsets */ +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C + #endif /* __PPC405_H__ */ diff --git a/include/ppc440.h b/include/ppc440.h index 54b4553139..c581f1b468 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -210,36 +210,6 @@ #define sdr_plbtr 0x4200 #define sdr_mfr 0x4300 /* SDR0_MFR reg */ -/*----------------------------------------------------------------------------- - | SDRAM Controller - +----------------------------------------------------------------------------*/ -/* values for memcfga register - indirect addressing of these regs */ -#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ -#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ -#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ -#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ -#define mem_bear 0x0010 /* bus error address reg */ -#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ -#define mem_mirq_set 0x0012 /* bus master interrupt (set) */ -#define mem_slio 0x0018 /* ddr sdram slave interface options */ -#define mem_cfg0 0x0020 /* ddr sdram options 0 */ -#define mem_cfg1 0x0021 /* ddr sdram options 1 */ -#define mem_devopt 0x0022 /* ddr sdram device options */ -#define mem_mcsts 0x0024 /* memory controller status */ -#define mem_rtr 0x0030 /* refresh timer register */ -#define mem_pmit 0x0034 /* power management idle timer */ -#define mem_uabba 0x0038 /* plb UABus base address */ -#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ -#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ -#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ -#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ -#define mem_tr0 0x0080 /* sdram timing register 0 */ -#define mem_tr1 0x0081 /* sdram timing register 1 */ -#define mem_clktr 0x0082 /* ddr clock timing register */ -#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ -#define mem_dlycal 0x0084 /* delay line calibration register */ -#define mem_eccesr 0x0098 /* ECC error status */ - #ifdef CONFIG_440GX #define sdr_amp 0x0240 #define sdr_xpllc 0x01c1 @@ -380,872 +350,6 @@ #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ #endif /* CONFIG_440SPE */ -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -/*----------------------------------------------------------------------------+ -| SDRAM Controller -+----------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------+ -| SDRAM DLYCAL Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - -/*----------------------------------------------------------------------------+ -| Memory queue defines -+----------------------------------------------------------------------------*/ -/* A REVOIR versus RWC - SG*/ -#define SDRAMQ_DCR_BASE 0x040 - -#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ -#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ -#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ -#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ -#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ -#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ -#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ -#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ -#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ -#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ -#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ -#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ -#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ -#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-7 configuration -+-----------------------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2) -#endif /* CONFIG_440SPE */ -#if defined(CONFIG_440SP) -#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000)) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000)) -#endif /* CONFIG_440SP */ -#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ -#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6) -#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF) -#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */ -#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */ -#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */ -#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */ -#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */ -#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */ -#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */ -#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */ -#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */ -#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */ -#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */ - -/*----------------------------------------------------------------------------+ -| Memory controller defines -+----------------------------------------------------------------------------*/ -/* A REVOIR versus specs 4 bank - SG*/ -#define SDRAM_MCSTAT 0x14 /* memory controller status */ -#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ -#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ -#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ -#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ -#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ -#define SDRAM_CODT 0x26 /* on die termination for controller */ -#define SDRAM_VVPR 0x27 /* variable VRef programmming */ -#define SDRAM_OPARS 0x28 /* on chip driver control setup */ -#define SDRAM_OPART 0x29 /* on chip driver control trigger */ -#define SDRAM_RTR 0x30 /* refresh timer */ -#define SDRAM_PMIT 0x34 /* power management idle timer */ -#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ -#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ -#define SDRAM_MB2CF 0x48 -#define SDRAM_MB3CF 0x4C -#define SDRAM_INITPLR0 0x50 /* manual initialization control */ -#define SDRAM_INITPLR1 0x51 /* manual initialization control */ -#define SDRAM_INITPLR2 0x52 /* manual initialization control */ -#define SDRAM_INITPLR3 0x53 /* manual initialization control */ -#define SDRAM_INITPLR4 0x54 /* manual initialization control */ -#define SDRAM_INITPLR5 0x55 /* manual initialization control */ -#define SDRAM_INITPLR6 0x56 /* manual initialization control */ -#define SDRAM_INITPLR7 0x57 /* manual initialization control */ -#define SDRAM_INITPLR8 0x58 /* manual initialization control */ -#define SDRAM_INITPLR9 0x59 /* manual initialization control */ -#define SDRAM_INITPLR10 0x5a /* manual initialization control */ -#define SDRAM_INITPLR11 0x5b /* manual initialization control */ -#define SDRAM_INITPLR12 0x5c /* manual initialization control */ -#define SDRAM_INITPLR13 0x5d /* manual initialization control */ -#define SDRAM_INITPLR14 0x5e /* manual initialization control */ -#define SDRAM_INITPLR15 0x5f /* manual initialization control */ -#define SDRAM_RQDC 0x70 /* read DQS delay control */ -#define SDRAM_RFDC 0x74 /* read feedback delay control */ -#define SDRAM_RDCC 0x78 /* read data capture control */ -#define SDRAM_DLCR 0x7A /* delay line calibration */ -#define SDRAM_CLKTR 0x80 /* DDR clock timing */ -#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ -#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ -#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ -#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ -#define SDRAM_MMODE 0x88 /* memory mode */ -#define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_CID 0xA4 /* core ID */ -#define SDRAM_RID 0xA8 /* revision ID */ -#define SDRAM_RTSR 0xB1 /* run time status tracking */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Status -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ -#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ -#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */ -#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */ -#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 1 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/ -#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ -#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ -#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) -#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ -#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ -#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ -#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ -#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ -#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ -#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ -#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ -#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ -#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ -#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ -#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ -#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ -#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ -#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ -#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ -#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ -#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ -#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ -#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ -#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ -#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ -#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ -#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 2 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ -#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ -#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ -#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ -#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ -#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ -#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ -#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ -#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ -#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ -#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ -#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ -#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ - -/*-----------------------------------------------------------------------------+ -| SDRAM Refresh Timer Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFF80000 -#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) -#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) - -/*-----------------------------------------------------------------------------+ -| SDRAM Read DQS Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RQDC_RQDE_MASK 0x80000000 -#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 -#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 -#define SDRAM_RQDC_RQFD_MASK 0x000001FF -#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) - -#define SDRAM_RQDC_RQFD_MAX 0x1FF - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Data Capture Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RDCC_RDSS_MASK 0xC0000000 -#define SDRAM_RDCC_RDSS_T1 0x00000000 -#define SDRAM_RDCC_RDSS_T2 0x40000000 -#define SDRAM_RDCC_RDSS_T3 0x80000000 -#define SDRAM_RDCC_RDSS_T4 0xC0000000 -#define SDRAM_RDCC_RSAE_MASK 0x00000001 -#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 -#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Feedback Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RFDC_ARSE_MASK 0x80000000 -#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 -#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 -#define SDRAM_RFDC_RFOS_MASK 0x007F0000 -#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define SDRAM_RFDC_RFFD_MASK 0x000007FF -#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0) - -#define SDRAM_RFDC_RFFD_MAX 0x7FF - -/*-----------------------------------------------------------------------------+ -| SDRAM Delay Line Calibration Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 -#define SDRAM_DLCR_DCLM_AUTO 0x00000000 -#define SDRAM_DLCR_DLCR_MASK 0x08000000 -#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 -#define SDRAM_DLCR_DLCR_IDLE 0x00000000 -#define SDRAM_DLCR_DLCS_MASK 0x07000000 -#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 -#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 -#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 -#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 -#define SDRAM_DLCR_DLCS_ERROR 0x04000000 -#define SDRAM_DLCR_DLCV_MASK 0x000001FF -#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) -#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) - -/*-----------------------------------------------------------------------------+ -| SDRAM Controller On Die Termination Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 - -/*-----------------------------------------------------------------------------+ -| SDRAM Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 - -/*-----------------------------------------------------------------------------+ -| SDRAM Extended Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Clock Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 -#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000 -#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Write Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_WRDTR_LLWP_MASK 0x10000000 -#define SDRAM_WRDTR_LLWP_DIS 0x10000000 -#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 -#define SDRAM_WRDTR_WTR_MASK 0x0E000000 -#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 -#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000 -#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 -#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR1 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR1_LDOF_MASK 0x80000000 -#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 -#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 -#define SDRAM_SDTR1_RTW_MASK 0x00F00000 -#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 -#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 -#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 -#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 -#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 -#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 -#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000 -#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR2 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR2_RCD_MASK 0xF0000000 -#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 -#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 -#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 -#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 -#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 -#define SDRAM_SDTR2_WTR_MASK 0x0F000000 -#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 -#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 -#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 -#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 -#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 -#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 -#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 -#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 -#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 -#define SDRAM_SDTR2_WPC_MASK 0x0000F000 -#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 -#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 -#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 -#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 -#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 -#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) -#define SDRAM_SDTR2_RPC_MASK 0x00000F00 -#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 -#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 -#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 -#define SDRAM_SDTR2_RP_MASK 0x000000F0 -#define SDRAM_SDTR2_RP_3_CLK 0x00000030 -#define SDRAM_SDTR2_RP_4_CLK 0x00000040 -#define SDRAM_SDTR2_RP_5_CLK 0x00000050 -#define SDRAM_SDTR2_RP_6_CLK 0x00000060 -#define SDRAM_SDTR2_RP_7_CLK 0x00000070 -#define SDRAM_SDTR2_RRD_MASK 0x0000000F -#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 -#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR3 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR3_RAS_MASK 0x1F000000 -#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define SDRAM_SDTR3_RC_MASK 0x001F0000 -#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define SDRAM_SDTR3_XCS_MASK 0x00001F00 -#define SDRAM_SDTR3_XCS 0x00000D00 -#define SDRAM_SDTR3_RFC_MASK 0x0000003F -#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-1 configuration -+-----------------------------------------------------------------------------*/ -#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ -#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ -#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ -#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ -#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ -#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ -#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ -#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ -#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ -#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ -#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ -#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ - -#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/ -#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */ -#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */ -#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */ -#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */ - -#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/*----------------------------------------------------------------------------- - | SDRAM Controller - +----------------------------------------------------------------------------*/ -#define DDR0_00 0x00 -#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -/* Status */ -#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ -/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT0 0x00010000 -/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT1 0x00020000 -/* Bit2. Single correctable ECC event detected */ -#define DDR0_00_INT_STATUS_BIT2 0x00040000 -/* Bit3. Multiple correctable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT3 0x00080000 -/* Bit4. Single uncorrectable ECC event detected. */ -#define DDR0_00_INT_STATUS_BIT4 0x00100000 -/* Bit5. Multiple uncorrectable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT5 0x00200000 -/* Bit6. DRAM initialization complete. */ -#define DDR0_00_INT_STATUS_BIT6 0x00400000 -/* Bit7. Logical OR of all lower bits. */ -#define DDR0_00_INT_STATUS_BIT7 0x00800000 - -#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 -#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_00_DLL_START_POINT_MASK 0x0000007F -#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_01 0x01 -#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 -#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 -#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ -#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_02 0x02 -#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ -#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) -#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) -#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ -#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ -#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_02_START_MASK 0x00000001 -#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) -#define DDR0_02_START_OFF 0x00000000 -#define DDR0_02_START_ON 0x00000001 - -#define DDR0_03 0x03 -#define DDR0_03_BSTLEN_MASK 0x07000000 -#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_03_CASLAT_MASK 0x00070000 -#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 -#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_03_INITAREF_MASK 0x0000000F -#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_04 0x04 -#define DDR0_04_TRC_MASK 0x1F000000 -#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_04_TRRD_MASK 0x00070000 -#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_04_TRTP_MASK 0x00000700 -#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) - -#define DDR0_05 0x05 -#define DDR0_05_TMRD_MASK 0x1F000000 -#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_05_TEMRS_MASK 0x00070000 -#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_05_TRP_MASK 0x00000F00 -#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_05_TRAS_MIN_MASK 0x000000FF -#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#define DDR0_06 0x06 -#define DDR0_06_WRITEINTERP_MASK 0x01000000 -#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_06_TWTR_MASK 0x00070000 -#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_06_TDLL_MASK 0x0000FF00 -#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_06_TRFC_MASK 0x0000007F -#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_07 0x07 -#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 -#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_07_TFAW_MASK 0x001F0000 -#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 -#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_07_AREFRESH_MASK 0x00000001 -#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_08 0x08 -#define DDR0_08_WRLAT_MASK 0x07000000 -#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_08_TCPD_MASK 0x00FF0000 -#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_08_DQS_N_EN_MASK 0x00000100 -#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 -#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_09 0x09 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_09_RTT_0_MASK 0x00030000 -#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 -#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F -#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_10 0x0A -#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ -#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_10_CS_MAP_MASK 0x00000300 -#define DDR0_10_CS_MAP_NO_MEM 0x00000000 -#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 -#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 -#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F -#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) - -#define DDR0_11 0x0B -#define DDR0_11_SREFRESH_MASK 0x01000000 -#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_11_TXSNR_MASK 0x00FF0000 -#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_11_TXSR_MASK 0x0000FF00 -#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) - -#define DDR0_12 0x0C -#define DDR0_12_TCKE_MASK 0x0000007 -#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) - -#define DDR0_14 0x0E -#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 -#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_14_REDUC_MASK 0x00010000 -#define DDR0_14_REDUC_64BITS 0x00000000 -#define DDR0_14_REDUC_32BITS 0x00010000 -#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 -#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) - -#define DDR0_17 0x11 -#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 -#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ -#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) - -#define DDR0_18 0x12 -#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 -#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 -#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 -#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F -#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_19 0x13 -#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 -#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 -#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 -#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F -#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_20 0x14 -#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 -#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 -#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 -#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F -#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_21 0x15 -#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 -#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 -#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 -#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F -#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_22 0x16 -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ -#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 -#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F -#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_23 0x17 -#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 -#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ -#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ -#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ -#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_24 0x18 -#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 -#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 -#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 -#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 -#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) -#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) - -#define DDR0_25 0x19 -#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ -#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ -#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define DDR0_26 0x1A -#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 -#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_27 0x1B -#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 -#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_27_TINIT_MASK 0x0000FFFF -#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_28 0x1C -#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 -#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF -#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_31 0x1F -#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF -#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_32 0x20 -#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_33 0x21 -#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_34 0x22 -#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_35 0x23 -#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_36 0x24 -#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_37 0x25 -#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_38 0x26 -#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_39 0x27 -#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_40 0x28 -#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_41 0x29 -#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_42 0x2A -#define DDR0_42_ADDR_PINS_MASK 0x07000000 -#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F -#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_43 0x2B -#define DDR0_43_TWR_MASK 0x07000000 -#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_43_APREBIT_MASK 0x000F0000 -#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 -#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 -#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_44 0x2C -#define DDR0_44_TRCD_MASK 0x000000FF -#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#endif /* CONFIG_440EPX */ - /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ @@ -3367,6 +2471,8 @@ #define AHB_TOP 0xA4 #define AHB_BOT 0xA5 +#define SDR0_AHB_CFG 0x370 +#define SDR0_USB2HOST_CFG 0x371 #endif /* CONFIG_460EX || CONFIG_460GT */ #define SDR0_SDCS_SDD (0x80000000 >> 31) diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 76fe8727f5..0a8479f262 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,12 +22,52 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ +/* + * Configure which SDRAM/DDR/DDR2 controller is equipped + */ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ + defined(CONFIG_AP1000) || defined(CONFIG_ML2) +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ +#endif + +#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ +#endif + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */ +#endif + +#if defined(CONFIG_405EX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ +#endif + #if defined(CONFIG_440) #include <ppc440.h> #else #include <ppc405.h> #endif +#include <asm/ppc4xx-sdram.h> + +/* + * Macro for generating register field mnemonics + */ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + +/* + * Elide casts when assembling register mnemonics + */ +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + /* * Common stuff for 4xx (405 and 440) */ diff --git a/include/sha256.h b/include/sha256.h new file mode 100644 index 0000000000..e38ea898c3 --- /dev/null +++ b/include/sha256.h @@ -0,0 +1,16 @@ +#ifndef _SHA256_H +#define _SHA256_H + +#define SHA256_SUM_LEN 32 + +typedef struct { + uint32_t total[2]; + uint32_t state[8]; + uint8_t buffer[64]; +} sha256_context; + +void sha256_starts(sha256_context * ctx); +void sha256_update(sha256_context * ctx, uint8_t * input, uint32_t length); +void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]); + +#endif /* _SHA256_H */ diff --git a/include/spi.h b/include/spi.h index 3a55a68c4d..320e50e529 100644 --- a/include/spi.h +++ b/include/spi.h @@ -24,6 +24,15 @@ #ifndef _SPI_H_ #define _SPI_H_ +/* Controller-specific definitions: */ + +/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ +#ifdef CONFIG_MPC8XXX_SPI +# ifndef CONFIG_HARD_SPI +# define CONFIG_HARD_SPI +# endif +#endif + /* SPI mode flags */ #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ @@ -31,22 +40,87 @@ #define SPI_MODE_1 (0|SPI_CPHA) #define SPI_MODE_2 (SPI_CPOL|0) #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) -#define SPI_CS_HIGH 0x04 /* chipselect active high? */ +#define SPI_CS_HIGH 0x04 /* CS active high */ #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ #define SPI_3WIRE 0x10 /* SI/SO signals shared */ #define SPI_LOOP 0x20 /* loopback mode */ -/* - * The function call pointer type used to drive the chip select. - */ -typedef void (*spi_chipsel_type)(int cs); +/* SPI transfer flags */ +#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ +#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ +/*----------------------------------------------------------------------- + * Representation of a SPI slave, i.e. what we're communicating with. + * + * Drivers are expected to extend this with controller-specific data. + * + * bus: ID of the bus that the slave is attached to. + * cs: ID of the chip select connected to the slave. + */ +struct spi_slave { + unsigned int bus; + unsigned int cs; +}; /*----------------------------------------------------------------------- * Initialization, must be called once on start up. + * + * TODO: I don't think we really need this. */ void spi_init(void); +/*----------------------------------------------------------------------- + * Set up communications parameters for a SPI slave. + * + * This must be called once for each slave. Note that this function + * usually doesn't touch any actual hardware, it only initializes the + * contents of spi_slave so that the hardware can be easily + * initialized later. + * + * bus: Bus ID of the slave chip. + * cs: Chip select ID of the slave chip on the specified bus. + * max_hz: Maximum SCK rate in Hz. + * mode: Clock polarity, clock phase and other parameters. + * + * Returns: A spi_slave reference that can be used in subsequent SPI + * calls, or NULL if one or more of the parameters are not supported. + */ +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); + +/*----------------------------------------------------------------------- + * Free any memory associated with a SPI slave. + * + * slave: The SPI slave + */ +void spi_free_slave(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Claim the bus and prepare it for communication with a given slave. + * + * This must be called before doing any transfers with a SPI slave. It + * will enable and initialize any SPI hardware as necessary, and make + * sure that the SCK line is in the correct idle state. It is not + * allowed to claim the same bus for several slaves without releasing + * the bus in between. + * + * slave: The SPI slave + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ +int spi_claim_bus(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Release the SPI bus + * + * This must be called once for every call to spi_claim_bus() after + * all transfers have finished. It may disable any SPI hardware as + * appropriate. + * + * slave: The SPI slave + */ +void spi_release_bus(struct spi_slave *slave); /*----------------------------------------------------------------------- * SPI transfer @@ -60,28 +134,67 @@ void spi_init(void); * input data overwrites the output data (since both are buffered by * temporary variables, this is OK). * - * If the chipsel() function is not NULL, it is called with a parameter - * of '1' (chip select active) at the start of the transfer and again with - * a parameter of '0' at the end of the transfer. - * - * If the chipsel() function _is_ NULL, it the responsibility of the - * caller to make the appropriate chip select active before calling - * spi_xfer() and making it inactive after spi_xfer() returns. - * * spi_xfer() interface: - * chipsel: Routine to call to set/clear the chip select: - * if chipsel is NULL, it is not used. - * if(cs), make the chip select active (typically '0'). - * if(!cs), make the chip select inactive (typically '1'). - * dout: Pointer to a string of bits to send out. The bits are - * held in a byte array and are sent MSB first. - * din: Pointer to a string of bits that will be filled in. - * bitlen: How many bits to write and read. + * slave: The SPI slave which will be sending/receiving the data. + * bitlen: How many bits to write and read. + * dout: Pointer to a string of bits to send out. The bits are + * held in a byte array and are sent MSB first. + * din: Pointer to a string of bits that will be filled in. + * flags: A bitwise combination of SPI_XFER_* flags. * * Returns: 0 on success, not 0 on failure */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags); + +/*----------------------------------------------------------------------- + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs); + +/*----------------------------------------------------------------------- + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Write 8 bits, then read 8 bits. + * slave: The SPI slave we're communicating with + * byte: Byte to be written + * + * Returns: The value that was read, or a negative value on error. + * + * TODO: This function probably shouldn't be inlined. + */ +static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) +{ + unsigned char dout[2]; + unsigned char din[2]; + int ret; + + dout[0] = byte; + dout[1] = 0; -int spi_select(unsigned int bus, unsigned int dev, unsigned long mode); + ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); + return ret < 0 ? ret : din[1]; +} #endif /* _SPI_H_ */ diff --git a/include/spi_flash.h b/include/spi_flash.h new file mode 100644 index 0000000000..de4f174ad5 --- /dev/null +++ b/include/spi_flash.h @@ -0,0 +1,70 @@ +/* + * Interface to SPI flash + * + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SPI_FLASH_H_ +#define _SPI_FLASH_H_ + +#include <spi.h> + +struct spi_flash_region { + unsigned int count; + unsigned int size; +}; + +struct spi_flash { + struct spi_slave *spi; + + const char *name; + + u32 size; + + int (*read)(struct spi_flash *flash, u32 offset, + size_t len, void *buf); + int (*write)(struct spi_flash *flash, u32 offset, + size_t len, const void *buf); + int (*erase)(struct spi_flash *flash, u32 offset, + size_t len); +}; + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +void spi_flash_free(struct spi_flash *flash); + +static inline int spi_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + return flash->read(flash, offset, len, buf); +} + +static inline int spi_flash_write(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + return flash->write(flash, offset, len, buf); +} + +static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, + size_t len) +{ + return flash->erase(flash, offset, len); +} + +#endif /* _SPI_FLASH_H_ */ diff --git a/lib_arm/board.c b/lib_arm/board.c index 67506b35e1..80b149b534 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -45,6 +45,8 @@ #include <version.h> #include <net.h> #include <serial.h> +#include <nand.h> +#include <onenand_uboot.h> #ifdef CONFIG_DRIVER_SMC91111 #include "../drivers/net/smc91111.h" @@ -55,14 +57,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_NAND) -void nand_init (void); -#endif - -#if defined(CONFIG_CMD_ONENAND) -void onenand_init(void); -#endif - ulong monitor_flash_len; #ifdef CONFIG_HAS_DATAFLASH @@ -121,6 +115,20 @@ void *sbrk (ptrdiff_t increment) return ((void *) old); } +char *strmhz(char *buf, long hz) +{ + long l, n; + long m; + + n = hz / 1000000L; + l = sprintf (buf, "%ld", n); + m = (hz % 1000000L) / 1000L; + if (m != 0) + sprintf (buf + l, ".%03ld", m); + return (buf); +} + + /************************************************************************ * Coloured LED functionality ************************************************************************ @@ -279,7 +287,7 @@ void start_armboot (void) { init_fnc_t **init_fnc_ptr; char *s; -#ifndef CFG_NO_FLASH +#if !defined(CFG_NO_FLASH) || defined (CONFIG_VFD) || defined(CONFIG_LCD) ulong size; #endif #if defined(CONFIG_VFD) || defined(CONFIG_LCD) @@ -323,16 +331,19 @@ void start_armboot (void) #endif /* CONFIG_VFD */ #ifdef CONFIG_LCD -# ifndef PAGE_SIZE -# define PAGE_SIZE 4096 -# endif - /* - * reserve memory for LCD display (always full pages) - */ - /* bss_end is defined in the board-specific linker script */ - addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); - size = lcd_setmem (addr); - gd->fb_base = addr; + /* board init may have inited fb_base */ + if (!gd->fb_base) { +# ifndef PAGE_SIZE +# define PAGE_SIZE 4096 +# endif + /* + * reserve memory for LCD display (always full pages) + */ + /* bss_end is defined in the board-specific linker script */ + addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); + size = lcd_setmem (addr); + gd->fb_base = addr; + } #endif /* CONFIG_LCD */ /* armboot_start is defined in the board-specific linker script */ diff --git a/lib_avr32/memset.S b/lib_avr32/memset.S index dc3b09b42f..79e3c675a9 100644 --- a/lib_avr32/memset.S +++ b/lib_avr32/memset.S @@ -27,7 +27,7 @@ * * Returns b in r12 */ - .text + .section .text.memset, "ax", @progbits .global memset .type memset, @function diff --git a/lib_generic/Makefile b/lib_generic/Makefile index dca3a6cbdc..4f6ce73ab3 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -38,6 +38,7 @@ COBJS-y += lmb.o COBJS-y += ldiv.o COBJS-$(CONFIG_MD5) += md5.o COBJS-y += sha1.o +COBJS-$(CONFIG_SHA256) += sha256.o COBJS-y += string.o COBJS-y += vsprintf.o COBJS-y += zlib.o diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c index 5ddd94fd5a..2dc2567410 100644 --- a/lib_generic/display_options.c +++ b/lib_generic/display_options.c @@ -39,27 +39,35 @@ int display_options (void) } /* - * print sizes as "xxx kB", "xxx.y kB", "xxx MB" or "xxx.y MB" as needed; - * allow for optional trailing string (like "\n") + * print sizes as "xxx kB", "xxx.y kB", "xxx MB", "xxx.y MB", + * xxx GB, or xxx.y GB as needed; allow for optional trailing string + * (like "\n") */ -void print_size (ulong size, const char *s) +void print_size (phys_size_t size, const char *s) { - ulong m, n; - ulong d = 1 << 20; /* 1 MB */ - char c = 'M'; - - if (size < d) { /* print in kB */ - c = 'k'; - d = 1 << 10; + ulong m = 0, n; + phys_size_t d = 1 << 30; /* 1 GB */ + char c = 'G'; + + if (size < d) { /* try MB */ + c = 'M'; + d = 1 << 20; + if (size < d) { /* print in kB */ + c = 'k'; + d = 1 << 10; + } } n = size / d; - m = (10 * (size - (n * d)) + (d / 2) ) / d; + /* If there's a remainder, deal with it */ + if(size % d) { + m = (10 * (size - (n * d)) + (d / 2) ) / d; - if (m >= 10) { - m -= 10; - n += 1; + if (m >= 10) { + m -= 10; + n += 1; + } } printf ("%2ld", n); diff --git a/lib_generic/lmb.c b/lib_generic/lmb.c index 3b8c805e88..6b46fa8868 100644 --- a/lib_generic/lmb.c +++ b/lib_generic/lmb.c @@ -22,33 +22,34 @@ void lmb_dump_all(struct lmb *lmb) debug("lmb_dump_all:\n"); debug(" memory.cnt = 0x%lx\n", lmb->memory.cnt); - debug(" memory.size = 0x%08x\n", lmb->memory.size); + debug(" memory.size = 0x%llx\n", + (unsigned long long)lmb->memory.size); for (i=0; i < lmb->memory.cnt ;i++) { - debug(" memory.reg[0x%x].base = 0x%08x\n", i, + debug(" memory.reg[0x%x].base = 0x%llx\n", i, lmb->memory.region[i].base); - debug(" .size = 0x%08x\n", + debug(" .size = 0x%llx\n", lmb->memory.region[i].size); } debug("\n reserved.cnt = 0x%lx\n", lmb->reserved.cnt); - debug(" reserved.size = 0x%08x\n", lmb->reserved.size); + debug(" reserved.size = 0x%llx\n", lmb->reserved.size); for (i=0; i < lmb->reserved.cnt ;i++) { - debug(" reserved.reg[0x%x].base = 0x%08x\n", i, + debug(" reserved.reg[0x%x].base = 0x%llx\n", i, lmb->reserved.region[i].base); - debug(" .size = 0x%08x\n", + debug(" .size = 0x%llx\n", lmb->reserved.region[i].size); } #endif /* DEBUG */ } -static unsigned long lmb_addrs_overlap(ulong base1, - ulong size1, ulong base2, ulong size2) +static long lmb_addrs_overlap(phys_addr_t base1, + phys_size_t size1, phys_addr_t base2, phys_size_t size2) { return ((base1 < (base2+size2)) && (base2 < (base1+size1))); } -static long lmb_addrs_adjacent(ulong base1, ulong size1, - ulong base2, ulong size2) +static long lmb_addrs_adjacent(phys_addr_t base1, phys_size_t size1, + phys_addr_t base2, phys_size_t size2) { if (base2 == base1 + size1) return 1; @@ -61,10 +62,10 @@ static long lmb_addrs_adjacent(ulong base1, ulong size1, static long lmb_regions_adjacent(struct lmb_region *rgn, unsigned long r1, unsigned long r2) { - ulong base1 = rgn->region[r1].base; - ulong size1 = rgn->region[r1].size; - ulong base2 = rgn->region[r2].base; - ulong size2 = rgn->region[r2].size; + phys_addr_t base1 = rgn->region[r1].base; + phys_size_t size1 = rgn->region[r1].size; + phys_addr_t base2 = rgn->region[r2].base; + phys_size_t size2 = rgn->region[r2].size; return lmb_addrs_adjacent(base1, size1, base2, size2); } @@ -106,7 +107,7 @@ void lmb_init(struct lmb *lmb) } /* This routine called with relocation disabled. */ -static long lmb_add_region(struct lmb_region *rgn, ulong base, ulong size) +static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) { unsigned long coalesced = 0; long adjacent, i; @@ -119,8 +120,8 @@ static long lmb_add_region(struct lmb_region *rgn, ulong base, ulong size) /* First try and coalesce this LMB with another. */ for (i=0; i < rgn->cnt; i++) { - ulong rgnbase = rgn->region[i].base; - ulong rgnsize = rgn->region[i].size; + phys_addr_t rgnbase = rgn->region[i].base; + phys_size_t rgnsize = rgn->region[i].size; if ((rgnbase == base) && (rgnsize == size)) /* Already have this region, so we're done */ @@ -173,28 +174,77 @@ static long lmb_add_region(struct lmb_region *rgn, ulong base, ulong size) } /* This routine may be called with relocation disabled. */ -long lmb_add(struct lmb *lmb, ulong base, ulong size) +long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size) { struct lmb_region *_rgn = &(lmb->memory); return lmb_add_region(_rgn, base, size); } -long lmb_reserve(struct lmb *lmb, ulong base, ulong size) +long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) +{ + struct lmb_region *rgn = &(lmb->reserved); + phys_addr_t rgnbegin, rgnend; + phys_addr_t end = base + size; + int i; + + rgnbegin = rgnend = 0; /* supress gcc warnings */ + + /* Find the region where (base, size) belongs to */ + for (i=0; i < rgn->cnt; i++) { + rgnbegin = rgn->region[i].base; + rgnend = rgnbegin + rgn->region[i].size; + + if ((rgnbegin <= base) && (end <= rgnend)) + break; + } + + /* Didn't find the region */ + if (i == rgn->cnt) + return -1; + + /* Check to see if we are removing entire region */ + if ((rgnbegin == base) && (rgnend == end)) { + lmb_remove_region(rgn, i); + return 0; + } + + /* Check to see if region is matching at the front */ + if (rgnbegin == base) { + rgn->region[i].base = end; + rgn->region[i].size -= size; + return 0; + } + + /* Check to see if the region is matching at the end */ + if (rgnend == end) { + rgn->region[i].size -= size; + return 0; + } + + /* + * We need to split the entry - adjust the current one to the + * beginging of the hole and add the region after hole. + */ + rgn->region[i].size = base - rgn->region[i].base; + return lmb_add_region(rgn, end, rgnend - end); +} + +long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) { struct lmb_region *_rgn = &(lmb->reserved); return lmb_add_region(_rgn, base, size); } -long lmb_overlaps_region(struct lmb_region *rgn, ulong base, - ulong size) +long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, + phys_size_t size) { unsigned long i; for (i=0; i < rgn->cnt; i++) { - ulong rgnbase = rgn->region[i].base; - ulong rgnsize = rgn->region[i].size; + phys_addr_t rgnbase = rgn->region[i].base; + phys_size_t rgnsize = rgn->region[i].size; if ( lmb_addrs_overlap(base,size,rgnbase,rgnsize) ) { break; } @@ -203,14 +253,14 @@ long lmb_overlaps_region(struct lmb_region *rgn, ulong base, return (i < rgn->cnt) ? i : -1; } -ulong lmb_alloc(struct lmb *lmb, ulong size, ulong align) +phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align) { return lmb_alloc_base(lmb, size, align, LMB_ALLOC_ANYWHERE); } -ulong lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr) +phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr) { - ulong alloc; + phys_addr_t alloc; alloc = __lmb_alloc_base(lmb, size, align, max_addr); @@ -221,25 +271,28 @@ ulong lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr) return alloc; } -static ulong lmb_align_down(ulong addr, ulong size) +static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size) { return addr & ~(size - 1); } -static ulong lmb_align_up(ulong addr, ulong size) +static phys_addr_t lmb_align_up(phys_addr_t addr, ulong size) { return (addr + (size - 1)) & ~(size - 1); } -ulong __lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr) +phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr) { long i, j; - ulong base = 0; + phys_addr_t base = 0; + phys_addr_t res_base; for (i = lmb->memory.cnt-1; i >= 0; i--) { - ulong lmbbase = lmb->memory.region[i].base; - ulong lmbsize = lmb->memory.region[i].size; + phys_addr_t lmbbase = lmb->memory.region[i].base; + phys_size_t lmbsize = lmb->memory.region[i].size; + if (lmbsize < size) + continue; if (max_addr == LMB_ALLOC_ANYWHERE) base = lmb_align_down(lmbbase + lmbsize - size, align); else if (lmbbase < max_addr) { @@ -248,30 +301,31 @@ ulong __lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr) } else continue; - while ((lmbbase <= base) && - ((j = lmb_overlaps_region(&(lmb->reserved), base, size)) >= 0) ) - base = lmb_align_down(lmb->reserved.region[j].base - size, - align); - - if ((base != 0) && (lmbbase <= base)) - break; + while (base && lmbbase <= base) { + j = lmb_overlaps_region(&lmb->reserved, base, size); + if (j < 0) { + /* This area isn't reserved, take it */ + if (lmb_add_region(&lmb->reserved, base, + lmb_align_up(size, + align)) < 0) + return 0; + return base; + } + res_base = lmb->reserved.region[j].base; + if (res_base < size) + break; + base = lmb_align_down(res_base - size, align); + } } - - if (i < 0) - return 0; - - if (lmb_add_region(&(lmb->reserved), base, lmb_align_up(size, align)) < 0) - return 0; - - return base; + return 0; } -int lmb_is_reserved(struct lmb *lmb, ulong addr) +int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) { int i; for (i = 0; i < lmb->reserved.cnt; i++) { - ulong upper = lmb->reserved.region[i].base + + phys_addr_t upper = lmb->reserved.region[i].base + lmb->reserved.region[i].size - 1; if ((addr >= lmb->reserved.region[i].base) && (addr <= upper)) return 1; diff --git a/lib_generic/md5.c b/lib_generic/md5.c index 78ef47535e..9150510bbc 100644 --- a/lib_generic/md5.c +++ b/lib_generic/md5.c @@ -27,10 +27,12 @@ #ifndef USE_HOSTCC #include <common.h> +#include <linux/string.h> +#else +#include <string.h> #endif /* USE_HOSTCC */ #include <watchdog.h> #include <linux/types.h> -#include <linux/string.h> #include <u-boot/md5.h> static void diff --git a/lib_generic/sha1.c b/lib_generic/sha1.c index c8ef4d2827..da5bc16f3c 100644 --- a/lib_generic/sha1.c +++ b/lib_generic/sha1.c @@ -31,9 +31,11 @@ #ifndef USE_HOSTCC #include <common.h> +#include <linux/string.h> +#else +#include <string.h> #endif /* USE_HOSTCC */ #include <watchdog.h> -#include <linux/string.h> #include "sha1.h" /* diff --git a/lib_generic/sha256.c b/lib_generic/sha256.c new file mode 100644 index 0000000000..deb63a40b6 --- /dev/null +++ b/lib_generic/sha256.c @@ -0,0 +1,262 @@ +/* + * FIPS-180-2 compliant SHA-256 implementation + * + * Copyright (C) 2001-2003 Christophe Devine + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef USE_HOSTCC +#include <common.h> +#endif /* USE_HOSTCC */ +#include <watchdog.h> +#include <linux/string.h> +#include <sha256.h> + +/* + * 32-bit integer manipulation macros (big endian) + */ +#ifndef GET_UINT32_BE +#define GET_UINT32_BE(n,b,i) { \ + (n) = ( (unsigned long) (b)[(i) ] << 24 ) \ + | ( (unsigned long) (b)[(i) + 1] << 16 ) \ + | ( (unsigned long) (b)[(i) + 2] << 8 ) \ + | ( (unsigned long) (b)[(i) + 3] ); \ +} +#endif +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n,b,i) { \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ +} +#endif + +void sha256_starts(sha256_context * ctx) +{ + ctx->total[0] = 0; + ctx->total[1] = 0; + + ctx->state[0] = 0x6A09E667; + ctx->state[1] = 0xBB67AE85; + ctx->state[2] = 0x3C6EF372; + ctx->state[3] = 0xA54FF53A; + ctx->state[4] = 0x510E527F; + ctx->state[5] = 0x9B05688C; + ctx->state[6] = 0x1F83D9AB; + ctx->state[7] = 0x5BE0CD19; +} + +void sha256_process(sha256_context * ctx, uint8_t data[64]) +{ + uint32_t temp1, temp2; + uint32_t W[64]; + uint32_t A, B, C, D, E, F, G, H; + + GET_UINT32_BE(W[0], data, 0); + GET_UINT32_BE(W[1], data, 4); + GET_UINT32_BE(W[2], data, 8); + GET_UINT32_BE(W[3], data, 12); + GET_UINT32_BE(W[4], data, 16); + GET_UINT32_BE(W[5], data, 20); + GET_UINT32_BE(W[6], data, 24); + GET_UINT32_BE(W[7], data, 28); + GET_UINT32_BE(W[8], data, 32); + GET_UINT32_BE(W[9], data, 36); + GET_UINT32_BE(W[10], data, 40); + GET_UINT32_BE(W[11], data, 44); + GET_UINT32_BE(W[12], data, 48); + GET_UINT32_BE(W[13], data, 52); + GET_UINT32_BE(W[14], data, 56); + GET_UINT32_BE(W[15], data, 60); + +#define SHR(x,n) ((x & 0xFFFFFFFF) >> n) +#define ROTR(x,n) (SHR(x,n) | (x << (32 - n))) + +#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3)) +#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10)) + +#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22)) +#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25)) + +#define F0(x,y,z) ((x & y) | (z & (x | y))) +#define F1(x,y,z) (z ^ (x & (y ^ z))) + +#define R(t) \ +( \ + W[t] = S1(W[t - 2]) + W[t - 7] + \ + S0(W[t - 15]) + W[t - 16] \ +) + +#define P(a,b,c,d,e,f,g,h,x,K) { \ + temp1 = h + S3(e) + F1(e,f,g) + K + x; \ + temp2 = S2(a) + F0(a,b,c); \ + d += temp1; h = temp1 + temp2; \ +} + + A = ctx->state[0]; + B = ctx->state[1]; + C = ctx->state[2]; + D = ctx->state[3]; + E = ctx->state[4]; + F = ctx->state[5]; + G = ctx->state[6]; + H = ctx->state[7]; + + P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); + P(H, A, B, C, D, E, F, G, W[1], 0x71374491); + P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); + P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); + P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); + P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); + P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); + P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); + P(A, B, C, D, E, F, G, H, W[8], 0xD807AA98); + P(H, A, B, C, D, E, F, G, W[9], 0x12835B01); + P(G, H, A, B, C, D, E, F, W[10], 0x243185BE); + P(F, G, H, A, B, C, D, E, W[11], 0x550C7DC3); + P(E, F, G, H, A, B, C, D, W[12], 0x72BE5D74); + P(D, E, F, G, H, A, B, C, W[13], 0x80DEB1FE); + P(C, D, E, F, G, H, A, B, W[14], 0x9BDC06A7); + P(B, C, D, E, F, G, H, A, W[15], 0xC19BF174); + P(A, B, C, D, E, F, G, H, R(16), 0xE49B69C1); + P(H, A, B, C, D, E, F, G, R(17), 0xEFBE4786); + P(G, H, A, B, C, D, E, F, R(18), 0x0FC19DC6); + P(F, G, H, A, B, C, D, E, R(19), 0x240CA1CC); + P(E, F, G, H, A, B, C, D, R(20), 0x2DE92C6F); + P(D, E, F, G, H, A, B, C, R(21), 0x4A7484AA); + P(C, D, E, F, G, H, A, B, R(22), 0x5CB0A9DC); + P(B, C, D, E, F, G, H, A, R(23), 0x76F988DA); + P(A, B, C, D, E, F, G, H, R(24), 0x983E5152); + P(H, A, B, C, D, E, F, G, R(25), 0xA831C66D); + P(G, H, A, B, C, D, E, F, R(26), 0xB00327C8); + P(F, G, H, A, B, C, D, E, R(27), 0xBF597FC7); + P(E, F, G, H, A, B, C, D, R(28), 0xC6E00BF3); + P(D, E, F, G, H, A, B, C, R(29), 0xD5A79147); + P(C, D, E, F, G, H, A, B, R(30), 0x06CA6351); + P(B, C, D, E, F, G, H, A, R(31), 0x14292967); + P(A, B, C, D, E, F, G, H, R(32), 0x27B70A85); + P(H, A, B, C, D, E, F, G, R(33), 0x2E1B2138); + P(G, H, A, B, C, D, E, F, R(34), 0x4D2C6DFC); + P(F, G, H, A, B, C, D, E, R(35), 0x53380D13); + P(E, F, G, H, A, B, C, D, R(36), 0x650A7354); + P(D, E, F, G, H, A, B, C, R(37), 0x766A0ABB); + P(C, D, E, F, G, H, A, B, R(38), 0x81C2C92E); + P(B, C, D, E, F, G, H, A, R(39), 0x92722C85); + P(A, B, C, D, E, F, G, H, R(40), 0xA2BFE8A1); + P(H, A, B, C, D, E, F, G, R(41), 0xA81A664B); + P(G, H, A, B, C, D, E, F, R(42), 0xC24B8B70); + P(F, G, H, A, B, C, D, E, R(43), 0xC76C51A3); + P(E, F, G, H, A, B, C, D, R(44), 0xD192E819); + P(D, E, F, G, H, A, B, C, R(45), 0xD6990624); + P(C, D, E, F, G, H, A, B, R(46), 0xF40E3585); + P(B, C, D, E, F, G, H, A, R(47), 0x106AA070); + P(A, B, C, D, E, F, G, H, R(48), 0x19A4C116); + P(H, A, B, C, D, E, F, G, R(49), 0x1E376C08); + P(G, H, A, B, C, D, E, F, R(50), 0x2748774C); + P(F, G, H, A, B, C, D, E, R(51), 0x34B0BCB5); + P(E, F, G, H, A, B, C, D, R(52), 0x391C0CB3); + P(D, E, F, G, H, A, B, C, R(53), 0x4ED8AA4A); + P(C, D, E, F, G, H, A, B, R(54), 0x5B9CCA4F); + P(B, C, D, E, F, G, H, A, R(55), 0x682E6FF3); + P(A, B, C, D, E, F, G, H, R(56), 0x748F82EE); + P(H, A, B, C, D, E, F, G, R(57), 0x78A5636F); + P(G, H, A, B, C, D, E, F, R(58), 0x84C87814); + P(F, G, H, A, B, C, D, E, R(59), 0x8CC70208); + P(E, F, G, H, A, B, C, D, R(60), 0x90BEFFFA); + P(D, E, F, G, H, A, B, C, R(61), 0xA4506CEB); + P(C, D, E, F, G, H, A, B, R(62), 0xBEF9A3F7); + P(B, C, D, E, F, G, H, A, R(63), 0xC67178F2); + + ctx->state[0] += A; + ctx->state[1] += B; + ctx->state[2] += C; + ctx->state[3] += D; + ctx->state[4] += E; + ctx->state[5] += F; + ctx->state[6] += G; + ctx->state[7] += H; +} + +void sha256_update(sha256_context * ctx, uint8_t * input, uint32_t length) +{ + uint32_t left, fill; + + if (!length) + return; + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += length; + ctx->total[0] &= 0xFFFFFFFF; + + if (ctx->total[0] < length) + ctx->total[1]++; + + if (left && length >= fill) { + memcpy((void *) (ctx->buffer + left), (void *) input, fill); + sha256_process(ctx, ctx->buffer); + length -= fill; + input += fill; + left = 0; + } + + while (length >= 64) { + sha256_process(ctx, input); + length -= 64; + input += 64; + } + + if (length) + memcpy((void *) (ctx->buffer + left), (void *) input, length); +} + +static uint8_t sha256_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +void sha256_finish(sha256_context * ctx, uint8_t digest[32]) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t msglen[8]; + + high = ((ctx->total[0] >> 29) + | (ctx->total[1] << 3)); + low = (ctx->total[0] << 3); + + PUT_UINT32_BE(high, msglen, 0); + PUT_UINT32_BE(low, msglen, 4); + + last = ctx->total[0] & 0x3F; + padn = (last < 56) ? (56 - last) : (120 - last); + + sha256_update(ctx, sha256_padding, padn); + sha256_update(ctx, msglen, 8); + + PUT_UINT32_BE(ctx->state[0], digest, 0); + PUT_UINT32_BE(ctx->state[1], digest, 4); + PUT_UINT32_BE(ctx->state[2], digest, 8); + PUT_UINT32_BE(ctx->state[3], digest, 12); + PUT_UINT32_BE(ctx->state[4], digest, 16); + PUT_UINT32_BE(ctx->state[5], digest, 20); + PUT_UINT32_BE(ctx->state[6], digest, 24); + PUT_UINT32_BE(ctx->state[7], digest, 28); +} diff --git a/lib_mips/board.c b/lib_mips/board.c index 1645f2c7e0..532550b603 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -28,6 +28,8 @@ #include <version.h> #include <net.h> #include <environment.h> +#include <nand.h> +#include <spi.h> DECLARE_GLOBAL_DATA_PTR; @@ -416,6 +418,17 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif +#ifdef CONFIG_CMD_NAND + puts ("NAND: "); + nand_init (); /* go init the NAND */ +#endif + +#ifdef CONFIG_CMD_SPI + puts ("SPI: "); + spi_init (); /* go init the SPI */ + puts ("ready\n"); +#endif + #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r (); diff --git a/lib_mips/bootm.c b/lib_mips/bootm.c index f813fc5831..8fe3782b75 100644 --- a/lib_mips/bootm.c +++ b/lib_mips/bootm.c @@ -54,6 +54,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], char *commandline = getenv ("bootargs"); char env_buf[12]; int ret; + const char *cp; /* find kernel entry point */ if (images->legacy_hdr_valid) { @@ -113,6 +114,16 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); linux_env_set ("flash_size", env_buf); + cp = getenv("ethaddr"); + if (cp != NULL) { + linux_env_set("ethaddr", cp); + } + + cp = getenv("eth1addr"); + if (cp != NULL) { + linux_env_set("eth1addr", cp); + } + if (!images->autostart) return ; diff --git a/lib_mips/time.c b/lib_mips/time.c index cd8dc721e2..1e9278996e 100644 --- a/lib_mips/time.c +++ b/lib_mips/time.c @@ -22,26 +22,12 @@ */ #include <common.h> +#include <asm/mipsregs.h> +static unsigned long timestamp; -static inline void mips_compare_set(u32 v) -{ - asm volatile ("mtc0 %0, $11" : : "r" (v)); -} - -static inline void mips_count_set(u32 v) -{ - asm volatile ("mtc0 %0, $9" : : "r" (v)); -} - - -static inline u32 mips_count_get(void) -{ - u32 count; - - asm volatile ("mfc0 %0, $9" : "=r" (count) :); - return count; -} +/* how many counter cycles in a jiffy */ +#define CYCLES_PER_JIFFY (CFG_MIPS_TIMER_FREQ + CFG_HZ / 2) / CFG_HZ /* * timer without interrupts @@ -49,34 +35,47 @@ static inline u32 mips_count_get(void) int timer_init(void) { - mips_compare_set(0); - mips_count_set(0); + /* Set up the timer for the first expiration. */ + timestamp = 0; + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); return 0; } void reset_timer(void) { - mips_count_set(0); + timestamp = 0; + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); } ulong get_timer(ulong base) { - return mips_count_get() - base; + unsigned int count; + unsigned int expirelo = read_c0_compare(); + + /* Check to see if we have missed any timestamps. */ + count = read_c0_count(); + while ((count - expirelo) < 0x7fffffff) { + expirelo += CYCLES_PER_JIFFY; + timestamp++; + } + write_c0_compare(expirelo); + + return (timestamp - base); } void set_timer(ulong t) { - mips_count_set(t); + timestamp = t; + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); } -void udelay (unsigned long usec) +void udelay(unsigned long usec) { - ulong tmo; - ulong start = get_timer(0); + unsigned int tmo; - tmo = usec * (CFG_HZ / 1000000); - while ((ulong)((mips_count_get() - start)) < tmo) + tmo = read_c0_count() + (usec * (CFG_MIPS_TIMER_FREQ / 1000000)); + while ((tmo - read_c0_count()) < 0x7fffffff) /*NOP*/; } @@ -86,7 +85,7 @@ void udelay (unsigned long usec) */ unsigned long long get_ticks(void) { - return mips_count_get(); + return get_timer(0); } /* diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c index 912efa72b4..8546333868 100644 --- a/lib_ppc/bat_rw.c +++ b/lib_ppc/bat_rw.c @@ -29,46 +29,72 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) { switch (bat) { + case DBAT0: + mtspr (DBAT0L, lower); + mtspr (DBAT0U, upper); + break; case IBAT0: mtspr (IBAT0L, lower); mtspr (IBAT0U, upper); break; - + case DBAT1: + mtspr (DBAT1L, lower); + mtspr (DBAT1U, upper); + break; case IBAT1: mtspr (IBAT1L, lower); mtspr (IBAT1U, upper); break; - + case DBAT2: + mtspr (DBAT2L, lower); + mtspr (DBAT2U, upper); + break; case IBAT2: mtspr (IBAT2L, lower); mtspr (IBAT2U, upper); break; - + case DBAT3: + mtspr (DBAT3L, lower); + mtspr (DBAT3U, upper); + break; case IBAT3: mtspr (IBAT3L, lower); mtspr (IBAT3U, upper); break; - - case DBAT0: - mtspr (DBAT0L, lower); - mtspr (DBAT0U, upper); +#ifdef CONFIG_HIGH_BATS + case DBAT4: + mtspr (DBAT4L, lower); + mtspr (DBAT4U, upper); break; - - case DBAT1: - mtspr (DBAT1L, lower); - mtspr (DBAT1U, upper); + case IBAT4: + mtspr (IBAT4L, lower); + mtspr (IBAT4U, upper); break; - - case DBAT2: - mtspr (DBAT2L, lower); - mtspr (DBAT2U, upper); + case DBAT5: + mtspr (DBAT5L, lower); + mtspr (DBAT5U, upper); break; - - case DBAT3: - mtspr (DBAT3L, lower); - mtspr (DBAT3U, upper); + case IBAT5: + mtspr (IBAT5L, lower); + mtspr (IBAT5U, upper); break; - + case DBAT6: + mtspr (DBAT6L, lower); + mtspr (DBAT6U, upper); + break; + case IBAT6: + mtspr (IBAT6L, lower); + mtspr (IBAT6U, upper); + break; + case DBAT7: + mtspr (DBAT7L, lower); + mtspr (DBAT7U, upper); + break; + case IBAT7: + mtspr (IBAT7L, lower); + mtspr (IBAT7U, upper); + break; +#endif default: return (-1); } @@ -82,46 +108,72 @@ int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) unsigned long register l; switch (bat) { + case DBAT0: + l = mfspr (DBAT0L); + u = mfspr (DBAT0U); + break; case IBAT0: l = mfspr (IBAT0L); u = mfspr (IBAT0U); break; - + case DBAT1: + l = mfspr (DBAT1L); + u = mfspr (DBAT1U); + break; case IBAT1: l = mfspr (IBAT1L); u = mfspr (IBAT1U); break; - + case DBAT2: + l = mfspr (DBAT2L); + u = mfspr (DBAT2U); + break; case IBAT2: l = mfspr (IBAT2L); u = mfspr (IBAT2U); break; - + case DBAT3: + l = mfspr (DBAT3L); + u = mfspr (DBAT3U); + break; case IBAT3: l = mfspr (IBAT3L); u = mfspr (IBAT3U); break; - - case DBAT0: - l = mfspr (DBAT0L); - u = mfspr (DBAT0U); +#ifdef CONFIG_HIGH_BATS + case DBAT4: + l = mfspr (DBAT4L); + u = mfspr (DBAT4U); break; - - case DBAT1: - l = mfspr (DBAT1L); - u = mfspr (DBAT1U); + case IBAT4: + l = mfspr (IBAT4L); + u = mfspr (IBAT4U); break; - - case DBAT2: - l = mfspr (DBAT2L); - u = mfspr (DBAT2U); + case DBAT5: + l = mfspr (DBAT5L); + u = mfspr (DBAT5U); break; - - case DBAT3: - l = mfspr (DBAT3L); - u = mfspr (DBAT3U); + case IBAT5: + l = mfspr (IBAT5L); + u = mfspr (IBAT5U); break; - + case DBAT6: + l = mfspr (DBAT6L); + u = mfspr (DBAT6U); + break; + case IBAT6: + l = mfspr (IBAT6L); + u = mfspr (IBAT6U); + break; + case DBAT7: + l = mfspr (DBAT7L); + u = mfspr (DBAT7U); + break; + case IBAT7: + l = mfspr (IBAT7L); + u = mfspr (IBAT7U); + break; +#endif default: return (-1); } @@ -131,3 +183,44 @@ int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) return (0); } + +void print_bats(void) +{ + printf("BAT registers:\n"); + + printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L)); + printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U)); + printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L)); + printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U)); + printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L)); + printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U)); + printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L)); + printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U)); + printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L)); + printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U)); + printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L)); + printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U)); + printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L)); + printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U)); + printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L)); + printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U)); + +#ifdef CONFIG_HIGH_BATS + printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L)); + printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U)); + printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L)); + printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U)); + printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L)); + printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U)); + printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L)); + printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U)); + printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L)); + printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U)); + printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L)); + printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U)); + printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L)); + printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U)); + printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L)); + printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U)); +#endif +} diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 4956403cce..9afa88a700 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -90,12 +90,8 @@ void doc_init (void); defined(CONFIG_SOFT_I2C) #include <i2c.h> #endif -#if defined(CONFIG_HARD_SPI) #include <spi.h> -#endif -#if defined(CONFIG_CMD_NAND) -void nand_init (void); -#endif +#include <nand.h> static char *failed = "*** failed ***\n"; @@ -398,6 +394,13 @@ ulong get_effective_memsize(void) ************************************************************************ */ +#ifdef CONFIG_LOGBUFFER +unsigned long logbuffer_base(void) +{ + return CFG_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; +} +#endif + void board_init_f (ulong bootflag) { bd_t *bd; @@ -416,7 +419,8 @@ void board_init_f (ulong bootflag) /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); -#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) +#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) && \ + !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); #endif @@ -621,7 +625,7 @@ void board_init_f (ulong bootflag) defined(CONFIG_440EPX) || defined(CONFIG_440GRX) bd->bi_pci_busfreq = get_PCI_freq (); bd->bi_opbfreq = get_OPB_freq (); -#elif defined(CONFIG_XILINX_ML300) +#elif defined(CONFIG_XILINX_405) bd->bi_pci_busfreq = get_PCI_freq (); #endif #endif diff --git a/lib_ppc/bootm.c b/lib_ppc/bootm.c index 9194fd8b0a..81803ddef3 100644 --- a/lib_ppc/bootm.c +++ b/lib_ppc/bootm.c @@ -51,6 +51,10 @@ static int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, #include <asm/cache.h> #endif +#ifndef CFG_FDT_PAD +#define CFG_FDT_PAD 0x3000 +#endif + DECLARE_GLOBAL_DATA_PTR; extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -71,6 +75,7 @@ do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong initrd_start, initrd_end; ulong rd_data_start, rd_data_end, rd_len; ulong size; + phys_size_t bootm_size; ulong cmd_start, cmd_end, bootmap_base; bd_t *kbd; @@ -85,22 +90,23 @@ do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], #endif bootmap_base = getenv_bootm_low(); - size = getenv_bootm_size(); + bootm_size = getenv_bootm_size(); #ifdef DEBUG - if (((u64)bootmap_base + size) > (CFG_SDRAM_BASE + (u64)gd->ram_size)) + if (((u64)bootmap_base + bootm_size) > + (CFG_SDRAM_BASE + (u64)gd->ram_size)) puts("WARNING: bootm_low + bootm_size exceed total memory\n"); - if ((bootmap_base + size) > get_effective_memsize()) + if ((bootmap_base + bootm_size) > get_effective_memsize()) puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); #endif - size = min(size, get_effective_memsize()); + size = min(bootm_size, get_effective_memsize()); size = min(size, CFG_LINUX_LOWMEM_MAX_SIZE); - if (size < getenv_bootm_size()) { + if (size < bootm_size) { ulong base = bootmap_base + size; - printf("WARNING: adjusting available memory to %x\n", size); - lmb_reserve(lmb, base, getenv_bootm_size() - size); + printf("WARNING: adjusting available memory to %lx\n", size); + lmb_reserve(lmb, base, bootm_size - size); } /* @@ -189,6 +195,45 @@ do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ft_board_setup(of_flat_tree, gd->bd); #endif } + + /* Fixup the fdt memreserve now that we know how big it is */ + if (of_flat_tree) { + int j; + uint64_t addr, size; + int total = fdt_num_mem_rsv(of_flat_tree); + uint actualsize; + + for (j = 0; j < total; j++) { + fdt_get_mem_rsv(of_flat_tree, j, &addr, &size); + if (addr == (uint64_t)(u32)of_flat_tree) { + fdt_del_mem_rsv(of_flat_tree, j); + break; + } + } + + /* Delete the old LMB reservation */ + lmb_free(lmb, (phys_addr_t)(u32)of_flat_tree, + (phys_size_t)fdt_totalsize(of_flat_tree)); + + /* Calculate the actual size of the fdt */ + actualsize = fdt_off_dt_strings(of_flat_tree) + + fdt_size_dt_strings(of_flat_tree); + + /* Make it so the fdt ends on a page boundary */ + actualsize = ALIGN(actualsize, 0x1000); + actualsize = actualsize - ((uint)of_flat_tree & 0xfff); + + /* Change the fdt header to reflect the correct size */ + fdt_set_totalsize(of_flat_tree, actualsize); + of_size = actualsize; + + /* Add the new reservation */ + ret = fdt_add_mem_rsv(of_flat_tree, (uint)of_flat_tree, + of_size); + + /* Create a new LMB reservation */ + lmb_reserve(lmb, (ulong)of_flat_tree, of_size); + } #endif /* CONFIG_OF_LIBFDT */ ret = boot_ramdisk_high (lmb, rd_data_start, rd_len, &initrd_start, &initrd_end); @@ -628,7 +673,7 @@ static int boot_get_fdt (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], */ fdt_blob = (char *)fdt_addr; debug ("* fdt: raw FDT blob\n"); - printf ("## Flattened Device Tree blob at %08lx\n", fdt_blob); + printf ("## Flattened Device Tree blob at %08lx\n", (long)fdt_blob); } break; default: @@ -636,7 +681,7 @@ static int boot_get_fdt (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], goto error; } - printf (" Booting using the fdt blob at 0x%x\n", fdt_blob); + printf (" Booting using the fdt blob at 0x%x\n", (int)fdt_blob); } else if (images->legacy_hdr_valid && image_check_type (&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) { @@ -655,7 +700,7 @@ static int boot_get_fdt (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (fdt_len) { fdt_blob = (char *)fdt_data; - printf (" Booting using the fdt at 0x%x\n", fdt_blob); + printf (" Booting using the fdt at 0x%x\n", (int)fdt_blob); if (fdt_check_header (fdt_blob) != 0) { fdt_error ("image is not a fdt"); @@ -711,22 +756,25 @@ static int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, #endif /* - * The blob must be within CFG_BOOTMAPSZ, - * so we flag it to be copied if it is not. + * The blob needs to be inside the boot mapping. */ - if (fdt_blob >= (char *)CFG_BOOTMAPSZ) + if (fdt_blob < (char *)bootmap_base) relocate = 1; - of_len = be32_to_cpu (fdt_totalsize (fdt_blob)); + if ((fdt_blob + *of_size + CFG_FDT_PAD) >= + ((char *)CFG_BOOTMAPSZ + bootmap_base)) + relocate = 1; /* move flattend device tree if needed */ if (relocate) { int err; - ulong of_start; + ulong of_start = 0; /* position on a 4K boundary before the alloc_current */ - of_start = lmb_alloc_base(lmb, of_len, 0x1000, - (CFG_BOOTMAPSZ + bootmap_base)); + /* Pad the FDT by a specified amount */ + of_len = *of_size + CFG_FDT_PAD; + of_start = (unsigned long)lmb_alloc_base(lmb, of_len, 0x1000, + (CFG_BOOTMAPSZ + bootmap_base)); if (of_start == 0) { puts("device tree - allocation error\n"); @@ -734,7 +782,7 @@ static int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, } debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", - (ulong)fdt_blob, (ulong)fdt_blob + of_len - 1, + (ulong)fdt_blob, (ulong)fdt_blob + *of_size - 1, of_len, of_len); printf (" Loading Device Tree to %08lx, end %08lx ... ", @@ -748,9 +796,14 @@ static int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, puts ("OK\n"); *of_flat_tree = (char *)of_start; + *of_size = of_len; } else { *of_flat_tree = fdt_blob; - lmb_reserve(lmb, (ulong)fdt, of_len); + of_len = (CFG_BOOTMAPSZ + bootmap_base) - (ulong)fdt_blob; + lmb_reserve(lmb, (ulong)fdt_blob, of_len); + fdt_set_totalsize(*of_flat_tree, of_len); + + *of_size = of_len; } return 0; diff --git a/lib_sh/Makefile b/lib_sh/Makefile index 0e4fdee093..40343812f7 100644 --- a/lib_sh/Makefile +++ b/lib_sh/Makefile @@ -26,7 +26,7 @@ SOBJS-y += COBJS-y += board.o COBJS-y += bootm.o -#COBJS-y += time.o +# COBJS-y += time.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/lib_sh/board.c b/lib_sh/board.c index 883c381e64..eb81bd97ec 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -76,7 +76,7 @@ static int sh_flash_init(void) } #if defined(CONFIG_CMD_NAND) -void nand_init (void); +#include <nand.h> static int sh_nand_init(void) { printf("NAND: "); @@ -112,6 +112,7 @@ static int sh_mem_env_init(void) return 0; } +#if defined(CONFIG_CMD_NET) static int sh_net_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -127,6 +128,7 @@ static int sh_net_init(void) return 0; } +#endif typedef int (init_fnc_t) (void); @@ -170,8 +172,8 @@ void sh_generic_init (void) bd_t *bd; init_fnc_t **init_fnc_ptr; - char *s; int i; + char *s; memset (gd, 0, CFG_GBL_DATA_SIZE); diff --git a/lib_sh/time.c b/lib_sh/time.c index 3d33918f28..9c1dc509bb 100644 --- a/lib_sh/time.c +++ b/lib_sh/time.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <asm/processer.h> +#include <asm/processor.h> static void tmu_timer_start (unsigned int timer) { diff --git a/libfdt/fdt.c b/libfdt/fdt.c index cfa1989d8e..cb08ba0a94 100644 --- a/libfdt/fdt.c +++ b/libfdt/fdt.c @@ -133,16 +133,23 @@ uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset) return tag; } +int _fdt_check_node_offset(const void *fdt, int offset) +{ + if ((offset < 0) || (offset % FDT_TAGSIZE) + || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE)) + return -FDT_ERR_BADOFFSET; + + return offset; +} + int fdt_next_node(const void *fdt, int offset, int *depth) { int nextoffset = 0; uint32_t tag; - if (offset >= 0) { - tag = fdt_next_tag(fdt, offset, &nextoffset); - if (tag != FDT_BEGIN_NODE) - return -FDT_ERR_BADOFFSET; - } + if (offset >= 0) + if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0) + return nextoffset; do { offset = nextoffset; diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c index 11d80d2fa2..69af7bb843 100644 --- a/libfdt/fdt_ro.c +++ b/libfdt/fdt_ro.c @@ -161,16 +161,12 @@ int fdt_path_offset(const void *fdt, const char *path) const char *fdt_get_name(const void *fdt, int nodeoffset, int *len) { - const struct fdt_node_header *nh; + const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset); int err; - if ((err = fdt_check_header(fdt)) != 0) - goto fail; - - err = -FDT_ERR_BADOFFSET; - nh = fdt_offset_ptr(fdt, nodeoffset, sizeof(*nh)); - if (!nh || (fdt32_to_cpu(nh->tag) != FDT_BEGIN_NODE)) - goto fail; + if (((err = fdt_check_header(fdt)) != 0) + || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0)) + goto fail; if (len) *len = strlen(nh->name); @@ -193,17 +189,11 @@ const struct fdt_property *fdt_get_property(const void *fdt, int offset, nextoffset; int err; - if ((err = fdt_check_header(fdt)) != 0) - goto fail; - - err = -FDT_ERR_BADOFFSET; - if (nodeoffset % FDT_TAGSIZE) - goto fail; - - tag = fdt_next_tag(fdt, nodeoffset, &nextoffset); - if (tag != FDT_BEGIN_NODE) - goto fail; + if (((err = fdt_check_header(fdt)) != 0) + || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0)) + goto fail; + nextoffset = err; do { offset = nextoffset; diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c index 8609fa7d76..95a5c2c62b 100644 --- a/libfdt/fdt_rw.c +++ b/libfdt/fdt_rw.c @@ -176,8 +176,7 @@ int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size) struct fdt_reserve_entry *re; int err; - if ((err = rw_check_header(fdt))) - return err; + RW_CHECK_HEADER(fdt); re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt)); err = _blob_splice_mem_rsv(fdt, re, 0, 1); @@ -194,8 +193,8 @@ int fdt_del_mem_rsv(void *fdt, int n) struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n); int err; - if ((err = rw_check_header(fdt))) - return err; + RW_CHECK_HEADER(fdt); + if (n >= fdt_num_mem_rsv(fdt)) return -FDT_ERR_NOTFOUND; @@ -227,15 +226,13 @@ static int _resize_property(void *fdt, int nodeoffset, const char *name, int len static int _add_property(void *fdt, int nodeoffset, const char *name, int len, struct fdt_property **prop) { - uint32_t tag; int proplen; int nextoffset; int namestroff; int err; - tag = fdt_next_tag(fdt, nodeoffset, &nextoffset); - if (tag != FDT_BEGIN_NODE) - return -FDT_ERR_BADOFFSET; + if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0) + return nextoffset; namestroff = _find_add_string(fdt, name); if (namestroff < 0) @@ -260,8 +257,7 @@ int fdt_set_name(void *fdt, int nodeoffset, const char *name) int oldlen, newlen; int err; - if ((err = rw_check_header(fdt))) - return err; + RW_CHECK_HEADER(fdt); namep = (char *)fdt_get_name(fdt, nodeoffset, &oldlen); if (!namep) @@ -284,8 +280,7 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, struct fdt_property *prop; int err; - if ((err = rw_check_header(fdt))) - return err; + RW_CHECK_HEADER(fdt); err = _resize_property(fdt, nodeoffset, name, len, &prop); if (err == -FDT_ERR_NOTFOUND) @@ -456,11 +451,8 @@ int fdt_open_into(const void *fdt, void *buf, int bufsize) int fdt_pack(void *fdt) { int mem_rsv_size; - int err; - err = rw_check_header(fdt); - if (err) - return err; + RW_CHECK_HEADER(fdt); mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) * sizeof(struct fdt_reserve_entry); diff --git a/libfdt/fdt_sw.c b/libfdt/fdt_sw.c index dda2de34b2..df0987606e 100644 --- a/libfdt/fdt_sw.c +++ b/libfdt/fdt_sw.c @@ -55,13 +55,21 @@ #include "libfdt_internal.h" -static int check_header_sw(void *fdt) +static int sw_check_header(void *fdt) { if (fdt_magic(fdt) != SW_MAGIC) return -FDT_ERR_BADMAGIC; + /* FIXME: should check more details about the header state */ return 0; } +#define SW_CHECK_HEADER(fdt) \ + { \ + int err; \ + if ((err = sw_check_header(fdt)) != 0) \ + return err; \ + } + static void *grab_space(void *fdt, int len) { int offset = fdt_size_dt_struct(fdt); @@ -102,11 +110,10 @@ int fdt_create(void *buf, int bufsize) int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size) { struct fdt_reserve_entry *re; - int err = check_header_sw(fdt); int offset; - if (err) - return err; + SW_CHECK_HEADER(fdt); + if (fdt_size_dt_struct(fdt)) return -FDT_ERR_BADSTATE; @@ -131,11 +138,9 @@ int fdt_finish_reservemap(void *fdt) int fdt_begin_node(void *fdt, const char *name) { struct fdt_node_header *nh; - int err = check_header_sw(fdt); int namelen = strlen(name) + 1; - if (err) - return err; + SW_CHECK_HEADER(fdt); nh = grab_space(fdt, sizeof(*nh) + ALIGN(namelen, FDT_TAGSIZE)); if (! nh) @@ -149,10 +154,8 @@ int fdt_begin_node(void *fdt, const char *name) int fdt_end_node(void *fdt) { uint32_t *en; - int err = check_header_sw(fdt); - if (err) - return err; + SW_CHECK_HEADER(fdt); en = grab_space(fdt, FDT_TAGSIZE); if (! en) @@ -188,11 +191,9 @@ static int find_add_string(void *fdt, const char *s) int fdt_property(void *fdt, const char *name, const void *val, int len) { struct fdt_property *prop; - int err = check_header_sw(fdt); int nameoff; - if (err) - return err; + SW_CHECK_HEADER(fdt); nameoff = find_add_string(fdt, name); if (nameoff == 0) @@ -211,15 +212,13 @@ int fdt_property(void *fdt, const char *name, const void *val, int len) int fdt_finish(void *fdt) { - int err = check_header_sw(fdt); char *p = (char *)fdt; uint32_t *end; int oldstroffset, newstroffset; uint32_t tag; int offset, nextoffset; - if (err) - return err; + SW_CHECK_HEADER(fdt); /* Add terminator */ end = grab_space(fdt, sizeof(*end)); diff --git a/libfdt/libfdt_internal.h b/libfdt/libfdt_internal.h index 52e1b8d810..f72e70dbe6 100644 --- a/libfdt/libfdt_internal.h +++ b/libfdt/libfdt_internal.h @@ -66,6 +66,7 @@ } uint32_t _fdt_next_tag(const void *fdt, int startoffset, int *nextoffset); +int _fdt_check_node_offset(const void *fdt, int offset); const char *_fdt_find_string(const char *strtab, int tabsize, const char *s); int _fdt_node_end_offset(void *fdt, int nodeoffset); diff --git a/mips_config.mk b/mips_config.mk index 67fb67d291..05eb05d045 100644 --- a/mips_config.mk +++ b/mips_config.mk @@ -40,10 +40,9 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # LDFLAGS_vmlinux += -G 0 -static -n -nostdlib # MODFLAGS += -mlong-calls # - -# -# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly. +# On the other hand, we want PIC in the U-Boot code to relocate it from ROM +# to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -pipe +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 4272108b51..931f04b29a 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -51,7 +51,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index aed7960709..e1c146750b 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -50,7 +50,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c index ac77d066cb..adede44c37 100644 --- a/nand_spl/board/amcc/bamboo/sdram.c +++ b/nand_spl/board/amcc/bamboo/sdram.c @@ -36,7 +36,7 @@ static void wait_init_complete(void) } /* - * early_sdram_init() + * phys_size_t initdram(int board_type) * * As the name already indicates, this function is called very early * from start.S and configures the SDRAM with fixed values. This is needed, @@ -51,7 +51,7 @@ static void wait_init_complete(void) * modules are still plugged in. So it is recommended to remove the DIMM * modules while using the NAND booting code with the fixed SDRAM setup! */ -void early_sdram_init(void) +phys_size_t initdram(int board_type) { /* * Soft-reset SDRAM controller. @@ -87,12 +87,6 @@ void early_sdram_init(void) */ mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/ wait_init_complete(); -} -long int initdram(int board_type) -{ - /* - * Nothing to do here, just return size of fixed SDRAM setup - */ return CFG_MBYTES_SDRAM << 20; } diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile index 47c7d02c3c..fb86752002 100644 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -55,7 +55,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c index 9010fca15a..29d7d3f819 100644 --- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c +++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c @@ -35,7 +35,7 @@ static void wait_init_complete(void) } while (!(val & 0x80000000)); } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* * Reset the DDR-SDRAM controller. diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 84bd29824d..0667fc1a54 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -29,8 +29,8 @@ LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL -SOBJS = start.o init.o resetvec.o cache.o -COBJS = memory.o nand_boot.o nand_ecc.o ndfc.o +SOBJS = start.o resetvec.o cache.o +COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -50,17 +50,25 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl # create symbolic links for common files # from cpu directory +$(obj)44x_spd_ddr2.c: ecc.h + @rm -f $(obj)44x_spd_ddr2.c + ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c + $(obj)cache.S: @rm -f $(obj)cache.S ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S +$(obj)ecc.h: + @rm -f $(obj)ecc.h + ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h + $(obj)ndfc.c: @rm -f $(obj)ndfc.c ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c @@ -73,15 +81,6 @@ $(obj)start.S: @rm -f $(obj)start.S ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S -# from board directory -$(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/kilauea/init.S $(obj)init.S - -$(obj)memory.c: - @rm -f $(obj)memory.c - ln -s $(SRCTREE)/board/amcc/kilauea/memory.c $(obj)memory.c - # from nand_spl directory $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk index 22490918d0..d89ed3f047 100644 --- a/nand_spl/board/amcc/kilauea/config.mk +++ b/nand_spl/board/amcc/kilauea/config.mk @@ -29,8 +29,9 @@ # # On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, # in the last 4kBytes of memory space in cache. -# We will copy this SPL into instruction-cache in start.S. So we set -# TEXT_BASE to starting address in i-cache here. +# We will copy this SPL into SDRAM since we can't access the NAND +# controller at CS0 while running from this location. So we set +# TEXT_BASE to starting address in SDRAM here. # TEXT_BASE = 0x00800000 diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds index 084db08dd6..03e0b798f9 100644 --- a/nand_spl/board/amcc/kilauea/u-boot.lds +++ b/nand_spl/board/amcc/kilauea/u-boot.lds @@ -32,7 +32,6 @@ SECTIONS .text : { start.o (.text) - init.o (.text) nand_boot.o (.text) ndfc.o (.text) diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile index 93150aad1b..fba0322a72 100644 --- a/nand_spl/board/amcc/sequoia/Makefile +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -50,7 +50,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index bc577252cf..563a80b953 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -221,20 +221,19 @@ static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) return 0; } +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ void nand_boot(void) { - ulong mem_size; struct nand_chip nand_chip; nand_info_t nand_info; int ret; void (*uboot)(void); /* - * Init sdram, so we have access to memory - */ - mem_size = initdram(0); - - /* * Init board specific nand support */ nand_info.priv = &nand_chip; @@ -28,6 +28,17 @@ #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +/* + * CPU and board-specific Ethernet initializations. Aliased function + * signals caller to move on + */ +static int __def_eth_init(bd_t *bis) +{ + return -1; +} +int cpu_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init"))); +int board_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init"))); + #ifdef CFG_GT_6426x extern int gt6426x_eth_initialize(bd_t *bis); #endif @@ -55,7 +66,6 @@ extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); extern int tsi108_eth_initialize(bd_t*); extern int uli526x_initialize(bd_t *); -extern int tsec_initialize(bd_t*, int, char *); extern int npe_initialize(bd_t *); extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); @@ -165,6 +175,10 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_init(); #endif + /* Try board-specific initialization first. If it fails or isn't + * present, try the cpu-specific initialization */ + if (board_eth_init(bis) < 0) + cpu_eth_init(bis); #if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750) mv6436x_eth_initialize(bis); @@ -196,22 +210,6 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_SK98) skge_initialize(bis); #endif -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); -#endif -#if defined(CONFIG_MPC85XX_FEC) - tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); -#else -# if defined(CONFIG_TSEC3) - tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); -# endif -# if defined(CONFIG_TSEC4) - tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); -# endif -#endif #if defined(CONFIG_UEC_ETH1) uec_initialize(0); #endif @@ -288,7 +286,8 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_FSLDMAFEC) mcdmafec_initialize(bis); #endif -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) +#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ + defined(CONFIG_AT91SAM9263) at91sam9_eth_initialize(bis); #endif @@ -1407,6 +1407,10 @@ NetReceive(volatile uchar * inpkt, int len) if (ip->ip_off & htons(0x1fff)) { /* Can't deal w/ fragments */ return; } + /* can't deal with headers > 20 bytes */ + if ((ip->ip_hl_v & 0x0f) > 0x05) { + return; + } if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2)) { puts ("checksum bad\n"); return; diff --git a/net/tftp.c b/net/tftp.c index ea8fea2f7e..84d83ca97b 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -178,7 +178,7 @@ TftpSend (void) pkt += 5 /*strlen("octet")*/ + 1; strcpy ((char *)pkt, "timeout"); pkt += 7 /*strlen("timeout")*/ + 1; - sprintf((char *)pkt, "%d", TIMEOUT); + sprintf((char *)pkt, "%lu", TIMEOUT); #ifdef ET_DEBUG printf("send option \"timeout %s\"\n", (char *)pkt); #endif diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c index b48390ba98..ef641d7899 100644 --- a/post/board/lwmon5/fpga.c +++ b/post/board/lwmon5/fpga.c @@ -41,6 +41,15 @@ DECLARE_GLOBAL_DATA_PTR; #if CONFIG_POST & CFG_POST_BSPEC3 +/* Testpattern for fpga memorytest */ +static uint pattern[] = { + 0x55555555, + 0xAAAAAAAA, + 0xAA5555AA, + 0x55AAAA55, + 0x0 +}; + static int one_scratch_test(uint value) { uint read_value; @@ -60,9 +69,42 @@ static int one_scratch_test(uint value) return ret; } +/* FPGA Memory-pattern-test */ +static int fpga_mem_test(void * address) +{ + int ret = 1; + uint read_value; + uint old_value; + uint i = 0; + /* save content */ + old_value = in_be32(address); + + while (pattern[i] != 0) { + out_be32(address, pattern[i]); + /* read other location (protect against data lines capacity) */ + ret = in_be16((void *)FPGA_VERSION_REG); + /* verify test pattern */ + read_value = in_be32(address); + + if (read_value != pattern[i]) { + post_log("FPGA Memory test failed."); + post_log(" write %08X, read %08X at address %08X\n", + pattern[i], read_value, address); + ret = 1; + goto out; + } + i++; + } + + ret = 0; +out: + out_be32(address, old_value); + return ret; +} /* Verify FPGA, get version & memory size */ int fpga_post_test(int flags) { + uint address; uint old_value; ushort version; uint read_value; @@ -88,6 +130,14 @@ int fpga_post_test(int flags) read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000); post_log("FPGA RAM size: %d bytes\n", read_value); + for (address = 0; address < 0x1000; address++) { + if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) { + ret = 1; + goto out; + } + } + +out: return ret; } diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 27cfb91594..1a57c3dd1f 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -79,13 +79,13 @@ #define UDIV_SUBTRACT 0 #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPe) +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define UART2_SDR sdr_uart2 #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) #define UART3_SDR sdr_uart3 #endif #define MFREG(a, d) mfsdr(a, d) diff --git a/post/post.c b/post/post.c index d31829ba16..99dc8c9a74 100644 --- a/post/post.c +++ b/post/post.c @@ -319,6 +319,7 @@ int post_run (char *name, int flags) } if (i < post_list_size) { + WATCHDOG_RESET(); return post_run_single (post_list + i, test_flags[i], flags, i); diff --git a/post/tests.c b/post/tests.c index a790c789d6..e88d92ed74 100644 --- a/post/tests.c +++ b/post/tests.c @@ -240,7 +240,7 @@ struct post_test post_list[] = "DSP test", "dsp", "This test checks any connected DSP(s).", - POST_RAM | POST_MANUAL, + POST_RAM | POST_ALWAYS | POST_MANUAL, &dsp_post_test, NULL, NULL, diff --git a/tools/Makefile b/tools/Makefile index 5285055dc8..8533a8e5ce 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -44,6 +44,10 @@ LOGO_H = $(OBJTREE)/include/bmp_logo.h ifeq ($(LOGO_BMP),) LOGO_BMP= logos/denx.bmp endif +ifeq ($(VENDOR),atmel) +LOGO_BMP= logos/atmel.bmp +endif + #------------------------------------------------------------------------- diff --git a/tools/logos/atmel.bmp b/tools/logos/atmel.bmp Binary files differnew file mode 100644 index 0000000000..3c445c9bc3 --- /dev/null +++ b/tools/logos/atmel.bmp diff --git a/tools/logos/linux_logo_ttcontrol.bmp b/tools/logos/linux_logo_ttcontrol.bmp Binary files differnew file mode 100644 index 0000000000..031d3a41ec --- /dev/null +++ b/tools/logos/linux_logo_ttcontrol.bmp diff --git a/tools/logos/linux_logo_ttcontrol_palfin.bmp b/tools/logos/linux_logo_ttcontrol_palfin.bmp Binary files differnew file mode 100644 index 0000000000..e3e38d1bf6 --- /dev/null +++ b/tools/logos/linux_logo_ttcontrol_palfin.bmp |
