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| author | Stefano Babic <sbabic@denx.de> | 2015-11-12 17:13:26 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-11-12 17:13:26 +0100 |
| commit | 5f5620ab2679608f94b3a77e51c77d0a770103bd (patch) | |
| tree | ec983c06d2f62384909968bb870add121b8a1502 | |
| parent | 78e9ca52edaab74ad645d719676ff4c24d2f462c (diff) | |
| parent | 038be18fd95aa6283eafb85ceabc0b880976424b (diff) | |
| download | blackbird-obmc-uboot-5f5620ab2679608f94b3a77e51c77d0a770103bd.tar.gz blackbird-obmc-uboot-5f5620ab2679608f94b3a77e51c77d0a770103bd.zip | |
Merge git://git.denx.de/u-boot
557 files changed, 13346 insertions, 2246 deletions
@@ -152,6 +152,16 @@ config SPL_STACK_R_MALLOC_SIMPLE_LEN to give board_init_r() a larger heap then the initial heap in SRAM which is limited to SYS_MALLOC_F_LEN bytes. +config SPL_SEPARATE_BSS + depends on SPL + bool "BSS section is in a different memory region from text" + help + Some platforms need a large BSS region in SPL and can provide this + because RAM is already set up. In this case BSS can be moved to RAM. + This option should then be enabled so that the correct device tree + location is used. Normally we put the device tree at the end of BSS + but with this option enabled, it goes at _image_binary_end. + config TPL bool depends on SPL && SUPPORT_TPL @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + VERSION = 2015 PATCHLEVEL = 10 SUBLEVEL = @@ -605,6 +609,8 @@ KBUILD_CFLAGS += $(KCFLAGS) UBOOTINCLUDE := \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ + $(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \ + -I$(srctree)/arch/$(ARCH)/thumb1/include),) \ -I$(srctree)/arch/$(ARCH)/include \ -include $(srctree)/include/linux/kconfig.h @@ -1130,7 +1136,11 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) ifeq ($(ARCH),arm) +ifdef CONFIG_DM +UBOOT_BINLOAD := u-boot-dtb.img +else UBOOT_BINLOAD := u-boot.img +endif else UBOOT_BINLOAD := u-boot.bin endif diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 5bc6f44c1a..d481fcdc69 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h index 85721aaee3..370cb46e9f 100644 --- a/arch/arc/include/asm/bitops.h +++ b/arch/arc/include/asm/bitops.h @@ -16,4 +16,9 @@ #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + #endif /* __ASM_ARC_BITOPS_H */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2632099874..5ab0254f3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -10,6 +10,9 @@ config ARM64 config HAS_VBAR bool +config HAS_THUMB2 + bool + config CPU_ARM720T bool @@ -32,9 +35,11 @@ config CPU_ARM1176 config CPU_V7 bool select HAS_VBAR + select HAS_THUMB2 config CPU_V7M bool + select HAS_THUMB2 config CPU_PXA bool @@ -543,13 +548,20 @@ config ARCH_ZYNQ select CPU_V7 select SUPPORT_SPL select OF_CONTROL + select SPL_OF_CONTROL select DM + select SPL_DM select DM_SPI + select DM_SERIAL select DM_SPI_FLASH + select SPL_SEPARATE_BSS config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" select ARM64 + select DM + select OF_CONTROL + select DM_SERIAL config TEGRA bool "NVIDIA Tegra" @@ -627,6 +639,14 @@ config TARGET_LS1021ATWR select CPU_V7 select SUPPORT_SPL +config TARGET_LS1043ARDB + bool "Support ls1043ardb" + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + help + Support for Freescale LS1043ARDB platform. + config TARGET_H2200 bool "Support h2200" select CPU_PXA @@ -743,6 +763,7 @@ source "board/freescale/ls2085aqds/Kconfig" source "board/freescale/ls2085ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index 6bea3d3a2d..950e680c7a 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj- += dummy.o diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 63fa159db6..fe78922170 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_cpu.o := -marm +CFLAGS_cache.o := -marm + +endif +endif diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index e5c1a6ae6c..2839c863e8 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -82,4 +82,9 @@ void flush_dcache_all(void) /* * Stub implementations for l2 cache operations */ + __weak void l2_cache_disable(void) {} + +#if defined CONFIG_SYS_THUMB_BUILD +__weak void invalidate_l2_cache(void) {} +#endif diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2d55782749..2311468ac9 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -9,6 +9,7 @@ obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index e2eb5f383a..df2e1b76f1 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -301,6 +301,7 @@ int arch_cpu_init(void) void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; u32 state; /* @@ -328,6 +329,8 @@ int arch_cpu_init(void) */ fsl_epu_clean(epu_base); + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR); + return 0; } diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index e01d911780..856abed941 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -171,7 +171,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, CONFIG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c new file mode 100644 index 0000000000..deeb674c69 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -0,0 +1,42 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <ahci.h> +#include <scsi.h> + +/* port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28183411 +#define AHCI_PORT_PHY_3_CFG 0x0e081004 +#define AHCI_PORT_PHY_4_CFG 0x00480811 +#define AHCI_PORT_PHY_5_CFG 0x192c96a4 +#define AHCI_PORT_TRANS_CFG 0x08000025 + +#define SATA_ECC_REG_ADDR 0x20220520 +#define SATA_ECC_DISABLE 0x00020000 + +int ls1021a_sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); +#endif + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); + out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)AHCI_BASE_ADDR); + scsi_scan(0); + + return 0; +} diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index 154d67490d..764c6614ea 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -5,9 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <fdtdec.h> #include <asm/io.h> #include <asm/arch/clk.h> +DECLARE_GLOBAL_DATA_PTR; + /* Default is s5pc100 */ unsigned int s5p_cpu_id = 0xC100; /* Default is EVT1 */ @@ -30,7 +33,16 @@ u32 get_device_type(void) #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { - printf("CPU: %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id); + const char *cpu_model; + int len; + + /* For SoC with no real CPU ID in naming convention. */ + cpu_model = fdt_getprop(gd->fdt_blob, 0, "cpu-model", &len); + if (cpu_model) + printf("CPU: %.*s @ ", len, cpu_model); + else + printf("CPU: %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id); + print_freq(get_arm_clk(), "\n"); return 0; diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c index e5c6111330..dd058bd643 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/cpu/armv7m/stm32f4/flash.c @@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last) while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) ; + /* clear old sector number before writing a new one */ + clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK); + if (bank == 0) { setbits_le32(&STM32_FLASH->cr, (i << STM32_FLASH_CR_SNB_OFFSET)); @@ -114,9 +117,9 @@ int flash_erase(flash_info_t *info, int first, int last) ; clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); - stm32f4_flash_lock(1); } + stm32f4_flash_lock(1); return 0; } diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index adb11b3bda..48c041bb9b 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -15,6 +15,6 @@ obj-y += cache.o obj-y += tlb.o obj-y += transition.o -obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ +obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index b1ea8227cb..1ece6a2c12 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) } /* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +__weak void mmu_setup(void) { bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile new file mode 100644 index 0000000000..6fa08c8f3c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -0,0 +1,30 @@ +# +# Copyright 2014-2015, Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += lowlevel.o +obj-y += soc.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_SPL) += spl.o + +ifneq ($(CONFIG_FSL_LSCH3),) +obj-y += fsl_lsch3_speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o +else +ifneq ($(CONFIG_FSL_LSCH2),) +obj-y += fsl_lsch2_speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o +endif +endif + +ifneq ($(CONFIG_LS2085A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o +else +ifneq ($(CONFIG_LS1043A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o +endif +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 new file mode 100644 index 0000000000..a6ef830069 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 @@ -0,0 +1,10 @@ +# +# Copyright 2015 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Freescale LayerScape with Chassis Generation 2 + +This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, +for example LS1043A. diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 index 08da7e4d1d..03e18f6573 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -1,5 +1,5 @@ # -# Copyright 2014 Freescale Semiconductor +# Copyright 2014-2015 Freescale Semiconductor # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index eb1213e9f0..0cb0afa0b3 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,34 +10,28 @@ #include <asm/system.h> #include <asm/armv8/mmu.h> #include <asm/io.h> -#include <asm/arch-fsl-lsch3/soc.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <asm/arch/cpu.h> +#include <asm/arch/speed.h> +#ifdef CONFIG_MP +#include <asm/arch/mp.h> +#endif +#include <fm_eth.h> #include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> -#include <asm/arch/fsl_serdes.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#include "cpu.h" -#include "mp.h" -#include "speed.h" DECLARE_GLOBAL_DATA_PTR; -static struct cpu_type cpu_type_list[] = { -#ifdef CONFIG_LS2085A - CPU_TYPE_ENTRY(LS2085, LS2085, 8), - CPU_TYPE_ENTRY(LS2080, LS2080, 8), - CPU_TYPE_ENTRY(LS2045, LS2045, 4), -#endif -}; - void cpu_name(char *name) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int i, svr, ver; - svr = in_le32(&gur->svr); + svr = gur_in32(&gur->svr); ver = SVR_SOC_VER(svr); for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) @@ -54,146 +48,6 @@ void cpu_name(char *name) } #ifndef CONFIG_SYS_DCACHE_OFF - -#define SECTION_SHIFT_L0 39UL -#define SECTION_SHIFT_L1 30UL -#define SECTION_SHIFT_L2 21UL -#define BLOCK_SIZE_L0 0x8000000000 -#define BLOCK_SIZE_L1 0x40000000 -#define BLOCK_SIZE_L2 0x200000 - -#define NUM_OF_ENTRY 512 - -#define TCR_EL2_PS_40BIT (2 << 16) -#define LSCH3_VA_BITS (40) -#define LSCH3_TCR (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_NON | \ - TCR_ORGN_NC | \ - TCR_IRGN_NC | \ - TCR_T0SZ(LSCH3_VA_BITS)) -#define LSCH3_TCR_FINAL (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_OUTER | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(LSCH3_VA_BITS)) - -#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 -#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 -#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 -#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 -#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 -#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 -#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 -#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 -#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 -#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 -#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 -#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 -#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 -#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 -#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 -#define CONFIG_SYS_FSL_NI_BASE 0x810000000 -#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 -#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 -#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 -#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 -#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 - -struct sys_mmu_table { - u64 virt_addr; - u64 phys_addr; - u64 size; - u64 memory_type; - u64 share; -}; - -static const struct sys_mmu_table lsch3_early_mmu_table[] = { - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, - /* For IFC Region #1, only the first 4MB is cache-enabled */ - { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, -}; - -static const struct sys_mmu_table lsch3_final_mmu_table[] = { - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, - { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - /* For QBMAN portal, only the first 64MB is cache-enabled */ - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2085A - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#endif - { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, -}; - -struct table_info { - u64 *ptr; - u64 table_base; - u64 entry_size; -}; - /* * Set the block entries according to the information of the table. */ @@ -311,6 +165,7 @@ static inline void early_mmu_setup(void) u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; /* Invalidate all table entries */ @@ -320,19 +175,23 @@ static inline void early_mmu_setup(void) set_pgtable_table(level0_table, 0, level1_table0); set_pgtable_table(level0_table, 1, level1_table1); set_pgtable_table(level1_table0, 0, level2_table0); + +#ifdef CONFIG_FSL_LSCH3 set_pgtable_table(level1_table0, CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, level2_table1); - +#elif defined(CONFIG_FSL_LSCH2) + set_pgtable_table(level1_table0, 1, level2_table1); +#endif /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) { - if (find_table(&lsch3_early_mmu_table[i], + for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) { + if (find_table(&early_mmu_table[i], &table, level0_table) == 0) { /* * If find_table() returns error, it cannot be dealt * with here. Breakpoint can be added for debugging. */ - set_block_entry(&lsch3_early_mmu_table[i], &table); + set_block_entry(&early_mmu_table[i], &table); /* * If set_block_entry() returns error, it cannot be * dealt with here too. @@ -341,7 +200,9 @@ static inline void early_mmu_setup(void) } el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES); + + set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR, + MEMORY_ATTRIBUTES); set_sctlr(get_sctlr() | CR_M); } @@ -353,7 +214,12 @@ static inline void early_mmu_setup(void) * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. + * + * For LSCH3: * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. + * For LSCH2: + * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB. + * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB. */ static inline void final_mmu_setup(void) { @@ -362,7 +228,12 @@ static inline void final_mmu_setup(void) u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); +#ifdef CONFIG_FSL_LSCH3 + u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); +#elif defined(CONFIG_FSL_LSCH2) u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); + u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000); +#endif struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; /* Invalidate all table entries */ @@ -372,23 +243,30 @@ static inline void final_mmu_setup(void) set_pgtable_table(level0_table, 0, level1_table0); set_pgtable_table(level0_table, 1, level1_table1); set_pgtable_table(level1_table0, 0, level2_table0); +#ifdef CONFIG_FSL_LSCH3 set_pgtable_table(level1_table0, CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, level2_table1); +#elif defined(CONFIG_FSL_LSCH2) + set_pgtable_table(level1_table0, 1, level2_table1); + set_pgtable_table(level1_table0, + CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, + level2_table2); +#endif /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) { - if (find_table(&lsch3_final_mmu_table[i], + for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) { + if (find_table(&final_mmu_table[i], &table, level0_table) == 0) { - if (set_block_entry(&lsch3_final_mmu_table[i], + if (set_block_entry(&final_mmu_table[i], &table) != 0) { printf("MMU error: could not set block entry for %p\n", - &lsch3_final_mmu_table[i]); + &final_mmu_table[i]); } } else { printf("MMU error: could not find the table for %p\n", - &lsch3_final_mmu_table[i]); + &final_mmu_table[i]); } } @@ -396,9 +274,13 @@ static inline void final_mmu_setup(void) flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); +#ifdef CONFIG_SYS_DPAA_FMAN + flush_dcache_all(); +#endif /* point TTBR to the new table */ el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL, + + set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); /* * MMU is already enabled, just need to invalidate TLB to load the @@ -434,8 +316,9 @@ static inline u32 initiator_type(u32 cluster, int init_id) { struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; - u32 type = in_le32(&gur->tp_ityp[idx]); + u32 type = 0; + type = gur_in32(&gur->tp_ityp[idx]); if (type & TP_ITYP_AV) return type; @@ -450,7 +333,8 @@ u32 cpu_mask(void) do { int j; - cluster = in_le32(&gur->tp_cluster[i].lower); + + cluster = gur_in32(&gur->tp_cluster[i].lower); for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { type = initiator_type(cluster, j); if (type) { @@ -460,7 +344,7 @@ u32 cpu_mask(void) } } i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + } while ((cluster & TP_CLUSTER_EOC) == 0x0); return mask; } @@ -482,7 +366,8 @@ int fsl_qoriq_core_to_cluster(unsigned int core) do { int j; - cluster = in_le32(&gur->tp_cluster[i].lower); + + cluster = gur_in32(&gur->tp_cluster[i].lower); for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { if (initiator_type(cluster, j)) { if (count == core) @@ -491,7 +376,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core) } } i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + } while ((cluster & TP_CLUSTER_EOC) == 0x0); return -1; /* cannot identify the cluster */ } @@ -505,7 +390,8 @@ u32 fsl_qoriq_core_to_type(unsigned int core) do { int j; - cluster = in_le32(&gur->tp_cluster[i].lower); + + cluster = gur_in32(&gur->tp_cluster[i].lower); for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { type = initiator_type(cluster, j); if (type) { @@ -515,7 +401,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core) } } i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + } while ((cluster & TP_CLUSTER_EOC) == 0x0); return -1; /* cannot identify the cluster */ } @@ -527,15 +413,13 @@ int print_cpuinfo(void) struct sys_info sysinfo; char buf[32]; unsigned int i, core; - u32 type; + u32 type, rcw; puts("SoC: "); cpu_name(buf); - printf(" %s (0x%x)\n", buf, in_le32(&gur->svr)); - + printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); - get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { @@ -551,18 +435,23 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); +#ifdef CONFIG_SYS_DPAA_FMAN + printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); +#endif +#ifdef CONFIG_FSL_LSCH3 printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); +#endif puts("\n"); - /* Display the RCW, so that no one gets confused as to what RCW + /* + * Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_le32(&gur->rcwsr[i]); - + rcw = gur_in32(&gur->rcwsr[i]); if ((i % 4) == 0) - printf("\n %02x:", i * 4); + printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); @@ -585,27 +474,37 @@ int cpu_eth_init(bd_t *bis) #ifdef CONFIG_FSL_MC_ENET error = fsl_mc_ldpaa_init(bis); #endif +#ifdef CONFIG_FMAN_ENET + fm_standard_init(bis); +#endif return error; } int arch_early_init_r(void) { - int rv; - rv = fsl_lsch3_wake_seconday_cores(); +#ifdef CONFIG_MP + int rv = 1; + rv = fsl_layerscape_wake_seconday_cores(); if (rv) printf("Did not wake secondary cores\n"); +#endif #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif +#ifdef CONFIG_FMAN_ENET + fman_enet_init(); +#endif return 0; } int timer_init(void) { u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; +#ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; +#endif #ifdef COUNTER_FREQUENCY_REAL unsigned long cntfrq = COUNTER_FREQUENCY_REAL; @@ -613,10 +512,12 @@ int timer_init(void) asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); #endif +#ifdef CONFIG_FSL_LSCH3 /* Enable timebase for all clusters. * It is safe to do so even some clusters are not enabled. */ out_le32(cltbenr, 0xf); +#endif /* Enable clock for timer * This is a global setting. @@ -632,7 +533,7 @@ void reset_cpu(ulong addr) u32 val; /* Raise RESET_REQ_B */ - val = in_le32(rstcr); + val = scfg_in32(rstcr); val |= 0x02; - out_le32(rstcr, val); + scfg_out32(rstcr, val); } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h index 2e3312b99b..8072f3ca6a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright 2014, Freescale Semiconductor + * Copyright 2014-2015, Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 567c41927a..47599c1217 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,11 +7,22 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> -#include <asm/arch-fsl-lsch3/fdt.h> +#include <phy.h> +#ifdef CONFIG_FSL_LSCH3 +#include <asm/arch/fdt.h> +#endif #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#include "mp.h" +#ifdef CONFIG_MP +#include <asm/arch/mp.h> +#endif + +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) +{ + return fdt_setprop_string(blob, offset, "phy-connection-type", + phy_string_for_interface(phyc)); +} #ifdef CONFIG_MP void ft_fixup_cpu(void *blob) @@ -33,8 +44,8 @@ void ft_fixup_cpu(void *blob) off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); - core_id = of_read_number(reg, addr_cells); if (reg) { + core_id = of_read_number(reg, addr_cells); if (core_id == 0 || (is_core_online(core_id))) { val = spin_tbl_addr; val += id_to_core(core_id) * @@ -150,6 +161,7 @@ void append_mmu_masters(void *blob, const char *smmu_path, * for all DPAA2 devices. * */ +#ifdef CONFIG_FSL_LSCH3 static void fdt_fixup_smmu(void *blob) { int nodeoffset; @@ -165,6 +177,7 @@ static void fdt_fixup_smmu(void *blob) fdt_fixup_smmu_pcie(blob); #endif } +#endif void ft_cpu_setup(void *blob, bd_t *bd) { @@ -181,9 +194,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_pci_setup(blob, bd); #endif -#if defined(CONFIG_FSL_ESDHC) +#ifdef CONFIG_FSL_ESDHC fdt_fixup_esdhc(blob, bd); #endif +#ifdef CONFIG_FSL_LSCH3 fdt_fixup_smmu(blob); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c new file mode 100644 index 0000000000..f7178d1470 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -0,0 +1,117 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> + +#ifdef CONFIG_SYS_FSL_SRDS_1 +static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = 0; + +#ifdef CONFIG_SYS_FSL_SRDS_1 + ret |= serdes1_prtcl_map[device]; +#endif + + return !!ret; +} + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg = gur_in32(&gur->rcwsr[4]); + int i; + + switch (sd) { +#ifdef CONFIG_SYS_FSL_SRDS_1 + case FSL_SRDS_1: + cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + break; +#endif + default: + printf("invalid SerDes%d\n", sd); + break; + } + + /* Is serdes enabled at all? */ + if (unlikely(cfg == 0)) + return -ENODEV; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(sd, cfg, i) == device) + return i; + } + + return -ENODEV; +} + +int get_serdes_protocol(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg = gur_in32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + return cfg; +} + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "100"; + } +} + +void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, + u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg; + int lane; + + memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + + cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + + if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) + debug("Unknown SerDes lane protocol %d\n", lane_prtcl); + else + serdes_prtcl_map[lane_prtcl] = 1; + } +} + +void fsl_serdes_init(void) +{ +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_SERDES_ADDR, + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK, + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT, + serdes1_prtcl_map); +#endif +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c new file mode 100644 index 0000000000..6f6a588292 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -0,0 +1,180 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/compiler.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/arch/clock.h> +#include <asm/arch/soc.h> +#include <fsl_ifc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#endif + +void get_sys_info(struct sys_info *sys_info) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + u32 ccr; +#endif +#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN) + u32 rcw_tmp; +#endif + struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); + unsigned int cpu; + const u8 core_cplx_pll[8] = { + [0] = 0, /* CC1 PPL / 1 */ + [1] = 0, /* CC1 PPL / 2 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 1, /* CC2 PPL / 2 */ + }; + + const u8 core_cplx_pll_div[8] = { + [0] = 1, /* CC1 PPL / 1 */ + [1] = 2, /* CC1 PPL / 2 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 2, /* CC2 PPL / 2 */ + }; + + uint i; + uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else + sys_info->freq_ddrbus = sysclk; +#endif + + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; + if (ratio[i] > 4) + freq_c_pll[i] = sysclk * ratio[i]; + else + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; + } + + for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) { + u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + & 0xf; + u32 cplx_pll = core_cplx_pll[c_pll_sel]; + + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } + +#define HWA_CGA_M1_CLK_SEL 0xe0000000 +#define HWA_CGA_M1_CLK_SHIFT 29 +#ifdef CONFIG_SYS_DPAA_FMAN + rcw_tmp = in_be32(&gur->rcwsr[7]); + switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { + case 2: + sys_info->freq_fman[0] = freq_c_pll[0] / 2; + break; + case 3: + sys_info->freq_fman[0] = freq_c_pll[0] / 3; + break; + case 6: + sys_info->freq_fman[0] = freq_c_pll[1] / 2; + break; + case 7: + sys_info->freq_fman[0] = freq_c_pll[1] / 3; + break; + default: + printf("Error: Unknown FMan1 clock select!\n"); + break; + } +#endif + +#define HWA_CGA_M2_CLK_SEL 0x00000007 +#define HWA_CGA_M2_CLK_SHIFT 0 +#ifdef CONFIG_FSL_ESDHC + rcw_tmp = in_be32(&gur->rcwsr[15]); + rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT; + sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp; +#endif + +#if defined(CONFIG_FSL_IFC) + ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#endif +} + +int get_clocks(void) +{ + struct sys_info sys_info; + + get_sys_info(&sys_info); + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + +#ifdef CONFIG_FSL_ESDHC + gd->arch.sdhc_clk = sys_info.freq_sdhc; +#endif + + if (gd->cpu_clk != 0) + return 0; + else + return 1; +} + +ulong get_bus_freq(ulong dummy) +{ + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + return gd->mem_clk; +} + +#ifdef CONFIG_FSL_ESDHC +int get_sdhc_freq(ulong dummy) +{ + return gd->arch.sdhc_clk; +} +#endif + +int get_serial_clock(void) +{ + return gd->bus_clk; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_I2C_CLK: + return get_bus_freq(0); +#if defined(CONFIG_FSL_ESDHC) + case MXC_ESDHC_CLK: + return get_sdhc_freq(0); +#endif + case MXC_DSPI_CLK: + return get_bus_freq(0); + case MXC_UART_CLK: + return get_bus_freq(0); + default: + printf("Unsupported clock\n"); + } + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index ae0834365e..2ab8da6403 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <asm/arch/soc.h> #include <fsl-mc/ldpaa_wriop.h> #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 cfg = in_le32(&gur->rcwsr[28]); + u32 cfg = gur_in32(&gur->rcwsr[28]); int i; switch (sd) { @@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); - cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask; + cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index d9f137cc2d..4054c3c7d2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2014, Freescale Semiconductor, Inc. + * Copyright 2014-2015, Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ * @@ -11,8 +11,8 @@ #include <fsl_ifc.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> #include <asm/arch/clock.h> +#include <asm/arch/soc.h> #include "cpu.h" DECLARE_GLOBAL_DATA_PTR; @@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus2 = sysclk; #endif - sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; /* Platform clock is half of platform PLL */ sys_info->freq_systembus /= 2; - sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; - sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >> + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; @@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = in_le32(&ifc_regs.gregs->ifc_ccr); + ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; sys_info->freq_localbus = sys_info->freq_systembus / ccr; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6b19d36f11..41e1704986 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 Freescale Semiconductor + * (C) Copyright 2014-2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ * @@ -10,11 +10,14 @@ #include <linux/linkage.h> #include <asm/gic.h> #include <asm/macro.h> -#include "mp.h" +#ifdef CONFIG_MP +#include <asm/arch/mp.h> +#endif ENTRY(lowlevel_init) mov x29, lr /* Save LR */ +#ifdef CONFIG_FSL_LSCH3 /* Add fully-coherent masters to DVM domain */ ldr x0, =CCI_MN_BASE ldr x1, =CCI_MN_RNF_NODEID_LIST @@ -81,6 +84,7 @@ ENTRY(lowlevel_init) ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) ldr x1, =0x00FF000C bl ccn504_set_qos +#endif /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE @@ -106,10 +110,12 @@ ENTRY(lowlevel_init) branch_if_master x0, x1, 2f +#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) ldr x0, =secondary_boot_func blr x0 -2: +#endif +2: #ifdef CONFIG_FSL_TZPC_BP147 /* Set Non Secure access for all devices protected via TZPC */ ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */ @@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache) ret ENDPROC(__asm_flush_l3_cache) +#ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */ .ltorg @@ -353,3 +360,4 @@ __real_cntfrq: /* Secondary Boot Code ends here */ __secondary_boot_code_size: .quad .-secondary_boot_code +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c new file mode 100644 index 0000000000..e54d3899bb --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c @@ -0,0 +1,86 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/immap_lsch2.h> + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} }, + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} }, + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} }, + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} }, + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, + PCIE3} }, + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} }, + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} }, + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} }, + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} }, + {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} }, + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} }, + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} }, + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c index 0b79a501d9..ea3114cca4 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c @@ -1,12 +1,11 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> struct serdes_config { u8 protocol; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index da7853a5af..0d600db090 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,9 +7,8 @@ #include <common.h> #include <asm/io.h> #include <asm/system.h> -#include <asm/io.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> -#include "mp.h" +#include <asm/arch/mp.h> +#include <asm/arch/soc.h> DECLARE_GLOBAL_DATA_PTR; @@ -23,10 +22,14 @@ phys_addr_t determine_mp_bootpg(void) return (phys_addr_t)&secondary_boot_code; } -int fsl_lsch3_wake_seconday_cores(void) +int fsl_layerscape_wake_seconday_cores(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_LSCH3 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); +#elif defined(CONFIG_FSL_LSCH2) + struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); +#endif u32 cores, cpu_up_mask = 1; int i, timeout = 10; u64 *table = get_spin_tbl_addr(); @@ -48,13 +51,24 @@ int fsl_lsch3_wake_seconday_cores(void) (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); printf("Waking secondary cores to start from %lx\n", gd->relocaddr); - out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); - out_le32(&gur->bootlocptrl, (u32)gd->relocaddr); - out_le32(&gur->scratchrw[6], 1); + +#ifdef CONFIG_FSL_LSCH3 + gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); + gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); + gur_out32(&gur->scratchrw[6], 1); asm volatile("dsb st" : : : "memory"); rst->brrl = cores; asm volatile("dsb st" : : : "memory"); +#elif defined(CONFIG_FSL_LSCH2) + scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32)); + scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr); + asm volatile("dsb st" : : : "memory"); + gur_out32(&gur->brrl, cores); + asm volatile("dsb st" : : : "memory"); + /* Bootup online cores */ + scfg_out32(&scfg->corebcr, cores); +#endif /* This is needed as a precautionary measure. * If some code before this has accidentally released the secondary * cores then the pre-bootloader code will trap them in a "wfe" unless diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2538001bca..637853d51f 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,19 +1,18 @@ /* - * Copyright 2015 Freescale Semiconductor + * Copyright 2014-2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <fsl_ifc.h> -#include <nand.h> -#include <spl.h> -#include <asm/arch-fsl-lsch3/soc.h> +#include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_LS2085A static void erratum_a008751(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 @@ -78,30 +77,27 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); } -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) +#elif defined(CONFIG_LS1043A) +void fsl_lsch2_early_init_f(void) { - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - arch_cpu_init(); - board_early_init_f(); - timer_init(); - env_init(); - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - - serial_init(); - console_init_f(); - dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); /* tighten IFC timing */ +#endif - board_init_r(NULL, 0); + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A53 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); } +#endif -u32 spl_boot_device(void) +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) { - return BOOT_DEVICE_NAND; + return 0; } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c new file mode 100644 index 0000000000..ba551aaa6e --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -0,0 +1,79 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <fsl_ifc.h> +#include <fsl_csu.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif +#ifdef CONFIG_SPL_NAND_SUPPORT + return BOOT_DEVICE_NAND; +#endif + return 0; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + case BOOT_DEVICE_NAND: + return 0; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Set global data pointer */ + gd = &gdata; + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); +#ifdef CONFIG_LS2085A + arch_cpu_init(); +#endif +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + board_early_init_f(); + timer_init(); +#ifdef CONFIG_LS2085A + env_init(); +#endif + get_clocks(); + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + dram_init(); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + board_init_r(NULL, 0); +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile deleted file mode 100644 index 9f7815bd52..0000000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2014, Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += cpu.o -obj-y += lowlevel.o -obj-y += soc.o -obj-y += speed.o -obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o -obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h deleted file mode 100644 index 15af5b9f91..0000000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void get_sys_info(struct sys_info *sys_info); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ddc6a057d5..9542fff47d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ @@ -65,6 +69,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += \ + zynqmp-ep108.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index d0a8621fda..690c747289 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -31,6 +31,18 @@ 0xb0000000 0xea00000>; }; + adc@12D10000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + i2c@12CA0000 { + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + }; + }; + ehci@12110000 { samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index bd3619d751..daa6a33c5b 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -42,6 +42,13 @@ xhci1 = "/xhci@12400000"; }; + adc@12D10000 { + compatible = "samsung,exynos-adc-v2"; + reg = <0x12D10000 0x100>; + interrupts = <0 106 0>; + status = "disabled"; + }; + i2c@12CA0000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 1d7ff23c93..76826dc23b 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -12,6 +12,7 @@ / { model = "Samsung/Google Peach Pi board based on Exynos5800"; + cpu-model = "Exynos5800"; compatible = "google,pit-rev#", "google,pit", "google,peach", "samsung,exynos5800", "samsung,exynos5"; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 546560979b..9eb5a2209c 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -89,7 +89,7 @@ #size-cells = <1>; compatible = "n25q00"; reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + spi-max-frequency = <100000000>; m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index bd86f09326..ccadd817c0 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -54,6 +54,14 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index a57f8ae335..a11b628f19 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -221,7 +221,7 @@ reg = <0x65c00000 0x100>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 135 4>; + interrupts = <0 137 4>; }; pinctrl: pinctrl@5f801000 { diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index 912bc27bea..52dd1f96b0 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -44,6 +44,10 @@ status = "okay"; }; +&usb1 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index a15c7b2161..6f19bf81dc 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -210,6 +210,24 @@ reg = <0x60001000 0x1000>, <0x60000100 0x100>; }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + interrupts = <0 134 4>; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + interrupts = <0 137 4>; + }; }; }; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index 81d2385bf9..d0af8acd37 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -42,6 +42,14 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index fba7b742ca..92d74044c1 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -42,6 +42,10 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 8b496a7210..cd0cf4e74b 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -235,6 +235,24 @@ reg = <0x60001000 0x1000>, <0x60000100 0x100>; }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + interrupts = <0 134 4>; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + interrupts = <0 137 4>; + }; }; }; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 84c15b5c79..83be51ae9d 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -54,6 +54,7 @@ }; amba: amba { + u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index d5e0050893..e841a1d616 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -26,3 +26,8 @@ &qspi { status = "okay"; }; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts index 686b98fe7e..3408df8b8b 100644 --- a/arch/arm/dts/zynq-picozed.dts +++ b/arch/arm/dts/zynq-picozed.dts @@ -21,3 +21,8 @@ reg = <0 0x40000000>; }; }; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 4d8696021b..c41723641e 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -376,6 +376,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index fc336ea5c9..5088cfee3e 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -297,6 +297,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index cf56ac8d82..07e2b7a738 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -88,6 +88,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index f73c0ddcb8..77e3bb0e63 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -55,6 +55,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 4289e31f46..3e1769acb5 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -62,5 +62,6 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 5124cdc5cd..288e248374 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -75,5 +75,6 @@ }; &uart0 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 363049085f..51d67d93f2 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -54,6 +54,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 10f7815524..dcfc00e096 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -49,5 +49,6 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi new file mode 100644 index 0000000000..f864526553 --- /dev/null +++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi @@ -0,0 +1,119 @@ +/* + * clock specification for Xilinx ZynqMP ep108 development board + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&amba { + misc_clk: misc_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + i2c_clk: i2c_clk { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <111111111>; + }; + + sata_clk: sata_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <75000000>; + }; + + dp_aclk: clock0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-accuracy = <100>; + }; + + dp_aud_clk: clock1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + clock-accuracy = <100>; + }; +}; + +&can0 { + clocks = <&misc_clk &misc_clk>; +}; + +&gem0 { + clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; +}; + +&gpio { + clocks = <&misc_clk>; +}; + +&i2c0 { + clocks = <&i2c_clk>; +}; + +&i2c1 { + clocks = <&i2c_clk>; +}; + +&qspi { + clocks = <&misc_clk &misc_clk>; +}; + +&sata { + clocks = <&sata_clk>; +}; + +&sdhci0 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&sdhci1 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&spi0 { + clocks = <&misc_clk &misc_clk>; +}; + +&spi1 { + clocks = <&misc_clk &misc_clk>; +}; + +&uart0 { + clocks = <&misc_clk &misc_clk>; +}; + +&usb0 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&usb1 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&watchdog0 { + clocks= <&misc_clk>; +}; + +&xilinx_drm { + clocks = <&misc_clk>; +}; + +&xlnx_dp { + clocks = <&dp_aclk>, <&dp_aud_clk>; +}; + +&xlnx_dp_snd_codec0 { + clocks = <&dp_aud_clk>; +}; + +&xlnx_dpdma { + clocks = <&misc_clk>; +}; diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts new file mode 100644 index 0000000000..4481bd07c9 --- /dev/null +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -0,0 +1,174 @@ +/* + * dts file for Xilinx ZynqMP ep108 development board + * + * (C) Copyright 2014 - 2015, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "zynqmp.dtsi" +/include/ "zynqmp-ep108-clk.dtsi" + +/ { + model = "ZynqMP EP108"; + + aliases { + serial0 = &uart0; + spi0 = &qspi; + spi1 = &spi0; + spi2 = &spi1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x40000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0{ + reg = <0>; + max-speed = <100>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + eeprom@54 { + compatible = "at,24c64"; + reg = <0x54>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + eeprom@55 { + compatible = "at,24c64"; + reg = <0x55>; + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "n25q512a11"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <10000000>; + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&sata { + status = "okay"; + ceva,broken-gen2; +}; + +&sdhci0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <1>; + spi0_flash0: spi0_flash0@0 { + compatible = "m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + spi0_flash0@00000000 { + label = "spi0_flash0"; + reg = <0x0 0x100000>; + }; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <1>; + spi1_flash0: spi1_flash0@0 { + compatible = "m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + spi1_flash0@00000000 { + label = "spi1_flash0"; + reg = <0x0 0x100000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + maximum-speed = "high-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xlnx_dp { + xlnx,max-pclock-frequency = <200000>; +}; + +&xlnx_dpdma { + xlnx,axi-clock-freq = <200000000>; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi new file mode 100644 index 0000000000..24a34e6d85 --- /dev/null +++ b/arch/arm/dts/zynqmp.dtsi @@ -0,0 +1,668 @@ +/* + * dts file for Xilinx ZynqMP + * + * (C) Copyright 2014 - 2015, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/ { + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 143 4>, + <0 144 4>, + <0 145 4>, + <0 146 4>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + firmware { + compatible = "xlnx,zynqmp-pm"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <1 13 0xf01>, + <1 14 0xf01>, + <1 11 0xf01>, + <1 10 0xf01>; + }; + + amba_apu: amba_apu { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@f9010000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + reg = <0x0 0xf9010000 0x10000>, + <0x0 0xf902f000 0x2000>, + <0x0 0xf9040000 0x20000>, + <0x0 0xf906f000 0x2000>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <1 9 0xf04>; + }; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + can0: can@ff060000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clock-names = "can_clk", "pclk"; + reg = <0x0 0xff060000 0x1000>; + interrupts = <0 23 4>; + interrupt-parent = <&gic>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + can1: can@ff070000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clock-names = "can_clk", "pclk"; + reg = <0x0 0xff070000 0x1000>; + interrupts = <0 24 4>; + interrupt-parent = <&gic>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + /* GDMA */ + fpd_dma_chan1: dma@fd500000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 124 4>; + xlnx,id = <0>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan2: dma@fd510000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd510000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 125 4>; + xlnx,id = <1>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan3: dma@fd520000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd520000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 126 4>; + xlnx,id = <2>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan4: dma@fd530000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd530000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 127 4>; + xlnx,id = <3>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan5: dma@fd540000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd540000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 128 4>; + xlnx,id = <4>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan6: dma@fd550000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd550000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 129 4>; + xlnx,id = <5>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan7: dma@fd560000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd560000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 130 4>; + xlnx,id = <6>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan8: dma@fd570000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd570000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 131 4>; + xlnx,id = <7>; + xlnx,bus-width = <128>; + }; + + gpu: gpu@fd4b0000 { + status = "disabled"; + compatible = "arm,mali-400", "arm,mali-utgard"; + reg = <0x0 0xfd4b0000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; + interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; + }; + + /* ADMA */ + lpd_dma_chan1: dma@ffa80000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffa80000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 77 4>; + xlnx,id = <0>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan2: dma@ffa90000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffa90000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 78 4>; + xlnx,id = <1>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan3: dma@ffaa0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffaa0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 79 4>; + xlnx,id = <2>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan4: dma@ffab0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffab0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 80 4>; + xlnx,id = <3>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan5: dma@ffac0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffac0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 81 4>; + xlnx,id = <4>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan6: dma@ffad0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffad0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 82 4>; + xlnx,id = <5>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan7: dma@ffae0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffae0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 83 4>; + xlnx,id = <6>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan8: dma@ffaf0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffaf0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 84 4>; + xlnx,id = <7>; + xlnx,bus-width = <64>; + }; + + nand0: nand@ff100000 { + compatible = "arasan,nfc-v3p10"; + status = "disabled"; + reg = <0x0 0xff100000 0x1000>; + clock-names = "clk_sys", "clk_flash"; + interrupt-parent = <&gic>; + interrupts = <0 14 4>; + #address-cells = <2>; + #size-cells = <1>; + }; + + gem0: ethernet@ff0b0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 57 4>, <0 57 4>; + reg = <0x0 0xff0b0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gem1: ethernet@ff0c0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 59 4>, <0 59 4>; + reg = <0x0 0xff0c0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gem2: ethernet@ff0d0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 61 4>, <0 61 4>; + reg = <0x0 0xff0d0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gem3: ethernet@ff0e0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 63 4>, <0 63 4>; + reg = <0x0 0xff0e0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gpio: gpio@ff0a0000 { + compatible = "xlnx,zynqmp-gpio-1.0"; + status = "disabled"; + #gpio-cells = <0x2>; + interrupt-parent = <&gic>; + interrupts = <0 16 4>; + reg = <0x0 0xff0a0000 0x1000>; + }; + + i2c0: i2c@ff020000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 17 4>; + reg = <0x0 0xff020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@ff030000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 18 4>; + reg = <0x0 0xff030000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pcie: pcie@fd0e0000 { + compatible = "xlnx,nwl-pcie-2.11"; + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = < 0 118 4>, + < 0 116 4>, + < 0 115 4>, /* MSI_1 [63...32] */ + < 0 114 4 >; /* MSI_0 [31...0] */ + interrupt-names = "misc", "intx", "msi_1", "msi_0"; + reg = <0x0 0xfd0e0000 0x1000>, + <0x0 0xfd480000 0x1000>, + <0x0 0xe0000000 0x1000000>; + reg-names = "breg", "pcireg", "cfg"; + ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; + }; + + qspi: spi@ff0f0000 { + compatible = "xlnx,zynqmp-qspi-1.0"; + status = "disabled"; + clock-names = "ref_clk", "pclk"; + interrupts = <0 15 4>; + interrupt-parent = <&gic>; + num-cs = <1>; + reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + rtc: rtc@ffa60000 { + compatible = "xlnx,zynqmp-rtc"; + status = "disabled"; + reg = <0x0 0xffa60000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 26 4>, <0 27 4>; + interrupt-names = "alarm", "sec"; + }; + + sata: ahci@fd0c0000 { + compatible = "ceva,ahci-1v84"; + status = "disabled"; + reg = <0x0 0xfd0c0000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 133 4>; + }; + + sdhci0: sdhci@ff160000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 48 4>; + reg = <0x0 0xff160000 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + sdhci1: sdhci@ff170000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 49 4>; + reg = <0x0 0xff170000 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + smmu: smmu@fd800000 { + compatible = "arm,mmu-500"; + reg = <0x0 0xfd800000 0x20000>; + #global-interrupts = <1>; + interrupt-parent = <&gic>; + interrupts = <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; + }; + + spi0: spi@ff040000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 19 4>; + reg = <0x0 0xff040000 0x1000>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@ff050000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 20 4>; + reg = <0x0 0xff050000 0x1000>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ttc0: timer@ff110000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 36 4>, <0 37 4>, <0 38 4>; + reg = <0x0 0xff110000 0x1000>; + timer-width = <32>; + }; + + ttc1: timer@ff120000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 39 4>, <0 40 4>, <0 41 4>; + reg = <0x0 0xff120000 0x1000>; + timer-width = <32>; + }; + + ttc2: timer@ff130000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 42 4>, <0 43 4>, <0 44 4>; + reg = <0x0 0xff130000 0x1000>; + timer-width = <32>; + }; + + ttc3: timer@ff140000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 45 4>, <0 46 4>, <0 47 4>; + reg = <0x0 0xff140000 0x1000>; + timer-width = <32>; + }; + + uart0: serial@ff000000 { + compatible = "cdns,uart-r1p8"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 21 4>; + reg = <0x0 0xff000000 0x1000>; + clock-names = "uart_clk", "pclk"; + }; + + uart1: serial@ff010000 { + compatible = "cdns,uart-r1p8"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 22 4>; + reg = <0x0 0xff010000 0x1000>; + clock-names = "uart_clk", "pclk"; + }; + + usb0: usb@fe200000 { + compatible = "snps,dwc3"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 65 4>; + reg = <0x0 0xfe200000 0x40000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + usb1: usb@fe300000 { + compatible = "snps,dwc3"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 70 4>; + reg = <0x0 0xfe300000 0x40000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + watchdog0: watchdog@fd4d0000 { + compatible = "cdns,wdt-r1p2"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 52 1>; + reg = <0x0 0xfd4d0000 0x1000>; + timeout-sec = <10>; + }; + + xilinx_drm: xilinx_drm { + compatible = "xlnx,drm"; + status = "disabled"; + xlnx,encoder-slave = <&xlnx_dp>; + xlnx,connector-type = "DisplayPort"; + xlnx,dp-sub = <&xlnx_dp_sub>; + planes { + xlnx,pixel-format = "rgb565"; + plane0 { + dmas = <&xlnx_dpdma 3>; + dma-names = "dma"; + }; + plane1 { + dmas = <&xlnx_dpdma 0>; + dma-names = "dma"; + }; + }; + }; + + xlnx_dp: dp@43c00000 { + compatible = "xlnx,v-dp"; + status = "disabled"; + reg = <0x0 0xfd4a0000 0x1000>; + interrupts = <0 119 4>; + interrupt-parent = <&gic>; + clock-names = "aclk", "aud_clk"; + xlnx,dp-version = "v1.2"; + xlnx,max-lanes = <2>; + xlnx,max-link-rate = <540000>; + xlnx,max-bpc = <16>; + xlnx,enable-ycrcb; + xlnx,colormetry = "rgb"; + xlnx,bpc = <8>; + xlnx,audio-chan = <2>; + xlnx,dp-sub = <&xlnx_dp_sub>; + }; + + xlnx_dp_snd_card: dp_snd_card { + compatible = "xlnx,dp-snd-card"; + status = "disabled"; + xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; + xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; + }; + + xlnx_dp_snd_codec0: dp_snd_codec0 { + compatible = "xlnx,dp-snd-codec"; + status = "disabled"; + clock-names = "aud_clk"; + }; + + xlnx_dp_snd_pcm0: dp_snd_pcm0 { + compatible = "xlnx,dp-snd-pcm"; + status = "disabled"; + dmas = <&xlnx_dpdma 4>; + dma-names = "tx"; + }; + + xlnx_dp_snd_pcm1: dp_snd_pcm1 { + compatible = "xlnx,dp-snd-pcm"; + status = "disabled"; + dmas = <&xlnx_dpdma 5>; + dma-names = "tx"; + }; + + xlnx_dp_sub: dp_sub@43c0a000 { + compatible = "xlnx,dp-sub"; + status = "disabled"; + reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; + reg-names = "blend", "av_buf", "aud"; + xlnx,output-fmt = "rgb"; + }; + + xlnx_dpdma: dma@fd4c0000 { + compatible = "xlnx,dpdma"; + status = "disabled"; + reg = <0x0 0xfd4c0000 0x1000>; + interrupts = <0 122 4>; + interrupt-parent = <&gic>; + clock-names = "axi_clk"; + dma-channels = <6>; + #dma-cells = <1>; + dma-video0channel@43c10000 { + compatible = "xlnx,video0"; + }; + dma-video1channel@43c10000 { + compatible = "xlnx,video1"; + }; + dma-video2channel@43c10000 { + compatible = "xlnx,video2"; + }; + dma-graphicschannel@43c10000 { + compatible = "xlnx,graphics"; + }; + dma-audio0channel@43c10000 { + compatible = "xlnx,audio0"; + }; + dma-audio1channel@43c10000 { + compatible = "xlnx,audio1"; + }; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index 62bc53c2fe..69359135d5 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -1,12 +1,12 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ * */ -#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_ -#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_ +#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ +#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ #include <common.h> @@ -21,4 +21,4 @@ enum mxc_clock { unsigned int mxc_get_clock(enum mxc_clock clk); -#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */ +#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h new file mode 100644 index 0000000000..87bb937582 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -0,0 +1,143 @@ +/* + * Copyright 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ + +#include <fsl_ddrc_version.h> + +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#else +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ +#endif +#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 + +#if defined(CONFIG_LS2085A) +#define CONFIG_MAX_CPUS 16 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define SRDS_MAX_LANES 8 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ + +/* DDR */ +#define CONFIG_SYS_FSL_DDR_LE +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_IFC_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06100000 + +/* SMMU Defintions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE 0x04000000 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + +#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) +#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) +#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) +#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) +#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) +#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) + +#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) +#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) +#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +#define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008511 +#define CONFIG_SYS_FSL_ERRATUM_A008514 +#define CONFIG_SYS_FSL_ERRATUM_A008585 +#define CONFIG_SYS_FSL_ERRATUM_A008751 +#elif defined(CONFIG_LS1043A) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ +#define CONFIG_SYS_FSL_DDR_BE +#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_BE +#define CONFIG_SYS_FSL_CCSR_SCFG_BE +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_QSPI_BE + +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +#define SRDS_MAX_LANES 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" + +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SNVS_LE +#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION + +/* SMMU Defintions */ +#define SMMU_BASE 0x09000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x01401000 +#define GICC_BASE 0x01402000 + +#else +#error SoC not defined +#endif + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h new file mode 100644 index 0000000000..29039963f1 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -0,0 +1,229 @@ +/* + * Copyright 2014-2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_LAYERSCAPE_CPU_H +#define _FSL_LAYERSCAPE_CPU_H + +static struct cpu_type cpu_type_list[] = { + CPU_TYPE_ENTRY(LS2085, LS2085, 8), + CPU_TYPE_ENTRY(LS2080, LS2080, 8), + CPU_TYPE_ENTRY(LS2045, LS2045, 4), + CPU_TYPE_ENTRY(LS1043, LS1043, 4), +}; + +#ifndef CONFIG_SYS_DCACHE_OFF + +#define SECTION_SHIFT_L0 39UL +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000 +#define BLOCK_SIZE_L1 0x40000000 +#define BLOCK_SIZE_L2 0x200000 +#define NUM_OF_ENTRY 512 +#define TCR_EL2_PS_40BIT (2 << 16) + +#define LAYERSCAPE_VA_BITS (40) +#define LAYERSCAPE_TCR (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_NON | \ + TCR_ORGN_NC | \ + TCR_IRGN_NC | \ + TCR_T0SZ(LAYERSCAPE_VA_BITS)) +#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_OUTER | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(LAYERSCAPE_VA_BITS)) + +#ifdef CONFIG_FSL_LSCH3 +#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 +#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 +#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 +#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 +#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 +#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 +#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 +#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 +#define CONFIG_SYS_FSL_NI_BASE 0x810000000 +#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 +#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 +#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#elif defined(CONFIG_FSL_LSCH2) +#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 +#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 +#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 +#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 +#define CONFIG_SYS_FSL_IFC_BASE 0x60000000 +#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ +#endif + +struct sys_mmu_table { + u64 virt_addr; + u64 phys_addr; + u64 size; + u64 memory_type; + u64 share; +}; + +struct table_info { + u64 *ptr; + u64 table_base; + u64 entry_size; +}; + +static const struct sys_mmu_table early_mmu_table[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#endif +}; + +static const struct sys_mmu_table final_mmu_table[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#ifdef CONFIG_LS2085A + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, + CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#endif +}; +#endif + +int fsl_qoriq_core_to_cluster(unsigned int core); +u32 cpu_mask(void); +#endif /* _FSL_LAYERSCAPE_CPU_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 21d20fba21..4da73ab142 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -4,7 +4,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ + void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); void append_mmu_masters(void *blob, const char *smmu_path, const char *master_name, u32 *stream_ids, int count); void fdt_fixup_smmu_pcie(void *blob); +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h new file mode 100644 index 0000000000..e1043b5a5f --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -0,0 +1,157 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SERDES_H__ +#define __FSL_SERDES_H__ + +#include <config.h> + +#if defined(CONFIG_LS2085A) +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + XAUI1, + XAUI2, + XFI1, + XFI2, + XFI3, + XFI4, + XFI5, + XFI6, + XFI7, + XFI8, + SGMII1, + SGMII2, + SGMII3, + SGMII4, + SGMII5, + SGMII6, + SGMII7, + SGMII8, + SGMII9, + SGMII10, + SGMII11, + SGMII12, + SGMII13, + SGMII14, + SGMII15, + SGMII16, + QSGMII_A, /* A indicates MACs 1-4 */ + QSGMII_B, /* B indicates MACs 5-8 */ + QSGMII_C, /* C indicates MACs 9-12 */ + QSGMII_D, /* D indicates MACs 12-16 */ + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; +#elif defined(CONFIG_LS1043A) +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + SRIO1, + SRIO2, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, + SGMII_FM2_DTSEC5, + SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC10, + SGMII_TSEC1, + SGMII_TSEC2, + SGMII_TSEC3, + SGMII_TSEC4, + XAUI_FM1, + XAUI_FM2, + AURORA, + CPRI1, + CPRI2, + CPRI3, + CPRI4, + CPRI5, + CPRI6, + CPRI7, + CPRI8, + XAUI_FM1_MAC9, + XAUI_FM1_MAC10, + XAUI_FM2_MAC9, + XAUI_FM2_MAC10, + HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, + HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, + QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */ + QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ + QSGMII_FM2_A, + QSGMII_FM2_B, + XFI_FM1_MAC1, + XFI_FM1_MAC2, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + XFI_FM2_MAC9, + XFI_FM2_MAC10, + INTERLAKEN, + QSGMII_SW1_A, /* Indicates ports on L2 Switch */ + QSGMII_SW1_B, + SGMII_2500_FM1_DTSEC1, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC3, + SGMII_2500_FM1_DTSEC4, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC6, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM2_DTSEC1, + SGMII_2500_FM2_DTSEC2, + SGMII_2500_FM2_DTSEC3, + SGMII_2500_FM2_DTSEC4, + SGMII_2500_FM2_DTSEC5, + SGMII_2500_FM2_DTSEC6, + SGMII_2500_FM2_DTSEC9, + SGMII_2500_FM2_DTSEC10, + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, +}; + +#endif + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +int is_serdes_prtcl_valid(int serdes, u32 prtcl); + +#ifdef CONFIG_LS1043A +const char *serdes_clock_to_string(u32 clock); +int get_serdes_protocol(void); +#endif + +#endif /* __FSL_SERDES_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h new file mode 100644 index 0000000000..d941437d63 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -0,0 +1,555 @@ +/* + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_FSL_LSCH2_IMMAP_H__ +#define __ARCH_FSL_LSCH2_IMMAP_H__ + +#include <fsl_immap.h> + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) + +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) +#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) +#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) +#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) +#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) + +#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) + +#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) + +#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) +#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) + +#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) + +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) + +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 + +#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +/* + * Define default values for some CCSR macros to make header files cleaner* + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ +CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_sdhc; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif + unsigned long freq_qman; +}; + +#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 +#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 +#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 +#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 +#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 + +#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 +#define CONFIG_SYS_FSL_FM1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) +#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) + +/* Device Configuration and Pin Control */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ +#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; +#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 +#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F +#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 +#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_02c[0x70-0x2c]; + u32 devdisr; /* Device disable control */ +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u32 devdisr7; /* Device disable control 7 */ + u8 res_08c[0x94-0x8c]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_09c[0xa0-0x9c]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u32 mvr; /* Manufacturing version */ + u8 res_0ac[0xb0-0xac]; + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ + u8 res_0b8[0xc0-0xb8]; + u32 rstrqmr1; /* Reset request mask */ + u8 res_0c4[0xc8-0xc4]; + u32 rstrqsr1; /* Reset request status */ + u8 res_0cc[0xd4-0xcc]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res_0d8[0xdc-0xd8]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res_0e0[0xe4-0xe0]; + u32 brrl; /* Boot release */ + u8 res_0e8[0x100-0xe8]; + u32 rcwsr[16]; /* Reset control word status */ +#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 +#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 + u8 res_140[0x200-0x140]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res_210[0x300-0x210]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 crstsr[12]; + u8 res_430[0x500-0x430]; + + /* PCI Express n Logical I/O Device Number register */ + u32 dcfg_ccsr_pex1liodnr; + u32 dcfg_ccsr_pex2liodnr; + u32 dcfg_ccsr_pex3liodnr; + u32 dcfg_ccsr_pex4liodnr; + /* RIO n Logical I/O Device Number register */ + u32 dcfg_ccsr_rio1liodnr; + u32 dcfg_ccsr_rio2liodnr; + u32 dcfg_ccsr_rio3liodnr; + u32 dcfg_ccsr_rio4liodnr; + /* USB Logical I/O Device Number register */ + u32 dcfg_ccsr_usb1liodnr; + u32 dcfg_ccsr_usb2liodnr; + u32 dcfg_ccsr_usb3liodnr; + u32 dcfg_ccsr_usb4liodnr; + /* SD/MMC Logical I/O Device Number register */ + u32 dcfg_ccsr_sdmmc1liodnr; + u32 dcfg_ccsr_sdmmc2liodnr; + u32 dcfg_ccsr_sdmmc3liodnr; + u32 dcfg_ccsr_sdmmc4liodnr; + /* RIO Message Unit Logical I/O Device Number register */ + u32 dcfg_ccsr_riomaintliodnr; + + u8 res_544[0x550-0x544]; + u32 sataliodnr[4]; + u8 res_560[0x570-0x560]; + + u32 dcfg_ccsr_misc1liodnr; + u32 dcfg_ccsr_misc2liodnr; + u32 dcfg_ccsr_misc3liodnr; + u32 dcfg_ccsr_misc4liodnr; + u32 dcfg_ccsr_dma1liodnr; + u32 dcfg_ccsr_dma2liodnr; + u32 dcfg_ccsr_dma3liodnr; + u32 dcfg_ccsr_dma4liodnr; + u32 dcfg_ccsr_spare1liodnr; + u32 dcfg_ccsr_spare2liodnr; + u32 dcfg_ccsr_spare3liodnr; + u32 dcfg_ccsr_spare4liodnr; + u8 res_5a0[0x600-0x5a0]; + u32 dcfg_ccsr_pblsr; + + u32 pamubypenr; + u32 dmacr1; + + u8 res_60c[0x610-0x60c]; + u32 dcfg_ccsr_gensr1; + u32 dcfg_ccsr_gensr2; + u32 dcfg_ccsr_gensr3; + u32 dcfg_ccsr_gensr4; + u32 dcfg_ccsr_gencr1; + u32 dcfg_ccsr_gencr2; + u32 dcfg_ccsr_gencr3; + u32 dcfg_ccsr_gencr4; + u32 dcfg_ccsr_gencr5; + u32 dcfg_ccsr_gencr6; + u32 dcfg_ccsr_gencr7; + u8 res_63c[0x658-0x63c]; + u32 dcfg_ccsr_cgensr1; + u32 dcfg_ccsr_cgensr0; + u8 res_660[0x678-0x660]; + u32 dcfg_ccsr_cgencr1; + + u32 dcfg_ccsr_cgencr0; + u8 res_680[0x700-0x680]; + u32 dcfg_ccsr_sriopstecr; + u32 dcfg_ccsr_dcsrcr; + + u8 res_708[0x740-0x708]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[16]; + u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ + u32 dcfg_ccsr_qmbm_warmrst; + u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ + u32 dcfg_ccsr_reserved0; + u32 dcfg_ccsr_reserved1; +}; + +#define SCFG_QSPI_CLKSEL 0x40100000 +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 +#define SCFG_USBPWRFAULT_SHARED 0x00000001 +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 +#define SCFG_USBPWRFAULT_USB3_SHIFT 4 +#define SCFG_USBPWRFAULT_USB2_SHIFT 2 +#define SCFG_USBPWRFAULT_USB1_SHIFT 0 + +#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 +#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 + +/* Supplemental Configuration Unit */ +struct ccsr_scfg { + u8 res_000[0x100-0x000]; + u32 usb2_icid; + u32 usb3_icid; + u8 res_108[0x114-0x108]; + u32 dma_icid; + u32 sata_icid; + u32 usb1_icid; + u32 qe_icid; + u32 sdhc_icid; + u32 edma_icid; + u32 etr_icid; + u32 core_sft_rst[4]; + u8 res_140[0x158-0x140]; + u32 altcbar; + u32 qspi_cfg; + u8 res_160[0x180-0x160]; + u32 dmamcr; + u8 res_184[0x18c-0x184]; + u32 debug_icid; + u8 res_190[0x1a4-0x190]; + u32 snpcnfgcr; + u8 res_1a8[0x1ac-0x1a8]; + u32 intpcr; + u8 res_1b0[0x204-0x1b0]; + u32 coresrencr; + u8 res_208[0x220-0x208]; + u32 rvbar0_0; + u32 rvbar0_1; + u32 rvbar1_0; + u32 rvbar1_1; + u32 rvbar2_0; + u32 rvbar2_1; + u32 rvbar3_0; + u32 rvbar3_1; + u32 lpmcsr; + u8 res_244[0x400-0x244]; + u32 qspidqscr; + u32 ecgtxcmcr; + u32 sdhciovselcr; + u32 rcwpmuxcr0; + u32 usbdrvvbus_selcr; + u32 usbpwrfault_selcr; + u32 usb_refclk_selcr1; + u32 usb_refclk_selcr2; + u32 usb_refclk_selcr3; + u8 res_424[0x600-0x424]; + u32 scratchrw[4]; + u8 res_610[0x680-0x610]; + u32 corebcr; + u8 res_684[0x1000-0x684]; + u32 pex1msiir; + u32 pex1msir; + u8 res_1008[0x2000-0x1008]; + u32 pex2; + u32 pex2msir; + u8 res_2008[0x3000-0x2008]; + u32 pex3msiir; + u32 pex3msir; +}; + +/* Clocking */ +struct ccsr_clk { + struct { + u32 clkcncsr; /* core cluster n clock control status */ + u8 res_004[0x0c]; + u32 clkcghwacsr; /* Clock generator n hardware accelerator */ + u8 res_014[0x0c]; + } clkcsr[4]; + u8 res_040[0x780]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res_804[0x1c]; + } pllcgsr[2]; + u8 res_840[0x1c0]; + u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ + u8 res_a04[0x1fc]; + u32 pllpgsr; /* 0xc00 Platform PLL General Status */ + u8 res_c04[0x1c]; + u32 plldgsr; /* 0xc20 DDR PLL General Status */ + u8 res_c24[0x3dc]; +}; + +/* System Counter */ +struct sctr_regs { + u32 cntcr; + u32 cntsr; + u32 cntcv1; + u32 cntcv2; + u32 resv1[4]; + u32 cntfid0; + u32 cntfid1; + u32 resv2[1002]; + u32 counterid[12]; +}; + +#define SRDS_MAX_LANES 4 +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 +#define SRDS_RSTCTL_SWRST 0x10000000 +#define SRDS_RSTCTL_SDEN 0x00000020 +#define SRDS_RSTCTL_SDRST_B 0x00000040 +#define SRDS_RSTCTL_PLLRST_B 0x00000080 + u32 pllcr0; /* PLL Control Register 0 */ +#define SRDS_PLLCR0_POFF 0x80000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 +#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 +#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 +#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 +#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_PLL_LCK 0x00800000 +#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 +#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 +#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 +#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 +#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 + u32 pllcr1; /* PLL Control Register 1 */ +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + u32 res_0c; /* 0x00c */ + u32 pllcr3; + u32 pllcr4; + u8 res_18[0x20-0x18]; + } bank[2]; + u8 res_40[0x90-0x40]; + u32 srdstcalcr; /* 0x90 TX Calibration Control */ + u8 res_94[0xa0-0x94]; + u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ + u8 res_a4[0xb0-0xa4]; + u32 srdsgr0; /* 0xb0 General Register 0 */ + u8 res_b4[0xe0-0xb4]; + u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ + u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ + u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ + u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ + u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ + u8 res_f4[0x100-0xf4]; + struct { + u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u8 res_104[0x120-0x104]; + } srdslnpssr[4]; + u8 res_180[0x300-0x180]; + u32 srdspexeqcr; + u32 srdspexeqpcr[11]; + u8 res_330[0x400-0x330]; + u32 srdspexapcr; + u8 res_404[0x440-0x404]; + u32 srdspexbpcr; + u8 res_444[0x800-0x444]; + struct { + u32 gcr0; /* 0x800 General Control Register 0 */ + u32 gcr1; /* 0x804 General Control Register 1 */ + u32 gcr2; /* 0x808 General Control Register 2 */ + u32 sscr0; + u32 recr0; /* 0x810 Receive Equalization Control */ + u32 recr1; + u32 tecr0; /* 0x818 Transmit Equalization Control */ + u32 sscr1; + u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ + u8 res_824[0x83c-0x824]; + u32 tcsr3; + } lane[4]; /* Lane A, B, C, D, E, F, G, H */ + u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ +}; + +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 +#define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 + +/* CCI-400 registers */ +struct ccsr_cci400 { + u32 ctrl_ord; /* Control Override */ + u32 spec_ctrl; /* Speculation Control */ + u32 secure_access; /* Secure Access */ + u32 status; /* Status */ + u32 impr_err; /* Imprecise Error */ + u8 res_14[0x100 - 0x14]; + u32 pmcr; /* Performance Monitor Control */ + u8 res_104[0xfd0 - 0x104]; + u32 pid[8]; /* Peripheral ID */ + u32 cid[4]; /* Component ID */ + struct { + u32 snoop_ctrl; /* Snoop Control */ + u32 sha_ord; /* Shareable Override */ + u8 res_1008[0x1100 - 0x1008]; + u32 rc_qos_ord; /* read channel QoS Value Override */ + u32 wc_qos_ord; /* read channel QoS Value Override */ + u8 res_1108[0x110c - 0x1108]; + u32 qos_ctrl; /* QoS Control */ + u32 max_ot; /* Max OT */ + u8 res_1114[0x1130 - 0x1114]; + u32 target_lat; /* Target Latency */ + u32 latency_regu; /* Latency Regulation */ + u32 qos_range; /* QoS Range */ + u8 res_113c[0x2000 - 0x113c]; + } slave[5]; /* Slave Interface */ + u8 res_6000[0x9004 - 0x6000]; + u32 cycle_counter; /* Cycle counter */ + u32 count_ctrl; /* Count Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_9010[0xa000 - 0x9010]; + struct { + u32 event_select; /* Event Select */ + u32 event_count; /* Event Count */ + u32 counter_ctrl; /* Counter Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_a010[0xb000 - 0xa010]; + } pcounter[4]; /* Performance Counter */ + u8 res_e004[0x10000 - 0xe004]; +}; + +/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + +#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index d6bee60385..6a70d44305 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -6,9 +6,109 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __ARCH_FSL_LSCH3_IMMAP_H +#ifndef __ARCH_FSL_LSCH3_IMMAP_H_ #define __ARCH_FSL_LSCH3_IMMAP_H_ +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) +#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) +#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 +#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ + 0x18A0) + +#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) +#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) + +/* SP (Cortex-A5) related */ +#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) +#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ + (CONFIG_SYS_FSL_SP_ADDR + 0x0008) +#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ + (CONFIG_SYS_FSL_SP_ADDR + 0x1000) + +#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) + +#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL + +/* Device Configuration */ +#define DCFG_BASE 0x01e00000 +#define DCFG_PORSR1 0x000 +#define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define DCFG_RCWSR13 0x130 +#define DCFG_RCWSR13_DSPI (0 << 8) + +#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_PORCR1 0x000 + +/* Supplemental Configuration */ +#define SCFG_BASE 0x01fc0000 +#define SCFG_USB3PRM1CR 0x000 + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 + +#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 /* This is chassis generation 3 */ struct sys_info { @@ -109,21 +209,6 @@ struct ccsr_gur { u8 res_858[0x1000-0x858]; }; -#define TP_ITYP_AV 0x00000001 /* Initiator available */ -#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ -#define TP_ITYP_TYPE_ARM 0x0 -#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ -#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ -#define TY_ITYP_VER_A7 0x1 -#define TY_ITYP_VER_A53 0x2 -#define TY_ITYP_VER_A57 0x3 - -#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ -#define TP_INIT_PER_CLUSTER 4 struct ccsr_clk_cluster_group { struct { @@ -180,4 +265,4 @@ struct ccsr_reset { u32 ip_rev1; /* 0xbf8 */ u32 ip_rev2; /* 0xbfc */ }; -#endif /* __ARCH_FSL_LSCH3_IMMAP_H */ +#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h new file mode 100644 index 0000000000..57e417b9e0 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h @@ -0,0 +1,55 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ +#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#ifdef CONFIG_FSL_LPUART +#ifdef CONFIG_LPUART_32B_REG +struct lpuart_fsl { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; +#endif +#endif /* CONFIG_FSL_LPUART */ + +#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h index 5c945309a9..5c945309a9 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h new file mode 100644 index 0000000000..d54eacd4a0 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h @@ -0,0 +1,10 @@ +/* + * Copyright 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ +#include <asm/arch-armv8/mmu.h> +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index c985d6a6ba..e46e076f16 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -1,11 +1,11 @@ /* - * Copyright 2014, Freescale Semiconductor + * Copyright 2014-2015, Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _FSL_CH3_MP_H -#define _FSL_CH3_MP_H +#ifndef _FSL_LAYERSCAPE_MP_H +#define _FSL_LAYERSCAPE_MP_H /* * Each spin table element is defined as @@ -29,10 +29,10 @@ extern u64 __spin_table[]; extern u64 __real_cntfrq; extern u64 *secondary_boot_code; extern size_t __secondary_boot_code_size; -int fsl_lsch3_wake_seconday_cores(void); +int fsl_layerscape_wake_seconday_cores(void); void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); int is_core_online(u64 cpu_id); #endif -#endif /* _FSL_CH3_MP_H */ +#endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h new file mode 100644 index 0000000000..a3ccdb03c7 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -0,0 +1,158 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB1, + CSU_CSLX_QM_BM_SWPORTAL, + CSU_CSLX_PCIE3 = 16, + CSU_CSLX_PCIE3_IO, + CSU_CSLX_USB3 = 20, + CSU_CSLX_USB2, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI1 = 41, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_IFC = 45, + CSU_CSLX_I2C1, + CSU_CSLX_I2C3 = 48, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_SCFG, + CSU_CSLX_FM = 66, + CSU_CSLX_SEC5_5, + CSU_CSLX_BM, + CSU_CSLX_QM, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_IIC4 = 77, + CSU_CSLX_WDT4, + CSU_CSLX_WDT3, + CSU_CSLX_WDT5 = 81, + CSU_CSLX_FTM2 = 86, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_DSCR = 121, +}; + +static struct csu_ns_dev ns_dev[] = { + {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, + {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, + {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, + {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, + {CSU_CSLX_OCRAM, CSU_ALL_RW}, + {CSU_CSLX_GIC, CSU_ALL_RW}, + {CSU_CSLX_PCIE1, CSU_ALL_RW}, + {CSU_CSLX_OCRAM2, CSU_ALL_RW}, + {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, + {CSU_CSLX_PCIE2, CSU_ALL_RW}, + {CSU_CSLX_SATA, CSU_ALL_RW}, + {CSU_CSLX_USB1, CSU_ALL_RW}, + {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, + {CSU_CSLX_PCIE3, CSU_ALL_RW}, + {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, + {CSU_CSLX_USB3, CSU_ALL_RW}, + {CSU_CSLX_USB2, CSU_ALL_RW}, + {CSU_CSLX_SERDES, CSU_ALL_RW}, + {CSU_CSLX_QDMA, CSU_ALL_RW}, + {CSU_CSLX_LPUART2, CSU_ALL_RW}, + {CSU_CSLX_LPUART1, CSU_ALL_RW}, + {CSU_CSLX_LPUART4, CSU_ALL_RW}, + {CSU_CSLX_LPUART3, CSU_ALL_RW}, + {CSU_CSLX_LPUART6, CSU_ALL_RW}, + {CSU_CSLX_LPUART5, CSU_ALL_RW}, + {CSU_CSLX_DSPI1, CSU_ALL_RW}, + {CSU_CSLX_QSPI, CSU_ALL_RW}, + {CSU_CSLX_ESDHC, CSU_ALL_RW}, + {CSU_CSLX_IFC, CSU_ALL_RW}, + {CSU_CSLX_I2C1, CSU_ALL_RW}, + {CSU_CSLX_I2C3, CSU_ALL_RW}, + {CSU_CSLX_I2C2, CSU_ALL_RW}, + {CSU_CSLX_DUART2, CSU_ALL_RW}, + {CSU_CSLX_DUART1, CSU_ALL_RW}, + {CSU_CSLX_WDT2, CSU_ALL_RW}, + {CSU_CSLX_WDT1, CSU_ALL_RW}, + {CSU_CSLX_EDMA, CSU_ALL_RW}, + {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, + {CSU_CSLX_DDR, CSU_ALL_RW}, + {CSU_CSLX_QUICC, CSU_ALL_RW}, + {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, + {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, + {CSU_CSLX_SFP, CSU_ALL_RW}, + {CSU_CSLX_TMU, CSU_ALL_RW}, + {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, + {CSU_CSLX_SCFG, CSU_ALL_RW}, + {CSU_CSLX_FM, CSU_ALL_RW}, + {CSU_CSLX_SEC5_5, CSU_ALL_RW}, + {CSU_CSLX_BM, CSU_ALL_RW}, + {CSU_CSLX_QM, CSU_ALL_RW}, + {CSU_CSLX_GPIO2, CSU_ALL_RW}, + {CSU_CSLX_GPIO1, CSU_ALL_RW}, + {CSU_CSLX_GPIO4, CSU_ALL_RW}, + {CSU_CSLX_GPIO3, CSU_ALL_RW}, + {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, + {CSU_CSLX_CSU, CSU_ALL_RW}, + {CSU_CSLX_IIC4, CSU_ALL_RW}, + {CSU_CSLX_WDT4, CSU_ALL_RW}, + {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_FTM2, CSU_ALL_RW}, + {CSU_CSLX_FTM1, CSU_ALL_RW}, + {CSU_CSLX_FTM4, CSU_ALL_RW}, + {CSU_CSLX_FTM3, CSU_ALL_RW}, + {CSU_CSLX_FTM6, CSU_ALL_RW}, + {CSU_CSLX_FTM5, CSU_ALL_RW}, + {CSU_CSLX_FTM8, CSU_ALL_RW}, + {CSU_CSLX_FTM7, CSU_ALL_RW}, + {CSU_CSLX_DSCR, CSU_ALL_RW}, +}; + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h new file mode 100644 index 0000000000..5ed456e4e2 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#define gur_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) +#define gur_in32(a) in_be32(a) +#define gur_out32(a, v) out_be32(a, v) +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE +#define scfg_in32(a) in_le32(a) +#define scfg_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) +#define scfg_in32(a) in_be32(a) +#define scfg_out32(a, v) out_be32(a, v) +#endif + +struct cpu_type { + char name[15]; + u32 soc_ver; + u32 num_cores; +}; + +#define CPU_TYPE_ENTRY(n, v, nc) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} + +#define SVR_WO_E 0xFFFFFE +#define SVR_LS1043 0x879204 +#define SVR_LS2045 0x870120 +#define SVR_LS2080 0x870110 +#define SVR_LS2085 0x870100 + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) + +#ifdef CONFIG_FSL_LSCH3 +void fsl_lsch3_early_init_f(void); +#elif defined(CONFIG_FSL_LSCH2) +void fsl_lsch2_early_init_f(void); +#endif + +void cpu_name(char *name); +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h new file mode 100644 index 0000000000..de795f6056 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h @@ -0,0 +1,10 @@ +/* + * Copyright 2014-2015, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_LAYERSCAPE_SPEED_H +#define _FSL_LAYERSCAPE_SPEED_H +void get_sys_info(struct sys_info *sys_info); +#endif /* _FSL_LAYERSCAPE_SPEED_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h deleted file mode 100644 index 96d6c98cb8..0000000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ -#define _ASM_ARMV8_FSL_LSCH3_CONFIG_ - -#include <fsl_ddrc_version.h> - -#define CONFIG_SYS_PAGE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#ifndef L1_CACHE_BYTES -#define L1_CACHE_SHIFT 6 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#endif - -#define CONFIG_MP -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ -/* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) - -#define CONFIG_SYS_IMMR 0x01000000 -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) -#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) -#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) -#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) -#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) -#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) -#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 -#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ - 0x18A0) - -#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) -#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) - -/* SP (Cortex-A5) related */ -#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) -#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ - (CONFIG_SYS_FSL_SP_ADDR + 0x0008) -#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ - (CONFIG_SYS_FSL_SP_ADDR + 0x1000) - -#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL -#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL -#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL -#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL - -#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) -#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) -#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) -#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) - -#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) - -/* TZ Protection Controller Definitions */ -#define TZPC_BASE 0x02200000 -#define TZPCR0SIZE_BASE (TZPC_BASE) -#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) -#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) -#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) -#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) -#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) -#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) -#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) -#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) - -/* TZ Address Space Controller Definitions */ -#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ -#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ -#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ -#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ -#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) -#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) -#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) -#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) -#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) -#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) -#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) -#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) -#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x06000000 -#define GICR_BASE 0x06100000 - -/* SMMU Defintions */ -#define SMMU_BASE 0x05000000 /* GR0 Base */ - -/* DDR */ -#define CONFIG_SYS_FSL_DDR_LE -#define CONFIG_VERY_BIG_RAM -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#else -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ -#endif -#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ -#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 - -#define CONFIG_SYS_FSL_ESDHC_LE -/* IFC */ -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - -/* PCIe */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL - -/* Cache Coherent Interconnect */ -#define CCI_MN_BASE 0x04000000 -#define CCI_MN_RNF_NODEID_LIST 0x180 -#define CCI_MN_DVM_DOMAIN_CTL 0x200 -#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 - -#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) -#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) -#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) -#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) -#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) -#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) - -#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) -#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) -#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) - -/* Device Configuration */ -#define DCFG_BASE 0x01e00000 -#define DCFG_PORSR1 0x000 -#define DCFG_PORSR1_RCW_SRC 0xff800000 -#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 -#define DCFG_RCWSR13 0x130 -#define DCFG_RCWSR13_DSPI (0 << 8) - -#define DCFG_DCSR_BASE 0X700100000ULL -#define DCFG_DCSR_PORCR1 0x000 - -/* Supplemental Configuration */ -#define SCFG_BASE 0x01fc0000 -#define SCFG_USB3PRM1CR 0x000 - -#ifdef CONFIG_LS2085A -#define CONFIG_MAX_CPUS 16 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SRDS_2 -#else -#error SoC not defined -#endif - -#ifdef CONFIG_LS2085A -#define CONFIG_SYS_FSL_ERRATUM_A008336 -#define CONFIG_SYS_FSL_ERRATUM_A008511 -#define CONFIG_SYS_FSL_ERRATUM_A008514 -#define CONFIG_SYS_FSL_ERRATUM_A008585 -#define CONFIG_SYS_FSL_ERRATUM_A008751 -#endif - -#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h deleted file mode 100644 index 2810f3f6d9..0000000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FSL_SERDES_H -#define __FSL_SERDES_H - -#include <config.h> - -#define SRDS_MAX_LANES 8 - -enum srds_prtcl { - NONE = 0, - PCIE1, - PCIE2, - PCIE3, - PCIE4, - SATA1, - SATA2, - XAUI1, - XAUI2, - XFI1, - XFI2, - XFI3, - XFI4, - XFI5, - XFI6, - XFI7, - XFI8, - SGMII1, - SGMII2, - SGMII3, - SGMII4, - SGMII5, - SGMII6, - SGMII7, - SGMII8, - SGMII9, - SGMII10, - SGMII11, - SGMII12, - SGMII13, - SGMII14, - SGMII15, - SGMII16, - QSGMII_A, /* A indicates MACs 1-4 */ - QSGMII_B, /* B indicates MACs 5-8 */ - QSGMII_C, /* C indicates MACs 9-12 */ - QSGMII_D, /* D indicates MACs 12-16 */ - SERDES_PRCTL_COUNT -}; - -enum srds { - FSL_SRDS_1 = 0, - FSL_SRDS_2 = 1, -}; - -int is_serdes_configured(enum srds_prtcl device); -void fsl_serdes_init(void); - -int serdes_get_first_lane(u32 sd, enum srds_prtcl device); -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); -int is_serdes_prtcl_valid(int serdes, u32 prtcl); - -#endif /* __FSL_SERDES_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h deleted file mode 100644 index f23a78c62d..0000000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_ -#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_ -#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h deleted file mode 100644 index 8f005353b4..0000000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ - -#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ -#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ - -#define I2C_QUIRK_REG /* enable 8-bit driver */ - -#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h deleted file mode 100644 index 9a29272072..0000000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -struct cpu_type { - char name[15]; - u32 soc_ver; - u32 num_cores; -}; - -#define CPU_TYPE_ENTRY(n, v, nc) \ - { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} - -#define SVR_WO_E 0xFFFFFE -#define SVR_LS2045 0x870120 -#define SVR_LS2080 0x870110 -#define SVR_LS2085 0x870100 - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) -#define SVR_MIN(svr) (((svr) >> 0) & 0xf) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) - -void fsl_lsch3_early_init_f(void); -void cpu_name(char *name); - diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index bcaf7bf2e4..f066480c0c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -79,6 +79,21 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ CONFIG_SYS_PCIE2_VIRT_ADDR) +/* SATA */ +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_ERRATUM_A008407 + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 60aa0d3b6f..09ed9809f1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -144,6 +144,7 @@ struct ccsr_gur { }; #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 @@ -397,4 +398,28 @@ struct ccsr_cci400 { u8 res_e004[0x10000 - 0xe004]; }; +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 paxic; /* port AXI config */ + u32 axicc; /* AXI cache control */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h new file mode 100644 index 0000000000..d097a6a14c --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h @@ -0,0 +1,11 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SATA_H_ +#define __FSL_SATA_H_ + +int ls1021a_sata_init(void); +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h index b53f69951a..a921fb6d14 100644 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -7,22 +7,6 @@ #ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ -enum csu_cslx_access { - CSU_NS_SUP_R = 0x08, - CSU_NS_SUP_W = 0x80, - CSU_NS_SUP_RW = 0x88, - CSU_NS_USER_R = 0x04, - CSU_NS_USER_W = 0x40, - CSU_NS_USER_RW = 0x44, - CSU_S_SUP_R = 0x02, - CSU_S_SUP_W = 0x20, - CSU_S_SUP_RW = 0x22, - CSU_S_USER_R = 0x01, - CSU_S_USER_W = 0x10, - CSU_S_USER_RW = 0x11, - CSU_ALL_RW = 0xff, -}; - enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, CSU_CSLX_PCIE1_IO, @@ -108,11 +92,88 @@ enum csu_cslx_ind { CSU_CSLX_MAX, }; -struct csu_ns_dev { - unsigned long ind; - uint32_t val; +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, }; -void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num); - #endif diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 3ed3801dfe..7ca6dc3de8 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -104,6 +104,7 @@ struct stm32_flash_regs { #define STM32_FLASH_CR_STRT (1 << 16) #define STM32_FLASH_CR_LOCK (1 << 31) #define STM32_FLASH_CR_SNB_OFFSET 3 +#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) enum clock { CLOCK_CORE, diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index f5c90d11dc..f1e95a2a28 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -13,7 +13,7 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { } -int zynq_sdhci_init(unsigned long regbase); +int zynq_sdhci_init(phys_addr_t regbase); int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 587ee39909..d8d9af45db 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -65,6 +65,7 @@ /* * Section */ +#define PMD_SECT_NS (1 << 5) #define PMD_SECT_NON_SHARE (0 << 8) #define PMD_SECT_OUTER_SHARE (2 << 8) #define PMD_SECT_INNER_SHARE (3 << 8) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 9b78043db7..d479a38291 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -190,4 +190,9 @@ found_middle: #endif /* __KERNEL__ */ +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/fls64.h> + #endif /* _ARM_BITOPS_H */ diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index a836e9f2ab..1f63127bdc 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -16,6 +16,9 @@ /* * Invalidate L2 Cache using co-proc instruction */ +#ifdef CONFIG_SYS_THUMB_BUILD +void invalidate_l2_cache(void); +#else static inline void invalidate_l2_cache(void) { unsigned int val=0; @@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void) : : "r" (val) : "cc"); isb(); } +#endif void l2_cache_enable(void); void l2_cache_disable(void); diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 22fff02778..435fc4521c 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -15,14 +15,11 @@ #define CONFIG_STATIC_RELA #endif -#ifdef CONFIG_FSL_LSCH3 -#include <asm/arch-fsl-lsch3/config.h> -#endif - #if defined(CONFIG_LS102XA) || \ defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_MONAHANS) || \ - defined(CONFIG_CPU_PXA25X) + defined(CONFIG_CPU_PXA25X) || \ + defined(CONFIG_FSL_LAYERSCAPE) #include <asm/arch/config.h> #endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index bfbe0a0988..75773bdbe0 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -46,7 +46,7 @@ static inline void sync(void) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { - return (void *)paddr; + return (void *)((unsigned long)paddr); } /* @@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) static inline phys_addr_t virt_to_phys(void * vaddr) { - return (phys_addr_t)(vaddr); + return (phys_addr_t)((unsigned long)vaddr); } /* diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index cfc7834ed9..71b31085b4 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -17,6 +17,7 @@ #define PGTABLE_SIZE (0x10000) /* 2MB granularity */ #define MMU_SECTION_SHIFT 21 +#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) #ifndef __ASSEMBLY__ @@ -278,11 +279,6 @@ enum { */ void mmu_page_table_flush(unsigned long start, unsigned long stop); -#ifdef CONFIG_SYS_NONCACHED_MEMORY -void noncached_init(void); -phys_addr_t noncached_alloc(size_t size, size_t align); -#endif /* CONFIG_SYS_NONCACHED_MEMORY */ - #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) @@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align); void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); +#ifdef CONFIG_SYS_NONCACHED_MEMORY +void noncached_init(void); +phys_addr_t noncached_alloc(size_t size, size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ + #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index ee77c4179f..388058e04c 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -45,12 +45,16 @@ typedef unsigned long long u64; #define BITS_PER_LONG 32 #endif /* CONFIG_ARM64 */ -/* Dma addresses are 32-bits wide. */ - +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long dma_addr_t; +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +/* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; - typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; +#endif #endif /* __KERNEL__ */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 2bdfaba5b7..f3db7b58cb 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL) += debug.o ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) extra-y += eabi_compat.o endif + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +# for C files, just apend -marm, which will override previous -mthumb* + +CFLAGS_cache.o := -marm +CFLAGS_cache-cp15.o := -marm + +# For .S, drop -mthumb* and other thumb-related options. +# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_* +# was implemented and is used here. +# Also, define ${target}_NO_THUMB_BUILD for these two targets +# so that the code knows it should not use Thumb. + +AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork +AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork +AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD +AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD + +endif +endif diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index cd13db3440..3bd87105c5 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align) return next; } #endif /* CONFIG_SYS_NONCACHED_MEMORY */ + +#if defined(CONFIG_SYS_THUMB_BUILD) +void invalidate_l2_cache(void) +{ + unsigned int val = 0; + + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); + isb(); +} +#endif diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index eeaf003529..7d9fc0f9be 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -13,7 +13,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) #define W(instr) instr.w #else #define W(instr) instr @@ -62,7 +62,7 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ .syntax unified -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 7208f20dda..df053a31d5 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -16,7 +16,7 @@ .align 5 .syntax unified -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index c3e964eabc..e32ad90945 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) register long result asm("r0"); #if defined(CONFIG_ARM64) asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); +#elif defined(CONFIG_CPU_V7M) + asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr)); #else /* Note - untested placeholder */ asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); @@ -90,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len) size_t len; } read; - debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len); + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); read.fd = fd; read.memp = memp; @@ -104,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len) * hard to maintain partial read loops and such, just fail * with an error message. */ - printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n", + printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n", __func__, ret, fd, len, memp); return -1; } diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 313eb47894..30f2b49b69 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o ifneq ($(CONFIG_SPL_BUILD),) obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 0bf453eff5..41dbf16afd 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -5,11 +5,13 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com> + * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <asm/errno.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> @@ -173,3 +175,96 @@ void at91_periph_clk_disable(int id) writel(regval, &pmc->pcr); } + +int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval, status; + u32 timeout = 1000; + + if (id > AT91_PMC_PCR_PID_MASK) + return -EINVAL; + + if (div > 0xff) + return -EINVAL; + + writel(id, &pmc->pcr); + regval = readl(&pmc->pcr); + regval &= ~AT91_PMC_PCR_GCKCSS; + regval &= ~AT91_PMC_PCR_GCKDIV; + + switch (clk_source) { + case GCK_CSS_SLOW_CLK: + regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK; + break; + case GCK_CSS_MAIN_CLK: + regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK; + break; + case GCK_CSS_PLLA_CLK: + regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK; + break; + case GCK_CSS_UPLL_CLK: + regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK; + break; + case GCK_CSS_MCK_CLK: + regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK; + break; + case GCK_CSS_AUDIO_CLK: + regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK; + break; + default: + printf("Error GCK clock source selection!\n"); + return -EINVAL; + } + + regval |= AT91_PMC_PCR_CMD_WRITE | + AT91_PMC_PCR_GCKDIV_(div) | + AT91_PMC_PCR_GCKEN; + + writel(regval, &pmc->pcr); + + do { + udelay(1); + status = readl(&pmc->sr); + } while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY))); + + if (!timeout) + printf("Timeout waiting for GCK ready!\n"); + + return 0; +} + +u32 at91_get_periph_generated_clk(u32 id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval, clk_source, div; + u32 freq; + + if (id > AT91_PMC_PCR_PID_MASK) + return 0; + + writel(id, &pmc->pcr); + regval = readl(&pmc->pcr); + + clk_source = regval & AT91_PMC_PCR_GCKCSS; + switch (clk_source) { + case AT91_PMC_PCR_GCKCSS_SLOW_CLK: + freq = CONFIG_SYS_AT91_SLOW_CLOCK; + break; + case AT91_PMC_PCR_GCKCSS_MAIN_CLK: + freq = gd->arch.main_clk_rate_hz; + break; + case AT91_PMC_PCR_GCKCSS_PLLA_CLK: + freq = gd->arch.plla_rate_hz; + break; + default: + printf("Improper GCK clock source selection!\n"); + freq = 0; + break; + } + + div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET); + div += 1; + + return freq / div; +} diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 8d86f97e3d..7843aed813 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -12,7 +12,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/at91_dbu.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_gpbr.h> @@ -65,12 +64,14 @@ void enable_caches(void) dcache_enable(); } +#define ATMEL_CHIPID_CIDR_VERSION 0x1f + unsigned int get_chip_id(void) { - return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK; + return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION; } unsigned int get_extension_chip_id(void) { - return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID); + return readl(ATMEL_CHIPID_EXID); } diff --git a/arch/arm/mach-at91/include/mach/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h index 7346fc0569..3181138322 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbu.h @@ -35,8 +35,4 @@ typedef struct at91_dbu { #define AT91_DBU_CID_ARCH_9xx 0x01900000 #define AT91_DBU_CID_ARCH_9XExx 0x02900000 -#define AT91_DBU_CIDR_MASK 0x1f -#define AT91_DBU_CIDR 0x40 -#define AT91_DBU_EXID 0x44 - #endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 8a3fb942f7..5a51be6288 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -153,8 +153,20 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_MOSCSELS 0x00010000 #define AT91_PMC_PCR_PID_MASK (0x3f) +#define AT91_PMC_PCR_GCKCSS (0x7 << 8) +#define AT91_PMC_PCR_GCKCSS_SLOW_CLK (0x0 << 8) +#define AT91_PMC_PCR_GCKCSS_MAIN_CLK (0x1 << 8) +#define AT91_PMC_PCR_GCKCSS_PLLA_CLK (0x2 << 8) +#define AT91_PMC_PCR_GCKCSS_UPLL_CLK (0x3 << 8) +#define AT91_PMC_PCR_GCKCSS_MCK_CLK (0x4 << 8) +#define AT91_PMC_PCR_GCKCSS_AUDIO_CLK (0x5 << 8) #define AT91_PMC_PCR_CMD_WRITE (0x1 << 12) +#define AT91_PMC_PCR_DIV (0x3 << 16) +#define AT91_PMC_PCR_GCKDIV (0xff << 20) +#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20) +#define AT91_PMC_PCR_GCKDIV_OFFSET 20 #define AT91_PMC_PCR_EN (0x1 << 28) +#define AT91_PMC_PCR_GCKEN (0x1 << 29) #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ @@ -236,6 +248,7 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_GCKRDY (1 << 24) #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ #endif diff --git a/arch/arm/mach-at91/include/mach/atmel_sdhci.h b/arch/arm/mach-at91/include/mach/atmel_sdhci.h new file mode 100644 index 0000000000..9652bc20c8 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/atmel_sdhci.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_SDHCI_H +#define __ATMEL_SDHCI_H + +int atmel_sdhci_init(void *regbase, u32 id); + +#endif diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index 1d45e2dc11..ad839275ec 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -13,6 +13,13 @@ #include <asm/arch/at91_pmc.h> #include <asm/global_data.h> +#define GCK_CSS_SLOW_CLK 0 +#define GCK_CSS_MAIN_CLK 1 +#define GCK_CSS_PLLA_CLK 2 +#define GCK_CSS_UPLL_CLK 3 +#define GCK_CSS_MCK_CLK 4 +#define GCK_CSS_AUDIO_CLK 5 + static inline unsigned long get_cpu_clk_rate(void) { DECLARE_GLOBAL_DATA_PTR; @@ -119,4 +126,7 @@ static inline unsigned long get_pit_clk_rate(void) int at91_clock_init(unsigned long main_clock); void at91_periph_clk_enable(int id); void at91_periph_clk_disable(int id); +int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div); +u32 at91_get_periph_generated_clk(u32 id); + #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index b749cb3359..33f6c97c11 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -158,6 +158,9 @@ #define ATMEL_BASE_RTC 0xfffffeb0 /* Reserved: 0xfffffee0 - 0xffffffff */ +#define ATMEL_CHIPID_CIDR 0xffffee40 +#define ATMEL_CHIPID_EXID 0xffffee44 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index 7773ace439..3da8aff27e 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -144,6 +144,9 @@ #define ATMEL_BASE_PIOE 0xfc06d000 #define ATMEL_BASE_AIC 0xfc06e000 +#define ATMEL_CHIPID_CIDR 0xfc069040 +#define ATMEL_CHIPID_EXID 0xfc069044 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 8ac53353e6..b2fb51d0ac 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -98,9 +98,4 @@ void board_init_f(ulong dummy) preloader_console_init(); mem_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - board_init_r(NULL, 0); } diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 18eadf545f..3d31f9d524 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -159,8 +159,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420() - || proid_is_exynos5800()) + else if (proid_is_exynos5250() || proid_is_exynos5420() || + proid_is_exynos5422()) div = PLL_DIV_65536; else return 0; @@ -346,7 +346,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral) int i; struct clk_bit_info *info; - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) info = exynos542x_bit_info; else info = exynos5_bit_info; @@ -558,7 +558,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral) unsigned long clock_get_periph_rate(int peripheral) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos542x_get_periph_rate(peripheral); return exynos5_get_periph_rate(peripheral); } else { @@ -1576,7 +1576,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else if (cpu_is_exynos4()) { @@ -1692,7 +1692,7 @@ void set_mmc_clk(int dev_index, unsigned int div) div -= 1; if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1708,7 +1708,7 @@ unsigned long get_lcd_clk(void) } else if (cpu_is_exynos5()) { if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); - else if (proid_is_exynos5800()) + else if (proid_is_exynos5422()) return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); @@ -1740,7 +1740,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c index 0200fd154f..1b7498d9d5 100644 --- a/arch/arm/mach-exynos/clock_init_exynos5.c +++ b/arch/arm/mach-exynos/clock_init_exynos5.c @@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void) void system_clock_init(void) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) exynos5420_system_clock_init(); else exynos5250_system_clock_init(); diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index 67aac2d575..2829fb269e 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -78,7 +78,7 @@ static inline void configure_l2_ctlr(void) CACHE_TAG_RAM_LATENCY_2_CYCLES | CACHE_DATA_RAM_LATENCY_2_CYCLES; - if (proid_is_exynos5420() || proid_is_exynos5800()) { + if (proid_is_exynos5420() || proid_is_exynos5422()) { val |= CACHE_ECC_AND_PARITY | CACHE_TAG_RAM_LATENCY_3_CYCLES | CACHE_DATA_RAM_LATENCY_3_CYCLES; @@ -97,7 +97,7 @@ static inline void configure_l2_actlr(void) { uint32_t val; - if (proid_is_exynos5420() || proid_is_exynos5800()) { + if (proid_is_exynos5420() || proid_is_exynos5422()) { mrc_l2_aux_ctlr(val); val |= CACHE_ENABLE_FORCE_L2_LOGIC | CACHE_DISABLE_CLEAN_EVICT; diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index 7c0b12ae51..25a9df9364 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -20,8 +20,8 @@ #define TIMEOUT_US 10000 #define NUM_BYTE_LANES 4 #define DEFAULT_DQS 8 -#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ - || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) +#define DEFAULT_DQS_X4 ((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)) #ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) @@ -856,10 +856,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) */ val = readl(&drex0->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex0->concontrol); + writel(val, &drex0->concontrol); val = readl(&drex1->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex1->concontrol); + writel(val, &drex1->concontrol); return 0; } diff --git a/arch/arm/mach-exynos/include/mach/adc.h b/arch/arm/mach-exynos/include/mach/adc.h index a0e26d7052..9af51ab381 100644 --- a/arch/arm/mach-exynos/include/mach/adc.h +++ b/arch/arm/mach-exynos/include/mach/adc.h @@ -9,6 +9,39 @@ #ifndef __ASM_ARM_ARCH_ADC_H_ #define __ASM_ARM_ARCH_ADC_H_ +#define ADC_V2_CON1_SOFT_RESET (0x2 << 1) +#define ADC_V2_CON1_STC_EN 0x1 + +#define ADC_V2_CON2_OSEL(x) (((x) & 0x1) << 10) +#define OSEL_2S 0x0 +#define OSEL_BINARY 0x1 +#define ADC_V2_CON2_ESEL(x) (((x) & 0x1) << 9) +#define ESEL_ADC_EVAL_TIME_40CLK 0x0 +#define ESEL_ADC_EVAL_TIME_20CLK 0x1 +#define ADC_V2_CON2_HIGHF(x) (((x) & 0x1) << 8) +#define HIGHF_CONV_RATE_30KSPS 0x0 +#define HIGHF_CONV_RATE_600KSPS 0x1 +#define ADC_V2_CON2_C_TIME(x) (((x) & 0x7) << 4) +#define ADC_V2_CON2_CHAN_SEL_MASK 0xf +#define ADC_V2_CON2_CHAN_SEL(x) ((x) & ADC_V2_CON2_CHAN_SEL_MASK) + +#define ADC_V2_GET_STATUS_FLAG(x) (((x) >> 2) & 0x1) +#define FLAG_CONV_END 0x1 + +#define ADC_V2_INT_DISABLE 0x0 +#define ADC_V2_INT_ENABLE 0x1 +#define INT_NOT_GENERATED 0x0 +#define INT_GENERATED 0x1 + +#define ADC_V2_VERSION 0x80000008 + +#define ADC_V2_MAX_CHANNEL 9 + +/* For default 8 time convertion with sample rate 600 kSPS - 15us timeout */ +#define ADC_V2_CONV_TIMEOUT_US 15 + +#define ADC_V2_DAT_MASK 0xfff + #ifndef __ASSEMBLY__ struct s5p_adc { unsigned int adccon; @@ -21,6 +54,17 @@ struct s5p_adc { unsigned int adcmux; unsigned int adcclrintpndnup; }; + +struct exynos_adc_v2 { + unsigned int con1; + unsigned int con2; + unsigned int status; + unsigned int dat; + unsigned int int_en; + unsigned int int_status; + unsigned int reserved[2]; + unsigned int version; +}; #endif #endif /* __ASM_ARM_ARCH_ADC_H_ */ diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index cb3d2cc06f..14a1692467 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -237,7 +237,7 @@ static inline void s5p_set_cpu_id(void) * Exynos5800 is a variant of Exynos5420 * and has product id 0x5422 */ - s5p_cpu_id = 0x5800; + s5p_cpu_id = 0x5422; break; } } @@ -267,7 +267,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) IS_EXYNOS_TYPE(exynos5420, 0x5420) -IS_EXYNOS_TYPE(exynos5800, 0x5800) +IS_EXYNOS_TYPE(exynos5422, 0x5422) #define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -278,7 +278,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420() || proid_is_exynos5800()) \ + if (proid_is_exynos5420() || proid_is_exynos5422()) \ return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h index 9699954a7d..7fc8e61f9c 100644 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ b/arch/arm/mach-exynos/include/mach/gpio.h @@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos5420_gpio_data; else return exynos5_gpio_data; @@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return EXYNOS5420_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 179b29449e..12eb79cb0c 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -737,10 +737,10 @@ static int exynos4x12_mmc_config(int peripheral, int flags) return -1; } for (i = start; i < (start + 7); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); if (i == (start + 2)) continue; gpio_cfg_pin(i, func); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); gpio_set_drv(i, S5P_GPIO_DRV_4X); } if (flags & PINMUX_FLAG_8BIT_MODE) { @@ -858,7 +858,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos5420_pinmux_config(peripheral, flags); else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index 1b12051656..cd2d6618ac 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -125,7 +125,7 @@ static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable) void set_usbdrd_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) exynos5420_set_usbdev_phy_ctrl(enable); else exynos5_set_usbdrd_phy_ctrl(enable); diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index aab5d19b5f..f7737bfb22 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -4,6 +4,9 @@ choice prompt "Marvell Kirkwood board select" optional +config TARGET_OPENRD + bool "Marvell OpenRD Board" + config TARGET_DREAMPLUG bool "DreamPlug Board" @@ -51,6 +54,7 @@ endchoice config SYS_SOC default "kirkwood" +source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index df4756e4bd..5abcf70b28 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -9,3 +9,9 @@ obj-y = cpu.o obj-y += cache.o obj-y += mpp.o + +# cpu.o and cache.o contain CP15 instructions which cannot be run in +# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD + +CFLAGS_cpu.o := -marm +CFLAGS_cache.o := -marm diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 771cce6fa3..346278e1be 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -52,7 +52,7 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#include <linux/compat.h> +#include <linux/log2.h> #include <linux/mbus.h> /* DDR target is the same on all platforms */ diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 546ebcb52e..33dcad40f2 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -16,3 +16,13 @@ obj-y += timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_cpu.o := -marm + +endif +endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 8e59578f37..666a2ef8df 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -69,9 +69,9 @@ struct socfpga_reset_manager { #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5) -#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22) -#define RSTMGR_DMA RSTMGR_DEFINE(0, 28) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) /* Create a human-readable reference to SoCFPGA reset. */ diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 75924ad848..98431a91f8 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o obj-$(CONFIG_PWM_TEGRA) += pwm.o endif +obj-$(CONFIG_ARM64) += arm64-mmu.o obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c new file mode 100644 index 0000000000..c2276523cb --- /dev/null +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/system.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000UL +#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) +#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) + +#define TCR_TG1_4K (1 << 31) +#define TCR_EPD1_DISABLE (1 << 23) +#define TEGRA_VA_BITS 40 +#define TEGRA_TCR TCR_TG1_4K | \ + TCR_EPD1_DISABLE | \ + TCR_SHARED_OUTER | \ + TCR_SHARED_INNER | \ + TCR_IRGN_WBWA | \ + TCR_ORGN_WBWA | \ + TCR_T0SZ(TEGRA_VA_BITS) + +#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ + PMD_ATTRINDX(MT_NORMAL) | \ + PMD_TYPE_SECT +#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ + PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \ + PMD_TYPE_SECT + +/* 4K size is required to place 512 entries in each level */ +#define TLB_TABLE_SIZE 0x1000 + +/* + * This mmu table looks as below + * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 + * and other Level1 Table1. + * Level1 Table0 contains entries for each 1GB from 0 to 511GB. + * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. + * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains + * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. + */ +void mmu_setup(void) +{ + int el; + u64 i, section_l1t0, section_l1t1; + u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); + u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); + u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); + u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); + u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); + u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); + + /* Invalidate all table entries */ + memset(level0_table, 0, PGTABLE_SIZE); + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0, covering 0 to 512GB + * set level 1 table 1, covering 512GB to 1TB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + + for (i = 0; i < 512; i++) { + level1_table_0[i] = section_l1t0; + if (i >= 4) + level1_table_0[i] |= MEMORY_ATTR; + level1_table_1[i] = section_l1t1; + level1_table_1[i] |= MEMORY_ATTR; + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + } + + level1_table_0[0] = + (u64)level2_table_0 | PMD_TYPE_TABLE; + level1_table_0[1] = + (u64)level2_table_1 | PMD_TYPE_TABLE; + level1_table_0[2] = + (u64)level2_table_2 | PMD_TYPE_TABLE; + level1_table_0[3] = + (u64)level2_table_3 | PMD_TYPE_TABLE; + + section_l2t0 = 0; + section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ + section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ + section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ + + for (i = 0; i < 512; i++) { + level2_table_0[i] = section_l2t0 | DEVICE_ATTR; + level2_table_1[i] = section_l2t1 | DEVICE_ATTR; + level2_table_2[i] = section_l2t2 | MEMORY_ATTR; + level2_table_3[i] = section_l2t3 | MEMORY_ATTR; + section_l2t0 += BLOCK_SIZE_L2; + section_l2t1 += BLOCK_SIZE_L2; + section_l2t2 += BLOCK_SIZE_L2; + section_l2t3 += BLOCK_SIZE_L2; + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TEGRA_TCR, MEMORY_ATTRIBUTES); + + set_sctlr(get_sctlr() | CR_M); +} + +u64 *arch_get_page_table(void) +{ + return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); +} diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index 7489f5f146..ea7f7b717a 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -1,17 +1,7 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. +# SPDX-License-Identifier: GPL-2.0 # obj-$(CONFIG_SPL_BUILD) += cpu.o diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index bc250deba8..d3d3b6e7c4 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -1,17 +1,7 @@ # # Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. +# SPDX-License-Identifier: GPL-2.0 # obj-$(CONFIG_SPL_BUILD) += cpu.o diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 22ab798b96..9e6ac3a0ff 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -3,12 +3,8 @@ if ARCH_UNIPHIER config SYS_CONFIG_NAME default "uniphier" -config UNIPHIER_SMP - bool - config ARCH_UNIPHIER_PH1_SLD3 bool "UniPhier PH1-sLD3 SoC" - select UNIPHIER_SMP help This enables support for UniPhier PH1-sLD3 SoC. @@ -20,7 +16,6 @@ config ARCH_UNIPHIER_PH1_LD4 config ARCH_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 @@ -35,7 +30,6 @@ config ARCH_UNIPHIER_PH1_SLD8 config ARCH_UNIPHIER_PH1_PRO5 bool "UniPhier PH1-Pro5 SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 @@ -44,7 +38,6 @@ config ARCH_UNIPHIER_PH1_PRO5 config ARCH_UNIPHIER_PROXSTREAM2 bool "UniPhier ProXstream2 SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 @@ -53,7 +46,6 @@ config ARCH_UNIPHIER_PROXSTREAM2 config ARCH_UNIPHIER_PH1_LD6B bool "UniPhier PH1-LD6b SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile index 5b95bdad95..b8b0323cd2 100644 --- a/arch/arm/mach-uniphier/bcu/Makefile +++ b/arch/arm/mach-uniphier/bcu/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 30c8874905..0797d6e615 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += boot-mode.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 4f397b986b..bc0f27c398 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile index e2d109df57..d0f4bd3519 100644 --- a/arch/arm/mach-uniphier/ddrphy/Makefile +++ b/arch/arm/mach-uniphier/ddrphy/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile index 393ea96f90..3e1e1b2bc8 100644 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile index e497d28f79..3be71fbf07 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/Makefile +++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile @@ -1 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile index 98833b55de..ef80953623 100644 --- a/arch/arm/mach-uniphier/init/Makefile +++ b/arch/arm/mach-uniphier/init/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += init.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 66cad42dde..5936045e86 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -44,59 +44,6 @@ ENTRY(lowlevel_init) bl enable_mmu -#ifdef CONFIG_UNIPHIER_SMP -secondary_startup: - /* - * Entry point for secondary CPUs - * - * The Boot ROM has already enabled MMU for the secondary CPUs as well - * as for the primary one. The MMU table embedded in the Boot ROM - * prohibits the DRAM access, so it is impossible to bring the - * secondary CPUs into DRAM directly. They must jump here into SPL, - * which is run on L2 cache. - * - * Boot Sequence - * [primary CPU] [secondary CPUs] - * start from Boot ROM start from Boot ROM - * jump to SPL sleep in Boot ROM - * kick secondaries ---(sev)---> jump to SPL - * jump to U-Boot main sleep in SPL - * jump to Linux - * kick secondaries ---(sev)---> jump to Linux - */ - - /* branch by CPU ID */ - mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register) - and r0, r0, #0x3 - cmp r0, #0x0 - beq primary_cpu - /* only for secondary CPUs */ - ldr r1, =ROM_BOOT_ROMRSV2 @ The last data access to L2 cache - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) - orr r0, r0, #CR_I @ Enable ICache - bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache must be disabled - mcr p15, 0, r0, c1, c0, 0 @ before jumping to Linux - mov r0, #0 - str r0, [r1] - b 1f - /* - * L2 cache is shared among all the CPUs and it might be disabled by - * the primary one. Before that, the following 5 lines must be cached - * on the Icaches of the secondary CPUs. - */ -0: wfe @ kicked by Linux -1: ldr r0, [r1] - cmp r0, #0 - bxne r0 @ r0: Linux entry for secondary CPUs - b 0b -primary_cpu: - ldr r1, =ROM_BOOT_ROMRSV2 - ldr r0, =secondary_startup - str r0, [r1] - ldr r0, [r1] @ make sure str is complete before sev - sev @ kick the secondary CPU -#endif - bl setup_init_ram @ RAM area for temporary stack pointer mov lr, r8 @ restore link diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile index 42057a2077..a152f61266 100644 --- a/arch/arm/mach-uniphier/memconf/Makefile +++ b/arch/arm/mach-uniphier/memconf/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += memconf.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += memconf-proxstream2.o diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile index 85175955d3..80a9cdaa80 100644 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile index d33f99e446..ca88521a1d 100644 --- a/arch/arm/mach-uniphier/pll/Makefile +++ b/arch/arm/mach-uniphier/pll/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \ pll-spectrum-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \ diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index db622d2034..57eb44b646 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile index dd35e77dab..89b2dec118 100644 --- a/arch/arm/mach-uniphier/umc/Makefile +++ b/arch/arm/mach-uniphier/umc/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 7a1aec45e7..afe6cc3edd 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -21,13 +21,6 @@ config TARGET_ZYNQ_MICROZED config TARGET_ZYNQ_PICOZED bool "Zynq PicoZed" -config TARGET_ZYNQ_ZC70X - bool "Zynq ZC702/ZC706 Board (deprecated)" - select ZYNQ_CUSTOM_INIT - help - This option is deprecated. Use TARGET_ZYNQ_ZC702 - or TARGET_ZYNQ_706. - config TARGET_ZYNQ_ZC702 bool "Zynq ZC702 Board" @@ -57,8 +50,7 @@ config SYS_CONFIG_NAME default "zynq_zed" if TARGET_ZYNQ_ZED default "zynq_microzed" if TARGET_ZYNQ_MICROZED default "zynq_picozed" if TARGET_ZYNQ_PICOZED - default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 \ - || TARGET_ZYNQ_ZC70X + default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 default "zynq_zc770" if TARGET_ZYNQ_ZC770 default "zynq_zybo" if TARGET_ZYNQ_ZYBO diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 7bdac3b12d..723019d252 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -4,11 +4,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <debug_uart.h> #include <spl.h> #include <asm/io.h> -#include <asm/arch/hardware.h> #include <asm/spl.h> +#include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -17,11 +18,12 @@ void board_init_f(ulong dummy) { ps7_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - arch_cpu_init(); - board_init_r(NULL, 0); + /* + * The debug UART can be used from this point: + * debug_uart_init(); + * printch('x'); + */ } #ifdef CONFIG_SPL_BOARD_INIT diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds index 0f2f756f83..ecdf6a031e 100644 --- a/arch/arm/mach-zynq/u-boot-spl.lds +++ b/arch/arm/mach-zynq/u-boot-spl.lds @@ -38,10 +38,18 @@ SECTIONS } > .sram . = ALIGN(4); +#ifdef CONFIG_SPL_DM + .u_boot_list : { + KEEP(*(SORT(.u_boot_list_*_driver_*))); + KEEP(*(SORT(.u_boot_list_*_uclass_*))); + } > .sram + + . = ALIGN(4); +#endif . = .; - __image_copy_end = .; + _image_binary_end = .; _end = .; diff --git a/arch/arm/thumb1/include/asm/proc-armv/system.h b/arch/arm/thumb1/include/asm/proc-armv/system.h new file mode 100644 index 0000000000..7dfbf3d33d --- /dev/null +++ b/arch/arm/thumb1/include/asm/proc-armv/system.h @@ -0,0 +1,69 @@ +/* + * Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h + * + * (C) Copyright 2015 + * Albert ARIBAUD <albert.u.boot@aribaud.net> + * + * The original file does not build in Thumb mode. However, in U-Boot + * we don't use interrupt context, so we can redefine these as empty + * memory barriers, which makes Thumb-1 compiler happy. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Use the same macro name as linux/include/asm-arm/proc-armv/system.h + * here, so that if the original ever gets included after us, it won't + * try to re-redefine anything. + */ + +#ifndef __ASM_PROC_SYSTEM_H +#define __ASM_PROC_SYSTEM_H + +/* + * Redefine all original macros with static inline functions containing + * a simple memory barrier, so that they produce the same instruction + * ordering constraints as their original counterparts. + * We use static inline functions rather than macros so that we can tell + * the compiler to not complain about unused arguments. + */ + +static inline void local_irq_save( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_enable(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_disable(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void __stf(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void __clf(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_save_flags( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_restore( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +#endif /* __ASM_PROC_SYSTEM_H */ diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h index 0ec678487d..0d425c20f9 100644 --- a/arch/avr32/include/asm/bitops.h +++ b/arch/avr32/include/asm/bitops.h @@ -6,4 +6,9 @@ #ifndef __ASM_AVR32_BITOPS_H #define __ASM_AVR32_BITOPS_H +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + #endif /* __ASM_AVR32_BITOPS_H */ diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index cfbcd3124f..7cd0bbf24e 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# Licensed under the GPL-2 or later. +# SPDX-License-Identifier: GPL-2.0+ # extra-y := init.elf diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index b0abeda90a..29e7a441bc 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -183,7 +183,7 @@ int drv_jtag_console_init(void) memset(&dev, 0x00, sizeof(dev)); strcpy(dev.name, "jtag"); - dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; dev.putc = jtag_putc; dev.puts = jtag_puts; dev.tstc = jtag_tstc; diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index cd7e356459..6cde6dbfde 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -15,6 +15,10 @@ #include <asm/byteorder.h> #include <asm/system.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> #ifdef __KERNEL__ /* diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h index 97401a7ce2..f146efd6e7 100644 --- a/arch/blackfin/include/asm/delay.h +++ b/arch/blackfin/include/asm/delay.h @@ -16,7 +16,7 @@ * Delay routines, using a pre-computed "loops_per_second" value. */ -extern __inline__ void __delay(unsigned long loops) +static __inline__ void __delay(unsigned long loops) { __asm__ __volatile__("1:\t%0 += -1;\n\t" "cc = %0 == 0;\n\t" @@ -31,7 +31,7 @@ extern __inline__ void __delay(unsigned long loops) * first constant multiplications gets optimized away if the delay is * a constant) */ -extern __inline__ void __udelay(unsigned long usecs) +static __inline__ void __udelay(unsigned long usecs) { __delay(usecs); } diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index f9c434b4a3..4a3f6b97ad 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -6,25 +6,28 @@ #define _M68K_BITOPS_H #include <asm/byteorder.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> extern void set_bit(int nr, volatile void *addr); extern void clear_bit(int nr, volatile void *addr); extern void change_bit(int nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void *addr); extern int test_and_clear_bit(int nr, volatile void *addr); extern int test_and_change_bit(int nr, volatile void *addr); #ifdef __KERNEL__ -extern inline int test_bit(int nr, __const__ volatile void *addr) +static inline int test_bit(int nr, __const__ volatile void *addr) { __const__ unsigned int *p = (__const__ unsigned int *) addr; return (p[nr >> 5] & (1UL << (nr & 31))) != 0; } -extern inline int test_and_set_bit(int nr, volatile void *vaddr) +static inline int test_and_set_bit(int nr, volatile void *vaddr) { char retval; diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h index 908a99b7c8..7244b75820 100644 --- a/arch/m68k/include/asm/byteorder.h +++ b/arch/m68k/include/asm/byteorder.h @@ -22,25 +22,25 @@ (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ (((__u32)(x)) >> 24) )) -extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +static __inline__ unsigned ld_le16(const volatile unsigned short *addr) { unsigned result = *addr; return __sw16(result); } -extern __inline__ void st_le16(volatile unsigned short *addr, +static __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) { *addr = __sw16(val); } -extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +static __inline__ unsigned ld_le32(const volatile unsigned *addr) { unsigned result = *addr; return __sw32(result); } -extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +static __inline__ void st_le32(volatile unsigned *addr, const unsigned val) { *addr = __sw32(val); } diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index 2d2a51901b..384308b747 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -67,28 +67,28 @@ #define mb() __asm__ __volatile__ ("" : : : "memory") -extern inline void _insb(volatile u8 * port, void *buf, int ns) +static inline void _insb(volatile u8 * port, void *buf, int ns) { u8 *data = (u8 *) buf; while (ns--) *data++ = *port; } -extern inline void _outsb(volatile u8 * port, const void *buf, int ns) +static inline void _outsb(volatile u8 * port, const void *buf, int ns) { u8 *data = (u8 *) buf; while (ns--) *port = *data++; } -extern inline void _insw(volatile u16 * port, void *buf, int ns) +static inline void _insw(volatile u16 * port, void *buf, int ns) { u16 *data = (u16 *) buf; while (ns--) *data++ = __sw16(*port); } -extern inline void _outsw(volatile u16 * port, const void *buf, int ns) +static inline void _outsw(volatile u16 * port, const void *buf, int ns) { u16 *data = (u16 *) buf; while (ns--) { @@ -97,14 +97,14 @@ extern inline void _outsw(volatile u16 * port, const void *buf, int ns) } } -extern inline void _insl(volatile u32 * port, void *buf, int nl) +static inline void _insl(volatile u32 * port, void *buf, int nl) { u32 *data = (u32 *) buf; while (nl--) *data++ = __sw32(*port); } -extern inline void _outsl(volatile u32 * port, const void *buf, int nl) +static inline void _outsl(volatile u32 * port, const void *buf, int nl) { u32 *data = (u32 *) buf; while (nl--) { @@ -113,14 +113,14 @@ extern inline void _outsl(volatile u32 * port, const void *buf, int nl) } } -extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) +static inline void _insw_ns(volatile u16 * port, void *buf, int ns) { u16 *data = (u16 *) buf; while (ns--) *data++ = *port; } -extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) +static inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) { u16 *data = (u16 *) buf; while (ns--) { @@ -128,14 +128,14 @@ extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) } } -extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) +static inline void _insl_ns(volatile u32 * port, void *buf, int nl) { u32 *data = (u32 *) buf; while (nl--) *data++ = *port; } -extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) +static inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) { u32 *data = (u32 *) buf; while (nl--) { @@ -159,52 +159,52 @@ extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) /* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. */ -extern inline int in_8(volatile u8 * addr) +static inline int in_8(volatile u8 * addr) { return (int)*addr; } -extern inline void out_8(volatile u8 * addr, int val) +static inline void out_8(volatile u8 * addr, int val) { *addr = (u8) val; } -extern inline int in_le16(volatile u16 * addr) +static inline int in_le16(volatile u16 * addr) { return __sw16(*addr); } -extern inline int in_be16(volatile u16 * addr) +static inline int in_be16(volatile u16 * addr) { return (*addr & 0xFFFF); } -extern inline void out_le16(volatile u16 * addr, int val) +static inline void out_le16(volatile u16 * addr, int val) { *addr = __sw16(val); } -extern inline void out_be16(volatile u16 * addr, int val) +static inline void out_be16(volatile u16 * addr, int val) { *addr = (u16) val; } -extern inline unsigned in_le32(volatile u32 * addr) +static inline unsigned in_le32(volatile u32 * addr) { return __sw32(*addr); } -extern inline unsigned in_be32(volatile u32 * addr) +static inline unsigned in_be32(volatile u32 * addr) { return (*addr); } -extern inline void out_le32(volatile unsigned *addr, int val) +static inline void out_le32(volatile unsigned *addr, int val) { *addr = __sw32(val); } -extern inline void out_be32(volatile unsigned *addr, int val) +static inline void out_be32(volatile unsigned *addr, int val) { *addr = val; } diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 6d4a11f62f..5e70d9e110 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-y += microblaze-generic.dtb targets += $(dtb-y) diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h index 0ac78d76f9..d24f2cf9d3 100644 --- a/arch/microblaze/include/asm/bitops.h +++ b/arch/microblaze/include/asm/bitops.h @@ -7,6 +7,10 @@ #include <asm/byteorder.h> /* swab32 */ #include <asm/system.h> /* save_flags */ +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> #ifdef __KERNEL__ /* diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index b5c2a6367d..c31ff6efb4 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -17,6 +17,11 @@ #include <asm/sgidefs.h> #include <asm/system.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + /* * clear_bit() doesn't provide any barrier for the compiler. */ diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 9c647aa428..eed159cd46 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -15,24 +15,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#if defined(CONFIG_MALTA) -#define mips_boot_malta 1 -#else -#define mips_boot_malta 0 -#endif - -#if defined(CONFIG_MIPS_BOOT_CMDLINE_LEGACY) -#define mips_boot_cmdline_legacy 1 -#else -#define mips_boot_cmdline_legacy 0 -#endif - -#if defined(CONFIG_MIPS_BOOT_ENV_LEGACY) -#define mips_boot_env_legacy 1 -#else -#define mips_boot_env_legacy 0 -#endif - static int linux_argc; static char **linux_argv; static char *linux_argp; @@ -62,50 +44,6 @@ void arch_lmb_reserve(struct lmb *lmb) lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp); } -static int boot_setup_linux(bootm_headers_t *images) -{ - int ret; - ulong rd_len; - - rd_len = images->rd_end - images->rd_start; - ret = boot_ramdisk_high(&images->lmb, images->rd_start, - rd_len, &images->initrd_start, &images->initrd_end); - if (ret) - return ret; - -#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT) - if (images->ft_len) { - boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); - - ret = boot_relocate_fdt(&images->lmb, &images->ft_addr, - &images->ft_len); - if (ret) - return ret; - } -#endif - - return 0; -} - -static void boot_setup_fdt(bootm_headers_t *images) -{ -#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT) - u64 mem_start = 0; - u64 mem_size = gd->ram_size; - - debug("## setup FDT\n"); - - fdt_chosen(images->ft_addr); - fdt_fixup_memory_banks(images->ft_addr, &mem_start, &mem_size, 1); - fdt_fixup_ethernet(images->ft_addr); - fdt_initrd(images->ft_addr, images->initrd_start, images->initrd_end); - -#if defined(CONFIG_OF_BOARD_SETUP) - ft_board_setup(images->ft_addr, gd->bd); -#endif -#endif -} - static void linux_cmdline_init(void) { linux_argc = 1; @@ -197,18 +135,6 @@ static void linux_cmdline_append(bootm_headers_t *images) } } -static void boot_cmdline_linux(bootm_headers_t *images) -{ - if (mips_boot_cmdline_legacy && !images->ft_len) { - linux_cmdline_legacy(images); - - if (!mips_boot_env_legacy) - linux_cmdline_append(images); - - linux_cmdline_dump(); - } -} - static void linux_env_init(void) { linux_env = (char **)(((ulong) linux_argp + 15) & ~15); @@ -225,7 +151,7 @@ static void linux_env_set(const char *env_name, const char *env_val) strcpy(linux_env_p, env_name); linux_env_p += strlen(env_name); - if (mips_boot_malta) { + if (CONFIG_IS_ENABLED(MALTA)) { linux_env_p++; linux_env[++linux_env_idx] = linux_env_p; } else { @@ -246,14 +172,15 @@ static void linux_env_legacy(bootm_headers_t *images) const char *cp; ulong rd_start, rd_size; -#ifdef CONFIG_MEMSIZE_IN_BYTES - sprintf(env_buf, "%lu", (ulong)gd->ram_size); - debug("## Giving linux memsize in bytes, %lu\n", (ulong)gd->ram_size); -#else - sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20)); - debug("## Giving linux memsize in MB, %lu\n", - (ulong)(gd->ram_size >> 20)); -#endif /* CONFIG_MEMSIZE_IN_BYTES */ + if (CONFIG_IS_ENABLED(MEMSIZE_IN_BYTES)) { + sprintf(env_buf, "%lu", (ulong)gd->ram_size); + debug("## Giving linux memsize in bytes, %lu\n", + (ulong)gd->ram_size); + } else { + sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20)); + debug("## Giving linux memsize in MB, %lu\n", + (ulong)(gd->ram_size >> 20)); + } rd_start = UNCACHED_SDRAM(images->initrd_start); rd_size = images->initrd_end - images->initrd_start; @@ -282,19 +209,87 @@ static void linux_env_legacy(bootm_headers_t *images) if (cp) linux_env_set("eth1addr", cp); - if (mips_boot_malta) { + if (CONFIG_IS_ENABLED(MALTA)) { sprintf(env_buf, "%un8r", gd->baudrate); linux_env_set("modetty0", env_buf); } } +static int boot_reloc_ramdisk(bootm_headers_t *images) +{ + ulong rd_len = images->rd_end - images->rd_start; + + /* + * In case of legacy uImage's, relocation of ramdisk is already done + * by do_bootm_states() and should not repeated in 'bootm prep'. + */ + if (images->state & BOOTM_STATE_RAMDISK) { + debug("## Ramdisk already relocated\n"); + return 0; + } + + return boot_ramdisk_high(&images->lmb, images->rd_start, + rd_len, &images->initrd_start, &images->initrd_end); +} + +static int boot_reloc_fdt(bootm_headers_t *images) +{ + /* + * In case of legacy uImage's, relocation of FDT is already done + * by do_bootm_states() and should not repeated in 'bootm prep'. + */ + if (images->state & BOOTM_STATE_FDT) { + debug("## FDT already relocated\n"); + return 0; + } + +#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT) + boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); + return boot_relocate_fdt(&images->lmb, &images->ft_addr, + &images->ft_len); +#else + return 0; +#endif +} + +int arch_fixup_memory_node(void *blob) +{ +#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT) + u64 mem_start = 0; + u64 mem_size = gd->ram_size; + + return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1); +#else + return 0; +#endif +} + +static int boot_setup_fdt(bootm_headers_t *images) +{ + return image_setup_libfdt(images, images->ft_addr, images->ft_len, + &images->lmb); +} + static void boot_prep_linux(bootm_headers_t *images) { - if (mips_boot_env_legacy && !images->ft_len) - linux_env_legacy(images); + boot_reloc_ramdisk(images); - if (images->ft_len) + if (CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && images->ft_len) { + boot_reloc_fdt(images); boot_setup_fdt(images); + } else { + if (CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY)) + linux_env_legacy(images); + + if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) { + linux_cmdline_legacy(images); + + if (!CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY)) + linux_cmdline_append(images); + + linux_cmdline_dump(); + } + } } static void boot_jump_linux(bootm_headers_t *images) @@ -307,13 +302,13 @@ static void boot_jump_linux(bootm_headers_t *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); - if (mips_boot_malta) + if (CONFIG_IS_ENABLED(MALTA)) linux_extra = gd->ram_size; -#ifdef CONFIG_BOOTSTAGE_FDT +#if CONFIG_IS_ENABLED(BOOTSTAGE_FDT) bootstage_fdt_add_report(); #endif -#ifdef CONFIG_BOOTSTAGE_REPORT +#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT) bootstage_report(); #endif @@ -327,35 +322,28 @@ static void boot_jump_linux(bootm_headers_t *images) int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { - int ret; - /* No need for those on MIPS */ if (flag & BOOTM_STATE_OS_BD_T) return -1; - if (flag & BOOTM_STATE_OS_CMDLINE) { - boot_cmdline_linux(images); + /* + * Cmdline init has been moved to 'bootm prep' because it has to be + * done after relocation of ramdisk to always pass correct values + * for rd_start and rd_size to Linux kernel. + */ + if (flag & BOOTM_STATE_OS_CMDLINE) return 0; - } if (flag & BOOTM_STATE_OS_PREP) { boot_prep_linux(images); return 0; } - if (flag & BOOTM_STATE_OS_GO) { + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { boot_jump_linux(images); return 0; } - ret = boot_setup_linux(images); - if (ret) - return ret; - - boot_cmdline_linux(images); - boot_prep_linux(images); - boot_jump_linux(images); - /* does not return */ return 1; } diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h index f1aa9a356b..7ee37c37bc 100644 --- a/arch/nds32/include/asm/bitops.h +++ b/arch/nds32/include/asm/bitops.h @@ -21,6 +21,10 @@ #ifdef __KERNEL__ #include <asm/system.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> #define smp_mb__before_clear_bit() do { } while (0) #define smp_mb__after_clear_bit() do { } while (0) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index ff0fa20798..f6d5cd399a 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -117,7 +117,9 @@ static int altera_nios2_probe(struct udevice *dev) "altr,has-initda", 0); gd->arch.has_mmu = fdtdec_get_int(blob, node, "altr,has-mmu", 0); - gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000; + gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000; + gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000; + gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff; return 0; } diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 8758e7e847..54787c53ca 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -81,6 +81,7 @@ _cur: movhi r5, %hi(_cur - _start) mov r8, r4 movhi r5, %hi(_start) ori r5, r5, %lo(_start) /* r5 <- linked _start */ + mov sp, r5 /* initial stack below u-boot code */ beq r4, r5, 3f movhi r6, %hi(CONFIG_SYS_MONITOR_LEN) @@ -100,8 +101,6 @@ _cur: movhi r5, %hi(_cur - _start) _reloc: /* STACK INIT -- zero top two words for call back chain. */ - movhi sp, %hi(CONFIG_SYS_INIT_SP) - ori sp, sp, %lo(CONFIG_SYS_INIT_SP) addi sp, sp, -8 stw r0, 0(sp) stw r0, 4(sp) @@ -159,7 +158,7 @@ relocate_code: ori r6, r6, %lo(__bss_end) beq r5, r6, 5f -4: stwio r0, 0(r5) +4: stw r0, 0(r5) addi r5, r5, 4 bne r5, r6, 4b 5: diff --git a/arch/nios2/dts/10m50_devboard.dts b/arch/nios2/dts/10m50_devboard.dts new file mode 100644 index 0000000000..e89dbb2331 --- /dev/null +++ b/arch/nios2/dts/10m50_devboard.dts @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * This file is generated by sopc2dts. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + model = "Altera NiosII Max10"; + compatible = "altr,niosii-max10"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "altr,nios2-1.1"; + reg = <0x00000000>; + interrupt-controller; + #interrupt-cells = <1>; + altr,exception-addr = <0xc8000120>; + altr,fast-tlb-miss-addr = <0xc0000100>; + altr,has-div = <1>; + altr,has-initda = <1>; + altr,has-mmu = <1>; + altr,has-mul = <1>; + altr,implementation = "fast"; + altr,pid-num-bits = <8>; + altr,reset-addr = <0xd4000000>; + altr,tlb-num-entries = <256>; + altr,tlb-num-ways = <16>; + altr,tlb-ptr-sz = <8>; + clock-frequency = <75000000>; + dcache-line-size = <32>; + dcache-size = <32768>; + icache-line-size = <32>; + icache-size = <32768>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x08000000 0x08000000>, + <0x00000000 0x00000400>; + }; + + sopc0: sopc@0 { + device_type = "soc"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + compatible = "altr,avalon", "simple-bus"; + bus-frequency = <75000000>; + + jtag_uart: serial@18001530 { + compatible = "altr,juart-1.0"; + reg = <0x18001530 0x00000008>; + interrupt-parent = <&cpu>; + interrupts = <7>; + }; + + a_16550_uart_0: serial@18001600 { + compatible = "altr,16550-FIFO32", "ns16550a"; + reg = <0x18001600 0x00000200>; + interrupt-parent = <&cpu>; + interrupts = <1>; + auto-flow-control = <1>; + clock-frequency = <50000000>; + fifo-size = <32>; + reg-io-width = <4>; + reg-shift = <2>; + }; + + ext_flash: quadspi@0x180014a0 { + compatible = "altr,quadspi-1.0"; + reg = <0x180014a0 0x00000020>, + <0x14000000 0x04000000>; + reg-names = "avl_csr", "avl_mem"; + interrupt-parent = <&cpu>; + interrupts = <4>; + #address-cells = <1>; + #size-cells = <0>; + flash0: nor0@0 { + compatible = "micron,n25q512a"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + sysid: sysid@18001528 { + compatible = "altr,sysid-1.0"; + reg = <0x18001528 0x00000008>; + }; + + rgmii_0_eth_tse_0: ethernet@400 { + compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0"; + reg = <0x00000400 0x00000400>, + <0x00000820 0x00000020>, + <0x00000800 0x00000020>, + <0x000008c0 0x00000008>, + <0x00000840 0x00000020>, + <0x00000860 0x00000020>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", + "tx_csr", "tx_desc"; + interrupt-parent = <&cpu>; + interrupts = <2 3>; + interrupt-names = "rx_irq", "tx_irq"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + address-bits = <48>; + max-frame-size = <1518>; + local-mac-address = [00 00 00 00 00 00]; + altr,has-supplementary-unicast; + altr,enable-sup-addr = <1>; + altr,has-hash-multicast-filter; + altr,enable-hash = <1>; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + rgmii_0_eth_tse_0_mdio: mdio { + compatible = "altr,tse-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; + }; + }; + + enet_pll: clock@0 { + compatible = "altr,pll-1.0"; + #clock-cells = <1>; + + enet_pll_c0: enet_pll_c0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "enet_pll-c0"; + }; + + enet_pll_c1: enet_pll_c1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "enet_pll-c1"; + }; + + enet_pll_c2: enet_pll_c2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000>; + clock-output-names = "enet_pll-c2"; + }; + }; + + sys_pll: clock@1 { + compatible = "altr,pll-1.0"; + #clock-cells = <1>; + + sys_pll_c0: sys_pll_c0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sys_pll-c0"; + }; + + sys_pll_c1: sys_pll_c1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sys_pll-c1"; + }; + + sys_pll_c2: sys_pll_c2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <75000000>; + clock-output-names = "sys_pll-c2"; + }; + }; + + sys_clk_timer: timer@18001440 { + compatible = "altr,timer-1.0"; + reg = <0x18001440 0x00000020>; + interrupt-parent = <&cpu>; + interrupts = <0>; + clock-frequency = <75000000>; + }; + + led_pio: gpio@180014d0 { + compatible = "altr,pio-1.0"; + reg = <0x180014d0 0x00000010>; + altr,gpio-bank-width = <4>; + resetvalue = <15>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "led"; + }; + + uart_0: serial@0x18001420 { + compatible = "altr,uart-1.0"; + reg = <0x18001420 0x00000020>; + interrupt-parent = <&cpu>; + interrupts = <1>; + clock-frequency = <75000000>; + current-speed = <115200>; + }; + + button_pio: gpio@180014c0 { + compatible = "altr,pio-1.0"; + reg = <0x180014c0 0x00000010>; + interrupt-parent = <&cpu>; + interrupts = <6>; + altr,gpio-bank-width = <3>; + altr,interrupt-type = <2>; + edge_type = <1>; + level_trigger = <0>; + resetvalue = <0>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "button"; + }; + + sys_clk_timer_1: timer@880 { + compatible = "altr,timer-1.0"; + reg = <0x00000880 0x00000020>; + interrupt-parent = <&cpu>; + interrupts = <5>; + clock-frequency = <75000000>; + }; + + fpga_leds: leds { + compatible = "gpio-leds"; + + led_fpga0: fpga0 { + label = "fpga_led0"; + gpios = <&led_pio 0 1>; + }; + + led_fpga1: fpga1 { + label = "fpga_led1"; + gpios = <&led_pio 1 1>; + }; + + led_fpga2: fpga2 { + label = "fpga_led2"; + gpios = <&led_pio 2 1>; + }; + + led_fpga3: fpga3 { + label = "fpga_led3"; + gpios = <&led_pio 3 1>; + }; + }; + }; + + chosen { + bootargs = "debug console=ttyS0,115200"; + stdout-path = &uart_0; + }; +}; diff --git a/arch/nios2/dts/Makefile b/arch/nios2/dts/Makefile index b40eca9e0a..f22fabf881 100644 --- a/arch/nios2/dts/Makefile +++ b/arch/nios2/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb targets += $(dtb-y) diff --git a/arch/nios2/include/asm/bitops.h b/arch/nios2/include/asm/bitops.h index 3e17964f25..ee46f3722c 100644 --- a/arch/nios2/include/asm/bitops.h +++ b/arch/nios2/include/asm/bitops.h @@ -13,4 +13,9 @@ #include <asm/bitops/non-atomic.h> #include <asm/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index d6a2cfab4f..9863fd9f88 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -18,6 +18,8 @@ struct arch_global_data { int has_initda; int has_mmu; u32 io_region_base; + u32 mem_region_base; + u32 physaddr_mask; }; #include <asm-generic/global_data.h> diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h index e7da35b0c9..95d88012dd 100644 --- a/arch/nios2/include/asm/io.h +++ b/arch/nios2/include/asm/io.h @@ -18,15 +18,19 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) +#define MAP_NOCACHE 1 +#define MAP_WRCOMBINE 0 +#define MAP_WRBACK 0 +#define MAP_WRTHROUGH 0 static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { - return (void *)paddr; + DECLARE_GLOBAL_DATA_PTR; + if (flags) + return (void *)(paddr | gd->arch.io_region_base); + else + return (void *)(paddr | gd->arch.mem_region_base); } /* @@ -40,10 +44,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) static inline phys_addr_t virt_to_phys(void * vaddr) { DECLARE_GLOBAL_DATA_PTR; - if (gd->arch.has_mmu) - return (phys_addr_t)vaddr & 0x1fffffff; - else - return (phys_addr_t)vaddr & 0x7fffffff; + return (phys_addr_t)vaddr & gd->arch.physaddr_mask; } static inline void *ioremap(unsigned long physaddr, unsigned long size) @@ -172,4 +173,8 @@ static inline void outsl (unsigned long port, const void *src, unsigned long cou #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) +#define memset_io(a, b, c) memset((void *)(a), (b), (c)) +#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) +#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) + #endif /* __ASM_NIOS2_IO_H_ */ diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h index 6d0b57c014..28c4658672 100644 --- a/arch/openrisc/include/asm/bitops.h +++ b/arch/openrisc/include/asm/bitops.h @@ -12,6 +12,10 @@ #define PLATFORM_FFS #include <asm/bitops/ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + #define hweight32(x) generic_hweight32(x) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile index 88b5298be0..b182aa66f3 100644 --- a/arch/powerpc/cpu/Makefile +++ b/arch/powerpc/cpu/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_MPC83xx) += mpc8xxx/ obj-$(CONFIG_MPC85xx) += mpc8xxx/ obj-$(CONFIG_MPC86xx) += mpc8xxx/ diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index 9658b21951..b32f74e002 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -24,7 +24,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) *(.fixup) diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index 719846526f..6a5357124d 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -33,7 +33,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index cd9e23fbb7..aa80d3dbb1 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -28,7 +28,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index 50cbf85d23..469fc293eb 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -27,7 +27,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c index 66c88b697e..262ae7f711 100644 --- a/arch/powerpc/cpu/mpc83xx/law.c +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/fsl_law.h> #include <asm/mmu.h> +#include <linux/log2.h> int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) { @@ -20,7 +21,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (start == 0) start_align = 1ull << (LAW_SIZE_2G + 1); else - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; @@ -40,7 +41,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (sz) { start += law_sz; - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; ecm = &immap->sysconf.ddrlaw[1]; diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds index 774772beaf..4101eaf3f3 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds @@ -24,7 +24,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); } __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 3c177fa291..dbd8bbe23c 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -26,7 +26,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index ae0823af65..0b89157fca 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -149,6 +149,9 @@ config TARGET_XPEDITE550X config TARGET_UCP1020 bool "Support uCP1020" +config TARGET_CYRUS + bool "Support Varisys Cyrus" + endchoice source "board/freescale/b4860qds/Kconfig" @@ -185,6 +188,7 @@ source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" source "board/socrates/Kconfig" +source "board/varisys/cyrus/Kconfig" source "board/xes/xpedite520x/Kconfig" source "board/xes/xpedite537x/Kconfig" source "board/xes/xpedite550x/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index d4c3d9df9b..7270be1b28 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -13,6 +13,7 @@ #include <asm/processor.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/fsl_fdt.h> #include <asm/fsl_portals.h> #include <hwconfig.h> #ifdef CONFIG_FSL_ESDHC @@ -943,3 +944,13 @@ int ft_verify_fdt(void *fdt) return 1; } + +void fdt_del_diu(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,diu")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d954fe2fd2..e732969e41 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -131,7 +131,8 @@ void get_sys_info(sys_info_t *sys_info) * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) + defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \ + defined(CONFIG_PPC_T2081) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 8e0508f362..cf31eb2ef3 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -14,6 +14,8 @@ #include <addr_map.h> #endif +#include <linux/log2.h> + DECLARE_GLOBAL_DATA_PTR; void invalidate_tlb(u8 tlb) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index f933b21944..0399f93e6e 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -44,7 +44,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index b83c55388c..f04456442c 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -22,7 +22,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 5ae7b3eedb..889a4c2400 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -29,7 +29,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 2cf0b25952..f15eaf3805 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -50,7 +50,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 58467c2cc8..6c48f40992 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -32,7 +32,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 659e6889bf..15cee3fd4a 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -1089,7 +1089,6 @@ int drv_video_init (void) memset (&videodev, 0, sizeof (videodev)); strcpy (videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ videodev.putc = video_putc; /* 'putc' function */ videodev.puts = video_puts; /* 'puts' function */ diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index e95539e0a3..ac45e0e3df 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -1,9 +1,7 @@ # # Copyright 2009-2010 Freescale Semiconductor, Inc. # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# Version 2 as published by the Free Software Foundation. +# SPDX-License-Identifier: GPL-2.0 # MINIMAL= diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 33d53a8cfe..24baad442e 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -11,6 +11,7 @@ #include <linux/compiler.h> #include <asm/fsl_law.h> #include <asm/io.h> +#include <linux/log2.h> DECLARE_GLOBAL_DATA_PTR; @@ -187,7 +188,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (start == 0) start_align = 1ull << (LAW_SIZE_32G + 1); else - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; @@ -202,7 +203,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (sz) { start += law_sz; - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 198050853a..55dd4e1300 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -46,7 +46,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index ad104b9315..5d9f5c2822 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb targets += $(dtb-y) diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index 43a2bb2b3e..87efcca68a 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h @@ -19,7 +19,7 @@ typedef struct { int counter; } atomic_t; extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); extern void atomic_set_mask(unsigned long mask, unsigned long *addr); -extern __inline__ int atomic_add_return(int a, atomic_t *v) +static __inline__ int atomic_add_return(int a, atomic_t *v) { int t; @@ -35,7 +35,7 @@ extern __inline__ int atomic_add_return(int a, atomic_t *v) return t; } -extern __inline__ int atomic_sub_return(int a, atomic_t *v) +static __inline__ int atomic_sub_return(int a, atomic_t *v) { int t; @@ -51,7 +51,7 @@ extern __inline__ int atomic_sub_return(int a, atomic_t *v) return t; } -extern __inline__ int atomic_inc_return(atomic_t *v) +static __inline__ int atomic_inc_return(atomic_t *v) { int t; @@ -67,7 +67,7 @@ extern __inline__ int atomic_inc_return(atomic_t *v) return t; } -extern __inline__ int atomic_dec_return(atomic_t *v) +static __inline__ int atomic_dec_return(atomic_t *v) { int t; diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index a6bcf3c3fe..96491b6e4e 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -6,13 +6,7 @@ #define _PPC_BITOPS_H #include <asm/byteorder.h> - -extern void set_bit(int nr, volatile void *addr); -extern void clear_bit(int nr, volatile void *addr); -extern void change_bit(int nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void *addr); -extern int test_and_clear_bit(int nr, volatile void *addr); -extern int test_and_change_bit(int nr, volatile void *addr); +#include <asm-generic/bitops/__ffs.h> /* * Arguably these bit operations don't imply any memory barrier or @@ -34,7 +28,7 @@ extern int test_and_change_bit(int nr, volatile void *addr); * These used to be if'd out here because using : "cc" as a constraint * resulted in errors from egcs. Things may be OK with gcc-2.95. */ -extern __inline__ void set_bit(int nr, volatile void * addr) +static __inline__ void set_bit(int nr, volatile void * addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); @@ -51,7 +45,7 @@ extern __inline__ void set_bit(int nr, volatile void * addr) : "cc" ); } -extern __inline__ void clear_bit(int nr, volatile void *addr) +static __inline__ void clear_bit(int nr, volatile void *addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); @@ -68,7 +62,7 @@ extern __inline__ void clear_bit(int nr, volatile void *addr) : "cc"); } -extern __inline__ void change_bit(int nr, volatile void *addr) +static __inline__ void change_bit(int nr, volatile void *addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); @@ -85,7 +79,7 @@ extern __inline__ void change_bit(int nr, volatile void *addr) : "cc"); } -extern __inline__ int test_and_set_bit(int nr, volatile void *addr) +static __inline__ int test_and_set_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -104,7 +98,7 @@ extern __inline__ int test_and_set_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) +static __inline__ int test_and_clear_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -123,7 +117,7 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern __inline__ int test_and_change_bit(int nr, volatile void *addr) +static __inline__ int test_and_change_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -143,7 +137,7 @@ extern __inline__ int test_and_change_bit(int nr, volatile void *addr) } #endif /* __INLINE_BITOPS */ -extern __inline__ int test_bit(int nr, __const__ volatile void *addr) +static __inline__ int test_bit(int nr, __const__ volatile void *addr) { __const__ unsigned int *p = (__const__ unsigned int *) addr; @@ -152,7 +146,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr) /* Return the bit position of the most significant 1 bit in a word */ /* - the result is undefined when x == 0 */ -extern __inline__ int __ilog2(unsigned int x) +static __inline__ int __ilog2(unsigned int x) { int lz; @@ -160,7 +154,7 @@ extern __inline__ int __ilog2(unsigned int x) return 31 - lz; } -extern __inline__ int ffz(unsigned int x) +static __inline__ int ffz(unsigned int x) { if ((x = ~x) == 0) return 32; @@ -209,16 +203,6 @@ static inline int fls64(__u64 x) #error BITS_PER_LONG not 32 or 64 #endif -static inline int __ilog2_u64(u64 n) -{ - return fls64(n) - 1; -} - -static inline int ffs64(u64 x) -{ - return __ilog2_u64(x & -x) + 1ull; -} - #ifdef __KERNEL__ /* @@ -226,7 +210,7 @@ static inline int ffs64(u64 x) * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ -extern __inline__ int ffs(int x) +static __inline__ int ffs(int x) { return __ilog2(x & -x) + 1; } @@ -250,7 +234,7 @@ extern __inline__ int ffs(int x) #define find_first_zero_bit(addr, size) \ find_next_zero_bit((addr), (size), 0) -extern __inline__ unsigned long find_next_zero_bit(void * addr, +static __inline__ unsigned long find_next_zero_bit(void * addr, unsigned long size, unsigned long offset) { unsigned int * p = ((unsigned int *) addr) + (offset >> 5); @@ -298,7 +282,7 @@ found_middle: #define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) #else -extern __inline__ int ext2_set_bit(int nr, void * addr) +static __inline__ int ext2_set_bit(int nr, void * addr) { int mask; unsigned char *ADDR = (unsigned char *) addr; @@ -311,7 +295,7 @@ extern __inline__ int ext2_set_bit(int nr, void * addr) return oldbit; } -extern __inline__ int ext2_clear_bit(int nr, void * addr) +static __inline__ int ext2_clear_bit(int nr, void * addr) { int mask; unsigned char *ADDR = (unsigned char *) addr; @@ -325,7 +309,7 @@ extern __inline__ int ext2_clear_bit(int nr, void * addr) } #endif /* __KERNEL__ */ -extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) +static __inline__ int ext2_test_bit(int nr, __const__ void * addr) { __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h index 3f5bcf63a1..f731d18e76 100644 --- a/arch/powerpc/include/asm/byteorder.h +++ b/arch/powerpc/include/asm/byteorder.h @@ -5,7 +5,7 @@ #ifdef __GNUC__ -extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +static __inline__ unsigned ld_le16(const volatile unsigned short *addr) { unsigned val; @@ -13,12 +13,12 @@ extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) return val; } -extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) +static __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) { __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +static __inline__ unsigned ld_le32(const volatile unsigned *addr) { unsigned val; @@ -26,7 +26,7 @@ extern __inline__ unsigned ld_le32(const volatile unsigned *addr) return val; } -extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +static __inline__ void st_le32(volatile unsigned *addr, const unsigned val) { __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } diff --git a/arch/powerpc/include/asm/fsl_fdt.h b/arch/powerpc/include/asm/fsl_fdt.h new file mode 100644 index 0000000000..82e8f45644 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_fdt.h @@ -0,0 +1,11 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _FSL_FDT_H_ +#define _FSL_FDT_H_ + +void fdt_del_diu(void *blob); + +#endif diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 3b504875e0..8e1d22adef 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -10,6 +10,7 @@ #define _FSL_LAW_H_ #include <asm/io.h> +#include <linux/log2.h> #define LAW_EN 0x80000000 diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h index e5aab2a71f..ec25e16829 100644 --- a/arch/powerpc/include/asm/fsl_srio.h +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -7,6 +7,8 @@ #ifndef _FSL_SRIO_H_ #define _FSL_SRIO_H_ +#include <linux/log2.h> + enum atmu_size { ATMU_SIZE_4K = 0xb, ATMU_SIZE_8K, diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 0c9d85ec96..101b8db0ee 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -19,7 +19,7 @@ #include <fsl_sec.h> #include <fsl_sfp.h> #include <asm/fsl_lbc.h> -#include <asm/fsl_fman.h> +#include <fsl_fman.h> #include <fsl_immap.h> typedef struct ccsr_local { diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index a5257e9b62..a54fc468d5 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -163,7 +163,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) * is actually performed (i.e. the data has come back) before we start * executing any following instructions. */ -extern inline u8 in_8(const volatile unsigned char __iomem *addr) +static inline u8 in_8(const volatile unsigned char __iomem *addr) { u8 ret; @@ -174,7 +174,7 @@ extern inline u8 in_8(const volatile unsigned char __iomem *addr) return ret; } -extern inline void out_8(volatile unsigned char __iomem *addr, u8 val) +static inline void out_8(volatile unsigned char __iomem *addr, u8 val) { __asm__ __volatile__("sync;\n" "stb%U0%X0 %1,%0;\n" @@ -182,7 +182,7 @@ extern inline void out_8(volatile unsigned char __iomem *addr, u8 val) : "r" (val)); } -extern inline u16 in_le16(const volatile unsigned short __iomem *addr) +static inline u16 in_le16(const volatile unsigned short __iomem *addr) { u16 ret; @@ -193,7 +193,7 @@ extern inline u16 in_le16(const volatile unsigned short __iomem *addr) return ret; } -extern inline u16 in_be16(const volatile unsigned short __iomem *addr) +static inline u16 in_be16(const volatile unsigned short __iomem *addr) { u16 ret; @@ -203,18 +203,18 @@ extern inline u16 in_be16(const volatile unsigned short __iomem *addr) return ret; } -extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val) +static inline void out_le16(volatile unsigned short __iomem *addr, u16 val) { __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val) +static inline void out_be16(volatile unsigned short __iomem *addr, u16 val) { __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } -extern inline u32 in_le32(const volatile unsigned __iomem *addr) +static inline u32 in_le32(const volatile unsigned __iomem *addr) { u32 ret; @@ -225,7 +225,7 @@ extern inline u32 in_le32(const volatile unsigned __iomem *addr) return ret; } -extern inline u32 in_be32(const volatile unsigned __iomem *addr) +static inline u32 in_be32(const volatile unsigned __iomem *addr) { u32 ret; @@ -235,13 +235,13 @@ extern inline u32 in_be32(const volatile unsigned __iomem *addr) return ret; } -extern inline void out_le32(volatile unsigned __iomem *addr, u32 val) +static inline void out_le32(volatile unsigned __iomem *addr, u32 val) { __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -extern inline void out_be32(volatile unsigned __iomem *addr, u32 val) +static inline void out_be32(volatile unsigned __iomem *addr, u32 val) { __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h index 619f3a8abe..617584d7c7 100644 --- a/arch/powerpc/include/asm/iopin_8260.h +++ b/arch/powerpc/include/asm/iopin_8260.h @@ -23,140 +23,140 @@ iopin_t; #define IOPIN_PORTC 2 #define IOPIN_PORTD 3 -extern __inline__ void +static __inline__ void iopin_set_high(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_low(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_high(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_low(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_out(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_in(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_out(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_in(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_odr(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_act(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_odr(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_act(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_ded(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_gen(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_ded(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_gen(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_opt2(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_opt1(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_opt2(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_opt1(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h index 0123bafcad..8db0fa2a1c 100644 --- a/arch/powerpc/include/asm/iopin_8xx.h +++ b/arch/powerpc/include/asm/iopin_8xx.h @@ -26,7 +26,7 @@ typedef struct { #define IOPIN_PORTC 2 #define IOPIN_PORTD 3 -extern __inline__ void +static __inline__ void iopin_set_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -44,7 +44,7 @@ iopin_set_high(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -62,7 +62,7 @@ iopin_set_low(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -81,7 +81,7 @@ iopin_is_high(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -100,7 +100,7 @@ iopin_is_low(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -118,7 +118,7 @@ iopin_set_out(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -136,7 +136,7 @@ iopin_set_in(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -155,7 +155,7 @@ iopin_is_out(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -174,7 +174,7 @@ iopin_is_in(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -186,7 +186,7 @@ iopin_set_odr(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -198,7 +198,7 @@ iopin_set_act(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -211,7 +211,7 @@ iopin_is_odr(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -224,7 +224,7 @@ iopin_is_act(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -242,7 +242,7 @@ iopin_set_ded(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -260,7 +260,7 @@ iopin_set_gen(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -279,7 +279,7 @@ iopin_is_ded(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -298,7 +298,7 @@ iopin_is_gen(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -307,7 +307,7 @@ iopin_set_opt2(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -316,7 +316,7 @@ iopin_set_opt1(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -326,7 +326,7 @@ iopin_is_opt2(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -336,7 +336,7 @@ iopin_is_opt1(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -345,7 +345,7 @@ iopin_set_falledge(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -354,7 +354,7 @@ iopin_set_anyedge(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -364,7 +364,7 @@ iopin_is_falledge(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index 517b555475..0197569262 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-$(CONFIG_SANDBOX) += sandbox.dtb dtb-$(CONFIG_UT_DM) += test.dtb diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi index 44a26b18ca..ce261b930e 100644 --- a/arch/sandbox/dts/sandbox_pmic.dtsi +++ b/arch/sandbox/dts/sandbox_pmic.dtsi @@ -55,7 +55,7 @@ regulator-always-on; }; - buck2 { + buck2: buck2 { regulator-name = "SUPPLY_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 730de8a57f..e2c4971d74 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -189,6 +189,12 @@ }; }; + adc@0 { + compatible = "sandbox,adc"; + vdd-supply = <&buck2>; + vss-microvolts = <0>; + }; + leds { compatible = "gpio-leds"; diff --git a/arch/sandbox/include/asm/bitops.h b/arch/sandbox/include/asm/bitops.h index f1a7aeee93..f27d5e98c5 100644 --- a/arch/sandbox/include/asm/bitops.h +++ b/arch/sandbox/include/asm/bitops.h @@ -21,6 +21,10 @@ #include <linux/compiler.h> #include <asm/system.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> #ifdef __KERNEL__ diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index c57d628478..8cb8385d76 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -1,6 +1,11 @@ #ifndef __ASM_SH_BITOPS_H #define __ASM_SH_BITOPS_H +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + #ifdef __KERNEL__ #include <asm/irqflags.h> /* For __swab32 */ diff --git a/arch/sparc/include/asm/bitops.h b/arch/sparc/include/asm/bitops.h index fa39fa3fc6..c66f730c88 100644 --- a/arch/sparc/include/asm/bitops.h +++ b/arch/sparc/include/asm/bitops.h @@ -9,4 +9,9 @@ #ifndef _SPARC_BITOPS_H #define _SPARC_BITOPS_H +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + #endif /* _SPARC_BITOPS_H */ diff --git a/arch/sparc/include/asm/irq.h b/arch/sparc/include/asm/irq.h index bbe0204387..2faf7a074e 100644 --- a/arch/sparc/include/asm/irq.h +++ b/arch/sparc/include/asm/irq.h @@ -12,7 +12,7 @@ #include <asm/psr.h> /* Set SPARC Processor Interrupt Level */ -extern inline void set_pil(unsigned int level) +static inline void set_pil(unsigned int level) { unsigned int psr = get_psr(); @@ -20,7 +20,7 @@ extern inline void set_pil(unsigned int level) } /* Get SPARC Processor Interrupt Level */ -extern inline unsigned int get_pil(void) +static inline unsigned int get_pil(void) { unsigned int psr = get_psr(); return (psr & PSR_PIL) >> PSR_PIL_OFS; diff --git a/arch/sparc/include/asm/psr.h b/arch/sparc/include/asm/psr.h index 70af8e0f54..a91bdc903c 100644 --- a/arch/sparc/include/asm/psr.h +++ b/arch/sparc/include/asm/psr.h @@ -42,7 +42,7 @@ #ifndef __ASSEMBLY__ /* Get the %psr register. */ -extern __inline__ unsigned int get_psr(void) +static __inline__ unsigned int get_psr(void) { unsigned int psr; __asm__ __volatile__("rd %%psr, %0\n\t" @@ -53,7 +53,7 @@ extern __inline__ unsigned int get_psr(void) return psr; } -extern __inline__ void put_psr(unsigned int new_psr) +static __inline__ void put_psr(unsigned int new_psr) { __asm__ __volatile__("wr %0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t": /* no outputs */ :"r"(new_psr) @@ -67,7 +67,7 @@ extern __inline__ void put_psr(unsigned int new_psr) extern unsigned int fsr_storage; -extern __inline__ unsigned int get_fsr(void) +static __inline__ unsigned int get_fsr(void) { unsigned int fsr = 0; diff --git a/arch/sparc/include/asm/srmmu.h b/arch/sparc/include/asm/srmmu.h index 74b15549fa..8da2f67f1c 100644 --- a/arch/sparc/include/asm/srmmu.h +++ b/arch/sparc/include/asm/srmmu.h @@ -148,7 +148,7 @@ extern void *srmmu_nocache_pool; #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR)) /* Accessing the MMU control register. */ -extern __inline__ unsigned int srmmu_get_mmureg(void) +static __inline__ unsigned int srmmu_get_mmureg(void) { unsigned int retval; __asm__ __volatile__("lda [%%g0] %1, %0\n\t": @@ -156,14 +156,14 @@ extern __inline__ unsigned int srmmu_get_mmureg(void) return retval; } -extern __inline__ void srmmu_set_mmureg(unsigned long regval) +static __inline__ void srmmu_set_mmureg(unsigned long regval) { __asm__ __volatile__("sta %0, [%%g0] %1\n\t"::"r"(regval), "i"(ASI_M_MMUREGS):"memory"); } -extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) +static __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) { paddr = ((paddr >> 4) & SRMMU_CTX_PMASK); __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(paddr), @@ -171,7 +171,7 @@ extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) "i"(ASI_M_MMUREGS):"memory"); } -extern __inline__ unsigned long srmmu_get_ctable_ptr(void) +static __inline__ unsigned long srmmu_get_ctable_ptr(void) { unsigned int retval; @@ -181,13 +181,13 @@ extern __inline__ unsigned long srmmu_get_ctable_ptr(void) return (retval & SRMMU_CTX_PMASK) << 4; } -extern __inline__ void srmmu_set_context(int context) +static __inline__ void srmmu_set_context(int context) { __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(context), "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS):"memory"); } -extern __inline__ int srmmu_get_context(void) +static __inline__ int srmmu_get_context(void) { register int retval; __asm__ __volatile__("lda [%1] %2, %0\n\t": @@ -196,7 +196,7 @@ extern __inline__ int srmmu_get_context(void) return retval; } -extern __inline__ unsigned int srmmu_get_fstatus(void) +static __inline__ unsigned int srmmu_get_fstatus(void) { unsigned int retval; @@ -206,7 +206,7 @@ extern __inline__ unsigned int srmmu_get_fstatus(void) return retval; } -extern __inline__ unsigned int srmmu_get_faddr(void) +static __inline__ unsigned int srmmu_get_faddr(void) { unsigned int retval; @@ -217,7 +217,7 @@ extern __inline__ unsigned int srmmu_get_faddr(void) } /* This is guaranteed on all SRMMU's. */ -extern __inline__ void srmmu_flush_whole_tlb(void) +static __inline__ void srmmu_flush_whole_tlb(void) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400), /* Flush entire TLB!! */ "i"(ASI_M_FLUSH_PROBE):"memory"); @@ -225,14 +225,14 @@ extern __inline__ void srmmu_flush_whole_tlb(void) } /* These flush types are not available on all chips... */ -extern __inline__ void srmmu_flush_tlb_ctx(void) +static __inline__ void srmmu_flush_tlb_ctx(void) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x300), /* Flush TLB ctx.. */ "i"(ASI_M_FLUSH_PROBE):"memory"); } -extern __inline__ void srmmu_flush_tlb_region(unsigned long addr) +static __inline__ void srmmu_flush_tlb_region(unsigned long addr) { addr &= SRMMU_PGDIR_MASK; __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x200), /* Flush TLB region.. */ @@ -240,7 +240,7 @@ extern __inline__ void srmmu_flush_tlb_region(unsigned long addr) } -extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr) +static __inline__ void srmmu_flush_tlb_segment(unsigned long addr) { addr &= SRMMU_REAL_PMD_MASK; __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x100), /* Flush TLB segment.. */ @@ -248,7 +248,7 @@ extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr) } -extern __inline__ void srmmu_flush_tlb_page(unsigned long page) +static __inline__ void srmmu_flush_tlb_page(unsigned long page) { page &= PAGE_MASK; __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(page), /* Flush TLB page.. */ @@ -256,7 +256,7 @@ extern __inline__ void srmmu_flush_tlb_page(unsigned long page) } -extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) +static __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) { unsigned long retval; @@ -268,7 +268,7 @@ extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) return retval; } -extern __inline__ int srmmu_get_pte(unsigned long addr) +static __inline__ int srmmu_get_pte(unsigned long addr) { register unsigned long entry; diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 83a2b8c1cf..64e569432c 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-y += bayleybay.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 5a7e4cba2b..f97dc66439 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -14,6 +14,10 @@ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). */ +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> + #ifdef CONFIG_SMP #define LOCK_PREFIX "lock ; " #else @@ -332,6 +336,20 @@ static __inline__ unsigned long ffz(unsigned long word) #ifdef __KERNEL__ /** + * __ffs - find first set bit in word + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline unsigned long __ffs(unsigned long word) +{ + __asm__("rep; bsf %1,%0" + : "=r" (word) + : "rm" (word)); + return word; +} + +/** * ffs - find first bit set * @x: the word to search * @@ -346,7 +364,8 @@ static __inline__ int ffs(int x) __asm__("bsfl %1,%0\n\t" "jnz 1f\n\t" "movl $-1,%0\n" - "1:" : "=r" (r) : "g" (x)); + "1:" : "=r" (r) : "rm" (x)); + return r+1; } #define PLATFORM_FFS diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig new file mode 100644 index 0000000000..124b66da0f --- /dev/null +++ b/board/Marvell/openrd/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OPENRD + +config SYS_BOARD + default "openrd" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "openrd" + +endif diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS new file mode 100644 index 0000000000..3789a04c89 --- /dev/null +++ b/board/Marvell/openrd/MAINTAINERS @@ -0,0 +1,12 @@ +OPENRD BOARD +M: Albert ARIBAUD <albert-u-boot@aribaud.net> +S: Maintained +F: board/Marvell/openrd/ +F: include/configs/openrd.h +F: configs/openrd_base_defconfig + +OPENRD_CLIENT BOARD +M: Albert ARIBAUD <albert-u-boot@aribaud.net> +S: Maintained +F: configs/openrd_client_defconfig +F: configs/openrd_ultimate_defconfig diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile new file mode 100644 index 0000000000..8f95b7922e --- /dev/null +++ b/board/Marvell/openrd/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2009 +# Net Insight <www.netinsight.net> +# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> +# +# Based on sheevaplug: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := openrd.o diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg new file mode 100644 index 0000000000..8e5993715e --- /dev/null +++ b/board/Marvell/openrd/kwbimage.cfg @@ -0,0 +1,152 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strength reduced +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) + +DATA 0xFFD0149C 0x0000E40f # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c new file mode 100644 index 0000000000..17a65600e4 --- /dev/null +++ b/board/Marvell/openrd/openrd.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * + * Based on sheevaplug.c: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include "openrd.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, /* Alt UART1_TXD */ + MPP14_SD_D0, /* Alt UART1_RXD */ + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, /* UART1 / SD sel */ + MPP35_TDM_CH0_TX_QL, + MPP36_TDM_SPI_CS1, + MPP37_TDM_CH2_TX_QL, + MPP38_TDM_CH2_RX_QL, + MPP39_AUDIO_I2SBCLK, + MPP40_AUDIO_I2SDO, + MPP41_AUDIO_I2SLRC, + MPP42_AUDIO_I2SMCLK, + MPP43_AUDIO_I2SDI, + MPP44_AUDIO_EXTCLK, + MPP45_TDM_PCLK, + MPP46_TDM_FS, + MPP47_TDM_DRX, + MPP48_TDM_DTX, + MPP49_TDM_CH0_RX_QL, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ +#if defined(CONFIG_BOARD_IS_OPENRD_BASE) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; +#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; +#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; +#endif + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116/88E1121 PHY */ +void mv_phy_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { + printf("Err..%s could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf(PHY_NO" Initialized on %s\n", name); +} + +void reset_phy(void) +{ + mv_phy_init("egiga0"); + +#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT + /* Kirkwood ethernet driver is written with the assumption that in case + * of multiple PHYs, their addresses are consecutive. But unfortunately + * in case of OpenRD-Client, PHY addresses are not consecutive.*/ + miiphy_write("egiga1", 0xEE, 0xEE, 24); +#endif + +#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ + defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) + /* configure and initialize both PHY's */ + mv_phy_init("egiga1"); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h new file mode 100644 index 0000000000..56dfeea1a8 --- /dev/null +++ b/board/Marvell/openrd/openrd.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OPENRD_BASE_H +#define __OPENRD_BASE_H + +#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ +#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ +#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ +#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __OPENRD_BASE_H */ diff --git a/board/altera/nios2/MAINTAINERS b/board/altera/nios2/MAINTAINERS new file mode 100644 index 0000000000..aff618b52c --- /dev/null +++ b/board/altera/nios2/MAINTAINERS @@ -0,0 +1,13 @@ +3C120 DEVBOARD +M: Thomas Chou <thomas@wytron.com.tw> +S: Maintained +F: arch/nios2/dts/3c120_devboard.dts +F: configs/3c120_defconfig +F: include/configs/3c120_devboard.h + +10M50 DEVBOARD +M: Thomas Chou <thomas@wytron.com.tw> +S: Maintained +F: arch/nios2/dts/10m50_devboard.dts +F: configs/10m50_defconfig +F: include/configs/10m50_devboard.h diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile index 2743809e57..97342a8570 100644 --- a/board/atmark-techno/armadillo-800eva/Makefile +++ b/board/atmark-techno/armadillo-800eva/Makefile @@ -1,20 +1,8 @@ # # Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License. +# SPDX-License-Identifier: GPL-2.0 # -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA obj-y += armadillo-800eva.o diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index c2bf145013..a57f9fecaf 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -438,8 +438,6 @@ int drv_video_init(void) memset(&videodev, 0, sizeof(videodev)); strcpy(videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ - videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ error = stdio_register(&videodev); diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c index 75b8adca15..e9b9a9abdf 100644 --- a/board/bf533-stamp/video.c +++ b/board/bf533-stamp/video.c @@ -164,8 +164,6 @@ int drv_video_init(void) memset(&videodev, 0, sizeof(videodev)); strcpy(videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; - videodev.flags = DEV_FLAGS_SYSTEM; return stdio_register(&videodev); } diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index 47e68c6a97..37659932f2 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -328,8 +328,6 @@ int drv_video_init(void) memset(&videodev, 0, sizeof(videodev)); strcpy(videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ - videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ error = stdio_register(&videodev); diff --git a/board/birdland/bav335x/Makefile b/board/birdland/bav335x/Makefile index 2fc56143c3..d2aba7b397 100644 --- a/board/birdland/bav335x/Makefile +++ b/board/birdland/bav335x/Makefile @@ -3,6 +3,8 @@ # # Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem # +# SPDX-License-Identifier: GPL-2.0+ +# ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) obj-y := mux.o diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index b098615d4c..b8cc873863 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -332,8 +332,6 @@ int drv_video_init(void) memset(&videodev, 0, sizeof(videodev)); strcpy(videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ - videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ error = stdio_register(&videodev); diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index b5fde8d098..aa56643e48 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -4,14 +4,7 @@ # See file CREDITS for list of people who contributed to this # project. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. +# SPDX-License-Identifier: GPL-2.0 # obj-y := paz00.o diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index c5994e0a4a..b7f9f90cde 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -3,7 +3,7 @@ * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009-2011 + * (C) Copyright 2009-2015 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -28,6 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; * Miscelaneous platform dependent initialisations */ +#ifdef CONFIG_REVISION_TAG static int hw_rev = -1; /* hardware revision */ int get_hw_rev(void) @@ -45,6 +46,7 @@ int get_hw_rev(void) return hw_rev; } +#endif /* CONFIG_REVISION_TAG */ #ifdef CONFIG_CMD_NAND static void meesc_nand_hw_init(void) @@ -125,12 +127,18 @@ static void meesc_ethercat_hw_init(void) int dram_init(void) { - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, + PHYS_SDRAM_SIZE); return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; +} + int board_eth_init(bd_t *bis) { int rc = 0; @@ -140,6 +148,7 @@ int board_eth_init(bd_t *bis) return rc; } +#ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { char str[32]; @@ -173,10 +182,13 @@ int checkboard(void) puts(", serial# "); puts(str); } +#ifdef CONFIG_REVISION_TAG printf("\nHardware-revision: 1.%d\n", get_hw_rev()); +#endif printf("Mach-type: %lu\n", gd->bd->bi_arch_number); return 0; } +#endif /* CONFIG_DISPLAY_BOARDINFO */ #ifdef CONFIG_SERIAL_TAG void get_board_serial(struct tag_serialnr *serialnr) diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 501d4b3aff..df90476a77 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -26,7 +26,7 @@ #include <fsl_mdio.h> #include <malloc.h> #include <fdt_support.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include "../common/ngpixis.h" #include "../common/fman.h" diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 87d05780fe..51d2814a43 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -71,7 +71,7 @@ obj-$(CONFIG_P4080DS) += p_corenet/ obj-$(CONFIG_P5020DS) += p_corenet/ obj-$(CONFIG_P5040DS) += p_corenet/ -obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o ifdef CONFIG_SECURE_BOOT obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 8e8b7fa204..a498c65f04 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -12,7 +12,6 @@ #include <asm/secure.h> #endif #include <asm/armv7.h> -#include <asm/cache.h> #if defined(CONFIG_LS102XA) #include <asm/arch/immap_ls102xa.h> @@ -65,8 +64,6 @@ static void dp_ddr_restore(void) for (i = 0; i < DDR_BUFF_LEN / 8; i++) *dst++ = *src++; - - flush_dcache_all(); } static void dp_resume_prepare(void) @@ -74,7 +71,6 @@ static void dp_resume_prepare(void) dp_ddr_restore(); board_sleep_prepare(); armv7_init_nonsec(); - cleanup_before_linux(); #ifdef CONFIG_U_QE u_qe_resume(); #endif diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 9dc540211e..26cf5175c7 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,7 +10,11 @@ #include <fdt_support.h> #include <fm_eth.h> +#ifdef CONFIG_FSL_LAYERSCAPE +#include <asm/arch/fsl_serdes.h> +#else #include <asm/fsl_serdes.h> +#endif /* * Given the following ... diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 5283648a4d..73b6718db9 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img) * address */ #if defined(CONFIG_MPC85xx) -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); - ulong flash_addr, addr; + u32 flash_addr, addr; int found = 0; int i = 0; @@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) flash_addr = flash_info[i].start[0]; addr = flash_info[i].start[0] + csf_flash_offset; if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { - debug("Barker found on addr %lx\n", addr); + debug("Barker found on addr %x\n", addr); found = 1; break; } @@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) /* For platforms like LS1020, correct flash address is present in * the header. So the function reqturns flash base address as 0 */ -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); @@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) } #endif -static int get_ie_info_addr(ulong *ie_addr) +static int get_ie_info_addr(u32 *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; - ulong flash_base_addr, csf_addr; + u32 flash_base_addr, csf_addr; if (get_csf_base_addr(&csf_addr, &flash_base_addr)) return -1; @@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + - (ulong)hdr->psgtable); + (u32)hdr->psgtable); #endif /* IE Key Table is the first entry in the SG Table */ @@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr) *ie_addr = sg_tbl->src_addr; #endif - debug("IE Table address is %lx\n", *ie_addr); + debug("IE Table address is %x\n", *ie_addr); return 0; } @@ -246,7 +246,7 @@ static void fsl_secboot_image_verification_failure(void) struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); - u32 its = sfp_in32(&sfp_regs->ospr) & ITS_MASK >> ITS_BIT; + u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; /* * Read the SEC_MON status register @@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; - sprintf(buf, "%p", hdr->pimg); + sprintf(buf, "%x", hdr->pimg); setenv("img_addr", buf); if (!hdr->img_size) diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index d7de9822d0..d8d16c520f 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -6,9 +6,10 @@ #include <common.h> #include <asm/io.h> +#include <fsl_csu.h> #include <asm/arch/ns_access.h> -void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; u32 *reg; @@ -28,3 +29,8 @@ void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) out_be32(reg, val); } } + +void enable_layerscape_ns_access(void) +{ + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +} diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 51ce9c328d..0aa56a090e 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -125,8 +125,13 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */ #define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */ #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ + #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 +#define QIXIS_DAT5_6_7 0X02 +#define QIXIS_DAT4 0X01 + +#define QIXIS_EVDD_BY_SDHC_VS 0x0c #endif #endif diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 396103f990..172a55b988 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -55,7 +55,7 @@ #include <fsl_mdio.h> #include <malloc.h> #include <fdt_support.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include "../common/ngpixis.h" #include "../common/fman.h" diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 5cbec7f5f2..c68dc2c246 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -24,7 +24,7 @@ #include "../common/ngpixis.h" #include "../common/fman.h" -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #define EMI_NONE 0xffffffff #define EMI_MASK 0xf0000000 diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index ad1bffd74b..62b163580b 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -55,7 +55,7 @@ #include <fsl_mdio.h> #include <malloc.h> #include <fdt_support.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include "../common/ngpixis.h" #include "../common/fman.h" diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 655fc644fe..d889ad50fd 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -8,13 +8,14 @@ #include <i2c.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> -#include <asm/arch/ns_access.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> +#include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_sec.h> @@ -56,92 +57,6 @@ enum { GE1_CLK125, }; -#ifdef CONFIG_LS102XA_NS_ACCESS -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; -#endif - int checkboard(void) { #ifndef CONFIG_QSPI_BOOT @@ -382,9 +297,8 @@ void board_init_f(ulong dummy) dram_init(); /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(&ns_dev[4], 1); - enable_devices_ns_access(&ns_dev[7], 1); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif board_init_r(NULL, 0); @@ -494,6 +408,17 @@ int config_serdes_mux(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_init(); +#endif + + return 0; +} +#endif + int misc_init_r(void) { int conflict_flag; @@ -602,8 +527,8 @@ int board_init(void) ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif #ifdef CONFIG_U_QE @@ -627,8 +552,8 @@ void board_sleep_prepare(void) } -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif } #endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index e9f6f0a973..b997bb00ec 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -6,5 +6,6 @@ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig F: configs/ls1021atwr_nor_lpuart_defconfig -F: configs/ls1021atwr_sdcard_defconfig +F: configs/ls1021atwr_sdcard_ifc_defconfig +F: configs/ls1021atwr_sdcard_qspi_defconfig F: configs/ls1021atwr_qspi_defconfig diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 228dbf81bb..4918c1192e 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -8,13 +8,14 @@ #include <i2c.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> -#include <asm/arch/ns_access.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> +#include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_immap.h> @@ -69,92 +70,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PIN_QE_LCD_MUX_LCD 0x0 #define PIN_QE_LCD_MUX_QE 0x1 -#ifdef CONFIG_LS102XA_NS_ACCESS -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; -#endif - struct cpld_data { u8 cpld_ver; /* cpld revision */ u8 cpld_ver_sub; /* cpld sub revision */ @@ -175,7 +90,7 @@ struct cpld_data { u8 rev2; /* Reserved */ }; -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void convert_serdes_mux(int type, int need_reset); void cpld_show(void) @@ -216,7 +131,7 @@ void cpld_show(void) int checkboard(void) { puts("Board: LS1021ATWR\n"); -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) cpld_show(); #endif @@ -380,7 +295,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) int config_serdes_mux(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -414,7 +329,7 @@ int config_serdes_mux(void) } #endif -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) int config_board_mux(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -521,8 +436,10 @@ int board_early_init_f(void) } #if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); + if (is_warm_boot()) { + timer_init(); + dram_init(); + } #endif return 0; @@ -531,6 +448,8 @@ int board_early_init_f(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { + void (*second_uboot)(void); + /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -546,11 +465,22 @@ void board_init_f(ulong dummy) dram_init(); /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(&ns_dev[4], 1); - enable_devices_ns_access(&ns_dev[7], 1); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); + enable_layerscape_ns_access(); #endif + /* + * if it is woken up from deep sleep, then jump to second + * stage uboot and continue executing without recopying + * it from SD since it has already been reserved in memeory + * in last boot. + */ + if (is_warm_boot()) { + second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; + second_uboot(); + } + board_init_r(NULL, 0); } #endif @@ -627,7 +557,7 @@ int board_init(void) { #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) config_serdes_mux(); #endif #endif @@ -637,8 +567,8 @@ int board_init(void) ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif #ifdef CONFIG_U_QE @@ -651,13 +581,24 @@ int board_init(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_init(); +#endif + + return 0; +} +#endif + #if defined(CONFIG_MISC_INIT_R) int misc_init_r(void) { #ifdef CONFIG_FSL_DEVICE_DISABLE device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); #endif -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) config_board_mux(); #endif @@ -670,8 +611,8 @@ int misc_init_r(void) #if defined(CONFIG_DEEP_SLEEP) void board_sleep_prepare(void) { -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif } #endif @@ -706,7 +647,7 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg deleted file mode 100644 index 9c3e3b080b..0000000000 --- a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -0608000a 00000000 00000000 00000000 -20000000 00407900 60040a00 21046000 -00000000 00000000 00000000 00038000 -00080000 881b7340 00000000 00000000 - -#disable IFC, enable QSPI and DSPI -#0608000a 00000000 00000000 00000000 -#20000000 00407900 60040a00 21046000 -#00000000 00000000 00000000 00038000 -#20084800 881b7340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg new file mode 100644 index 0000000000..205606f4d2 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +30000000 00007900 60040a00 21046000 +00000000 00000000 00000000 20000000 +00080000 881b7340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg new file mode 100644 index 0000000000..6767e09388 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#disable IFC, enable QSPI and DSPI +0608000a 00000000 00000000 00000000 +30000000 00007900 60040a00 21046000 +00000000 00000000 00000000 20000000 +20024800 881b7340 00000000 00000000 diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig new file mode 100644 index 0000000000..51818ec580 --- /dev/null +++ b/board/freescale/ls1043ardb/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS1043ARDB + +config SYS_BOARD + default "ls1043ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1043ardb" + +endif diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS new file mode 100644 index 0000000000..efca5bf245 --- /dev/null +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -0,0 +1,9 @@ +LS1043A BOARD +M: Mingkai Hu <Mingkai.hu@freescale.com> +S: Maintained +F: board/freescale/ls1043ardb/ +F: board/freescale/ls1043ardb/ls1043ardb.c +F: include/configs/ls1043ardb.h +F: configs/ls1043ardb_defconfig +F: configs/ls1043ardb_nand_defconfig +F: configs/ls1043ardb_sdcard_defconfig diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile new file mode 100644 index 0000000000..5fe1cc9393 --- /dev/null +++ b/board/freescale/ls1043ardb/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2015 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpld.o +obj-y += ddr.o +obj-y += ls1043ardb.o +obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README new file mode 100644 index 0000000000..0556e73b3a --- /dev/null +++ b/board/freescale/ls1043ardb/README @@ -0,0 +1,87 @@ +Overview +-------- +The LS1043A Reference Design Board (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1043A +LayerScape Architecture processor. The LS1043ARDB provides SW development +platform for the Freescale LS1043A processor series, with a complete +debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. + +LS1043A SoC Overview +-------------------- +The LS1043A integrated multicore processor combines four ARM Cortex-A53 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1043A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A53 CPUs + - 1 MB unified L2 Cache + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Ethernet interfaces by FMan + - Up to 1 x XFI supporting 10G interface + - Up to 1 x QSGMII + - Up to 4 x SGMII supporting 1000Mbps + - Up to 2 x SGMII supporting 2500Mbps + - Up to 2 x RGMII supporting 1000Mbps + - High-speed peripheral interfaces + - Three PCIe 2.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 + + LS1043ARDB board Overview + ----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and + standard PCIe card + - QSGMII with x4 RJ45 connector + - XFI with x1 RJ45 connector + - DDR Controller + - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus + - One 128MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - CPLD connection + - USB 3.0 + - Two super speed USB 3.0 Type A ports + - SDHC: connects directly to a full SD/MMC slot + - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +Booting Options +--------------- +a) NOR boot +b) NAND boot +c) SD boot diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c new file mode 100644 index 0000000000..78c28246a8 --- /dev/null +++ b/board/freescale/ls1043ardb/cpld.c @@ -0,0 +1,152 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Freescale LS1043ARDB board-specific CPLD controlling supports. + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg7 = CPLD_READ(vbank); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); + + reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; + CPLD_WRITE(vbank, reg7); + + CPLD_WRITE(system_rst, 1); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + CPLD_WRITE(global_rst, 1); +} + +void cpld_set_nand(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_NAND; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} + +void cpld_set_sd(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_SD; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); + printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); + printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); + printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); + printf("vbank = %x\n", CPLD_READ(vbank)); + printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); + printf("uart_sel = %x\n", CPLD_READ(uart_sel)); + printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); + printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); + printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); + printf("status_led = %x\n", CPLD_READ(status_led)); + putc('\n'); +} +#endif + +void cpld_rev_bit(unsigned char *value) +{ + u8 rev_val, val; + int i; + + val = *value; + rev_val = val & 1; + for (i = 1; i <= 7; i++) { + val >>= 1; + rev_val <<= 1; + rev_val |= val & 1; + } + + *value = rev_val; +} + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else if (strcmp(argv[2], "nand") == 0) + cpld_set_nand(); + else if (strcmp(argv[2], "sd") == 0) + cpld_set_sd(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" + "cpld reset nand: reset to boot from NAND flash\n" + "cpld reset sd: reset to boot from SD card\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif +); diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h new file mode 100644 index 0000000000..bd59c0e5d5 --- /dev/null +++ b/board/freescale/ls1043ardb/cpld.h @@ -0,0 +1,45 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CPLD_H__ +#define __CPLD_H__ + +/* + * CPLD register set of LS1043ARDB board-specific. + */ +struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ + u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */ + u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */ + u8 vbank; /* 0x7 - Flash bank selection Control */ + u8 sysclk_sel; /* 0x8 - */ + u8 uart_sel; /* 0x9 - */ + u8 sd1refclk_sel; /* 0xA - */ + u8 tdmclk_mux_sel; /* 0xB - */ + u8 sdhc_spics_sel; /* 0xC - */ + u8 status_led; /* 0xD - */ + u8 global_rst; /* 0xE - */ +}; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); +void cpld_rev_bit(unsigned char *value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_SW_MUX_BANK_SEL 0x40 +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NAND 0x106 +#define CPLD_CFG_RCW_SRC_SD 0x040 +#endif diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c new file mode 100644 index 0000000000..b181579e8e --- /dev/null +++ b/board/freescale/ls1043ardb/ddr.c @@ -0,0 +1,191 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include "ddr.h" +#ifdef CONFIG_FSL_DEEP_SLEEP +#include <fsl_sleep.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +} + +/* DDR model number: MT40A512M8HX-093E */ +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 2147483648u, + .capacity = 2147483648u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .bank_addr_bits = 0, + .bank_group_bits = 2, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 938, + .tckmax_ps = 1500, + .caslat_x = 0x000DFA00, + .taa_ps = 13500, + .trcd_ps = 13500, + .trp_ps = 13500, + .tras_ps = 33000, + .trc_ps = 46500, + .trfc1_ps = 260000, + .trfc2_ps = 160000, + .trfc4_ps = 110000, + .tfaw_ps = 21000, + .trrds_ps = 3700, + .trrdl_ps = 5300, + .tccdl_ps = 5355, + .refresh_rate_ps = 7800000, + .dq_mapping[0] = 0x0, + .dq_mapping[1] = 0x0, + .dq_mapping[2] = 0x0, + .dq_mapping[3] = 0x0, + .dq_mapping[4] = 0x0, + .dq_mapping[5] = 0x0, + .dq_mapping[6] = 0x0, + .dq_mapping[7] = 0x0, + .dq_mapping[8] = 0x0, + .dq_mapping[9] = 0x0, + .dq_mapping[10] = 0x0, + .dq_mapping[11] = 0x0, + .dq_mapping[12] = 0x0, + .dq_mapping[13] = 0x0, + .dq_mapping[14] = 0x0, + .dq_mapping[15] = 0x0, + .dq_mapping[16] = 0x0, + .dq_mapping[17] = 0x0, + .dq_mapping_ors = 0, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + static const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) + puts("Initializing DDR....\n"); + dram_size = fsl_ddr_sdram(); +#else + dram_size = fsl_ddr_sdram_size(); +#endif +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + return dram_size; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h new file mode 100644 index 0000000000..b17eb80885 --- /dev/null +++ b/board/freescale/ls1043ardb/ddr.h @@ -0,0 +1,45 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,}, + {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,}, + {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,}, +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c new file mode 100644 index 0000000000..61f2b5d447 --- /dev/null +++ b/board/freescale/ls1043ardb/eth.c @@ -0,0 +1,77 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_dtsec.h> +#include <fsl_mdio.h> +#include <malloc.h> + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); + + switch (srds_s1) { + case 0x1455: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + fm_info_set_mdio(i, dev); + + /* XFI on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(FM1_10GEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c new file mode 100644 index 0000000000..9032ed36c8 --- /dev/null +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -0,0 +1,142 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_ifc.h> +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; +#ifndef CONFIG_SD_BOOT + u8 cfg_rcw_src1, cfg_rcw_src2; + u32 cfg_rcw_src; +#endif + u32 sd1refclk_sel; + + printf("Board: LS1043ARDB, boot from "); + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x25) + printf("vBank %d\n", CPLD_READ(vbank)); + else if (cfg_rcw_src == 0x106) + puts("NAND\n"); + else + printf("Invalid setting of SW4\n"); +#endif + + printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); + + puts("SERDES Reference Clocks:\n"); + sd1refclk_sel = CPLD_READ(sd1refclk_sel); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = initdram(0); + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_FSL_IFC + init_final_memctl_regs(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int config_board_mux(void) +{ + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + config_board_mux(); + + return 0; +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + return 0; +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg new file mode 100644 index 0000000000..f072274f47 --- /dev/null +++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg @@ -0,0 +1,14 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#flush PBI data +096100c0 000fffff diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg new file mode 100644 index 0000000000..935ffc0102 --- /dev/null +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0810000f 0c000000 00000000 00000000 +14550002 80004012 e0106000 61002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg new file mode 100644 index 0000000000..28cd95859d --- /dev/null +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0810000f 0c000000 00000000 00000000 +14550002 80004012 60040000 61002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2085a/Kconfig index f51afc8234..042f85b367 100644 --- a/board/freescale/ls2085a/Kconfig +++ b/board/freescale/ls2085a/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "freescale" config SYS_SOC - default "fsl-lsch3" + default "fsl-layerscape" config SYS_CONFIG_NAME default "ls2085a_emu" @@ -23,7 +23,7 @@ config SYS_VENDOR default "freescale" config SYS_SOC - default "fsl-lsch3" + default "fsl-layerscape" config SYS_CONFIG_NAME default "ls2085a_simu" diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index 73c44102c4..27481e2ba3 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -15,7 +15,7 @@ #include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> #include <environment.h> -#include <asm/arch-fsl-lsch3/soc.h> +#include <asm/arch/soc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2085aqds/Kconfig index deb640d474..8d6acbac93 100644 --- a/board/freescale/ls2085aqds/Kconfig +++ b/board/freescale/ls2085aqds/Kconfig @@ -8,7 +8,7 @@ config SYS_VENDOR default "freescale" config SYS_SOC - default "fsl-lsch3" + default "fsl-layerscape" config SYS_CONFIG_NAME default "ls2085aqds" diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c index 007b433d81..b8a2bf49e6 100644 --- a/board/freescale/ls2085aqds/eth.c +++ b/board/freescale/ls2085aqds/eth.c @@ -8,7 +8,6 @@ #include <netdev.h> #include <asm/io.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> #include <hwconfig.h> #include <fsl_mdio.h> #include <malloc.h> diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c index 2315bdb130..b02d6e86b4 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2085aqds/ls2085aqds.c @@ -17,7 +17,7 @@ #include <environment.h> #include <i2c.h> #include <rtc.h> -#include <asm/arch-fsl-lsch3/soc.h> +#include <asm/arch/soc.h> #include <hwconfig.h> #include "../common/qixis.h" diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2085ardb/Kconfig index 85a3dcdc45..cb40db9b55 100644 --- a/board/freescale/ls2085ardb/Kconfig +++ b/board/freescale/ls2085ardb/Kconfig @@ -8,7 +8,7 @@ config SYS_VENDOR default "freescale" config SYS_SOC - default "fsl-lsch3" + default "fsl-layerscape" config SYS_CONFIG_NAME default "ls2085ardb" diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c index 0a1163ab8e..d578757dfd 100644 --- a/board/freescale/ls2085ardb/eth_ls2085rdb.c +++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c @@ -16,7 +16,6 @@ #include <asm/io.h> #include <exports.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> #include <fsl-mc/ldpaa_wriop.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c index 5e7997c869..18953b8ecb 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2085ardb/ls2085ardb.c @@ -17,7 +17,7 @@ #include <fsl-mc/fsl_mc.h> #include <environment.h> #include <i2c.h> -#include <asm/arch-fsl-lsch3/soc.h> +#include <asm/arch/soc.h> #include "../common/qixis.h" #include "ls2085ardb_qixis.h" diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c index 56f561a505..074b71326f 100644 --- a/board/freescale/p1023rdb/p1023rdb.c +++ b/board/freescale/p1023rdb/p1023rdb.c @@ -26,7 +26,7 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 532eeac84b..95fe85bbfa 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -19,7 +19,7 @@ #include <fm_eth.h> #include <fsl_mdio.h> #include <malloc.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include "cpld.h" #include "../common/fman.h" diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c index 441d6a3e61..99c23f79f4 100644 --- a/board/freescale/t102xqds/eth_t102xqds.c +++ b/board/freescale/t102xqds/eth_t102xqds.c @@ -21,7 +21,7 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <asm/fsl_serdes.h> #include "../common/qixis.h" #include "../common/fman.h" diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 856ec6e227..02b283d26f 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -21,7 +21,7 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <asm/fsl_serdes.h> #include "../common/fman.h" diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 8c8293426b..8bf34fa79a 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -17,7 +17,7 @@ #include <fm_eth.h> #include <fsl_mdio.h> #include <malloc.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <vsc9953.h> #include "../common/fman.h" diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 2fb4105275..86de26cc9d 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -44,3 +44,4 @@ void cpld_write(unsigned int reg, u8 value); cpld_write(offsetof(struct cpld_data, reg), value) #define MISC_CTL_SG_SEL 0x80 #define MISC_CTL_AURORA_SEL 0x02 +#define MISC_MUX_QE_TDM 0xc0 diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 71d0457d43..52cd112249 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -11,7 +11,7 @@ #include <fm_eth.h> #include <fsl_mdio.h> #include <malloc.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <vsc9953.h> #include "../common/fman.h" diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index d982dfc872..322765288b 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -6,12 +6,14 @@ #include <common.h> #include <command.h> +#include <hwconfig.h> #include <netdev.h> #include <linux/compiler.h> #include <asm/mmu.h> #include <asm/processor.h> #include <asm/cache.h> #include <asm/immap_85xx.h> +#include <asm/fsl_fdt.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> @@ -110,6 +112,12 @@ int misc_init_r(void) MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); #if defined(CONFIG_T1040D4RDB) + if (hwconfig("qe-tdm")) { + CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | + MISC_MUX_QE_TDM); + printf("QECSR : 0x%02x, mux to qe-tdm\n", + CPLD_READ(sfp_ctl_status)); + } /* Mask all CPLD interrupt sources, except QSGMII interrupts */ if (CPLD_READ(sw_ver) < 0x03) { debug("CPLD SW version 0x%02x doesn't support int_mask\n", @@ -149,5 +157,7 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); #endif + if (hwconfig("qe-tdm")) + fdt_del_diu(blob); return 0; } diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index b82e9e7540..1c0ce2492c 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -21,7 +21,7 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <asm/fsl_serdes.h> #include <hwconfig.h> #include "../common/qixis.h" diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index cbbc625831..ea51195698 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -21,7 +21,7 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <asm/fsl_serdes.h> int board_eth_init(bd_t *bis) diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 9b416b138a..2dfdcbbd39 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -21,7 +21,7 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <asm/fsl_serdes.h> #include <hwconfig.h> #include "../common/qixis.h" diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index 879bd1a347..e563a6169a 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -23,7 +23,7 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <asm/fsl_serdes.h> #include <hwconfig.h> diff --git a/board/gdsys/p1022/Makefile b/board/gdsys/p1022/Makefile index 6e02447987..482a9aa15c 100644 --- a/board/gdsys/p1022/Makefile +++ b/board/gdsys/p1022/Makefile @@ -1,10 +1,7 @@ # # Copyright 2010 Freescale Semiconductor, Inc. # -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by the Free -# Software Foundation; either version 2 of the License, or (at your option) -# any later version. +# SPDX-License-Identifier: GPL-2.0+ # obj-y += law.o diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile index 44b7c0ae43..fd0c2f9d16 100644 --- a/board/intercontrol/digsy_mtc/Makefile +++ b/board/intercontrol/digsy_mtc/Makefile @@ -1,6 +1,8 @@ # # Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com # +# SPDX-License-Identifier: GPL-2.0+ +# obj-y := digsy_mtc.o cmd_mtc.o obj-$(CONFIG_VIDEO) += cmd_disp.o diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 69f5be3b9c..919133b7d3 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -77,7 +77,7 @@ int drv_keyboard_init(void) int error; struct stdio_dev dev = { .name = "button", - .flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM, + .flags = DEV_FLAGS_INPUT, .start = novena_gpio_button_init, .getc = novena_gpio_button_getc, .tstc = novena_gpio_button_tstc, diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c index 99de2cad66..1da72c5398 100644 --- a/board/mpl/common/kbd.c +++ b/board/mpl/common/kbd.c @@ -203,7 +203,7 @@ int drv_isa_kbd_init (void) return -1; memset (&kbddev, 0, sizeof(kbddev)); strcpy(kbddev.name, DEVNAME); - kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.flags = DEV_FLAGS_INPUT; kbddev.getc = kbd_getc ; kbddev.tstc = kbd_testc ; diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index b9d88ee17e..958cdec136 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -566,7 +566,7 @@ void pci_con_connect(void) irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL); memset (&pci_con_dev, 0, sizeof (pci_con_dev)); strcpy (pci_con_dev.name, "pci_con"); - pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; pci_con_dev.putc = pci_con_putc; pci_con_dev.puts = pci_con_puts; pci_con_dev.getc = pci_con_getc; diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile index 1f7c31d64b..ef5dd136b4 100644 --- a/board/nvidia/beaver/Makefile +++ b/board/nvidia/beaver/Makefile @@ -1,17 +1,7 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. +# SPDX-License-Identifier: GPL-2.0 # obj-y = ../cardhu/cardhu.o diff --git a/board/nvidia/dalmore/Makefile b/board/nvidia/dalmore/Makefile index 7cdff9c61b..c9d76e88f1 100644 --- a/board/nvidia/dalmore/Makefile +++ b/board/nvidia/dalmore/Makefile @@ -1,17 +1,7 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. +# SPDX-License-Identifier: GPL-2.0 # obj-y := dalmore.o diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 6cbd90661b..ef1a8f318f 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -11,5 +11,8 @@ obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_BOARD_COMMON) += board.o -obj-$(CONFIG_EXYNOS5_DT) += exynos5-dt.o +ifdef CONFIG_EXYNOS5_DT +obj-y += exynos5-dt.o +obj-$(CONFIG_BOARD_TYPES) += exynos5-dt-types.o +endif endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index d32c75de50..1334c22ddd 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -304,8 +304,8 @@ int checkboard(void) printf("Board: %s\n", board_info ? board_info : "unknown"); #ifdef CONFIG_BOARD_TYPES board_info = get_board_type(); - - printf("Model: %s\n", board_info ? board_info : "unknown"); + if (board_info) + printf("Type: %s\n", board_info); #endif return 0; } diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c new file mode 100644 index 0000000000..48fd1f7d96 --- /dev/null +++ b/board/samsung/common/exynos5-dt-types.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <adc.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/s2mps11.h> +#include <samsung/exynos5-dt-types.h> +#include <samsung/misc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct udevice_id board_ids[] = { + { .compatible = "samsung,odroidxu3", .data = EXYNOS5_BOARD_ODROID_XU3 }, + { .compatible = "samsung,exynos5", .data = EXYNOS5_BOARD_GENERIC }, + { }, +}; + +/** + * Odroix XU3/4 board revisions: + * Rev ADCmax Board + * 0.1 0 XU3 0.1 + * 0.2 410 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231) + * 0.3 1408 XU4 0.1 + * Use +10 % for ADC value tolerance. + */ +struct odroid_rev_info odroid_info[] = { + { EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" }, + { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 410, "xu3" }, + { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1408, "xu4" }, + { EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" }, +}; + +static unsigned int odroid_get_rev(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { + if (odroid_info[i].board_type == gd->board_type) + return odroid_info[i].board_rev; + } + + return 0; +} + +static int odroid_get_board_type(void) +{ + unsigned int adcval; + int ret, i; + + ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN, &adcval); + if (ret) + goto rev_default; + + for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { + /* ADC tolerance: +20 % */ + if (adcval < odroid_info[i].adc_val) + return odroid_info[i].board_type; + } + +rev_default: + return EXYNOS5_BOARD_ODROID_XU3; +} + +/** + * odroid_get_type_str - returns pointer to one of the board type string. + * Board types: "xu3", "xu3-lite", "xu4". However the "xu3lite" can be + * detected only when the i2c controller is ready to use. Fortunately, + * XU3 and XU3L are compatible, and the information about board lite + * revision is needed before booting the linux, to set proper environment + * variable: $fdtfile. + */ +static const char *odroid_get_type_str(void) +{ + const char *type_xu3l = "xu3-lite"; + struct udevice *dev, *chip; + int i, ret; + + if (gd->board_type != EXYNOS5_BOARD_ODROID_XU3_REV02) + goto exit; + + ret = pmic_get("s2mps11", &dev); + if (ret) + goto exit; + + /* Enable LDO26: 3.0V */ + ret = pmic_reg_write(dev, S2MPS11_REG_L26CTRL, + S2MPS11_LDO26_ENABLE); + if (ret) + goto exit; + + /* Check XU3Lite by probe INA231 I2C0:0x40 */ + ret = uclass_get_device(UCLASS_I2C, 0, &dev); + if (ret) + goto exit; + + ret = dm_i2c_probe(dev, 0x40, 0x0, &chip); + if (ret) + return type_xu3l; + +exit: + for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { + if (odroid_info[i].board_type == gd->board_type) + return odroid_info[i].name; + } + + return NULL; +} + +bool board_is_odroidxu3(void) +{ + if (gd->board_type >= EXYNOS5_BOARD_ODROID_XU3 && + gd->board_type <= EXYNOS5_BOARD_ODROID_XU3_REV02) + return true; + + return false; +} + +bool board_is_odroidxu4(void) +{ + if (gd->board_type == EXYNOS5_BOARD_ODROID_XU4_REV01) + return true; + + return false; +} + +bool board_is_generic(void) +{ + if (gd->board_type == EXYNOS5_BOARD_GENERIC) + return true; + + return false; +} + +/** + * get_board_rev() - return detected board revision. + * + * @return: return board revision number for XU3 or 0 for generic + */ +u32 get_board_rev(void) +{ + if (board_is_generic()) + return 0; + + return odroid_get_rev(); +} + +/** + * get_board_type() - returns board type string. + * + * @return: return board type string for XU3 or empty string for generic + */ +const char *get_board_type(void) +{ + const char *generic = ""; + + if (board_is_generic()) + return generic; + + return odroid_get_type_str(); +} + +/** + * set_board_type() - set board type in gd->board_type. + * As default type set EXYNOS5_BOARD_GENERIC, if detect Odroid, + * then set its proper type. + */ +void set_board_type(void) +{ + const struct udevice_id *of_match = board_ids; + int ret; + + gd->board_type = EXYNOS5_BOARD_GENERIC; + + while (of_match->compatible) { + ret = fdt_node_check_compatible(gd->fdt_blob, 0, + of_match->compatible); + if (ret) + of_match++; + + gd->board_type = of_match->data; + break; + } + + /* If Odroid, then check its revision */ + if (board_is_odroidxu3()) + gd->board_type = odroid_get_board_type(); +} diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 4250f722da..4d9e151756 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -27,7 +27,10 @@ #include <power/pmic.h> #include <power/max77686_pmic.h> #include <power/regulator.h> +#include <power/s2mps11.h> #include <power/s5m8767.h> +#include <samsung/exynos5-dt-types.h> +#include <samsung/misc.h> #include <tmu.h> DECLARE_GLOBAL_DATA_PTR; @@ -335,15 +338,24 @@ int board_usb_init(int index, enum usb_init_type init) #ifdef CONFIG_SET_DFU_ALT_INFO char *get_dfu_alt_system(char *interface, char *devstr) { + char *info = "Not supported!"; + + if (board_is_odroidxu4()) + return info; + return getenv("dfu_alt_system"); } char *get_dfu_alt_boot(char *interface, char *devstr) { + char *info = "Not supported!"; struct mmc *mmc; char *alt_boot; int dev_num; + if (board_is_odroidxu4()) + return info; + dev_num = simple_strtoul(devstr, NULL, 10); mmc = find_mmc_device(dev_num); diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index e0e2c48632..da0d4db1f9 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -85,6 +85,9 @@ void set_board_info(void) #ifdef CONFIG_BOARD_TYPES bdtype = get_board_type(); + if (!bdtype) + bdtype = ""; + sprintf(info, "%s%s", bdname, bdtype); setenv("boardname", info); #endif @@ -256,9 +259,9 @@ static int mode_leave_menu(int mode) cmd = find_cmd(mode_name[mode][1]); if (cmd) { printf("Enter: %s %s\n", mode_name[mode][0], - mode_info[mode]); + mode_info[mode]); lcd_printf("\n\n\t%s %s\n", mode_name[mode][0], - mode_info[mode]); + mode_info[mode]); lcd_puts("\n\tDo not turn off device before finish!\n"); cmd_result = run_command(mode_cmd[mode], 0); @@ -315,8 +318,7 @@ static void display_download_menu(int mode) for (i = 0; i <= BOOT_MODE_EXIT; i++) lcd_printf("\t%s %s - %s\n\n", selection[i], - mode_name[i][0], - mode_info[i]); + mode_name[i][0], mode_info[i]); } static void download_menu(void) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 32155f1184..36d493d514 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -33,13 +33,6 @@ enum { ODROID_TYPES, }; -static const char *mmc_regulators[] = { - "VDDQ_EMMC_1.8V", - "VDDQ_EMMC_2.8V", - "TFLASH_2.8V", - NULL, -}; - void set_board_type(void) { /* Set GPA1 pin 1 to HI - enable XCL205 output */ @@ -428,6 +421,13 @@ int exynos_init(void) int exynos_power_init(void) { + const char *mmc_regulators[] = { + "VDDQ_EMMC_1.8V", + "VDDQ_EMMC_2.8V", + "TFLASH_2.8V", + NULL, + }; + if (regulator_list_autoset(mmc_regulators, NULL, true)) error("Unable to init all mmc regulators"); @@ -450,7 +450,6 @@ static int s5pc210_phy_control(int on) return regulator_set_mode(dev, OPMODE_ON); else return regulator_set_mode(dev, OPMODE_LPM); - } struct s3c_plat_otg_data s5pc210_otg_data = { diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index b75a0e34dd..6e678c744b 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -18,11 +18,11 @@ DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#if (FCLK_SPEED == 0) /* Fout = 203MHz, Fin = 12MHz for Audio */ #define M_MDIV 0xC3 #define M_PDIV 0x4 #define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ +#elif (FCLK_SPEED == 1) /* Fout = 202.8MHz */ #define M_MDIV 0xA1 #define M_PDIV 0x3 #define M_SDIV 0x1 @@ -30,11 +30,11 @@ DECLARE_GLOBAL_DATA_PTR; #define USB_CLOCK 1 -#if USB_CLOCK==0 +#if (USB_CLOCK == 0) #define U_M_MDIV 0xA1 #define U_M_PDIV 0x3 #define U_M_SDIV 0x1 -#elif USB_CLOCK==1 +#elif (USB_CLOCK == 1) #define U_M_MDIV 0x48 #define U_M_PDIV 0x3 #define U_M_SDIV 0x2 @@ -44,7 +44,7 @@ static inline void pll_delay(unsigned long loops) { __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); + "bne 1b" : "=r" (loops) : "0" (loops)); } /* diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index cb7f9b0ac8..fc0e8d252b 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -55,16 +55,16 @@ int dram_init(void) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); } diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile index 9e37ebbb92..293cf5f65b 100644 --- a/board/seco/common/Makefile +++ b/board/seco/common/Makefile @@ -1,2 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# obj-$(CONFIG_TARGET_SECOMX6) += mx6.o diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS index c99e06dc10..7dc2b83839 100644 --- a/board/ti/am335x/MAINTAINERS +++ b/board/ti/am335x/MAINTAINERS @@ -6,6 +6,7 @@ F: include/configs/am335x_evm.h F: configs/am335x_boneblack_defconfig F: configs/am335x_boneblack_vboot_defconfig F: configs/am335x_evm_defconfig +F: configs/am335x_gp_evm_defconfig F: configs/am335x_evm_nor_defconfig F: configs/am335x_evm_norboot_defconfig F: configs/am335x_evm_spiboot_defconfig diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS index 3d40b171d2..96ef85b462 100644 --- a/board/ti/am43xx/MAINTAINERS +++ b/board/ti/am43xx/MAINTAINERS @@ -7,3 +7,5 @@ F: configs/am43xx_evm_defconfig F: configs/am43xx_evm_qspiboot_defconfig F: configs/am43xx_evm_ethboot_defconfig F: configs/am43xx_evm_usbhost_boot_defconfig +F: configs/am437x_gp_evm_defconfig +F: configs/am437x_sk_evm_defconfig diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS index 5ec67697cf..3f638d0a7e 100644 --- a/board/ti/dra7xx/MAINTAINERS +++ b/board/ti/dra7xx/MAINTAINERS @@ -3,6 +3,8 @@ M: Lokesh Vutla <lokeshvutla@ti.com> S: Maintained F: board/ti/dra7xx/ F: include/configs/dra7xx_evm.h +F: configs/dra72_evm_defconfig +F: configs/dra74_evm_defconfig F: configs/dra7xx_evm_defconfig F: configs/dra7xx_evm_qspiboot_defconfig F: configs/dra7xx_evm_uart3_defconfig diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index b77ae56c51..44dfafae29 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -47,7 +47,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/board/varisys/common/Makefile b/board/varisys/common/Makefile new file mode 100644 index 0000000000..1e6dcbb6de --- /dev/null +++ b/board/varisys/common/Makefile @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +# necessary to create built-in.o +obj- := __dummy__.o +else +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o +endif +endif diff --git a/board/varisys/common/eeprom.h b/board/varisys/common/eeprom.h new file mode 100644 index 0000000000..004816a0fd --- /dev/null +++ b/board/varisys/common/eeprom.h @@ -0,0 +1,6 @@ +/* EEPROM init functions for Cyrus */ + + +void init_eeprom(int bus_num, int addr, int addr_len); +void mac_read_from_fixed_id(void); +int mac_read_from_eeprom_common(void); diff --git a/board/varisys/common/sys_eeprom.c b/board/varisys/common/sys_eeprom.c new file mode 100644 index 0000000000..b55ab818e6 --- /dev/null +++ b/board/varisys/common/sys_eeprom.c @@ -0,0 +1,498 @@ +/* + * Based on board/freescale/common/sys_eeprom.c + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor + * + * This defines the API for storing board information in the + * eeprom. It has been adapted from an earlier version of the + * Freescale API, but has a number of key differences. Because + * the two APIs are independent and may diverge further, the + * Varisys version of the API is implemented separately here. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <linux/ctype.h> + +#include "eeprom.h" + +#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC +#define MAX_NUM_PORTS CONFIG_SYS_I2C_EEPROM_NXID_MAC +#else +#define MAX_NUM_PORTS 8 +#endif +#define NXID_VERSION 0 + +/** + * static eeprom: EEPROM layout for NXID formats + * + * See Freescale application note AN3638 for details. + */ +static struct __attribute__ ((__packed__)) eeprom { + u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */ + u8 sn[12]; /* 0x04 - 0x0F Serial Number */ + u8 errata[5]; /* 0x10 - 0x14 Errata Level */ + u8 date[6]; /* 0x15 - 0x1a Build Date */ + u8 res_0; /* 0x1b Reserved */ + u32 version; /* 0x1c - 0x1f NXID Version */ + u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */ + u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */ + u8 tempcalflags; /* 0x2a Temperature Calibration Flags */ + u8 res_1[21]; /* 0x2b - 0x3f Reserved */ + u8 mac_count; /* 0x40 Number of MAC addresses */ + u8 mac_flag; /* 0x41 MAC table flags */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ + u32 crc; /* x+1 CRC32 checksum */ +} e; + +/* Set to 1 if we've read EEPROM into memory */ +static int has_been_read; + +/* Is this a valid NXID EEPROM? */ +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) + +/** Fixed ID field in EEPROM */ +static unsigned char uid[16]; + +static int eeprom_bus_num = -1; +static int eeprom_addr; +static int eeprom_addr_len; + +/** + * This must be called before any eeprom access. + */ +void init_eeprom(int bus_num, int addr, int addr_len) +{ + eeprom_bus_num = bus_num; + eeprom_addr = addr; + eeprom_addr_len = addr_len; +} + +/** + * show_eeprom - display the contents of the EEPROM + */ +void show_eeprom(void) +{ + int i; + unsigned int crc; + + /* EEPROM tag ID, either CCID or NXID */ + printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], + be32_to_cpu(e.version)); + + /* Serial number */ + printf("SN: %s\n", e.sn); + + printf("UID: "); + for (i = 0; i < 16; i++) + printf("%02x", uid[i]); + printf("\n"); + + /* Errata level. */ + printf("Errata: %s\n", e.errata); + + /* Build date, BCD date values, as YYMMDDhhmmss */ + printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", + e.date[0], e.date[1], e.date[2], + e.date[3] & 0x7F, e.date[4], e.date[5], + e.date[3] & 0x80 ? "PM" : ""); + + /* Show MAC addresses */ + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { + u8 *p = e.mac[i]; + + printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i, + p[0], p[1], p[2], p[3], p[4], p[5]); + } + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + + if (crc == be32_to_cpu(e.crc)) + printf("CRC: %08x\n", be32_to_cpu(e.crc)); + else + printf("CRC: %08x (should be %08x)\n", + be32_to_cpu(e.crc), crc); + +#ifdef DEBUG + printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); + for (i = 0; i < sizeof(e); i++) { + if ((i % 16) == 0) + printf("%02X: ", i); + printf("%02X ", ((u8 *)&e)[i]); + if (((i % 16) == 15) || (i == sizeof(e) - 1)) + printf("\n"); + } +#endif +} + +/** + * read_eeprom - read the EEPROM into memory + */ +int read_eeprom(void) +{ + int ret; + unsigned int bus; + + if (eeprom_bus_num < 0) { + printf("EEPROM not configured\n"); + return -1; + } + + if (has_been_read) + return 0; + + bus = i2c_get_bus_num(); + i2c_set_bus_num(eeprom_bus_num); + + ret = i2c_read(eeprom_addr, 0, eeprom_addr_len, + (void *)&e, sizeof(e)); + + + /* Fixed address of ID field */ + i2c_read(0x5f, 0x80, 1, uid, 16); + + i2c_set_bus_num(bus); + +#ifdef DEBUG + show_eeprom(); +#endif + + has_been_read = (ret == 0) ? 1 : 0; + + return ret; +} + +/** + * update_crc - update the CRC + * + * This function should be called after each update to the EEPROM structure, + * to make sure the CRC is always correct. + */ +static void update_crc(void) +{ + u32 crc, crc_offset = offsetof(struct eeprom, crc); + + crc = crc32(0, (void *)&e, crc_offset); + e.crc = cpu_to_be32(crc); +} + +/** + * prog_eeprom - write the EEPROM from memory + */ +static int prog_eeprom(void) +{ + int ret = 0; + int i; + void *p; + unsigned int bus; + + if (eeprom_bus_num < 0) { + printf("EEPROM not configured\n"); + return -1; + } + + /* Set the reserved values to 0xFF */ + e.res_0 = 0xFF; + memset(e.res_1, 0xFF, sizeof(e.res_1)); + update_crc(); + + bus = i2c_get_bus_num(); + i2c_set_bus_num(eeprom_bus_num); + + /* + * The AT24C02 datasheet says that data can only be written in page + * mode, which means 8 bytes at a time, and it takes up to 5ms to + * complete a given write. + */ + for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { + ret = i2c_write(eeprom_addr, i, eeprom_addr_len, + p, min((int)(sizeof(e) - i), 8)); + if (ret) + break; + udelay(5000); /* 5ms write cycle timing */ + } + + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct eeprom e2; + + ret = i2c_read(eeprom_addr, 0, + eeprom_addr_len, (void *)&e2, sizeof(e2)); + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + + i2c_set_bus_num(bus); + + if (ret) { + printf("Programming failed.\n"); + has_been_read = 0; + return -1; + } + + printf("Programming passed.\n"); + return 0; +} + +/** + * h2i - converts hex character into a number + * + * This function takes a hexadecimal character (e.g. '7' or 'C') and returns + * the integer equivalent. + */ +static inline u8 h2i(char p) +{ + if ((p >= '0') && (p <= '9')) + return p - '0'; + + if ((p >= 'A') && (p <= 'F')) + return (p - 'A') + 10; + + if ((p >= 'a') && (p <= 'f')) + return (p - 'a') + 10; + + return 0; +} + +/** + * set_date - stores the build date into the EEPROM + * + * This function takes a pointer to a string in the format "YYMMDDhhmmss" + * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, + * and stores it in the build date field of the EEPROM local copy. + */ +static void set_date(const char *string) +{ + unsigned int i; + + if (strlen(string) != 12) { + printf("Usage: mac date YYMMDDhhmmss\n"); + return; + } + + for (i = 0; i < 6; i++) + e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); + + update_crc(); +} + +/** + * set_mac_address - stores a MAC address into the EEPROM + * + * This function takes a pointer to MAC address string + * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and + * stores it in one of the MAC address fields of the EEPROM local copy. + */ +static void set_mac_address(unsigned int index, const char *string) +{ + char *p = (char *)string; + unsigned int i; + + if ((index >= MAX_NUM_PORTS) || !string) { + printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n"); + return; + } + + for (i = 0; *p && (i < 6); i++) { + e.mac[index][i] = simple_strtoul(p, &p, 16); + if (*p == ':') + p++; + } + + update_crc(); +} + +int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char cmd; + + if (argc == 1) { + show_eeprom(); + return 0; + } + + cmd = argv[1][0]; + + if (cmd == 'r') { + read_eeprom(); + return 0; + } + + if (cmd == 'i') { + memcpy(e.id, "NXID", sizeof(e.id)); + e.version = NXID_VERSION; + update_crc(); + return 0; + } + + if (!is_valid) { + printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n"); + return 0; + } + + if (argc == 2) { + switch (cmd) { + case 's': /* save */ + prog_eeprom(); + break; + default: + return cmd_usage(cmdtp); + } + + return 0; + } + + /* We know we have at least one parameter */ + + switch (cmd) { + case 'n': /* serial number */ + memset(e.sn, 0, sizeof(e.sn)); + strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); + update_crc(); + break; + case 'e': /* errata */ + memset(e.errata, 0, 5); + strncpy((char *)e.errata, argv[2], 4); + update_crc(); + break; + case 'd': /* date BCD format YYMMDDhhmmss */ + set_date(argv[2]); + break; + case 'p': /* MAC table size */ + e.mac_count = simple_strtoul(argv[2], NULL, 16); + update_crc(); + break; + case '0' ... '9': /* "mac 0" through "mac 22" */ + set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]); + break; + case 'h': /* help */ + default: + return cmd_usage(cmdtp); + } + + return 0; +} + +int mac_read_from_generic_eeprom(const char *envvar, int chip, + int address, int mac_bus) +{ + int ret; + unsigned int bus; + unsigned char mac[6]; + char ethaddr[18]; + + bus = i2c_get_bus_num(); + i2c_set_bus_num(mac_bus); + + ret = i2c_read(chip, address, 1, mac, 6); + + i2c_set_bus_num(bus); + + if (!ret) { + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + mac[0], + mac[1], + mac[2], + mac[3], + mac[4], + mac[5]); + + printf("MAC: %s\n", ethaddr); + setenv(envvar, ethaddr); + } + + return ret; +} + +void mac_read_from_fixed_id(void) +{ +#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR + mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR, + CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS); +#endif +#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR + mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR, + CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS); +#endif +} + +/** + * mac_read_from_eeprom - read the MAC addresses from EEPROM + * + * This function reads the MAC addresses from EEPROM and sets the + * appropriate environment variables for each one read. + * + * The environment variables are only set if they haven't been set already. + * This ensures that any user-saved variables are never overwritten. + * + * This function must be called after relocation. + * + * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0 + * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is + * located at a different offset. + */ +int mac_read_from_eeprom_common(void) +{ + unsigned int i; + u32 crc, crc_offset = offsetof(struct eeprom, crc); + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ + + puts("EEPROM: "); + + if (read_eeprom()) { + printf("Read failed.\n"); + return 0; + } + + if (!is_valid) { + printf("Invalid ID (%02x %02x %02x %02x)\n", + e.id[0], e.id[1], e.id[2], e.id[3]); + return 0; + } + + crc = crc32(0, (void *)&e, crc_offset); + crcp = (void *)&e + crc_offset; + if (crc != be32_to_cpu(*crcp)) { + printf("CRC mismatch (%08x != %08x)\n", crc, + be32_to_cpu(e.crc)); + return 0; + } + + /* + * MAC address #9 in v1 occupies the same position as the CRC in v0. + * Erase it so that it's not mistaken for a MAC address. We'll + * update the CRC later. + */ + if (e.version == 0) + memset(e.mac[8], 0xff, 6); + + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { + if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && + memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { + char ethaddr[18]; + char enetvar[9]; + + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + e.mac[i][0], + e.mac[i][1], + e.mac[i][2], + e.mac[i][3], + e.mac[i][4], + e.mac[i][5]); + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!getenv(enetvar)) + setenv(enetvar, ethaddr); + } + } + + printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], + be32_to_cpu(e.version)); + + return 0; +} diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig new file mode 100644 index 0000000000..d9ea7ef89c --- /dev/null +++ b/board/varisys/cyrus/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CYRUS + +config SYS_BOARD + default "cyrus" + +config SYS_VENDOR + default "varisys" + +config SYS_CONFIG_NAME + default "cyrus" + +endif diff --git a/board/varisys/cyrus/MAINTAINERS b/board/varisys/cyrus/MAINTAINERS new file mode 100644 index 0000000000..53b4a886bd --- /dev/null +++ b/board/varisys/cyrus/MAINTAINERS @@ -0,0 +1,7 @@ +Cyrus BOARD +M: Andy Fleming <afleming@gmail.com> +S: Maintained +F: board/varisys/cyrus/ +F: include/configs/cyrus.h +F: configs/Cyrus_P5020_defconfig +F: configs/Cyrus_P5040_defconfig diff --git a/board/varisys/cyrus/Makefile b/board/varisys/cyrus/Makefile new file mode 100644 index 0000000000..a7978a0d53 --- /dev/null +++ b/board/varisys/cyrus/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += $(BOARD).o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/varisys/cyrus/README b/board/varisys/cyrus/README new file mode 100644 index 0000000000..9595dcb7cc --- /dev/null +++ b/board/varisys/cyrus/README @@ -0,0 +1,19 @@ +Rebuilding u-boot for Cyrus + +The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig. + +They currently disable size optimization in order to avoid a relocation +bug in some versions of GCC. As the output size is a constant, the size +optimization is not currently important. + +Cyrus boots off a microSD card in a slot on the motherboard. This requires +that the u-boot is built for the Pre-Boot Loader on the P5020/P5040. +In order to reflash u-boot, you must download u-boot.pbl, then write it +onto the card. To do that from u-boot: + +> tftp 1000000 u-boot.pbl +> mmc write 1000000 8 672 + +If you want to do this via a card reader in linux: + +> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8 diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c new file mode 100644 index 0000000000..79c363cf84 --- /dev/null +++ b/board/varisys/cyrus/cyrus.c @@ -0,0 +1,116 @@ +/* + * Based on corenet_ds.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> +#include <pci.h> + +#include "cyrus.h" +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_OPENDRAIN 0x30000000 +#define GPIO_DIR 0x3c000004 +#define GPIO_INITIAL 0x30000000 +#define GPIO_VGA_SWITCH 0x00001000 + +int checkboard(void) +{ + printf("Board: CYRUS\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + + /* + * Only use DDR1_MCK0/3 and DDR2_MCK0/3 + * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce + * the noise introduced by these unterminated and unused clock pairs. + */ + setbits_be32(&gur->ddrclkdr, 0x001B001B); + + /* Set GPIO reset lines to open-drain, tristate */ + setbits_be32(&pgpio->gpdat, GPIO_INITIAL); + setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN); + + /* Set GPIO Direction */ + setbits_be32(&pgpio->gpdir, GPIO_DIR); + + return 0; +} + +int board_early_init_r(void) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + + out_be32(&lbc->lbcr, 0); + /* 1 clock LALE cycle */ + out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR); + + set_liodns(); + +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + print_lbc_regs(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + return 0; +} + +int mac_read_from_eeprom(void) +{ + init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN); + + return mac_read_from_eeprom_common(); +} diff --git a/board/varisys/cyrus/cyrus.h b/board/varisys/cyrus/cyrus.h new file mode 100644 index 0000000000..8cd52ba3c5 --- /dev/null +++ b/board/varisys/cyrus/cyrus.h @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CYRUS_H +#define __CYRUS_H + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/varisys/cyrus/ddr.c b/board/varisys/cyrus/ddr.c new file mode 100644 index 0000000000..bb1d29a94c --- /dev/null +++ b/board/varisys/cyrus/ddr.c @@ -0,0 +1,188 @@ +/* + * Based on corenet_ds ddr code + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 5, 6, 0xff, 2, 0}, + {2, 1050, 5, 7, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +/* + * The two slots have slightly different timing. The center values are good + * for both slots. We use identical speed tables for them. In future use, if + * DIMMs have fewer center values that require two separated tables, copy the + * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 4, 6, 0xff, 2, 0}, + {2, 1050, 4, 7, 0xff, 2, 0}, + {2, 1666, 4, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +/* + * The two slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); + } +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing...."); + + if (!fsl_use_spd()) + panic("Cyrus only supports using SPD for DRAM\n"); + + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c new file mode 100644 index 0000000000..bcadc67794 --- /dev/null +++ b/board/varisys/cyrus/eth.c @@ -0,0 +1,100 @@ +/* + * Author Adrian Cox + * Based somewhat on board/freescale/corenet_ds/eth_hydra.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/fsl_serdes.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fdt_support.h> +#include <fsl_dtsec.h> + +#ifdef CONFIG_FMAN_ENET + +#define FIRST_PORT_ADDR 3 +#define SECOND_PORT_ADDR 7 + +#ifdef CONFIG_PPC_P5040 +#define FIRST_PORT FM1_DTSEC5 +#define SECOND_PORT FM2_DTSEC5 +#else +#define FIRST_PORT FM1_DTSEC4 +#define SECOND_PORT FM1_DTSEC5 +#endif + +#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT) + +static void cyrus_phy_tuning(int phy) +{ + /* + * Enable RGMII delay on Tx and Rx for CPU port + */ + printf("Tuning PHY @ %d\n", phy); + + /* sets address 0x104 or reg 260 for writing */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104); + /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0); + /* sets address 0x105 or reg 261 for writing */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105); + /* writes to address 0x105 , RXD[3..0] to -0. */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); + /* sets address 0x106 or reg 261 for writing */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106); + /* writes to address 0x106 , TXD[3..0] to -0.84ns */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); + /* force re-negotiation */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340); +} +#endif + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + unsigned int i; + + printf("Initializing Fman\n"); + + + /* Register the real 1G MDIO bus */ + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + + fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR); + fm_info_set_mdio(FIRST_PORT, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR); + fm_info_set_mdio(SECOND_PORT, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + + /* Never disable DTSEC1 - it controls MDIO */ + for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + if (!IS_VALID_PORT(i)) + fm_disable_port(i); + } + +#ifdef CONFIG_PPC_P5040 + for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + if (!IS_VALID_PORT(i)) + fm_disable_port(i); + } +#endif + + cpu_eth_init(bis); + + cyrus_phy_tuning(FIRST_PORT_ADDR); + cyrus_phy_tuning(SECOND_PORT_ADDR); +#endif + + return pci_eth_init(bis); +} diff --git a/board/varisys/cyrus/law.c b/board/varisys/cyrus/law.c new file mode 100644 index 0000000000..91e1d85246 --- /dev/null +++ b/board/varisys/cyrus/law.c @@ -0,0 +1,27 @@ +/* + * Author: Adrian Cox + * Based on corenet_ds law files. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/varisys/cyrus/pbi.cfg b/board/varisys/cyrus/pbi.cfg new file mode 100644 index 0000000000..9b330ddcc4 --- /dev/null +++ b/board/varisys/cyrus/pbi.cfg @@ -0,0 +1,35 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/varisys/cyrus/pci.c b/board/varisys/cyrus/pci.c new file mode 100644 index 0000000000..4780e8c147 --- /dev/null +++ b/board/varisys/cyrus/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/varisys/cyrus/rcw_p5020_v2.cfg b/board/varisys/cyrus/rcw_p5020_v2.cfg new file mode 100644 index 0000000000..9188080605 --- /dev/null +++ b/board/varisys/cyrus/rcw_p5020_v2.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for Cyrus P5020 +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +0c540000 00000000 1e1e0000 00000000 +44808c00 ff002000 68000000 45000000 +00000000 00000000 00000000 0003000f +a0000000 00000000 00000000 00000000 diff --git a/board/varisys/cyrus/rcw_p5040.cfg b/board/varisys/cyrus/rcw_p5040.cfg new file mode 100644 index 0000000000..5284481568 --- /dev/null +++ b/board/varisys/cyrus/rcw_p5040.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for Cyrus P5040 +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +90e00000 00000000 acac9800 00440000 +44808c00 ff29a000 68000000 61000000 +00000000 00000000 00000000 0003000f +a0000000 00000000 00000000 00000000 diff --git a/board/varisys/cyrus/tlb.c b/board/varisys/cyrus/tlb.c new file mode 100644 index 0000000000..3fa58644bb --- /dev/null +++ b/board/varisys/cyrus/tlb.c @@ -0,0 +1,106 @@ +/* + * Author: Adrian Cox + * Based on corenet_ds tlb code + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* Local Bus */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_64K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index fd5d6fe950..88047ec1de 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -36,13 +36,3 @@ CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes # To include xil_io.h CFLAGS_ps7_init_gpl.o := -I$(srctree)/$(src) - -# Warn if CONFIG_TARGET_ZYNQ_ZC70X is enabled -ifeq ($(CONFIG_TARGET_ZYNQ_ZC70X),y) -ifeq ($(CONFIG_SPL_BUILD),y) -$(warning CONFIG_TARGET_ZYNQ_ZC70X is deprecated.) -$(warning Enable CONFIG_TARGET_ZYNQ_ZC702 or CONFIG_TARGET_ZYNQ_706 instead.) -$(warning "make zynq_zc70x_defconfig" is also deprecated.) -$(warning Use "make zynq_zc702_defconfig" or "make zynq_zc706_defconfig".) -endif -endif diff --git a/common/board_f.c b/common/board_f.c index 486e828fe8..725eb18427 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -551,7 +551,7 @@ static int display_new_sp(void) return 0; } -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS) static int setup_board_part1(void) { bd_t *bd = gd->bd; @@ -580,7 +580,9 @@ static int setup_board_part1(void) return 0; } +#endif +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) static int setup_board_part2(void) { bd_t *bd = gd->bd; @@ -806,7 +808,7 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_BOARD_POSTCLK_INIT) board_postclk_init, #endif -#ifdef CONFIG_FSL_CLK +#ifdef CONFIG_SYS_FSL_CLK get_clocks, #endif #ifdef CONFIG_M68K @@ -894,7 +896,7 @@ static init_fnc_t init_sequence_f[] = { * - board info struct */ setup_dest_addr, -#if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) +#if defined(CONFIG_BLACKFIN) /* Blackfin u-boot monitor should be on top of the ram */ reserve_uboot, #endif @@ -919,7 +921,7 @@ static init_fnc_t init_sequence_f[] = { !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) reserve_video, #endif -#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) +#if !defined(CONFIG_BLACKFIN) reserve_uboot, #endif #ifndef CONFIG_SPL_BUILD @@ -933,8 +935,10 @@ static init_fnc_t init_sequence_f[] = { reserve_stacks, setup_dram_config, show_dram_config, -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS) setup_board_part1, +#endif +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) INIT_FUNC_WATCHDOG_RESET setup_board_part2, #endif diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index ed3b9351b1..adda55a263 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -157,10 +157,15 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + int i; bd_t *bd = gd->bd; - print_num("mem start", (ulong)bd->bi_memstart); - print_lnum("mem size", (u64)bd->bi_memsize); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + print_num("DRAM bank", i); + print_num("-> start", bd->bi_dram[i].start); + print_num("-> size", bd->bi_dram[i].size); + } + print_num("flash start", (ulong)bd->bi_flashstart); print_num("flash size", (ulong)bd->bi_flashsize); print_num("flash offset", (ulong)bd->bi_flashoffset); diff --git a/common/cmd_console.c b/common/cmd_console.c index 93dc505056..9a356ecfc3 100644 --- a/common/cmd_console.c +++ b/common/cmd_console.c @@ -27,10 +27,9 @@ static int do_coninfo(cmd_tbl_t *cmd, int flag, int argc, char * const argv[]) list_for_each(pos, list) { dev = list_entry(pos, struct stdio_dev, list); - printf ("%-8s %08x %c%c%c ", + printf ("%-8s %08x %c%c ", dev->name, dev->flags, - (dev->flags & DEV_FLAGS_SYSTEM) ? 'S' : '.', (dev->flags & DEV_FLAGS_INPUT) ? 'I' : '.', (dev->flags & DEV_FLAGS_OUTPUT) ? 'O' : '.'); diff --git a/common/cmd_sf.c b/common/cmd_sf.c index ac7f5dfb81..42862d9d92 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -348,6 +348,37 @@ static int do_spi_flash_erase(int argc, char * const argv[]) return ret == 0 ? 0 : 1; } +static int do_spi_protect(int argc, char * const argv[]) +{ + int ret = 0; + loff_t start, len; + bool prot = false; + + if (argc != 4) + return -1; + + if (!str2off(argv[2], &start)) { + puts("start sector is not a valid number\n"); + return 1; + } + + if (!str2off(argv[3], &len)) { + puts("len is not a valid number\n"); + return 1; + } + + if (strcmp(argv[1], "lock") == 0) + prot = true; + else if (strcmp(argv[1], "unlock") == 0) + prot = false; + else + return -1; /* Unknown parameter */ + + ret = spi_flash_protect(flash, start, len, prot); + + return ret == 0 ? 0 : 1; +} + #ifdef CONFIG_CMD_SF_TEST enum { STAGE_ERASE, @@ -540,6 +571,8 @@ static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, ret = do_spi_flash_read_write(argc, argv); else if (strcmp(cmd, "erase") == 0) ret = do_spi_flash_erase(argc, argv); + else if (strcmp(cmd, "protect") == 0) + ret = do_spi_protect(argc, argv); #ifdef CONFIG_CMD_SF_TEST else if (!strcmp(cmd, "test")) ret = do_spi_flash_test(argc, argv); @@ -579,5 +612,7 @@ U_BOOT_CMD( "sf update addr offset|partition len - erase and write `len' bytes from memory\n" " at `addr' to flash at `offset'\n" " or to start of mtd `partition'\n" + "sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n" + " at address 'sector'\n" SF_TEST_HELP ); diff --git a/common/fdt_support.c b/common/fdt_support.c index f86365e8f0..a7ff2dfb81 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -158,25 +158,30 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff) aliasoff = fdt_path_offset(fdt, "/aliases"); if (aliasoff < 0) { err = aliasoff; - goto error; + goto noalias; } path = fdt_getprop(fdt, aliasoff, sername, &len); if (!path) { err = len; - goto error; + goto noalias; } /* fdt_setprop may break "path" so we copy it to tmp buffer */ memcpy(tmp, path, len); err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len); -error: if (err < 0) printf("WARNING: could not set linux,stdout-path %s.\n", fdt_strerror(err)); return err; + +noalias: + printf("WARNING: %s: could not read %s alias: %s\n", + __func__, sername, fdt_strerror(err)); + + return 0; } #else static int fdt_fixup_stdout(void *fdt, int chosenoff) diff --git a/common/stdio.c b/common/stdio.c index adbfc890dd..ab4df20f6b 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -88,7 +88,7 @@ static void drv_system_init (void) memset (&dev, 0, sizeof (dev)); strcpy (dev.name, "serial"); - dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; dev.putc = stdio_serial_putc; dev.puts = stdio_serial_puts; dev.getc = stdio_serial_getc; @@ -99,7 +99,7 @@ static void drv_system_init (void) memset (&dev, 0, sizeof (dev)); strcpy (dev.name, "nulldev"); - dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; dev.putc = nulldev_putc; dev.puts = nulldev_puts; dev.getc = nulldev_input; diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 95912f99c7..0302e5bc93 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -503,7 +503,7 @@ static int probe_usb_keyboard(struct usb_device *dev) debug("USB KBD: register.\n"); memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev)); strcpy(usb_kbd_dev.name, DEVNAME); - usb_kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + usb_kbd_dev.flags = DEV_FLAGS_INPUT; usb_kbd_dev.getc = usb_kbd_getc; usb_kbd_dev.tstc = usb_kbd_testc; usb_kbd_dev.priv = (void *)dev; diff --git a/common/usb_storage.c b/common/usb_storage.c index 0ccaeb4a14..4fa6538db5 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1177,25 +1177,9 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct usb_endpoint_descriptor *ep_desc; unsigned int flags = 0; - int protocol = 0; - int subclass = 0; - /* let's examine the device now */ iface = &dev->config.if_desc[ifnum]; -#if 0 - /* this is the place to patch some storage devices */ - debug("iVendor %X iProduct %X\n", dev->descriptor.idVendor, - dev->descriptor.idProduct); - - if ((dev->descriptor.idVendor) == 0x066b && - (dev->descriptor.idProduct) == 0x0103) { - debug("patched for E-USB\n"); - protocol = US_PR_CB; - subclass = US_SC_UFI; /* an assumption */ - } -#endif - if (dev->descriptor.bDeviceClass != 0 || iface->desc.bInterfaceClass != USB_CLASS_MASS_STORAGE || iface->desc.bInterfaceSubClass < US_SC_MIN || @@ -1215,17 +1199,8 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, ss->ifnum = ifnum; ss->pusb_dev = dev; ss->attention_done = 0; - - /* If the device has subclass and protocol, then use that. Otherwise, - * take data from the specific interface. - */ - if (subclass) { - ss->subclass = subclass; - ss->protocol = protocol; - } else { - ss->subclass = iface->desc.bInterfaceSubClass; - ss->protocol = iface->desc.bInterfaceProtocol; - } + ss->subclass = iface->desc.bInterfaceSubClass; + ss->protocol = iface->desc.bInterfaceProtocol; /* set the handler pointers based on the protocol */ debug("Transport: "); diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig new file mode 100644 index 0000000000..af2cef7072 --- /dev/null +++ b/configs/10m50_defconfig @@ -0,0 +1,26 @@ +CONFIG_NIOS2=y +CONFIG_SYS_CONFIG_NAME="10m50_devboard" +CONFIG_DM_SERIAL=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ITEST is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ALTERA_PIO=y +CONFIG_MISC=y +CONFIG_ALTERA_SYSID=y +CONFIG_MTD=y +CONFIG_ALTERA_QSPI=y +CONFIG_DM_ETH=y +CONFIG_ALTERA_TSE=y +CONFIG_ALTERA_UART=y +CONFIG_TIMER=y +CONFIG_ALTERA_TIMER=y diff --git a/configs/nios2-generic_defconfig b/configs/3c120_defconfig index fbc27ea17f..736119e2d3 100644 --- a/configs/nios2-generic_defconfig +++ b/configs/3c120_defconfig @@ -1,5 +1,5 @@ CONFIG_NIOS2=y -CONFIG_SYS_CONFIG_NAME="nios2-generic" +CONFIG_SYS_CONFIG_NAME="3c120_devboard" CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" @@ -10,7 +10,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y @@ -18,6 +17,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ALTERA_PIO=y CONFIG_MISC=y CONFIG_ALTERA_SYSID=y +CONFIG_MTD=y +CONFIG_CFI_FLASH=y CONFIG_DM_ETH=y CONFIG_ALTERA_TSE=y CONFIG_ALTERA_JTAG_UART=y diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig new file mode 100644 index 0000000000..d9bee34cba --- /dev/null +++ b/configs/Cyrus_P5020_defconfig @@ -0,0 +1,9 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_CYRUS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig new file mode 100644 index 0000000000..c66238af19 --- /dev/null +++ b/configs/Cyrus_P5040_defconfig @@ -0,0 +1,9 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_CYRUS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 78a9470622..0b75781973 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -23,6 +23,7 @@ CONFIG_SPI_FLASH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index f1709edb36..2136ab285d 100644 --- a/configs/ls1021atwr_sdcard_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -2,6 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" -# CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig new file mode 100644 index 0000000000..458578b80d --- /dev/null +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021ATWR=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig new file mode 100644 index 0000000000..ae84d2e5c5 --- /dev/null +++ b/configs/ls1043ardb_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_FSL_LAYERSCAPE=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig new file mode 100644 index 0000000000..fffaca0631 --- /dev/null +++ b/configs/ls1043ardb_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig new file mode 100644 index 0000000000..5fe04706c3 --- /dev/null +++ b/configs/ls1043ardb_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig index de9776d7ed..9d04218fa9 100644 --- a/configs/ls2085a_simu_defconfig +++ b/configs/ls2085a_simu_defconfig @@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SIMU" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig index 0c770e4ea7..78b121deaf 100644 --- a/configs/ls2085aqds_defconfig +++ b/configs/ls2085aqds_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds" CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig index 10eda971ac..ce2a81cc34 100644 --- a/configs/ls2085aqds_nand_defconfig +++ b/configs/ls2085aqds_nand_defconfig @@ -3,5 +3,6 @@ CONFIG_TARGET_LS2085AQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig index 79565330df..d0f16f2b2d 100644 --- a/configs/ls2085ardb_defconfig +++ b/configs/ls2085ardb_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb" CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig index 96a0dfdc9c..25a6f71c01 100644 --- a/configs/ls2085ardb_nand_defconfig +++ b/configs/ls2085ardb_nand_defconfig @@ -3,5 +3,6 @@ CONFIG_TARGET_LS2085ARDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 8f99f0eadf..0f500e643e 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -23,6 +23,7 @@ CONFIG_DM_ETH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_USB=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 479af9e71a..4ab91fa828 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -9,7 +9,12 @@ CONFIG_SYS_PROMPT="ODROID-XU3 # " # CONFIG_CMD_SETEXPR is not set CONFIG_DM_I2C_COMPAT=y CONFIG_DM_PMIC=y +CONFIG_CMD_PMIC=y +CONFIG_ERRNO_STR=y CONFIG_DM_REGULATOR=y +CONFIG_PMIC_S2MPS11=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_BRIDGE=y +CONFIG_ADC=y +CONFIG_ADC_EXYNOS=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig new file mode 100644 index 0000000000..16861397c3 --- /dev/null +++ b/configs/openrd_base_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig new file mode 100644 index 0000000000..c34231560c --- /dev/null +++ b/configs/openrd_client_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig new file mode 100644 index 0000000000..530ba4d10c --- /dev/null +++ b/configs/openrd_ultimate_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 67ae99b638..94c8e685f0 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -65,3 +65,5 @@ CONFIG_UT_DM=y CONFIG_UT_ENV=y CONFIG_REMOTEPROC_SANDBOX=y CONFIG_CMD_REMOTEPROC=y +CONFIG_ADC=y +CONFIG_ADC_SANDBOX=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 770c797ffd..79304c1fb1 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set @@ -20,5 +20,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_REGEX is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 9cb2ca1bac..74ca3a98dc 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -9,7 +9,7 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index f2b71e9b82..3a42efbf0d 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -6,5 +6,5 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index c4922f3ec3..3e488bea9b 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -8,7 +8,7 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index b4c076ce44..edd3635a01 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -9,7 +9,7 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig deleted file mode 100644 index 97f8a5daee..0000000000 --- a/configs/zynq_zc70x_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZC70X=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" -CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_FIT_SIGNATURE=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPI_FLASH=y -CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 61106df818..69a0a9cd25 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 46d043b40e..2a61fe33ca 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -10,5 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 34d479fe3f..eb98a393e5 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -8,5 +8,5 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index c59599f7f7..8d65c05c2f 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -10,5 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 5e128fbc78..df5e25a14a 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -9,7 +9,7 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 77b94097fe..b7531d6acb 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -9,5 +9,9 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index 593237f04a..9caa512608 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -5,6 +5,9 @@ # to document the SRC - and how to read it. # To add a new book the only step required is to add the book to the # list of DOCBOOKS. +# +# SPDX-License-Identifier: GPL-2.0 +# DOCBOOKS := linker_lists.xml stdio.xml diff --git a/doc/README.fsl-clk b/doc/README.fsl-clk new file mode 100644 index 0000000000..9e83c24f23 --- /dev/null +++ b/doc/README.fsl-clk @@ -0,0 +1,6 @@ +Freescale system clock options + + - CONFIG_SYS_FSL_CLK + Enable to call get_clocks() in board_init_f() for + non-PPC platforms and PCC 8xx platforms such as + TQM866M and TQM885D. diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa index 0d8d4f6efc..3ef5eeb32e 100644 --- a/doc/README.fsl-dpaa +++ b/doc/README.fsl-dpaa @@ -2,9 +2,9 @@ This file documents Freescale DPAA-specific options. FMan (Frame Manager) - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION - on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: + on SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 - on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: + on SoCs T1024, etc, the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. diff --git a/doc/README.nios2 b/doc/README.nios2 index 2dab7d12e4..46c704e628 100644 --- a/doc/README.nios2 +++ b/doc/README.nios2 @@ -30,12 +30,12 @@ http://www.alterawiki.com/wiki/Sopc2dts $ java -jar sopc2dts.jar --force-altr -i mysystem.sopcinfo -o mysystem.dts You will need to add additional properties to the dts. Please find an -example at, arch/nios2/dts/3c120_devboard.dts. +example at, arch/nios2/dts/10m50_devboard.dts. 1. Add "stdout-path=..." property with your serial path to the chosen node, like this, chosen { - stdout-path = &jtag_uart; + stdout-path = &uart_0; }; 2. If you use SPI/EPCS or I2C, you will need to add aliases to number @@ -45,9 +45,9 @@ the sequence of these devices, like this, }; Next, you will need a default config file. You may start with -nios2-generic_defconfig, modify the options and save it. +10m50_defconfig, modify the options and save it. -$ make nios2-generic_defconfig +$ make 10m50_defconfig $ make menuconfig $ make savedefconfig $ cp defconfig configs/mysystem_defconfig @@ -72,15 +72,15 @@ copies all the u-boot-dtb.bin, not just u-boot.bin. binary. This is handy for development, eg, using gdb or nios2-download. The last thing, legacy board header file describes those config options -not covered in Kconfig yet. You may copy it from nios2-generic.h. +not covered in Kconfig yet. You may copy it from 10m50_devboard.h. -$ cp include/configs/nios2-generic.h include/configs/mysystem.h +$ cp include/configs/10m50_devboard.h include/configs/mysystem.h Please change the SDRAM base and size to match your board. The base should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx to 0xDxxx_xxxx. -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_BASE 0xc8000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 You will need to change the environment variables location and setting, diff --git a/doc/README.scrapyard b/doc/README.scrapyard index cddaff6938..b7cf62df9b 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,10 +12,10 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -ocotea powerpc ppc4xx - - Stefan Roese <sr@denx.de> -taishan powerpc ppc4xx - - Stefan Roese <sr@denx.de> -ebony powerpc ppc4xx - - Stefan Roese <sr@denx.de> -taihu powerpc ppc4xx - - John Otken <jotken@softadvances.com> +ocotea powerpc ppc4xx 29155e73 2015-10-27 Stefan Roese <sr@denx.de> +taishan powerpc ppc4xx bb5553c6 2015-10-27 Stefan Roese <sr@denx.de> +ebony powerpc ppc4xx 9d9e2f5d 2015-10-27 Stefan Roese <sr@denx.de> +taihu powerpc ppc4xx 123b6cd7 2015-10-27 John Otken <jotken@softadvances.com> lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr@denx.de> da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson@gefanuc.com> wireless_space arm arm926ejs b352182a 2015-09-12 Albert ARIBAUD <albert.u.boot@aribaud.net> @@ -64,9 +64,6 @@ nhk8815 arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linu nhk8815_onenand arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> omap3_mvblx arm armv7 8dc372f9 2015-08-30 Michael Jones <michael.jones@matrix-vision.de> omap3_sdp3430 arm armv7 93b25c08 2015-08-30 Nishanth Menon <nm@ti.com> -openrd_base arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> -openrd_client arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> -openrd_ultimate arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> otc570 arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu> otc570_dataflash arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu> palmld arm pxa 35782e9c 2015-08-30 Marek Vasut <marex@denx.de> diff --git a/doc/device-tree-bindings/adc/adc.txt b/doc/device-tree-bindings/adc/adc.txt new file mode 100644 index 0000000000..463de3c8c2 --- /dev/null +++ b/doc/device-tree-bindings/adc/adc.txt @@ -0,0 +1,62 @@ +ADC device binding + +There are no mandatory properties for ADC. However, if Voltage info is required, +then there are two options: +- use microvolts constraint or +- use regulator phandle to enable/read supply's Voltage + +Properties and constraints: +*optional and always checked, Voltage polarity info: +- vdd-polarity-negative: positive reference Voltage has a negative polarity +- vss-polarity-negative: negative reference Voltage has a negative polarity + +Chose one option, for each supply (Vdd/Vss): + +*optional and always checked, supply Voltage constants: +- vdd-supply: phandle to Vdd regulator's node +- vss-supply: phandle to Vss regulator's node + +*optional and checked only if the above corresponding, doesn't exist: +- vdd-microvolts: positive reference Voltage value [uV] +- vss-microvolts: negative reference Voltage value [uV] + +Example with constant 'Vdd' value: +adc@1000000 { + compatible = "some-adc"; + reg = <0xaabb000 0x100>; + status = "enabled"; + vdd-microvolts = <1800000>; +}; + +Example of supply phandle usage, for the ADC's VDD/VSS references as below: + _______ _______ + |Sandbox| |Sandbox| + : PMIC : : ADC : + . . . . + | | (Vdd) | AIN0|--> + | BUCK2|-------|VDDref | + | (3.3V)| _|VSSref | + |_______| | |_______| + _|_ + +For the above PMIC, the node can be defined as follows: +sandbox_pmic { + compatible = "sandbox,pmic"; + ... + buck2: buck2 { + regulator-name = "SUPPLY_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ... +}; + +For the above ADC, the node can be defined as follows: +adc@0 { + compatible = "sandbox,adc"; + vdd-supply = <&buck2>; + vss-microvolts = <0>; +}; + +The ADC uclass code, will enable the supply before start of the conversion, +but it will not configure the regulator settings. diff --git a/doc/device-tree-bindings/exynos/soc.txt b/doc/device-tree-bindings/exynos/soc.txt new file mode 100644 index 0000000000..9ba6f3b9f8 --- /dev/null +++ b/doc/device-tree-bindings/exynos/soc.txt @@ -0,0 +1,21 @@ +Exynos SoC model + +The "cpu-model" property is a non-standard extension for the device tree root +node. Since the cpu id of some Exynos variants does not correspond to product +name, this property fills the gap. + +For almost all Exynos based boards in the kernel, the product name corresponds +to the device tree file name. The same name is generated in U-Boot, so the new +property allows doing it automatically. + +Required properties: + - cpu-model : Exynos product name + +Example: + +/ { + model = "Samsung/Google Peach Pi board based on Exynos5800"; + cpu-model = "Exynos5800"; + + compatible = ... +}; diff --git a/doc/device-tree-bindings/mtd/altera_qspi.txt b/doc/device-tree-bindings/mtd/altera_qspi.txt new file mode 100644 index 0000000000..3361ac92a3 --- /dev/null +++ b/doc/device-tree-bindings/mtd/altera_qspi.txt @@ -0,0 +1,35 @@ +Altera QUADSPI driver + +Required properties: +- compatible: Should be "altr,quadspi-1.0" +- reg: Address and length of the register set for the device. It contains + the information of registers in the same order as described by reg-names +- reg-names: Should contain the reg names + "avl_csr": Should contain the register configuration base address + "avl_mem": Should contain the data base address +- #address-cells: Must be <1>. +- #size-cells: Must be <0>. +- flash device tree subnode, there must be a node with the following fields: + - compatible: Should contain the flash name: + 1. EPCS: epcs16, epcs64, epcs128 + 2. EPCQ: epcq16, epcq32, epcq64, epcq128, epcq256, epcq512, epcq1024 + 3. EPCQ-L: epcql256, epcql512, epcql1024 + - #address-cells: please refer to /mtd/partition.txt + - #size-cells: please refer to /mtd/partition.txt + For partitions inside each flash, please refer to /mtd/partition.txt + +Example: + + quadspi_controller_0: quadspi@0x180014a0 { + compatible = "altr,quadspi-1.0"; + reg = <0x180014a0 0x00000020>, + <0x14000000 0x04000000>; + reg-names = "avl_csr", "avl_mem"; + #address-cells = <1>; + #size-cells = <0>; + flash0: epcq512@0 { + compatible = "altr,epcq512"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; diff --git a/doc/device-tree-bindings/mtd/mtd-physmap.txt b/doc/device-tree-bindings/mtd/mtd-physmap.txt new file mode 100644 index 0000000000..4b8c489438 --- /dev/null +++ b/doc/device-tree-bindings/mtd/mtd-physmap.txt @@ -0,0 +1,88 @@ +CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) + +Flash chips (Memory Technology Devices) are often used for solid state +file systems on embedded devices. + + - compatible : should contain the specific model of mtd chip(s) + used, if known, followed by either "cfi-flash", "jedec-flash", + "mtd-ram" or "mtd-rom". + - reg : Address range(s) of the mtd chip(s) + It's possible to (optionally) define multiple "reg" tuples so that + non-identical chips can be described in one node. + - bank-width : Width (in bytes) of the bank. Equal to the + device width times the number of interleaved chips. + - device-width : (optional) Width of a single mtd chip. If + omitted, assumed to be equal to 'bank-width'. + - #address-cells, #size-cells : Must be present if the device has + sub-nodes representing partitions (see below). In this case + both #address-cells and #size-cells must be equal to 1. + - no-unaligned-direct-access: boolean to disable the default direct + mapping of the flash. + On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause + problems with JFFS2 usage, as the local bus (LPB) doesn't support + unaligned accesses as implemented in the JFFS2 code via memcpy(). + By defining "no-unaligned-direct-access", the flash will not be + exposed directly to the MTD users (e.g. JFFS2) any more. + - linux,mtd-name: allow to specify the mtd name for retro capability with + physmap-flash drivers as boot loader pass the mtd partition via the old + device name physmap-flash. + - use-advanced-sector-protection: boolean to enable support for the + advanced sector protection (Spansion: PPB - Persistent Protection + Bits) locking. + +For JEDEC compatible devices, the following additional properties +are defined: + + - vendor-id : Contains the flash chip's vendor id (1 byte). + - device-id : Contains the flash chip's device id (1 byte). + +For ROM compatible devices (and ROM fallback from cfi-flash), the following +additional (optional) property is defined: + + - erase-size : The chip's physical erase block size in bytes. + +The device tree may optionally contain sub-nodes describing partitions of the +address space. See partition.txt for more detail. + +Example: + + flash@ff000000 { + compatible = "amd,am29lv128ml", "cfi-flash"; + reg = <ff000000 01000000>; + bank-width = <4>; + device-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + fs@0 { + label = "fs"; + reg = <0 f80000>; + }; + firmware@f80000 { + label ="firmware"; + reg = <f80000 80000>; + read-only; + }; + }; + +Here an example with multiple "reg" tuples: + + flash@f0000000,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "intel,pc48f4400p0vb", "cfi-flash"; + reg = <0 0x00000000 0x02000000 + 0 0x02000000 0x02000000>; + bank-width = <2>; + partition@0 { + label = "test-part1"; + reg = <0 0x04000000>; + }; + }; + +An example using SRAM: + + sram@2,0 { + compatible = "samsung,k6f1616u6a", "mtd-ram"; + reg = <2 0 0x00200000>; + bank-width = <2>; + }; diff --git a/doc/device-tree-bindings/pmic/s2mps11.txt b/doc/device-tree-bindings/pmic/s2mps11.txt new file mode 100644 index 0000000000..422f14f13e --- /dev/null +++ b/doc/device-tree-bindings/pmic/s2mps11.txt @@ -0,0 +1,17 @@ +SAMSUNG, S2MPS11 PMIC + +This file describes the binding info for the PMIC driver: +- drivers/power/pmic/s2mps11.c + +Required properties: +- compatible: "samsung,s2mps11-pmic" +- reg = 0x66 + +With those two properties, the pmic device can be used for read/write only. + +Example: + +s2mps11@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; +}; diff --git a/drivers/Kconfig b/drivers/Kconfig index ba88b5ea37..c481e93356 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -4,6 +4,8 @@ source "drivers/core/Kconfig" # types of drivers sorted in alphabetical order +source "drivers/adc/Kconfig" + source "drivers/block/Kconfig" source "drivers/clk/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 4f49bfddb8..c9031f2ce8 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_$(SPL_)DM) += core/ obj-$(CONFIG_$(SPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_)LED) += led/ @@ -35,6 +39,7 @@ obj-$(CONFIG_SPL_SATA_SUPPORT) += block/ else +obj-y += adc/ obj-$(CONFIG_DM_DEMO) += demo/ obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig new file mode 100644 index 0000000000..e5335f7234 --- /dev/null +++ b/drivers/adc/Kconfig @@ -0,0 +1,30 @@ +config ADC + bool "Enable ADC drivers using Driver Model" + help + This enables ADC API for drivers, which allows driving ADC features + by single and multi-channel methods for: + - start/stop/get data for conversion of a single-channel selected by + a number or multi-channels selected by a bitmask + - get data mask (ADC resolution) + ADC reference Voltage supply options: + - methods for get Vdd/Vss reference Voltage values with polarity + - support supply's phandle with auto-enable + - supply polarity setting in fdt + +config ADC_EXYNOS + bool "Enable Exynos 54xx ADC driver" + help + This enables basic driver for Exynos ADC compatible with Exynos54xx. + It provides: + - 10 analog input channels + - 12-bit resolution + - 600 KSPS of sample rate + +config ADC_SANDBOX + bool "Enable Sandbox ADC test driver" + help + This enables driver for Sandbox ADC device emulation. + It provides: + - 4 analog input channels + - 16-bit resolution + - single and multi-channel conversion mode diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile new file mode 100644 index 0000000000..cebf26de07 --- /dev/null +++ b/drivers/adc/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2015 Samsung Electronics +# Przemyslaw Marczak <p.marczak@samsung.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ADC) += adc-uclass.o +obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o +obj-$(CONFIG_ADC_SANDBOX) += sandbox.o diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c new file mode 100644 index 0000000000..9233fcdb6c --- /dev/null +++ b/drivers/adc/adc-uclass.c @@ -0,0 +1,409 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> +#include <adc.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ADC_UCLASS_PLATDATA_SIZE sizeof(struct adc_uclass_platdata) +#define CHECK_NUMBER true +#define CHECK_MASK (!CHECK_NUMBER) + +/* TODO: add support for timer uclass (for early calls) */ +#ifdef CONFIG_SANDBOX_ARCH +#define sdelay(x) udelay(x) +#else +extern void sdelay(unsigned long loops); +#endif + +static int check_channel(struct udevice *dev, int value, bool number_or_mask, + const char *caller_function) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + unsigned mask = number_or_mask ? (1 << value) : value; + + /* For the real ADC hardware, some ADC channels can be inactive. + * For example if device has 4 analog channels, and only channels + * 1-st and 3-rd are valid, then channel mask is: 0b1010, so request + * with mask 0b1110 should return an error. + */ + if ((uc_pdata->channel_mask >= mask) && (uc_pdata->channel_mask & mask)) + return 0; + + printf("Error in %s/%s().\nWrong channel selection for device: %s\n", + __FILE__, caller_function, dev->name); + + return -EINVAL; +} + +static int adc_supply_enable(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + const char *supply_type; + int ret = 0; + + if (uc_pdata->vdd_supply) { + supply_type = "vdd"; + ret = regulator_set_enable(uc_pdata->vdd_supply, true); + } + + if (!ret && uc_pdata->vss_supply) { + supply_type = "vss"; + ret = regulator_set_enable(uc_pdata->vss_supply, true); + } + + if (ret) + error("%s: can't enable %s-supply!", dev->name, supply_type); + + return ret; +} + +int adc_data_mask(struct udevice *dev, unsigned int *data_mask) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + + if (!uc_pdata) + return -ENOSYS; + + *data_mask = uc_pdata->data_mask; + return 0; +} + +int adc_stop(struct udevice *dev) +{ + const struct adc_ops *ops = dev_get_driver_ops(dev); + + if (!ops->stop) + return -ENOSYS; + + return ops->stop(dev); +} + +int adc_start_channel(struct udevice *dev, int channel) +{ + const struct adc_ops *ops = dev_get_driver_ops(dev); + int ret; + + if (!ops->start_channel) + return -ENOSYS; + + ret = check_channel(dev, channel, CHECK_NUMBER, __func__); + if (ret) + return ret; + + ret = adc_supply_enable(dev); + if (ret) + return ret; + + return ops->start_channel(dev, channel); +} + +int adc_start_channels(struct udevice *dev, unsigned int channel_mask) +{ + const struct adc_ops *ops = dev_get_driver_ops(dev); + int ret; + + if (!ops->start_channels) + return -ENOSYS; + + ret = check_channel(dev, channel_mask, CHECK_MASK, __func__); + if (ret) + return ret; + + ret = adc_supply_enable(dev); + if (ret) + return ret; + + return ops->start_channels(dev, channel_mask); +} + +int adc_channel_data(struct udevice *dev, int channel, unsigned int *data) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + const struct adc_ops *ops = dev_get_driver_ops(dev); + unsigned int timeout_us = uc_pdata->data_timeout_us; + int ret; + + if (!ops->channel_data) + return -ENOSYS; + + ret = check_channel(dev, channel, CHECK_NUMBER, __func__); + if (ret) + return ret; + + do { + ret = ops->channel_data(dev, channel, data); + if (!ret || ret != -EBUSY) + break; + + /* TODO: use timer uclass (for early calls). */ + sdelay(5); + } while (timeout_us--); + + return ret; +} + +int adc_channels_data(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + unsigned int timeout_us = uc_pdata->multidata_timeout_us; + const struct adc_ops *ops = dev_get_driver_ops(dev); + int ret; + + if (!ops->channels_data) + return -ENOSYS; + + ret = check_channel(dev, channel_mask, CHECK_MASK, __func__); + if (ret) + return ret; + + do { + ret = ops->channels_data(dev, channel_mask, channels); + if (!ret || ret != -EBUSY) + break; + + /* TODO: use timer uclass (for early calls). */ + sdelay(5); + } while (timeout_us--); + + return ret; +} + +int adc_channel_single_shot(const char *name, int channel, unsigned int *data) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_ADC, name, &dev); + if (ret) + return ret; + + ret = adc_start_channel(dev, channel); + if (ret) + return ret; + + ret = adc_channel_data(dev, channel, data); + if (ret) + return ret; + + return 0; +} + +static int _adc_channels_single_shot(struct udevice *dev, + unsigned int channel_mask, + struct adc_channel *channels) +{ + unsigned int data; + int channel, ret; + + for (channel = 0; channel <= ADC_MAX_CHANNEL; channel++) { + /* Check channel bit. */ + if (!((channel_mask >> channel) & 0x1)) + continue; + + ret = adc_start_channel(dev, channel); + if (ret) + return ret; + + ret = adc_channel_data(dev, channel, &data); + if (ret) + return ret; + + channels->id = channel; + channels->data = data; + channels++; + } + + return 0; +} + +int adc_channels_single_shot(const char *name, unsigned int channel_mask, + struct adc_channel *channels) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_ADC, name, &dev); + if (ret) + return ret; + + ret = adc_start_channels(dev, channel_mask); + if (ret) + goto try_manual; + + ret = adc_channels_data(dev, channel_mask, channels); + if (ret) + return ret; + + return 0; + +try_manual: + if (ret != -ENOSYS) + return ret; + + return _adc_channels_single_shot(dev, channel_mask, channels); +} + +static int adc_vdd_platdata_update(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + int ret; + + /* Warning! + * This function can't return supply device before its bind. + * Please pay attention to proper fdt scan sequence. If ADC device + * will bind before its supply regulator device, then the below 'get' + * will return an error. + */ + ret = device_get_supply_regulator(dev, "vdd-supply", + &uc_pdata->vdd_supply); + if (ret) + return ret; + + ret = regulator_get_value(uc_pdata->vdd_supply); + if (ret < 0) + return ret; + + uc_pdata->vdd_microvolts = ret; + + return 0; +} + +static int adc_vss_platdata_update(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + int ret; + + ret = device_get_supply_regulator(dev, "vss-supply", + &uc_pdata->vss_supply); + if (ret) + return ret; + + ret = regulator_get_value(uc_pdata->vss_supply); + if (ret < 0) + return ret; + + uc_pdata->vss_microvolts = ret; + + return 0; +} + +int adc_vdd_value(struct udevice *dev, int *uV) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + int ret, value_sign = uc_pdata->vdd_polarity_negative ? -1 : 1; + + if (!uc_pdata->vdd_supply) + goto nodev; + + /* Update the regulator Value. */ + ret = adc_vdd_platdata_update(dev); + if (ret) + return ret; +nodev: + if (uc_pdata->vdd_microvolts == -ENODATA) + return -ENODATA; + + *uV = uc_pdata->vdd_microvolts * value_sign; + + return 0; +} + +int adc_vss_value(struct udevice *dev, int *uV) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + int ret, value_sign = uc_pdata->vss_polarity_negative ? -1 : 1; + + if (!uc_pdata->vss_supply) + goto nodev; + + /* Update the regulator Value. */ + ret = adc_vss_platdata_update(dev); + if (ret) + return ret; +nodev: + if (uc_pdata->vss_microvolts == -ENODATA) + return -ENODATA; + + *uV = uc_pdata->vss_microvolts * value_sign; + + return 0; +} + +static int adc_vdd_platdata_set(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + int ret, offset = dev->of_offset; + const void *fdt = gd->fdt_blob; + char *prop; + + prop = "vdd-polarity-negative"; + uc_pdata->vdd_polarity_negative = fdtdec_get_bool(fdt, offset, prop); + + ret = adc_vdd_platdata_update(dev); + if (ret != -ENOENT) + return ret; + + /* No vdd-supply phandle. */ + prop = "vdd-microvolts"; + uc_pdata->vdd_microvolts = fdtdec_get_int(fdt, offset, prop, -ENODATA); + + return 0; +} + +static int adc_vss_platdata_set(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + int ret, offset = dev->of_offset; + const void *fdt = gd->fdt_blob; + char *prop; + + prop = "vss-polarity-negative"; + uc_pdata->vss_polarity_negative = fdtdec_get_bool(fdt, offset, prop); + + ret = adc_vss_platdata_update(dev); + if (ret != -ENOENT) + return ret; + + /* No vss-supply phandle. */ + prop = "vss-microvolts"; + uc_pdata->vss_microvolts = fdtdec_get_int(fdt, offset, prop, -ENODATA); + + return 0; +} + +static int adc_pre_probe(struct udevice *dev) +{ + int ret; + + /* Set ADC VDD platdata: polarity, uV, regulator (phandle). */ + ret = adc_vdd_platdata_set(dev); + if (ret) + error("%s: Can't update Vdd. Error: %d", dev->name, ret); + + /* Set ADC VSS platdata: polarity, uV, regulator (phandle). */ + ret = adc_vss_platdata_set(dev); + if (ret) + error("%s: Can't update Vss. Error: %d", dev->name, ret); + + return 0; +} + +UCLASS_DRIVER(adc) = { + .id = UCLASS_ADC, + .name = "adc", + .pre_probe = adc_pre_probe, + .per_device_platdata_auto_alloc_size = ADC_UCLASS_PLATDATA_SIZE, +}; diff --git a/drivers/adc/exynos-adc.c b/drivers/adc/exynos-adc.c new file mode 100644 index 0000000000..534e68db8b --- /dev/null +++ b/drivers/adc/exynos-adc.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <adc.h> +#include <asm/arch/adc.h> + +struct exynos_adc_priv { + int active_channel; + struct exynos_adc_v2 *regs; +}; + +int exynos_adc_channel_data(struct udevice *dev, int channel, + unsigned int *data) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + + if (channel != priv->active_channel) { + error("Requested channel is not active!"); + return -EINVAL; + } + + if (ADC_V2_GET_STATUS_FLAG(readl(®s->status)) != FLAG_CONV_END) + return -EBUSY; + + *data = readl(®s->dat) & ADC_V2_DAT_MASK; + + return 0; +} + +int exynos_adc_start_channel(struct udevice *dev, int channel) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + unsigned int cfg; + + /* Choose channel */ + cfg = readl(®s->con2); + cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK; + cfg |= ADC_V2_CON2_CHAN_SEL(channel); + writel(cfg, ®s->con2); + + /* Start conversion */ + cfg = readl(®s->con1); + writel(cfg | ADC_V2_CON1_STC_EN, ®s->con1); + + priv->active_channel = channel; + + return 0; +} + +int exynos_adc_stop(struct udevice *dev) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + unsigned int cfg; + + /* Stop conversion */ + cfg = readl(®s->con1); + cfg |= ~ADC_V2_CON1_STC_EN; + + writel(cfg, ®s->con1); + + priv->active_channel = -1; + + return 0; +} + +int exynos_adc_probe(struct udevice *dev) +{ + struct exynos_adc_priv *priv = dev_get_priv(dev); + struct exynos_adc_v2 *regs = priv->regs; + unsigned int cfg; + + /* Check HW version */ + if (readl(®s->version) != ADC_V2_VERSION) { + error("This driver supports only ADC v2!"); + return -ENXIO; + } + + /* ADC Reset */ + writel(ADC_V2_CON1_SOFT_RESET, ®s->con1); + + /* Disable INT - will read status only */ + writel(0x0, ®s->int_en); + + /* CON2 - set conversion parameters */ + cfg = ADC_V2_CON2_C_TIME(3); /* Conversion times: (1 << 3) = 8 */ + cfg |= ADC_V2_CON2_OSEL(OSEL_BINARY); + cfg |= ADC_V2_CON2_ESEL(ESEL_ADC_EVAL_TIME_20CLK); + cfg |= ADC_V2_CON2_HIGHF(HIGHF_CONV_RATE_600KSPS); + writel(cfg, ®s->con2); + + priv->active_channel = -1; + + return 0; +} + +int exynos_adc_ofdata_to_platdata(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + struct exynos_adc_priv *priv = dev_get_priv(dev); + + priv->regs = (struct exynos_adc_v2 *)dev_get_addr(dev); + if (priv->regs == (struct exynos_adc_v2 *)FDT_ADDR_T_NONE) { + error("Dev: %s - can't get address!", dev->name); + return -ENODATA; + } + + uc_pdata->data_mask = ADC_V2_DAT_MASK; + uc_pdata->data_format = ADC_DATA_FORMAT_BIN; + uc_pdata->data_timeout_us = ADC_V2_CONV_TIMEOUT_US; + + /* Mask available channel bits: [0:9] */ + uc_pdata->channel_mask = (2 << ADC_V2_MAX_CHANNEL) - 1; + + return 0; +} + +static const struct adc_ops exynos_adc_ops = { + .start_channel = exynos_adc_start_channel, + .channel_data = exynos_adc_channel_data, + .stop = exynos_adc_stop, +}; + +static const struct udevice_id exynos_adc_ids[] = { + { .compatible = "samsung,exynos-adc-v2" }, + { } +}; + +U_BOOT_DRIVER(exynos_adc) = { + .name = "exynos-adc", + .id = UCLASS_ADC, + .of_match = exynos_adc_ids, + .ops = &exynos_adc_ops, + .probe = exynos_adc_probe, + .ofdata_to_platdata = exynos_adc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct exynos_adc_priv), +}; diff --git a/drivers/adc/sandbox.c b/drivers/adc/sandbox.c new file mode 100644 index 0000000000..371892237a --- /dev/null +++ b/drivers/adc/sandbox.c @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <adc.h> +#include <sandbox-adc.h> + +/** + * struct sandbox_adc_priv - sandbox ADC device's operation status and data + * + * @conversion_status - conversion status: ACTIVE (started) / INACTIVE (stopped) + * @conversion_mode - conversion mode: single or multi-channel + * @active_channel - active channel number, valid for single channel mode + * data[] - channels data + */ +struct sandbox_adc_priv { + int conversion_status; + int conversion_mode; + int active_channel_mask; + unsigned int data[4]; +}; + +int sandbox_adc_start_channel(struct udevice *dev, int channel) +{ + struct sandbox_adc_priv *priv = dev_get_priv(dev); + + /* Set single-channel mode */ + priv->conversion_mode = SANDBOX_ADC_MODE_SINGLE_CHANNEL; + /* Select channel */ + priv->active_channel_mask = 1 << channel; + /* Start conversion */ + priv->conversion_status = SANDBOX_ADC_ACTIVE; + + return 0; +} + +int sandbox_adc_start_channels(struct udevice *dev, unsigned int channel_mask) +{ + struct sandbox_adc_priv *priv = dev_get_priv(dev); + + /* Set single-channel mode */ + priv->conversion_mode = SANDBOX_ADC_MODE_MULTI_CHANNEL; + /* Select channel */ + priv->active_channel_mask = channel_mask; + /* Start conversion */ + priv->conversion_status = SANDBOX_ADC_ACTIVE; + + return 0; +} + +int sandbox_adc_channel_data(struct udevice *dev, int channel, + unsigned int *data) +{ + struct sandbox_adc_priv *priv = dev_get_priv(dev); + + /* For single-channel conversion mode, check if channel was selected */ + if ((priv->conversion_mode == SANDBOX_ADC_MODE_SINGLE_CHANNEL) && + !(priv->active_channel_mask & (1 << channel))) { + error("Request for an inactive channel!"); + return -EINVAL; + } + + /* The conversion must be started before reading the data */ + if (priv->conversion_status == SANDBOX_ADC_INACTIVE) + return -EIO; + + *data = priv->data[channel]; + + return 0; +} + +int sandbox_adc_channels_data(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels) +{ + struct sandbox_adc_priv *priv = dev_get_priv(dev); + int i; + + /* Return error for single-channel conversion mode */ + if (priv->conversion_mode == SANDBOX_ADC_MODE_SINGLE_CHANNEL) { + error("ADC in single-channel mode!"); + return -EPERM; + } + /* Check channel selection */ + if (!(priv->active_channel_mask & channel_mask)) { + error("Request for an inactive channel!"); + return -EINVAL; + } + /* The conversion must be started before reading the data */ + if (priv->conversion_status == SANDBOX_ADC_INACTIVE) + return -EIO; + + for (i = 0; i < SANDBOX_ADC_CHANNELS; i++) { + if (!((channel_mask >> i) & 0x1)) + continue; + + channels->data = priv->data[i]; + channels->id = i; + channels++; + } + + return 0; +} + +int sandbox_adc_stop(struct udevice *dev) +{ + struct sandbox_adc_priv *priv = dev_get_priv(dev); + + /* Start conversion */ + priv->conversion_status = SANDBOX_ADC_INACTIVE; + + return 0; +} + +int sandbox_adc_probe(struct udevice *dev) +{ + struct sandbox_adc_priv *priv = dev_get_priv(dev); + + /* Stop conversion */ + priv->conversion_status = SANDBOX_ADC_INACTIVE; + /* Set single-channel mode */ + priv->conversion_mode = SANDBOX_ADC_MODE_SINGLE_CHANNEL; + /* Deselect all channels */ + priv->active_channel_mask = 0; + + /* Set sandbox test data */ + priv->data[0] = SANDBOX_ADC_CHANNEL0_DATA; + priv->data[1] = SANDBOX_ADC_CHANNEL1_DATA; + priv->data[2] = SANDBOX_ADC_CHANNEL2_DATA; + priv->data[3] = SANDBOX_ADC_CHANNEL3_DATA; + + return 0; +} + +int sandbox_adc_ofdata_to_platdata(struct udevice *dev) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + + uc_pdata->data_mask = SANDBOX_ADC_DATA_MASK; + uc_pdata->data_format = ADC_DATA_FORMAT_BIN; + uc_pdata->data_timeout_us = 0; + + /* Mask available channel bits: [0:3] */ + uc_pdata->channel_mask = (1 << SANDBOX_ADC_CHANNELS) - 1; + + return 0; +} + +static const struct adc_ops sandbox_adc_ops = { + .start_channel = sandbox_adc_start_channel, + .start_channels = sandbox_adc_start_channels, + .channel_data = sandbox_adc_channel_data, + .channels_data = sandbox_adc_channels_data, + .stop = sandbox_adc_stop, +}; + +static const struct udevice_id sandbox_adc_ids[] = { + { .compatible = "sandbox,adc" }, + { } +}; + +U_BOOT_DRIVER(sandbox_adc) = { + .name = "sandbox-adc", + .id = UCLASS_ADC, + .of_match = sandbox_adc_ids, + .ops = &sandbox_adc_ops, + .probe = sandbox_adc_probe, + .ofdata_to_platdata = sandbox_adc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct sandbox_adc_priv), +}; diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 2ba43ac731..0a280742a7 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + X86DIR = x86emu obj-y = atibios.o biosemu.o besys.o bios.o \ diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index f9cae9144a..2559ccda8c 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -36,6 +36,23 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) +#ifdef CONFIG_PHYS_64BIT +union ptr_addr_t { + u64 m_whole; + struct { +#ifdef CONFIG_SYS_FSL_SEC_LE + u32 low; + u32 high; +#elif defined(CONFIG_SYS_FSL_SEC_BE) + u32 high; + u32 low; +#else +#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined +#endif + } m_halfs; +}; +#endif + static inline int desc_len(u32 *desc) { return *desc & HDR_DESCLEN_MASK; @@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) { dma_addr_t *offset = (dma_addr_t *)desc_end(desc); +#ifdef CONFIG_PHYS_64BIT + /* The Position of low and high part of 64 bit address + * will depend on the endianness of CAAM Block */ + union ptr_addr_t ptr_addr; + ptr_addr.m_halfs.high = (u32)(ptr >> 32); + ptr_addr.m_halfs.low = (u32)ptr; + *offset = ptr_addr.m_whole; +#else *offset = ptr; +#endif (*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ; } diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index c298404f25..887e88c9ca 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -84,7 +84,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, enum caam_hash_algos caam_algo) { uint32_t final = 0; - dma_addr_t addr = virt_to_phys((void *)buf); + phys_addr_t addr = virt_to_phys((void *)buf); struct sha_ctx *ctx = hash_ctx; if (ctx->sg_num >= MAX_SG_32) { @@ -93,11 +93,11 @@ static int caam_hash_update(void *hash_ctx, const void *buf, } #ifdef CONFIG_PHYS_64BIT - ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32; + sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32)); #else - ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0; + sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); #endif - ctx->sg_tbl[ctx->sg_num].addr_lo = addr; + sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr); sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, (size & SG_ENTRY_LENGTH_MASK)); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 17392c9813..f63eacb73e 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -11,6 +11,7 @@ #include "fsl_sec.h" #include "jr.h" #include "jobdesc.h" +#include "desc_constr.h" #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -154,19 +155,35 @@ static int jr_hw_reset(void) /* -1 --- error, can't enqueue -- no space available */ static int jr_enqueue(uint32_t *desc_addr, - void (*callback)(uint32_t desc, uint32_t status, void *arg), + void (*callback)(uint32_t status, void *arg), void *arg) { struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; int head = jr.head; - dma_addr_t desc_phys_addr = virt_to_phys(desc_addr); + uint32_t desc_word; + int length = desc_len(desc_addr); + int i; +#ifdef CONFIG_PHYS_64BIT + uint32_t *addr_hi, *addr_lo; +#endif + + /* The descriptor must be submitted to SEC block as per endianness + * of the SEC Block. + * So, if the endianness of Core and SEC block is different, each word + * of the descriptor will be byte-swapped. + */ + for (i = 0; i < length; i++) { + desc_word = desc_addr[i]; + sec_out32((uint32_t *)&desc_addr[i], desc_word); + } + + phys_addr_t desc_phys_addr = virt_to_phys(desc_addr); if (sec_in32(®s->irsa) == 0 || CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0) return -1; jr.info[head].desc_phys_addr = desc_phys_addr; - jr.info[head].desc_addr = (uint32_t)desc_addr; jr.info[head].callback = (void *)callback; jr.info[head].arg = arg; jr.info[head].op_done = 0; @@ -177,9 +194,29 @@ static int jr_enqueue(uint32_t *desc_addr, ARCH_DMA_MINALIGN); flush_dcache_range(start, end); - jr.input_ring[head] = desc_phys_addr; +#ifdef CONFIG_PHYS_64BIT + /* Write the 64 bit Descriptor address on Input Ring. + * The 32 bit hign and low part of the address will + * depend on endianness of SEC block. + */ +#ifdef CONFIG_SYS_FSL_SEC_LE + addr_lo = (uint32_t *)(&jr.input_ring[head]); + addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1; +#elif defined(CONFIG_SYS_FSL_SEC_BE) + addr_hi = (uint32_t *)(&jr.input_ring[head]); + addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1; +#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ + + sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32)); + sec_out32(addr_lo, (uint32_t)(desc_phys_addr)); + +#else + /* Write the 32 bit Descriptor address on Input Ring. */ + sec_out32(&jr.input_ring[head], desc_phys_addr); +#endif /* ifdef CONFIG_PHYS_64BIT */ + start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); + end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); jr.head = (head + 1) & (jr.size - 1); @@ -195,8 +232,13 @@ static int jr_dequeue(void) int head = jr.head; int tail = jr.tail; int idx, i, found; - void (*callback)(uint32_t desc, uint32_t status, void *arg); + void (*callback)(uint32_t status, void *arg); void *arg = NULL; +#ifdef CONFIG_PHYS_64BIT + uint32_t *addr_hi, *addr_lo; +#else + uint32_t *addr; +#endif while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { unsigned long start = (unsigned long)jr.output_ring & @@ -208,14 +250,34 @@ static int jr_dequeue(void) found = 0; - dma_addr_t op_desc = jr.output_ring[jr.tail].desc; - uint32_t status = jr.output_ring[jr.tail].status; - uint32_t desc_virt; + phys_addr_t op_desc; + #ifdef CONFIG_PHYS_64BIT + /* Read the 64 bit Descriptor address from Output Ring. + * The 32 bit hign and low part of the address will + * depend on endianness of SEC block. + */ + #ifdef CONFIG_SYS_FSL_SEC_LE + addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc); + addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; + #elif defined(CONFIG_SYS_FSL_SEC_BE) + addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc); + addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; + #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ + + op_desc = ((u64)sec_in32(addr_hi) << 32) | + ((u64)sec_in32(addr_lo)); + + #else + /* Read the 32 bit Descriptor address from Output Ring. */ + addr = (uint32_t *)&jr.output_ring[jr.tail].desc; + op_desc = sec_in32(addr); + #endif /* ifdef CONFIG_PHYS_64BIT */ + + uint32_t status = sec_in32(&jr.output_ring[jr.tail].status); for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) { idx = (tail + i) & (jr.size - 1); if (op_desc == jr.info[idx].desc_phys_addr) { - desc_virt = jr.info[idx].desc_addr; found = 1; break; } @@ -244,13 +306,13 @@ static int jr_dequeue(void) sec_out32(®s->orjr, 1); jr.info[idx].op_done = 0; - callback(desc_virt, status, arg); + callback(status, arg); } return 0; } -static void desc_done(uint32_t desc, uint32_t status, void *arg) +static void desc_done(uint32_t status, void *arg) { struct result *x = arg; x->status = status; diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 1526060088..5899696e8a 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -37,14 +37,13 @@ #define JQ_ENQ_ERR -3 struct op_ring { - dma_addr_t desc; + phys_addr_t desc; uint32_t status; } __packed; struct jr_info { - void (*callback)(dma_addr_t desc, uint32_t status, void *arg); - dma_addr_t desc_phys_addr; - uint32_t desc_addr; + void (*callback)(uint32_t status, void *arg); + phys_addr_t desc_phys_addr; uint32_t desc_len; uint32_t op_done; void *arg; diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile index df66c07230..01ea86217c 100644 --- a/drivers/ddr/fsl/Makefile +++ b/drivers/ddr/fsl/Makefile @@ -1,9 +1,7 @@ # # Copyright 2008-2014 Freescale Semiconductor, Inc. # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# Version 2 as published by the Free Software Foundation. +# SPDX-License-Identifier: GPL-2.0 # obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 8367c95cf8..8543679108 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -858,7 +858,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, break; } } - + sr_ie = popts->self_refresh_interrupt_en; num_pr = 1; /* Make this configurable */ /* diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index 7646c6b727..9702eeea20 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -115,8 +115,10 @@ static struct spi_flash *parse_dev(char *devstr) int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s) { char *st; + char *devstr_bkup = strdup(devstr); - dfu->data.sf.dev = parse_dev(devstr); + dfu->data.sf.dev = parse_dev(devstr_bkup); + free(devstr_bkup); if (!dfu->data.sf.dev) return -ENODEV; diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 0f977d706d..fa4c82f1a2 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -523,8 +523,8 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, #endif static struct mxc_i2c_bus mxc_i2c_buses[] = { -#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \ - defined(CONFIG_VF610) +#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \ + defined(CONFIG_FSL_LAYERSCAPE) { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c index a31aa77102..dd150eeb45 100644 --- a/drivers/input/cros_ec_keyb.c +++ b/drivers/input/cros_ec_keyb.c @@ -258,7 +258,7 @@ int drv_keyboard_init(void) memset(&dev, '\0', sizeof(dev)); strcpy(dev.name, "cros-ec-keyb"); - dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.flags = DEV_FLAGS_INPUT; dev.getc = kbd_getc; dev.tstc = kbd_tstc; dev.start = cros_ec_init_keyboard; diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c index be0f3330db..ca3886a18e 100644 --- a/drivers/input/keyboard.c +++ b/drivers/input/keyboard.c @@ -274,7 +274,7 @@ int kbd_init (void) return -1; memset (&kbddev, 0, sizeof(kbddev)); strcpy(kbddev.name, DEVNAME); - kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.flags = DEV_FLAGS_INPUT; kbddev.getc = kbd_getc ; kbddev.tstc = kbd_testc ; diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index c9c9fac5ad..6b88db4def 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -358,7 +358,7 @@ int drv_keyboard_init(void) memset(&dev, '\0', sizeof(dev)); strcpy(dev.name, "tegra-kbc"); - dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.flags = DEV_FLAGS_INPUT; dev.getc = kbd_getc; dev.tstc = kbd_tstc; dev.start = init_tegra_keyboard; diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 9bfb9c785d..6124e389bd 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + obj-$(CONFIG_TI_AEMIF) += ti-aemif.o diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c index 249b273fb3..737520f247 100644 --- a/drivers/misc/altera_sysid.c +++ b/drivers/misc/altera_sysid.c @@ -87,8 +87,8 @@ static const struct misc_ops altera_sysid_ops = { }; static const struct udevice_id altera_sysid_ids[] = { - { .compatible = "altr,sysid-1.0", }, - { } + { .compatible = "altr,sysid-1.0" }, + {} }; U_BOOT_DRIVER(altera_sysid) = { diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c index a592891f26..98d9fbe534 100644 --- a/drivers/misc/fsl_debug_server.c +++ b/drivers/misc/fsl_debug_server.c @@ -8,7 +8,6 @@ #include <errno.h> #include <asm/io.h> #include <asm/system.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> #include <fsl-mc/fsl_mc.h> #include <fsl_debug_server.h> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 99d02954ed..5d357056dd 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_DM_MMC) += mmc-uclass.o obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o +obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c new file mode 100644 index 0000000000..24b68b640b --- /dev/null +++ b/drivers/mmc/atmel_sdhci.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <sdhci.h> +#include <asm/arch/clk.h> + +#define ATMEL_SDHC_MIN_FREQ 400000 + +int atmel_sdhci_init(void *regbase, u32 id) +{ + struct sdhci_host *host; + u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; + + host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host)); + if (!host) { + printf("%s: sdhci_host calloc failed\n", __func__); + return -ENOMEM; + } + + host->name = "atmel_sdhci"; + host->ioaddr = regbase; + host->quirks = 0; + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + max_clk = at91_get_periph_generated_clk(id); + if (!max_clk) { + printf("%s: Failed to get the proper clock\n", __func__); + free(host); + return -ENODEV; + } + + add_sdhci(host, max_clk, min_clk); + + return 0; +} diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002659..c5054d66bd 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) xfertyp |= XFERTYP_RSPTYP_48; #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) + defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \ + defined(CONFIG_PPC_T4160) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif @@ -184,7 +185,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) int timeout; struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; -#ifdef CONFIG_LS2085A +#ifdef CONFIG_FSL_LAYERSCAPE dma_addr_t addr; #endif uint wml_value; @@ -197,7 +198,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#ifdef CONFIG_LS2085A +#ifdef CONFIG_FSL_LAYERSCAPE addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -223,7 +224,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#ifdef CONFIG_LS2085A +#ifdef CONFIG_FSL_LAYERSCAPE addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -277,7 +278,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) static void check_and_invalidate_dcache_range (struct mmc_cmd *cmd, struct mmc_data *data) { -#ifdef CONFIG_LS2085A +#ifdef CONFIG_FSL_LAYERSCAPE unsigned start = 0; #else unsigned start = (unsigned)data->dest ; @@ -285,7 +286,7 @@ static void check_and_invalidate_dcache_range unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); unsigned end = start+size ; -#ifdef CONFIG_LS2085A +#ifdef CONFIG_FSL_LAYERSCAPE dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); @@ -747,8 +748,14 @@ void mmc_adapter_card_type_ident(void) switch (card_id) { case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); + QIXIS_WRITE(brdcfg[5], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: + value = QIXIS_READ(pwr_ctl[1]); + value |= QIXIS_EVDD_BY_SDHC_VS; + QIXIS_WRITE(pwr_ctl[1], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: value = QIXIS_READ(brdcfg[5]); diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 45bcffb6b2..da870c646e 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -32,7 +32,11 @@ # define MCI_BUS 0 #endif -static int initialized = 0; +struct atmel_mci_priv { + struct mmc_config cfg; + struct atmel_mci *mci; + unsigned int initialized:1; +}; /* Read Atmel MCI IP version */ static unsigned int atmel_mci_get_version(struct atmel_mci *mci) @@ -48,14 +52,15 @@ static unsigned int atmel_mci_get_version(struct atmel_mci *mci) */ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) { - printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n", - cmdr, cmdr&0x3F, arg, status, msg); + debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n", + cmdr, cmdr & 0x3F, arg, status, msg); } /* Setup for MCI Clock and Block Size */ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { - atmel_mci_t *mci = mmc->priv; + struct atmel_mci_priv *priv = mmc->priv; + atmel_mci_t *mci = priv->mci; u32 bus_hz = get_mci_clk_rate(); u32 clkdiv = 255; unsigned int version = atmel_mci_get_version(mci); @@ -73,16 +78,16 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) clkodd = clkdiv & 1; clkdiv >>= 1; - printf("mci: setting clock %u Hz, block size %u\n", - bus_hz / (clkdiv * 2 + clkodd + 2), blklen); + debug("mci: setting clock %u Hz, block size %u\n", + bus_hz / (clkdiv * 2 + clkodd + 2), blklen); } else { /* find clkdiv yielding a rate <= than requested */ for (clkdiv = 0; clkdiv < 255; clkdiv++) { if ((bus_hz / (clkdiv + 1) / 2) <= hz) break; } - printf("mci: setting clock %u Hz, block size %u\n", - (bus_hz / (clkdiv + 1)) / 2, blklen); + debug("mci: setting clock %u Hz, block size %u\n", + (bus_hz / (clkdiv + 1)) / 2, blklen); } } @@ -113,7 +118,9 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS) writel(MMCI_BIT(HSMODE), &mci->cfg); - initialized = 1; + udelay(50); + + priv->initialized = 1; } /* Return the CMDR with flags for a given command and data packet */ @@ -196,12 +203,13 @@ io_fail: static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - atmel_mci_t *mci = mmc->priv; + struct atmel_mci_priv *priv = mmc->priv; + atmel_mci_t *mci = priv->mci; u32 cmdr; u32 error_flags = 0; u32 status; - if (!initialized) { + if (!priv->initialized) { puts ("MCI not initialized!\n"); return COMM_ERR; } @@ -321,7 +329,8 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Entered into mmc structure during driver init */ static void mci_set_ios(struct mmc *mmc) { - atmel_mci_t *mci = mmc->priv; + struct atmel_mci_priv *priv = mmc->priv; + atmel_mci_t *mci = priv->mci; int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; @@ -357,7 +366,8 @@ static void mci_set_ios(struct mmc *mmc) /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { - atmel_mci_t *mci = mmc->priv; + struct atmel_mci_priv *priv = mmc->priv; + atmel_mci_t *mci = priv->mci; /* Initialize controller */ writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ @@ -391,22 +401,24 @@ int atmel_mci_init(void *regs) { struct mmc *mmc; struct mmc_config *cfg; - struct atmel_mci *mci; + struct atmel_mci_priv *priv; unsigned int version; - cfg = malloc(sizeof(*cfg)); - if (cfg == NULL) - return -1; - memset(cfg, 0, sizeof(*cfg)); + priv = calloc(1, sizeof(*priv)); + if (!priv) + return -ENOMEM; - mci = (struct atmel_mci *)regs; + cfg = &priv->cfg; cfg->name = "mci"; cfg->ops = &atmel_mci_ops; + priv->mci = (struct atmel_mci *)regs; + priv->initialized = 0; + /* need to be able to pass these in on a board by board basis */ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - version = atmel_mci_get_version(mci); + version = atmel_mci_get_version(priv->mci); if ((version & 0xf00) >= 0x300) { cfg->host_caps = MMC_MODE_8BIT; cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; @@ -423,13 +435,13 @@ int atmel_mci_init(void *regs) cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc = mmc_create(cfg, regs); + mmc = mmc_create(cfg, priv); if (mmc == NULL) { - free(cfg); - return -1; + free(priv); + return -ENODEV; } - /* NOTE: possibly leaking the cfg structure */ + /* NOTE: possibly leaking the priv structure */ return 0; } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 15ecfee961..44353c72f4 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -106,6 +106,12 @@ static int do_sdhci_init(struct sdhci_host *host) flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; dev_id = host->index + PERIPH_ID_SDMMC0; + ret = exynos_pinmux_config(dev_id, flag); + if (ret) { + printf("external SD not configured\n"); + return ret; + } + if (dm_gpio_is_valid(&host->pwr_gpio)) { dm_gpio_set_value(&host->pwr_gpio, 1); ret = exynos_pinmux_config(dev_id, flag); @@ -121,12 +127,6 @@ static int do_sdhci_init(struct sdhci_host *host) debug("no SD card detected (%d)\n", ret); return -ENODEV; } - - ret = exynos_pinmux_config(dev_id, flag); - if (ret) { - printf("external SD not configured\n"); - return ret; - } } return s5p_sdhci_core_init(host); @@ -193,7 +193,7 @@ static int process_nodes(const void *blob, int node_list[], int count) } ret = do_sdhci_init(host); - if (ret) { + if (ret && ret != -ENODEV) { printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret); failed++; } diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index d89e302841..02d71b9344 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -286,9 +286,25 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { struct sdhci_host *host = mmc->priv; - unsigned int div, clk, timeout; + unsigned int div, clk, timeout, reg; - sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + /* Wait max 20 ms */ + timeout = 200; + while (sdhci_readl(host, SDHCI_PRESENT_STATE) & + (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { + if (timeout == 0) { + printf("%s: Timeout to wait cmd & data inhibit\n", + __func__); + return -1; + } + + timeout--; + udelay(100); + } + + reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + reg &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); if (clock == 0) return 0; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 59278d1eef..c58841e7d8 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -1,3 +1,35 @@ +menu "MTD Support" + +config MTD + bool "Enable Driver Model for MTD drivers" + depends on DM + help + Enable driver model for Memory Technology Devices (MTD), such as + flash, RAM and similar chips, often used for solid state file + systems on embedded devices. + +config CFI_FLASH + bool "Enable Driver Model for CFI Flash driver" + depends on MTD + help + The Common Flash Interface specification was developed by Intel, + AMD and other flash manufactures. It provides a universal method + for probing the capabilities of flash devices. If you wish to + support any device that is CFI-compliant, you need to enable this + option. Visit <http://www.amd.com/products/nvd/overview/cfi.html> + for more information on CFI. + +config ALTERA_QSPI + bool "Altera Generic Quad SPI Controller" + depends on MTD + help + This enables access to Altera EPCQ/EPCS flash chips using the + Altera Generic Quad SPI Controller. The controller converts SPI + NOR flash to parallel flash interface. Please find details on the + "Embedded Peripherals IP User Guide" of Altera. + +endmenu + source "drivers/mtd/nand/Kconfig" source "drivers/mtd/spi/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index a623f4c9fa..7f018a4eca 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -8,8 +8,10 @@ ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)$(CONFIG_CMD_SF))) obj-y += mtdcore.o mtd_uboot.o endif +obj-$(CONFIG_MTD) += mtd-uclass.o obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o +obj-$(CONFIG_ALTERA_QSPI) += altera_qspi.o obj-$(CONFIG_HAS_DATAFLASH) += at45.o obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c new file mode 100644 index 0000000000..1826dc8272 --- /dev/null +++ b/drivers/mtd/altera_qspi.c @@ -0,0 +1,273 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdt_support.h> +#include <flash.h> +#include <mtd.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The QUADSPI_MEM_OP register is used to do memory protect and erase operations + */ +#define QUADSPI_MEM_OP_BULK_ERASE 0x00000001 +#define QUADSPI_MEM_OP_SECTOR_ERASE 0x00000002 +#define QUADSPI_MEM_OP_SECTOR_PROTECT 0x00000003 + +/* + * The QUADSPI_ISR register is used to determine whether an invalid write or + * erase operation trigerred an interrupt + */ +#define QUADSPI_ISR_ILLEGAL_ERASE BIT(0) +#define QUADSPI_ISR_ILLEGAL_WRITE BIT(1) + +struct altera_qspi_regs { + u32 rd_status; + u32 rd_sid; + u32 rd_rdid; + u32 mem_op; + u32 isr; + u32 imr; + u32 chip_select; +}; + +struct altera_qspi_platdata { + struct altera_qspi_regs *regs; + void *base; + unsigned long size; +}; + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */ + +void flash_print_info(flash_info_t *info) +{ + printf("Altera QSPI flash Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + struct mtd_info *mtd = info->mtd; + struct erase_info instr; + int ret; + + memset(&instr, 0, sizeof(instr)); + instr.addr = mtd->erasesize * s_first; + instr.len = mtd->erasesize * (s_last + 1 - s_first); + ret = mtd_erase(mtd, &instr); + if (ret) + return ERR_NOT_ERASED; + + return 0; +} + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + struct mtd_info *mtd = info->mtd; + struct udevice *dev = mtd->dev; + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + ulong base = (ulong)pdata->base; + loff_t to = addr - base; + size_t retlen; + int ret; + + ret = mtd_write(mtd, to, cnt, &retlen, src); + if (ret) + return ERR_NOT_ERASED; + + return 0; +} + +unsigned long flash_init(void) +{ + struct udevice *dev; + + /* probe every MTD device */ + for (uclass_first_device(UCLASS_MTD, &dev); + dev; + uclass_next_device(&dev)) { + } + + return flash_info[0].size; +} + +static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr) +{ + struct udevice *dev = mtd->dev; + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + struct altera_qspi_regs *regs = pdata->regs; + size_t addr = instr->addr; + size_t len = instr->len; + size_t end = addr + len; + u32 sect; + u32 stat; + + instr->state = MTD_ERASING; + addr &= ~(mtd->erasesize - 1); /* get lower aligned address */ + while (addr < end) { + sect = addr / mtd->erasesize; + sect <<= 8; + sect |= QUADSPI_MEM_OP_SECTOR_ERASE; + debug("erase %08x\n", sect); + writel(sect, ®s->mem_op); + stat = readl(®s->isr); + if (stat & QUADSPI_ISR_ILLEGAL_ERASE) { + /* erase failed, sector might be protected */ + debug("erase %08x fail %x\n", sect, stat); + writel(stat, ®s->isr); /* clear isr */ + instr->state = MTD_ERASE_FAILED; + return -EIO; + } + addr += mtd->erasesize; + } + instr->state = MTD_ERASE_DONE; + mtd_erase_callback(instr); + + return 0; +} + +static int altera_qspi_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + struct udevice *dev = mtd->dev; + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + + memcpy_fromio(buf, pdata->base + from, len); + *retlen = len; + + return 0; +} + +static int altera_qspi_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + struct udevice *dev = mtd->dev; + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + struct altera_qspi_regs *regs = pdata->regs; + u32 stat; + + memcpy_toio(pdata->base + to, buf, len); + /* check whether write triggered a illegal write interrupt */ + stat = readl(®s->isr); + if (stat & QUADSPI_ISR_ILLEGAL_WRITE) { + /* write failed, sector might be protected */ + debug("write fail %x\n", stat); + writel(stat, ®s->isr); /* clear isr */ + return -EIO; + } + *retlen = len; + + return 0; +} + +static void altera_qspi_sync(struct mtd_info *mtd) +{ +} + +static int altera_qspi_probe(struct udevice *dev) +{ + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + struct altera_qspi_regs *regs = pdata->regs; + unsigned long base = (unsigned long)pdata->base; + struct mtd_info *mtd; + flash_info_t *flash = &flash_info[0]; + u32 rdid; + int i; + + rdid = readl(®s->rd_rdid); + debug("rdid %x\n", rdid); + + mtd = dev_get_uclass_priv(dev); + mtd->dev = dev; + mtd->name = "nor0"; + mtd->type = MTD_NORFLASH; + mtd->flags = MTD_CAP_NORFLASH; + mtd->size = 1 << ((rdid & 0xff) - 6); + mtd->writesize = 1; + mtd->writebufsize = mtd->writesize; + mtd->_erase = altera_qspi_erase; + mtd->_read = altera_qspi_read; + mtd->_write = altera_qspi_write; + mtd->_sync = altera_qspi_sync; + mtd->numeraseregions = 0; + mtd->erasesize = 0x10000; + if (add_mtd_device(mtd)) + return -ENOMEM; + + flash->mtd = mtd; + flash->size = mtd->size; + flash->sector_count = mtd->size / mtd->erasesize; + flash->flash_id = rdid; + flash->start[0] = base; + for (i = 1; i < flash->sector_count; i++) + flash->start[i] = flash->start[i - 1] + mtd->erasesize; + gd->bd->bi_flashstart = base; + + return 0; +} + +static int altera_qspi_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + void *blob = (void *)gd->fdt_blob; + int node = dev->of_offset; + const char *list, *end; + const fdt32_t *cell; + void *base; + unsigned long addr, size; + int parent, addrc, sizec; + int len, idx; + + /* + * decode regs. there are multiple reg tuples, and they need to + * match with reg-names. + */ + parent = fdt_parent_offset(blob, node); + of_bus_default_count_cells(blob, parent, &addrc, &sizec); + list = fdt_getprop(blob, node, "reg-names", &len); + if (!list) + return -ENOENT; + end = list + len; + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) + return -ENOENT; + idx = 0; + while (list < end) { + addr = fdt_translate_address((void *)blob, + node, cell + idx); + size = fdt_addr_to_cpu(cell[idx + addrc]); + base = ioremap(addr, size); + len = strlen(list); + if (strcmp(list, "avl_csr") == 0) { + pdata->regs = base; + } else if (strcmp(list, "avl_mem") == 0) { + pdata->base = base; + pdata->size = size; + } + idx += addrc + sizec; + list += (len + 1); + } + + return 0; +} + +static const struct udevice_id altera_qspi_ids[] = { + { .compatible = "altr,quadspi-1.0" }, + {} +}; + +U_BOOT_DRIVER(altera_qspi) = { + .name = "altera_qspi", + .id = UCLASS_MTD, + .of_match = altera_qspi_ids, + .ofdata_to_platdata = altera_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_qspi_platdata), + .probe = altera_qspi_probe, +}; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index fc7a878d59..e3cb59887c 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -18,6 +18,9 @@ /* #define DEBUG */ #include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdt_support.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/byteorder.h> @@ -47,6 +50,8 @@ * reading and writing ... (yes there is such a Hardware). */ +DECLARE_GLOBAL_DATA_PTR; + static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; #ifdef CONFIG_FLASH_CFI_MTD static uint flash_verbose = 1; @@ -87,10 +92,36 @@ static u16 cfi_flash_config_reg(int i) int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; #endif +#ifdef CONFIG_CFI_FLASH /* for driver model */ +static void cfi_flash_init_dm(void) +{ + struct udevice *dev; + + cfi_flash_num_flash_banks = 0; + /* + * The uclass_first_device() will probe the first device and + * uclass_next_device() will probe the rest if they exist. So + * that cfi_flash_probe() will get called assigning the base + * addresses that are available. + */ + for (uclass_first_device(UCLASS_MTD, &dev); + dev; + uclass_next_device(&dev)) { + } +} + +static phys_addr_t cfi_flash_base[CFI_MAX_FLASH_BANKS]; + +phys_addr_t cfi_flash_bank_addr(int i) +{ + return cfi_flash_base[i]; +} +#else __weak phys_addr_t cfi_flash_bank_addr(int i) { return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; } +#endif __weak unsigned long cfi_flash_bank_size(int i) { @@ -2322,6 +2353,10 @@ unsigned long flash_init (void) getenv_f("unlock", s, sizeof(s)); #endif +#ifdef CONFIG_CFI_FLASH /* for driver model */ + cfi_flash_init_dm(); +#endif + /* Init: no FLASHes known */ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; @@ -2398,3 +2433,46 @@ unsigned long flash_init (void) return (size); } + +#ifdef CONFIG_CFI_FLASH /* for driver model */ +static int cfi_flash_probe(struct udevice *dev) +{ + void *blob = (void *)gd->fdt_blob; + int node = dev->of_offset; + const fdt32_t *cell; + phys_addr_t addr; + int parent, addrc, sizec; + int len, idx; + + parent = fdt_parent_offset(blob, node); + of_bus_default_count_cells(blob, parent, &addrc, &sizec); + /* decode regs, there may be multiple reg tuples. */ + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) + return -ENOENT; + idx = 0; + len /= sizeof(fdt32_t); + while (idx < len) { + addr = fdt_translate_address((void *)blob, + node, cell + idx); + cfi_flash_base[cfi_flash_num_flash_banks++] = addr; + idx += addrc + sizec; + } + gd->bd->bi_flashstart = cfi_flash_base[0]; + + return 0; +} + +static const struct udevice_id cfi_flash_ids[] = { + { .compatible = "cfi-flash" }, + { .compatible = "jedec-flash" }, + {} +}; + +U_BOOT_DRIVER(cfi_flash) = { + .name = "cfi_flash", + .id = UCLASS_MTD, + .of_match = cfi_flash_ids, + .probe = cfi_flash_probe, +}; +#endif /* CONFIG_CFI_FLASH */ diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c new file mode 100644 index 0000000000..7b7c48ec5a --- /dev/null +++ b/drivers/mtd/mtd-uclass.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <mtd.h> + +/* + * Implement a MTD uclass which should include most flash drivers. + * The uclass private is pointed to mtd_info. + */ + +UCLASS_DRIVER(mtd) = { + .id = UCLASS_MTD, + .name = "mtd", + .per_device_auto_alloc_size = sizeof(struct mtd_info), +}; diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 2f2172b987..e3f56e5424 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -27,11 +27,11 @@ #include <linux/gfp.h> #include <linux/slab.h> #else -#include <linux/compat.h> #include <linux/err.h> #include <ubi_uboot.h> #endif +#include <linux/log2.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 8a3e5ec3d7..8793f1865a 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -105,6 +105,9 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN (1 << 1) #define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7) +#define SR_BP0 BIT(2) /* Block protect 0 */ +#define SR_BP1 BIT(3) /* Block protect 1 */ +#define SR_BP2 BIT(4) /* Block protect 2 */ /* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) @@ -173,6 +176,15 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); /* Program the status register */ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); +/* Lock stmicro spi flash region */ +int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); + +/* Unlock stmicro spi flash region */ +int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len); + +/* Check if a stmicro spi flash region is completely locked */ +int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); + /* Read the config register */ int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index f2a9244a14..d8324645b2 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -15,6 +15,7 @@ #include <spi_flash.h> #include <watchdog.h> #include <linux/compiler.h> +#include <linux/log2.h> #include "sf_internal.h" @@ -267,6 +268,11 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) return -1; } + if (flash->flash_is_locked(flash, offset, len) > 0) { + printf("offset 0x%x is protected and cannot be erased\n", offset); + return -EINVAL; + } + cmd[0] = flash->erase_cmd; while (len) { erase_addr = offset; @@ -309,6 +315,11 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, page_size = flash->page_size; + if (flash->flash_is_locked(flash, offset, len) > 0) { + printf("offset 0x%x is protected and cannot be written\n", offset); + return -EINVAL; + } + cmd[0] = flash->write_cmd; for (actual = 0; actual < len; actual += chunk_len) { write_addr = offset; @@ -565,3 +576,172 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, return ret; } #endif + +#ifdef CONFIG_SPI_FLASH_STMICRO +static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, + u32 *len) +{ + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + int shift = ffs(mask) - 1; + int pow; + + if (!(sr & mask)) { + /* No protection */ + *ofs = 0; + *len = 0; + } else { + pow = ((sr & mask) ^ mask) >> shift; + *len = flash->size >> pow; + *ofs = flash->size - *len; + } +} + +/* + * Return 1 if the entire region is locked, 0 otherwise + */ +static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len, + u8 sr) +{ + loff_t lock_offs; + u32 lock_len; + + stm_get_locked_range(flash, sr, &lock_offs, &lock_len); + + return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); +} + +/* + * Check if a region of the flash is (completely) locked. See stm_lock() for + * more info. + * + * Returns 1 if entire region is locked, 0 if any portion is unlocked, and + * negative on errors. + */ +int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) +{ + int status; + u8 sr; + + status = spi_flash_cmd_read_status(flash, &sr); + if (status < 0) + return status; + + return stm_is_locked_sr(flash, ofs, len, sr); +} + +/* + * Lock a region of the flash. Compatible with ST Micro and similar flash. + * Supports only the block protection bits BP{0,1,2} in the status register + * (SR). Does not support these features found in newer SR bitfields: + * - TB: top/bottom protect - only handle TB=0 (top protect) + * - SEC: sector/block protect - only handle SEC=0 (block protect) + * - CMP: complement protect - only support CMP=0 (range is not complemented) + * + * Sample table portion for 8MB flash (Winbond w25q64fw): + * + * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion + * -------------------------------------------------------------------------- + * X | X | 0 | 0 | 0 | NONE | NONE + * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 + * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 + * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 + * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 + * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 + * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 + * X | X | 1 | 1 | 1 | 8 MB | ALL + * + * Returns negative on errors, 0 on success. + */ +int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) +{ + u8 status_old, status_new; + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + u8 shift = ffs(mask) - 1, pow, val; + + spi_flash_cmd_read_status(flash, &status_old); + + /* SPI NOR always locks to the end */ + if (ofs + len != flash->size) { + /* Does combined region extend to end? */ + if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, + status_old)) + return -EINVAL; + len = flash->size - ofs; + } + + /* + * Need smallest pow such that: + * + * 1 / (2^pow) <= (len / size) + * + * so (assuming power-of-2 size) we do: + * + * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) + */ + pow = ilog2(flash->size) - ilog2(len); + val = mask - (pow << shift); + if (val & ~mask) + return -EINVAL; + + /* Don't "lock" with no region! */ + if (!(val & mask)) + return -EINVAL; + + status_new = (status_old & ~mask) | val; + + /* Only modify protection if it will not unlock other areas */ + if ((status_new & mask) <= (status_old & mask)) + return -EINVAL; + + spi_flash_cmd_write_status(flash, status_new); + + return 0; +} + +/* + * Unlock a region of the flash. See stm_lock() for more info + * + * Returns negative on errors, 0 on success. + */ +int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) +{ + uint8_t status_old, status_new; + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + u8 shift = ffs(mask) - 1, pow, val; + + spi_flash_cmd_read_status(flash, &status_old); + + /* Cannot unlock; would unlock larger region than requested */ + if (stm_is_locked_sr(flash, status_old, ofs - flash->erase_size, + flash->erase_size)) + return -EINVAL; + /* + * Need largest pow such that: + * + * 1 / (2^pow) >= (len / size) + * + * so (assuming power-of-2 size) we do: + * + * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) + */ + pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); + if (ofs + len == flash->size) { + val = 0; /* fully unlocked */ + } else { + val = mask - (pow << shift); + /* Some power-of-two sizes are not supported */ + if (val & ~mask) + return -EINVAL; + } + + status_new = (status_old & ~mask) | val; + + /* Only modify protection if it will not lock other areas */ + if ((status_new & mask) >= (status_old & mask)) + return -EINVAL; + + spi_flash_cmd_write_status(flash, status_new); + + return 0; +} +#endif /* CONFIG_SPI_FLASH_STMICRO */ diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index c000c53274..bc05d30221 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -182,6 +182,19 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, flash->read = spi_flash_cmd_read_ops; #endif + /* lock hooks are flash specific - assign them based on idcode0 */ + switch (idcode[0]) { +#ifdef CONFIG_SPI_FLASH_STMICRO + case SPI_FLASH_CFI_MFR_STMICRO: + flash->flash_lock = stm_lock; + flash->flash_unlock = stm_unlock; + flash->flash_is_locked = stm_is_locked; +#endif + break; + default: + debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); + } + /* Compute the flash size */ flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; /* diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index f0a3b67942..f484e62b32 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -30,7 +30,7 @@ #include <linux/slab.h> #include <linux/major.h> #else -#include <linux/compat.h> +#include <linux/log2.h> #endif #include <linux/err.h> #include <ubi_uboot.h> diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index 319983c482..5692fe9d4a 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -27,12 +27,12 @@ static inline void alt_sgdma_construct_descriptor( struct alt_sgdma_descriptor *next, void *read_addr, void *write_addr, - unsigned short length_or_eop, + u16 length_or_eop, int generate_eop, int read_fixed, int write_fixed_or_sop) { - unsigned char val; + u8 val; /* * Mark the "next" descriptor as "not" owned by hardware. This prevents @@ -100,7 +100,7 @@ static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs) static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs, struct alt_sgdma_descriptor *desc) { - unsigned int val; + u32 val; /* Point the controller at the descriptor */ writel(virt_to_phys(desc), ®s->next_descriptor_pointer); @@ -121,7 +121,7 @@ static void tse_adjust_link(struct altera_tse_priv *priv, struct phy_device *phydev) { struct alt_tse_mac *mac_dev = priv->mac_dev; - unsigned int refvar; + u32 refvar; if (!phydev->link) { debug("%s: No link.\n", phydev->dev->name); @@ -152,13 +152,11 @@ static void tse_adjust_link(struct altera_tse_priv *priv, writel(refvar, &mac_dev->command_config); } -static int altera_tse_send(struct udevice *dev, void *packet, int length) +static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length) { struct altera_tse_priv *priv = dev_get_priv(dev); struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; - unsigned long tx_buf = (unsigned long)packet; - flush_dcache_range(tx_buf, tx_buf + length); alt_sgdma_construct_descriptor( tx_desc, tx_desc + 1, @@ -178,7 +176,8 @@ static int altera_tse_send(struct udevice *dev, void *packet, int length) return tx_desc->actual_bytes_transferred; } -static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) +static int altera_tse_recv_sgdma(struct udevice *dev, int flags, + uchar **packetp) { struct altera_tse_priv *priv = dev_get_priv(dev); struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; @@ -186,6 +185,7 @@ static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) if (rx_desc->descriptor_status & ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { + alt_sgdma_wait_transfer(priv->sgdma_rx); packet_length = rx_desc->actual_bytes_transferred; debug("recv %d bytes\n", packet_length); *packetp = priv->rx_buf; @@ -196,15 +196,12 @@ static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) return -EAGAIN; } -static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, - int length) +static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet, + int length) { struct altera_tse_priv *priv = dev_get_priv(dev); struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; - unsigned long rx_buf = (unsigned long)priv->rx_buf; - alt_sgdma_wait_transfer(priv->sgdma_rx); - invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN); alt_sgdma_construct_descriptor( rx_desc, rx_desc + 1, @@ -223,16 +220,33 @@ static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, return 0; } -static void altera_tse_stop(struct udevice *dev) +static void altera_tse_stop_mac(struct altera_tse_priv *priv) { - struct altera_tse_priv *priv = dev_get_priv(dev); struct alt_tse_mac *mac_dev = priv->mac_dev; + u32 status; + ulong ctime; + + /* reset the mac */ + writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config); + ctime = get_timer(0); + while (1) { + status = readl(&mac_dev->command_config); + if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK)) + break; + if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { + debug("Reset mac timeout\n"); + break; + } + } +} + +static void altera_tse_stop_sgdma(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; - unsigned int status; int ret; - ulong ctime; /* clear rx desc & wait for sgdma to complete */ rx_desc->descriptor_control = 0; @@ -247,26 +261,128 @@ static void altera_tse_stop(struct udevice *dev) if (ret == -ETIMEDOUT) writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &tx_sgdma->control); +} - /* reset the mac */ - writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config); +static void msgdma_reset(struct msgdma_csr *csr) +{ + u32 status; + ulong ctime; + + /* Reset mSGDMA */ + writel(MSGDMA_CSR_STAT_MASK, &csr->status); + writel(MSGDMA_CSR_CTL_RESET, &csr->control); ctime = get_timer(0); while (1) { - status = readl(&mac_dev->command_config); - if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK)) + status = readl(&csr->status); + if (!(status & MSGDMA_CSR_STAT_RESETTING)) break; if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { - debug("Reset mac timeout\n"); + debug("Reset msgdma timeout\n"); + break; + } + } + /* Clear status */ + writel(MSGDMA_CSR_STAT_MASK, &csr->status); +} + +static u32 msgdma_wait(struct msgdma_csr *csr) +{ + u32 status; + ulong ctime; + + /* Wait for the descriptor to complete */ + ctime = get_timer(0); + while (1) { + status = readl(&csr->status); + if (!(status & MSGDMA_CSR_STAT_BUSY)) + break; + if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { + debug("sgdma timeout\n"); break; } } + /* Clear status */ + writel(MSGDMA_CSR_STAT_MASK, &csr->status); + + return status; +} + +static int altera_tse_send_msgdma(struct udevice *dev, void *packet, + int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct msgdma_extended_desc *desc = priv->tx_desc; + u32 tx_buf = virt_to_phys(packet); + u32 status; + + writel(tx_buf, &desc->read_addr_lo); + writel(0, &desc->read_addr_hi); + writel(0, &desc->write_addr_lo); + writel(0, &desc->write_addr_hi); + writel(length, &desc->len); + writel(0, &desc->burst_seq_num); + writel(MSGDMA_DESC_TX_STRIDE, &desc->stride); + writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control); + status = msgdma_wait(priv->sgdma_tx); + debug("sent %d bytes, status %08x\n", length, status); + + return 0; +} + +static int altera_tse_recv_msgdma(struct udevice *dev, int flags, + uchar **packetp) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct msgdma_csr *csr = priv->sgdma_rx; + struct msgdma_response *resp = priv->rx_resp; + u32 level, length, status; + + level = readl(&csr->resp_fill_level); + if (level & 0xffff) { + length = readl(&resp->bytes_transferred); + status = readl(&resp->status); + debug("recv %d bytes, status %08x\n", length, status); + *packetp = priv->rx_buf; + + return length; + } + + return -EAGAIN; +} + +static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet, + int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct msgdma_extended_desc *desc = priv->rx_desc; + u32 rx_buf = virt_to_phys(priv->rx_buf); + + writel(0, &desc->read_addr_lo); + writel(0, &desc->read_addr_hi); + writel(rx_buf, &desc->write_addr_lo); + writel(0, &desc->write_addr_hi); + writel(PKTSIZE_ALIGN, &desc->len); + writel(0, &desc->burst_seq_num); + writel(MSGDMA_DESC_RX_STRIDE, &desc->stride); + writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control); + debug("recv setup\n"); + + return 0; +} + +static void altera_tse_stop_msgdma(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + + msgdma_reset(priv->sgdma_rx); + msgdma_reset(priv->sgdma_tx); } static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { struct altera_tse_priv *priv = bus->priv; struct alt_tse_mac *mac_dev = priv->mac_dev; - unsigned int value; + u32 value; /* set mdio address */ writel(addr, &mac_dev->mdio_phy1_addr); @@ -337,7 +453,7 @@ static int altera_tse_write_hwaddr(struct udevice *dev) struct alt_tse_mac *mac_dev = priv->mac_dev; struct eth_pdata *pdata = dev_get_platdata(dev); u8 *hwaddr = pdata->enetaddr; - unsigned int mac_lo, mac_hi; + u32 mac_lo, mac_hi; mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) | (hwaddr[1] << 8) | hwaddr[0]; @@ -358,11 +474,47 @@ static int altera_tse_write_hwaddr(struct udevice *dev) return 0; } +static int altera_tse_send(struct udevice *dev, void *packet, int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + unsigned long tx_buf = (unsigned long)packet; + + flush_dcache_range(tx_buf, tx_buf + length); + + return priv->ops->send(dev, packet, length); +} + +static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + + return priv->ops->recv(dev, flags, packetp); +} + +static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + unsigned long rx_buf = (unsigned long)priv->rx_buf; + + invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN); + + return priv->ops->free_pkt(dev, packet, length); +} + +static void altera_tse_stop(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + + priv->ops->stop(dev); + altera_tse_stop_mac(priv); +} + static int altera_tse_start(struct udevice *dev) { struct altera_tse_priv *priv = dev_get_priv(dev); struct alt_tse_mac *mac_dev = priv->mac_dev; - unsigned int val; + u32 val; int ret; /* need to create sgdma */ @@ -405,24 +557,45 @@ static int altera_tse_start(struct udevice *dev) return 0; } +static const struct tse_ops tse_sgdma_ops = { + .send = altera_tse_send_sgdma, + .recv = altera_tse_recv_sgdma, + .free_pkt = altera_tse_free_pkt_sgdma, + .stop = altera_tse_stop_sgdma, +}; + +static const struct tse_ops tse_msgdma_ops = { + .send = altera_tse_send_msgdma, + .recv = altera_tse_recv_msgdma, + .free_pkt = altera_tse_free_pkt_msgdma, + .stop = altera_tse_stop_msgdma, +}; + static int altera_tse_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct altera_tse_priv *priv = dev_get_priv(dev); - const void *blob = gd->fdt_blob; + void *blob = (void *)gd->fdt_blob; int node = dev->of_offset; const char *list, *end; const fdt32_t *cell; void *base, *desc_mem = NULL; unsigned long addr, size; + int parent, addrc, sizec; int len, idx; int ret; + priv->dma_type = dev_get_driver_data(dev); + if (priv->dma_type == ALT_SGDMA) + priv->ops = &tse_sgdma_ops; + else + priv->ops = &tse_msgdma_ops; /* - * decode regs, assume address-cells and size-cells are both one. - * there are multiple reg tuples, and they need to match with - * reg-names. + * decode regs. there are multiple reg tuples, and they need to + * match with reg-names. */ + parent = fdt_parent_offset(blob, node); + of_bus_default_count_cells(blob, parent, &addrc, &sizec); list = fdt_getprop(blob, node, "reg-names", &len); if (!list) return -ENOENT; @@ -434,18 +607,24 @@ static int altera_tse_probe(struct udevice *dev) while (list < end) { addr = fdt_translate_address((void *)blob, node, cell + idx); - size = fdt_addr_to_cpu(cell[idx + 1]); + size = fdt_addr_to_cpu(cell[idx + addrc]); base = ioremap(addr, size); len = strlen(list); if (strcmp(list, "control_port") == 0) priv->mac_dev = base; else if (strcmp(list, "rx_csr") == 0) priv->sgdma_rx = base; + else if (strcmp(list, "rx_desc") == 0) + priv->rx_desc = base; + else if (strcmp(list, "rx_resp") == 0) + priv->rx_resp = base; else if (strcmp(list, "tx_csr") == 0) priv->sgdma_tx = base; + else if (strcmp(list, "tx_desc") == 0) + priv->tx_desc = base; else if (strcmp(list, "s1") == 0) desc_mem = base; - idx += 2; + idx += addrc + sizec; list += (len + 1); } /* decode fifo depth */ @@ -460,15 +639,18 @@ static int altera_tse_probe(struct udevice *dev) priv->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); /* init desc */ - len = sizeof(struct alt_sgdma_descriptor) * 4; - if (!desc_mem) { - desc_mem = dma_alloc_coherent(len, &addr); - if (!desc_mem) - return -ENOMEM; + if (priv->dma_type == ALT_SGDMA) { + len = sizeof(struct alt_sgdma_descriptor) * 4; + if (!desc_mem) { + desc_mem = dma_alloc_coherent(len, &addr); + if (!desc_mem) + return -ENOMEM; + } + memset(desc_mem, 0, len); + priv->tx_desc = desc_mem; + priv->rx_desc = priv->tx_desc + + 2 * sizeof(struct alt_sgdma_descriptor); } - memset(desc_mem, 0, len); - priv->tx_desc = desc_mem; - priv->rx_desc = priv->tx_desc + 2; /* allocate recv packet buffer */ priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN); if (!priv->rx_buf) @@ -515,8 +697,9 @@ static const struct eth_ops altera_tse_ops = { }; static const struct udevice_id altera_tse_ids[] = { - { .compatible = "altr,tse-1.0", }, - { } + { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA }, + { .compatible = "altr,tse-1.0", .data = ALT_SGDMA }, + {} }; U_BOOT_DRIVER(altera_tse) = { diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h index 08c4f660a0..2b1af81429 100644 --- a/drivers/net/altera_tse.h +++ b/drivers/net/altera_tse.h @@ -11,22 +11,18 @@ #ifndef _ALTERA_TSE_H_ #define _ALTERA_TSE_H_ -#define __packed_1_ __attribute__ ((packed, aligned(1))) +#define __packed_1_ __packed __aligned(1) -/* SGDMA Stuff */ -#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001) -#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002) -#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004) -#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008) -#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) +/* dma type */ +#define ALT_SGDMA 0 +#define ALT_MSGDMA 1 -#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) -#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) -#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) +/* SGDMA Stuff */ +#define ALT_SGDMA_STATUS_BUSY_MSK BIT(4) -#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \ - | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \ - | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK) +#define ALT_SGDMA_CONTROL_RUN_MSK BIT(5) +#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6) +#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16) /* * Descriptor control bit masks & offsets @@ -35,11 +31,10 @@ * The following bit-offsets are expressed relative to the LSB of * the control register bitfield. */ -#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) -#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) -#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) -#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008) -#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7) /* * Descriptor status bit masks & offsets @@ -48,15 +43,7 @@ * The following bit-offsets are expressed relative to the LSB of * the status register bitfield. */ -#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001) -#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002) -#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004) -#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008) -#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010) -#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020) -#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040) -#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) -#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F) +#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7) /* * The SGDMA controller buffer descriptor allocates @@ -71,70 +58,101 @@ * */ struct alt_sgdma_descriptor { - unsigned int source; /* the address of data to be read. */ - unsigned int source_pad; + u32 source; /* the address of data to be read. */ + u32 source_pad; - unsigned int destination; /* the address to write data */ - unsigned int destination_pad; + u32 destination; /* the address to write data */ + u32 destination_pad; - unsigned int next; /* the next descriptor in the list. */ - unsigned int next_pad; + u32 next; /* the next descriptor in the list. */ + u32 next_pad; - unsigned short bytes_to_transfer; /* the number of bytes to transfer */ - unsigned char read_burst; - unsigned char write_burst; + u16 bytes_to_transfer; /* the number of bytes to transfer */ + u8 read_burst; + u8 write_burst; - unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ - unsigned char descriptor_status; - unsigned char descriptor_control; + u16 actual_bytes_transferred;/* bytes transferred by DMA */ + u8 descriptor_status; + u8 descriptor_control; } __packed_1_; /* SG-DMA Control/Status Slave registers map */ struct alt_sgdma_registers { - unsigned int status; - unsigned int status_pad[3]; - unsigned int control; - unsigned int control_pad[3]; - unsigned int next_descriptor_pointer; - unsigned int descriptor_pad[3]; + u32 status; + u32 status_pad[3]; + u32 control; + u32 control_pad[3]; + u32 next_descriptor_pointer; + u32 descriptor_pad[3]; +}; + +/* mSGDMA Stuff */ + +/* mSGDMA extended descriptor format */ +struct msgdma_extended_desc { + u32 read_addr_lo; /* data buffer source address low bits */ + u32 write_addr_lo; /* data buffer destination address low bits */ + u32 len; + u32 burst_seq_num; + u32 stride; + u32 read_addr_hi; /* data buffer source address high bits */ + u32 write_addr_hi; /* data buffer destination address high bits */ + u32 control; /* characteristics of the transfer */ +}; + +/* mSGDMA descriptor control field bit definitions */ +#define MSGDMA_DESC_CTL_GEN_SOP BIT(8) +#define MSGDMA_DESC_CTL_GEN_EOP BIT(9) +#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12) +#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13) +#define MSGDMA_DESC_CTL_GO BIT(31) + +/* Tx buffer control flags */ +#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \ + MSGDMA_DESC_CTL_GEN_EOP | \ + MSGDMA_DESC_CTL_GO) + +#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \ + MSGDMA_DESC_CTL_END_ON_LEN | \ + MSGDMA_DESC_CTL_GO) + +/* mSGDMA extended descriptor stride definitions */ +#define MSGDMA_DESC_TX_STRIDE 0x00010001 +#define MSGDMA_DESC_RX_STRIDE 0x00010001 + +/* mSGDMA dispatcher control and status register map */ +struct msgdma_csr { + u32 status; /* Read/Clear */ + u32 control; /* Read/Write */ + u32 rw_fill_level; + u32 resp_fill_level; /* bit 15:0 */ + u32 rw_seq_num; + u32 pad[3]; /* reserved */ +}; + +/* mSGDMA CSR status register bit definitions */ +#define MSGDMA_CSR_STAT_BUSY BIT(0) +#define MSGDMA_CSR_STAT_RESETTING BIT(6) +#define MSGDMA_CSR_STAT_MASK 0x3FF + +/* mSGDMA CSR control register bit definitions */ +#define MSGDMA_CSR_CTL_RESET BIT(1) + +/* mSGDMA response register map */ +struct msgdma_response { + u32 bytes_transferred; + u32 status; }; /* TSE Stuff */ -#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) -#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) -#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004) -#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) -#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010) -#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020) -#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040) -#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080) -#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100) -#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200) -#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) -#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800) -#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000) -#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) -#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000) -#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000) -/* Bits (18:16) = address select */ -#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000) -#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000) -#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000) -#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000) -#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000) -#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000) -#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000) -#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) -#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000) -/* Bits (30..27) reserved */ -#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000) - -#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000) -#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000) - -#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000) +#define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0) +#define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1) +#define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3) +#define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10) +#define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13) +#define ALTERA_TSE_CMD_ENA_10_MSK BIT(25) #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ) @@ -142,116 +160,72 @@ struct alt_sgdma_registers { /* MAC register Space */ struct alt_tse_mac { - unsigned int megacore_revision; - unsigned int scratch_pad; - unsigned int command_config; - unsigned int mac_addr_0; - unsigned int mac_addr_1; - unsigned int max_frame_length; - unsigned int pause_quanta; - unsigned int rx_sel_empty_threshold; - unsigned int rx_sel_full_threshold; - unsigned int tx_sel_empty_threshold; - unsigned int tx_sel_full_threshold; - unsigned int rx_almost_empty_threshold; - unsigned int rx_almost_full_threshold; - unsigned int tx_almost_empty_threshold; - unsigned int tx_almost_full_threshold; - unsigned int mdio_phy0_addr; - unsigned int mdio_phy1_addr; - - /* only if 100/1000 BaseX PCS, reserved otherwise */ - unsigned int reservedx44[5]; - - unsigned int reg_read_access_status; - unsigned int min_tx_ipg_length; - - /* IEEE 802.3 oEntity Managed Object Support */ - unsigned int aMACID_1; /*The MAC addresses */ - unsigned int aMACID_2; - unsigned int aFramesTransmittedOK; - unsigned int aFramesReceivedOK; - unsigned int aFramesCheckSequenceErrors; - unsigned int aAlignmentErrors; - unsigned int aOctetsTransmittedOK; - unsigned int aOctetsReceivedOK; - - /* IEEE 802.3 oPausedEntity Managed Object Support */ - unsigned int aTxPAUSEMACCtrlFrames; - unsigned int aRxPAUSEMACCtrlFrames; - - /* IETF MIB (MIB-II) Object Support */ - unsigned int ifInErrors; - unsigned int ifOutErrors; - unsigned int ifInUcastPkts; - unsigned int ifInMulticastPkts; - unsigned int ifInBroadcastPkts; - unsigned int ifOutDiscards; - unsigned int ifOutUcastPkts; - unsigned int ifOutMulticastPkts; - unsigned int ifOutBroadcastPkts; - - /* IETF RMON MIB Object Support */ - unsigned int etherStatsDropEvent; - unsigned int etherStatsOctets; - unsigned int etherStatsPkts; - unsigned int etherStatsUndersizePkts; - unsigned int etherStatsOversizePkts; - unsigned int etherStatsPkts64Octets; - unsigned int etherStatsPkts65to127Octets; - unsigned int etherStatsPkts128to255Octets; - unsigned int etherStatsPkts256to511Octets; - unsigned int etherStatsPkts512to1023Octets; - unsigned int etherStatsPkts1024to1518Octets; - - unsigned int etherStatsPkts1519toXOctets; - unsigned int etherStatsJabbers; - unsigned int etherStatsFragments; - - unsigned int reservedxE4; + u32 megacore_revision; + u32 scratch_pad; + u32 command_config; + u32 mac_addr_0; + u32 mac_addr_1; + u32 max_frame_length; + u32 pause_quanta; + u32 rx_sel_empty_threshold; + u32 rx_sel_full_threshold; + u32 tx_sel_empty_threshold; + u32 tx_sel_full_threshold; + u32 rx_almost_empty_threshold; + u32 rx_almost_full_threshold; + u32 tx_almost_empty_threshold; + u32 tx_almost_full_threshold; + u32 mdio_phy0_addr; + u32 mdio_phy1_addr; + + u32 reserved1[0x29]; /*FIFO control register. */ - unsigned int tx_cmd_stat; - unsigned int rx_cmd_stat; + u32 tx_cmd_stat; + u32 rx_cmd_stat; - unsigned int ipaccTxConf; - unsigned int ipaccRxConf; - unsigned int ipaccRxStat; - unsigned int ipaccRxStatSum; - - /*Multicast address resolution table */ - unsigned int hash_table[64]; + u32 reserved2[0x44]; /*Registers 0 to 31 within PHY device 0/1 */ - unsigned int mdio_phy0[0x20]; - unsigned int mdio_phy1[0x20]; + u32 mdio_phy0[0x20]; + u32 mdio_phy1[0x20]; /*4 Supplemental MAC Addresses */ - unsigned int supp_mac_addr_0_0; - unsigned int supp_mac_addr_0_1; - unsigned int supp_mac_addr_1_0; - unsigned int supp_mac_addr_1_1; - unsigned int supp_mac_addr_2_0; - unsigned int supp_mac_addr_2_1; - unsigned int supp_mac_addr_3_0; - unsigned int supp_mac_addr_3_1; - - unsigned int reservedx320[56]; + u32 supp_mac_addr_0_0; + u32 supp_mac_addr_0_1; + u32 supp_mac_addr_1_0; + u32 supp_mac_addr_1_1; + u32 supp_mac_addr_2_0; + u32 supp_mac_addr_2_1; + u32 supp_mac_addr_3_0; + u32 supp_mac_addr_3_1; + + u32 reserved3[0x38]; +}; + +struct tse_ops { + int (*send)(struct udevice *dev, void *packet, int length); + int (*recv)(struct udevice *dev, int flags, uchar **packetp); + int (*free_pkt)(struct udevice *dev, uchar *packet, int length); + void (*stop)(struct udevice *dev); }; struct altera_tse_priv { struct alt_tse_mac *mac_dev; - struct alt_sgdma_registers *sgdma_rx; - struct alt_sgdma_registers *sgdma_tx; + void *sgdma_rx; + void *sgdma_tx; unsigned int rx_fifo_depth; unsigned int tx_fifo_depth; - struct alt_sgdma_descriptor *rx_desc; - struct alt_sgdma_descriptor *tx_desc; + void *rx_desc; + void *tx_desc; + void *rx_resp; unsigned char *rx_buf; unsigned int phyaddr; unsigned int interface; struct phy_device *phydev; struct mii_dev *bus; + const struct tse_ops *ops; + int dma_type; }; #endif /* _ALTERA_TSE_H_ */ diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index d052fcb372..a3c9f99627 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_PPC_T4160) += t4240.o obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o +obj-$(CONFIG_LS1043A) += ls1043.o diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c index 8d3dc0e308..b339a84e59 100644 --- a/drivers/net/fm/dtsec.c +++ b/drivers/net/fm/dtsec.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/types.h> #include <asm/io.h> -#include <asm/fsl_dtsec.h> +#include <fsl_dtsec.h> #include <fsl_mdio.h> #include <phy.h> diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 6702f5a520..eb8e93618f 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -13,8 +13,8 @@ #include <fsl_mdio.h> #include <miiphy.h> #include <phy.h> -#include <asm/fsl_dtsec.h> -#include <asm/fsl_tgec.h> +#include <fsl_dtsec.h> +#include <fsl_tgec.h> #include <fsl_memac.h> #include "fm.h" @@ -41,28 +41,35 @@ static void dtsec_configure_serdes(struct fm_eth *priv) bus.priv = priv->mac->phyregs; bool sgmii_2500 = (priv->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + int i = 0; +qsgmii_loop: /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ value = PHY_SGMII_IF_MODE_SGMII; if (!sgmii_2500) value |= PHY_SGMII_IF_MODE_AN; - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value); /* Dev ability according to SGMII specification */ value = PHY_SGMII_DEV_ABILITY_SGMII; - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value); /* Adjust link timer for SGMII - 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */ - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3); - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40); /* Restart AN */ value = PHY_SGMII_CR_DEF_VAL; if (!sgmii_2500) value |= PHY_SGMII_CR_RESET_AN; - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value); + + if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) { + i++; + goto qsgmii_loop; + } #else struct dtsec *regs = priv->mac->base; struct tsec_mii_mng *phyregs = priv->mac->phyregs; @@ -91,10 +98,12 @@ static void dtsec_init_phy(struct eth_device *dev) #endif if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII || fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) dtsec_configure_serdes(fm_eth); } +#ifdef CONFIG_PHYLIB static int tgec_is_fibre(struct eth_device *dev) { struct fm_eth *fm = dev->priv; @@ -105,15 +114,16 @@ static int tgec_is_fibre(struct eth_device *dev) return hwconfig_arg_cmp(phyopt, "xfi"); } #endif +#endif static u16 muram_readw(u16 *addr) { - u32 base = (u32)addr & ~0x3; - u32 val32 = *(u32 *)base; + ulong base = (ulong)addr & ~0x3UL; + u32 val32 = in_be32((void *)base); int byte_pos; u16 ret; - byte_pos = (u32)addr & 0x3; + byte_pos = (ulong)addr & 0x3UL; if (byte_pos) ret = (u16)(val32 & 0x0000ffff); else @@ -124,18 +134,18 @@ static u16 muram_readw(u16 *addr) static void muram_writew(u16 *addr, u16 val) { - u32 base = (u32)addr & ~0x3; - u32 org32 = *(u32 *)base; + ulong base = (ulong)addr & ~0x3UL; + u32 org32 = in_be32((void *)base); u32 val32; int byte_pos; - byte_pos = (u32)addr & 0x3; + byte_pos = (ulong)addr & 0x3UL; if (byte_pos) val32 = (org32 & 0xffff0000) | val; else val32 = (org32 & 0x0000ffff) | ((u32)val << 16); - *(u32 *)base = val32; + out_be32((void *)base, val32); } static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port) @@ -199,6 +209,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) u32 pram_page_offset; void *rx_bd_ring_base; void *rx_buf_pool; + u32 bd_ring_base_lo, bd_ring_base_hi; + u32 buf_lo, buf_hi; struct fm_port_bd *rxbd; struct fm_port_qd *rxqd; struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port; @@ -207,16 +219,21 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* alloc global parameter ram at MURAM */ pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN); + if (!pram) { + printf("%s: No muram for Rx global parameter\n", __func__); + return -ENOMEM; + } + fm_eth->rx_pram = pram; /* parameter page offset to MURAM */ - pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); + pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index); /* enable global mode- snooping data buffers and BDs */ - pram->mode = PRAM_MODE_GLOBAL; + out_be32(&pram->mode, PRAM_MODE_GLOBAL); /* init the Rx queue descriptor pionter */ - pram->rxqd_ptr = pram_page_offset + 0x20; + out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20); /* set the max receive buffer length, power of 2 */ muram_writew(&pram->mrblr, MAX_RXBUF_LOG2); @@ -225,15 +242,18 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) rx_bd_ring_base = malloc(sizeof(struct fm_port_bd) * RX_BD_RING_SIZE); if (!rx_bd_ring_base) - return 0; + return -ENOMEM; + memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd) * RX_BD_RING_SIZE); /* alloc Rx buffer from main memory */ rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE); if (!rx_buf_pool) - return 0; + return -ENOMEM; + memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); + debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool); /* save them to fm_eth */ fm_eth->rx_bd_ring = rx_bd_ring_base; @@ -243,18 +263,24 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* init Rx BDs ring */ rxbd = (struct fm_port_bd *)rx_bd_ring_base; for (i = 0; i < RX_BD_RING_SIZE; i++) { - rxbd->status = RxBD_EMPTY; - rxbd->len = 0; - rxbd->buf_ptr_hi = 0; - rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN; + muram_writew(&rxbd->status, RxBD_EMPTY); + muram_writew(&rxbd->len, 0); + buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool + + i * MAX_RXBUF_LEN)); + buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool + + i * MAX_RXBUF_LEN)); + muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi); + out_be32(&rxbd->buf_ptr_lo, buf_lo); rxbd++; } /* set the Rx queue descriptor */ rxqd = &pram->rxqd; muram_writew(&rxqd->gen, 0); - muram_writew(&rxqd->bd_ring_base_hi, 0); - rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base; + bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base)); + bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base)); + muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi); + out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo); muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd) * RX_BD_RING_SIZE); muram_writew(&rxqd->offset_in, 0); @@ -263,7 +289,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* set IM parameter ram pointer to Rx Frame Queue ID */ out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset); - return 1; + return 0; } static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) @@ -271,6 +297,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) struct fm_port_global_pram *pram; u32 pram_page_offset; void *tx_bd_ring_base; + u32 bd_ring_base_lo, bd_ring_base_hi; struct fm_port_bd *txbd; struct fm_port_qd *txqd; struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port; @@ -279,22 +306,27 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) /* alloc global parameter ram at MURAM */ pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN); + if (!pram) { + printf("%s: No muram for Tx global parameter\n", __func__); + return -ENOMEM; + } fm_eth->tx_pram = pram; /* parameter page offset to MURAM */ - pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); + pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index); /* enable global mode- snooping data buffers and BDs */ - pram->mode = PRAM_MODE_GLOBAL; + out_be32(&pram->mode, PRAM_MODE_GLOBAL); /* init the Tx queue descriptor pionter */ - pram->txqd_ptr = pram_page_offset + 0x40; + out_be32(&pram->txqd_ptr, pram_page_offset + 0x40); /* alloc Tx buffer descriptors from main memory */ tx_bd_ring_base = malloc(sizeof(struct fm_port_bd) * TX_BD_RING_SIZE); if (!tx_bd_ring_base) - return 0; + return -ENOMEM; + memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd) * TX_BD_RING_SIZE); /* save it to fm_eth */ @@ -304,16 +336,19 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) /* init Tx BDs ring */ txbd = (struct fm_port_bd *)tx_bd_ring_base; for (i = 0; i < TX_BD_RING_SIZE; i++) { - txbd->status = TxBD_LAST; - txbd->len = 0; - txbd->buf_ptr_hi = 0; - txbd->buf_ptr_lo = 0; + muram_writew(&txbd->status, TxBD_LAST); + muram_writew(&txbd->len, 0); + muram_writew(&txbd->buf_ptr_hi, 0); + out_be32(&txbd->buf_ptr_lo, 0); + txbd++; } /* set the Tx queue decriptor */ txqd = &pram->txqd; - muram_writew(&txqd->bd_ring_base_hi, 0); - txqd->bd_ring_base_lo = (u32)tx_bd_ring_base; + bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base)); + bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base)); + muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi); + out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo); muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd) * TX_BD_RING_SIZE); muram_writew(&txqd->offset_in, 0); @@ -322,29 +357,35 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */ out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset); - return 1; + return 0; } static int fm_eth_init(struct fm_eth *fm_eth) { + int ret; - if (!fm_eth_rx_port_parameter_init(fm_eth)) - return 0; + ret = fm_eth_rx_port_parameter_init(fm_eth); + if (ret) + return ret; - if (!fm_eth_tx_port_parameter_init(fm_eth)) - return 0; + ret = fm_eth_tx_port_parameter_init(fm_eth); + if (ret) + return ret; - return 1; + return 0; } static int fm_eth_startup(struct fm_eth *fm_eth) { struct fsl_enet_mac *mac; + int ret; + mac = fm_eth->mac; /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */ - if (!fm_eth_init(fm_eth)) - return 0; + ret = fm_eth_init(fm_eth); + if (ret) + return ret; /* setup the MAC controller */ mac->init_mac(mac); @@ -359,7 +400,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth) /* init bmi tx port, IM mode and disable */ bmi_tx_port_init(fm_eth->tx_port); - return 1; + return 0; } static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth) @@ -368,7 +409,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth) pram = fm_eth->tx_pram; /* graceful stop transmission of frames */ - pram->mode |= PRAM_MODE_GRACEFUL_STOP; + setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP); sync(); } @@ -378,7 +419,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) pram = fm_eth->tx_pram; /* re-enable transmission of frames */ - pram->mode &= ~PRAM_MODE_GRACEFUL_STOP; + clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP); sync(); } @@ -452,8 +493,10 @@ static void fm_eth_halt(struct eth_device *dev) /* disable bmi Rx port */ bmi_rx_port_disable(fm_eth->rx_port); +#ifdef CONFIG_PHYLIB if (fm_eth->phydev) phy_shutdown(fm_eth->phydev); +#endif } static int fm_eth_send(struct eth_device *dev, void *buf, int len) @@ -469,19 +512,20 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len) txbd = fm_eth->cur_txbd; /* find one empty TxBD */ - for (i = 0; txbd->status & TxBD_READY; i++) { + for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) { udelay(100); if (i > 0x1000) { - printf("%s: Tx buffer not ready\n", dev->name); + printf("%s: Tx buffer not ready, txbd->status = 0x%x\n", + dev->name, muram_readw(&txbd->status)); return 0; } } /* setup TxBD */ - txbd->buf_ptr_hi = 0; - txbd->buf_ptr_lo = (u32)buf; - txbd->len = len; + muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf))); + out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf))); + muram_writew(&txbd->len, len); sync(); - txbd->status = TxBD_READY | TxBD_LAST; + muram_writew(&txbd->status, TxBD_READY | TxBD_LAST); sync(); /* update TxQD, let RISC to send the packet */ @@ -493,10 +537,11 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len) sync(); /* wait for buffer to be transmitted */ - for (i = 0; txbd->status & TxBD_READY; i++) { + for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) { udelay(100); if (i > 0x10000) { - printf("%s: Tx error\n", dev->name); + printf("%s: Tx error, txbd->status = 0x%x\n", + dev->name, muram_readw(&txbd->status)); return 0; } } @@ -518,6 +563,7 @@ static int fm_eth_recv(struct eth_device *dev) struct fm_port_global_pram *pram; struct fm_port_bd *rxbd, *rxbd_base; u16 status, len; + u32 buf_lo, buf_hi; u8 *data; u16 offset_out; int ret = 1; @@ -525,12 +571,14 @@ static int fm_eth_recv(struct eth_device *dev) fm_eth = (struct fm_eth *)dev->priv; pram = fm_eth->rx_pram; rxbd = fm_eth->cur_rxbd; - status = rxbd->status; + status = muram_readw(&rxbd->status); while (!(status & RxBD_EMPTY)) { if (!(status & RxBD_ERROR)) { - data = (u8 *)rxbd->buf_ptr_lo; - len = rxbd->len; + buf_hi = muram_readw(&rxbd->buf_ptr_hi); + buf_lo = in_be32(&rxbd->buf_ptr_lo); + data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo); + len = muram_readw(&rxbd->len); net_process_received_packet(data, len); } else { printf("%s: Rx error\n", dev->name); @@ -538,8 +586,8 @@ static int fm_eth_recv(struct eth_device *dev) } /* clear the RxBDs */ - rxbd->status = RxBD_EMPTY; - rxbd->len = 0; + muram_writew(&rxbd->status, RxBD_EMPTY); + muram_writew(&rxbd->len, 0); sync(); /* advance RxBD */ @@ -548,7 +596,7 @@ static int fm_eth_recv(struct eth_device *dev) if (rxbd >= (rxbd_base + RX_BD_RING_SIZE)) rxbd = rxbd_base; /* read next status */ - status = rxbd->status; + status = muram_readw(&rxbd->status); /* update RxQD */ offset_out = muram_readw(&pram->rxqd.offset_out); @@ -601,7 +649,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) /* alloc mac controller */ mac = malloc(sizeof(struct fsl_enet_mac)); if (!mac) - return 0; + return -ENOMEM; memset(mac, 0, sizeof(struct fsl_enet_mac)); /* save the mac to fm_eth struct */ @@ -616,19 +664,21 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); #endif - return 1; + return 0; } static int init_phy(struct eth_device *dev) { struct fm_eth *fm_eth = dev->priv; +#ifdef CONFIG_PHYLIB struct phy_device *phydev = NULL; u32 supported; +#endif -#ifdef CONFIG_PHYLIB if (fm_eth->type == FM_ETH_1G_E) dtsec_init_phy(dev); +#ifdef CONFIG_PHYLIB if (fm_eth->bus) { phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev, fm_eth->enet_if); @@ -669,17 +719,18 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) struct eth_device *dev; struct fm_eth *fm_eth; int i, num = info->num; + int ret; /* alloc eth device */ dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) - return 0; + return -ENOMEM; memset(dev, 0, sizeof(struct eth_device)); /* alloc the FMan ethernet private struct */ fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth)); if (!fm_eth) - return 0; + return -ENOMEM; memset(fm_eth, 0, sizeof(struct fm_eth)); /* save off some things we need from the info struct */ @@ -694,8 +745,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) fm_eth->max_rx_len = MAX_RXBUF_LEN; /* init global mac structure */ - if (!fm_eth_init_mac(fm_eth, reg)) - return 0; + ret = fm_eth_init_mac(fm_eth, reg); + if (ret) + return ret; /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */ if (fm_eth->type == FM_ETH_1G_E) @@ -716,8 +768,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) fm_eth->enet_if = info->enet_if; /* startup the FM im */ - if (!fm_eth_startup(fm_eth)) - return 0; + ret = fm_eth_startup(fm_eth); + if (ret) + return ret; init_phy(dev); @@ -726,5 +779,5 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) dev->enetaddr[i] = 0; eth_register(dev); - return 1; + return 0; } diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 400e9dd5e2..df5db723ba 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -22,21 +22,22 @@ struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; -u32 fm_muram_base(int fm_idx) +void *fm_muram_base(int fm_idx) { return muram[fm_idx].base; } -u32 fm_muram_alloc(int fm_idx, u32 size, u32 align) +void *fm_muram_alloc(int fm_idx, size_t size, ulong align) { - u32 ret; - u32 align_mask, off; - u32 save; + void *ret; + ulong align_mask; + size_t off; + void *save; align_mask = align - 1; save = muram[fm_idx].alloc; - off = save & align_mask; + off = (ulong)save & align_mask; if (off != 0) muram[fm_idx].alloc += (align - off); off = size & align_mask; @@ -45,6 +46,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align) if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) { muram[fm_idx].alloc = save; printf("%s: run out of ram.\n", __func__); + return NULL; } ret = muram[fm_idx].alloc; @@ -56,7 +58,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align) static void fm_init_muram(int fm_idx, void *reg) { - u32 base = (u32)reg; + void *base = reg; muram[fm_idx].base = base; muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE; @@ -80,11 +82,11 @@ static void fm_upload_ucode(int fm_idx, struct fm_imem *imem, out_be32(&imem->iadd, IRAM_IADD_AIE); /* write microcode to IRAM */ for (i = 0; i < size / 4; i++) - out_be32(&imem->idata, ucode[i]); + out_be32(&imem->idata, (be32_to_cpu(ucode[i]))); /* verify if the writing is over */ out_be32(&imem->iadd, 0); - while ((in_be32(&imem->idata) != ucode[0]) && --timeout) + while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout) ; if (!timeout) printf("Fman%u: microcode upload timeout\n", fm_idx + 1); @@ -177,14 +179,15 @@ static int fman_upload_firmware(int fm_idx, const struct qe_microcode *ucode = &firmware->microcode[i]; /* Upload a microcode if it's present */ - if (ucode->code_offset) { + if (be32_to_cpu(ucode->code_offset)) { u32 ucode_size; u32 *code; printf("Fman%u: Uploading microcode version %u.%u.%u\n", fm_idx + 1, ucode->major, ucode->minor, ucode->revision); - code = (void *)firmware + ucode->code_offset; - ucode_size = sizeof(u32) * ucode->count; + code = (void *)firmware + + be32_to_cpu(ucode->code_offset); + ucode_size = sizeof(u32) * be32_to_cpu(ucode->count); fm_upload_ucode(fm_idx, fm_imem, code, ucode_size); } } @@ -255,7 +258,9 @@ static void fm_init_fpm(struct fm_fpm *fpm) static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi) { int blk, i, port_id; - u32 val, offset, base; + u32 val; + size_t offset; + void *base; /* alloc free buffer pool in MURAM */ base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN); diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index a9691c635a..fa9bc9f42d 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -10,7 +10,7 @@ #include <common.h> #include <phy.h> #include <fm_eth.h> -#include <asm/fsl_fman.h> +#include <fsl_fman.h> /* Port ID */ #define OH_PORT_ID_BASE 0x01 @@ -26,10 +26,10 @@ #define MIIM_TIMEOUT 0xFFFF struct fm_muram { - u32 base; - u32 top; - u32 size; - u32 alloc; + void *base; + void *top; + size_t size; + void *alloc; }; #define FM_MURAM_RES_SIZE 0x01000 @@ -95,8 +95,8 @@ struct fm_port_global_pram { #endif #define FM_FREE_POOL_ALIGN 256 -u32 fm_muram_alloc(int fm_idx, u32 size, u32 align); -u32 fm_muram_base(int fm_idx); +void *fm_muram_alloc(int fm_idx, size_t size, ulong align); +void *fm_muram_base(int fm_idx); int fm_init_common(int index, struct ccsr_fman *reg); int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info); phy_interface_t fman_port_enet_if(enum fm_port port); diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index b3ff4c50db..3a1de59fd8 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -1,13 +1,17 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include <errno.h> #include <common.h> #include <asm/io.h> -#include <asm/fsl_serdes.h> #include <fsl_mdio.h> +#ifdef CONFIG_FSL_LAYERSCAPE +#include <asm/arch/fsl_serdes.h> +#else +#include <asm/fsl_serdes.h> +#endif #include "fm.h" @@ -153,7 +157,9 @@ void fm_disable_port(enum fm_port port) return; fm_info[i].enabled = 0; +#ifndef CONFIG_SYS_FMAN_V3 fman_disable_port(port); +#endif } void fm_enable_port(enum fm_port port) diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c new file mode 100644 index 0000000000..cf2cc95a3a --- /dev/null +++ b/drivers/net/fm/ls1043.c @@ -0,0 +1,119 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> + +#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */ +#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000 +#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000 +#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */ +#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000 +#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000 +#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000 + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2, + [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3, + [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) { + printf("%s:%d: port(%d) is disabled\n", __func__, + __LINE__, port); + return PHY_INTERFACE_MODE_NONE; + } + + if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_NONE; + + if (port == FM1_DTSEC3) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == + FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { + printf("%s:%d: port(FM1_DTSEC3) is OK\n", + __func__, __LINE__); + return PHY_INTERFACE_MODE_RGMII; + } + if (port == FM1_DTSEC4) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == + FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { + printf("%s:%d: port(FM1_DTSEC4) is OK\n", + __func__, __LINE__); + return PHY_INTERFACE_MODE_RGMII; + } + + /* handle SGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if ((port == FM1_DTSEC2) && + is_serdes_configured(SGMII_2500_FM1_DTSEC2)) + return PHY_INTERFACE_MODE_SGMII_2500; + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + else if ((port == FM1_DTSEC9) && + is_serdes_configured(SGMII_2500_FM1_DTSEC9)) + return PHY_INTERFACE_MODE_SGMII_2500; + break; + default: + break; + } + + /* handle QSGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC5: + case FM1_DTSEC6: + /* only MAC 1,2,5,6 available for QSGMII */ + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c index 50171230ea..8d4622ff38 100644 --- a/drivers/net/fm/tgec.c +++ b/drivers/net/fm/tgec.c @@ -12,7 +12,7 @@ #include <phy.h> #include <asm/types.h> #include <asm/io.h> -#include <asm/fsl_tgec.h> +#include <fsl_tgec.h> #include "fm.h" diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c index 095f00cf97..24cb17b6ed 100644 --- a/drivers/net/fm/tgec_phy.c +++ b/drivers/net/fm/tgec_phy.c @@ -9,7 +9,7 @@ #include <miiphy.h> #include <phy.h> #include <asm/io.h> -#include <asm/fsl_tgec.h> +#include <fsl_tgec.h> #include <fm_eth.h> /* diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 4de7586408..99acb7a0c9 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -220,7 +220,6 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) { struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; struct dpni_queue_attr rx_queue_attr; - uint8_t mac_addr[6]; int err; if (net_dev->state == ETH_STATE_ACTIVE) @@ -240,21 +239,13 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) if (err) goto err_bind; - err = dpni_get_primary_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpni_handle, mac_addr); + err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpni_handle, net_dev->enetaddr); if (err) { - printf("dpni_get_primary_mac_addr() failed\n"); + printf("dpni_add_mac_addr() failed\n"); return err; } - memcpy(net_dev->enetaddr, mac_addr, 0x6); - - /* setup the MAC address */ - if (net_dev->enetaddr[0] & 0x01) { - printf("%s: MacAddress is multcast address\n", __func__); - return 1; - } - #ifdef CONFIG_PHYLIB /* TODO Check this path */ err = phy_startup(priv->phydev); diff --git a/drivers/net/ldpaa_eth/ls2085a.c b/drivers/net/ldpaa_eth/ls2085a.c index 6b7960a000..93ed4f18fe 100644 --- a/drivers/net/ldpaa_eth/ls2085a.c +++ b/drivers/net/ldpaa_eth/ls2085a.c @@ -7,9 +7,7 @@ #include <phy.h> #include <fsl-mc/ldpaa_wriop.h> #include <asm/io.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> #include <asm/arch/fsl_serdes.h> -#include <fsl-mc/ldpaa_wriop.h> u32 dpmac_to_devdisr[] = { [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index bf972dc39b..3500047577 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -330,7 +330,7 @@ int drv_nc_init(void) memset(&dev, 0, sizeof(dev)); strcpy(dev.name, "nc"); - dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; dev.start = nc_stdio_start; dev.putc = nc_stdio_putc; dev.puts = nc_stdio_puts; diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 2f24a6a39b..4cee038ede 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -11,7 +11,9 @@ #include <asm/io.h> #include <errno.h> #include <malloc.h> -#include <asm/arch-fsl-lsch3/fdt.h> +#ifdef CONFIG_FSL_LAYERSCAPE +#include <asm/arch/fdt.h> +#endif #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index e56a17f966..70d25dc981 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += pinctrl-uclass.o obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index e215b10972..c5cdd84881 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 547fd1aaa6..fb29843a5a 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -33,6 +33,20 @@ config DM_PMIC_MAX77686 This config enables implementation of driver-model pmic uclass features for PMIC MAX77686. The driver implements read/write operations. +config PMIC_S2MPS11 + bool "Enable Driver Model for PMIC Samsung S2MPS11" + depends on DM_PMIC + ---help--- + The Samsung S2MPS11 PMIC provides: + - 38 adjustable LDO regulators + - 9 High-Efficiency Buck Converters + - 1 BuckBoost Converter + - RTC with two alarms + - Backup battery charger + - I2C Configuration Interface + This driver provides access to I/O interface only. + Binding info: doc/device-tree-bindings/pmic/s2mps11.txt + config DM_PMIC_SANDBOX bool "Enable Driver Model for emulated Sandbox PMIC " depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 00fde71b2c..91e78f8149 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o +obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c new file mode 100644 index 0000000000..9d83059c40 --- /dev/null +++ b/drivers/power/pmic/s2mps11.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/s2mps11.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int s2mps11_reg_count(struct udevice *dev) +{ + return S2MPS11_REG_COUNT; +} + +static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) + error("write error to device: %p register: %#x!", dev, reg); + + return ret; +} + +static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) + error("read error from device: %p register: %#x!", dev, reg); + + return ret; +} + +static struct dm_pmic_ops s2mps11_ops = { + .reg_count = s2mps11_reg_count, + .read = s2mps11_read, + .write = s2mps11_write, +}; + +static const struct udevice_id s2mps11_ids[] = { + { .compatible = "samsung,s2mps11-pmic" }, + { } +}; + +U_BOOT_DRIVER(pmic_s2mps11) = { + .name = "s2mps11_pmic", + .id = UCLASS_PMIC, + .of_match = s2mps11_ids, + .ops = &s2mps11_ops, +}; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index a5170df916..4241a4c7f2 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -138,6 +138,13 @@ int regulator_get_by_devname(const char *devname, struct udevice **devp) return uclass_get_device_by_name(UCLASS_REGULATOR, devname, devp); } +int device_get_supply_regulator(struct udevice *dev, const char *supply_name, + struct udevice **devp) +{ + return uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + supply_name, devp); +} + int regulator_autoset(struct udevice *dev) { struct dm_regulator_uclass_platdata *uc_pdata; diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3092de1d9c..fc38a3f309 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # - #ccflags-y += -DDEBUG obj-$(CONFIG_DM_RTC) += rtc-uclass.o @@ -37,6 +36,7 @@ obj-$(CONFIG_RTC_M48T35A) += m48t35ax.o obj-$(CONFIG_RTC_MAX6900) += max6900.o obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o obj-$(CONFIG_RTC_MC146818) += mc146818.o +obj-$(CONFIG_RTC_MCP79411) += ds1307.o obj-$(CONFIG_MCFRTC) += mcfrtc.o obj-$(CONFIG_RTC_MK48T59) += mk48t59.o obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 03ab1a8c5d..3be1da6873 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -58,6 +58,10 @@ #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ +/* MCP7941X-specific bits */ +#define MCP7941X_BIT_ST 0x80 +#define MCP7941X_BIT_VBATEN 0x08 + static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -69,6 +73,9 @@ int rtc_get (struct rtc_time *tmp) int rel = 0; uchar sec, min, hour, mday, wday, mon, year; +#ifdef CONFIG_RTC_MCP79411 +read_rtc: +#endif sec = rtc_read (RTC_SEC_REG_ADDR); min = rtc_read (RTC_MIN_REG_ADDR); hour = rtc_read (RTC_HR_REG_ADDR); @@ -81,6 +88,7 @@ int rtc_get (struct rtc_time *tmp) "hr: %02x min: %02x sec: %02x\n", year, mon, mday, wday, hour, min, sec); +#ifdef CONFIG_RTC_DS1307 if (sec & RTC_SEC_BIT_CH) { printf ("### Warning: RTC oscillator has stopped\n"); /* clear the CH flag */ @@ -88,6 +96,23 @@ int rtc_get (struct rtc_time *tmp) rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); rel = -1; } +#endif + +#ifdef CONFIG_RTC_MCP79411 + /* make sure that the backup battery is enabled */ + if (!(wday & MCP7941X_BIT_VBATEN)) { + rtc_write(RTC_DAY_REG_ADDR, + wday | MCP7941X_BIT_VBATEN); + } + + /* clock halted? turn it on, so clock can tick. */ + if (!(sec & MCP7941X_BIT_ST)) { + rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST); + printf("Started RTC\n"); + goto read_rtc; + } +#endif + tmp->tm_sec = bcd2bin (sec & 0x7F); tmp->tm_min = bcd2bin (min & 0x7F); @@ -121,11 +146,20 @@ int rtc_set (struct rtc_time *tmp) rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); +#ifdef CONFIG_RTC_MCP79411 + rtc_write (RTC_DAY_REG_ADDR, + bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN); +#else rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); +#endif rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); +#ifdef CONFIG_RTC_MCP79411 + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST); +#else rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); +#endif return 0; } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 53b4e1b9d5..d462244a04 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -91,6 +91,13 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. +config DEBUG_UART_ZYNQ + bool "Xilinx Zynq" + help + Select this to enable a debug UART using the serial_s5p driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + endchoice config DEBUG_UART_BASE diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 39d4a4e933..c77bea3a1e 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -8,9 +8,20 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <asm/io.h> -#include <linux/compiler.h> #include <serial.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* data register */ +#define ALTERA_JTAG_RVALID BIT(15) /* Read valid */ + +/* control register */ +#define ALTERA_JTAG_AC BIT(10) /* activity indicator */ +#define ALTERA_JTAG_RRDY BIT(12) /* read available */ +#define ALTERA_JTAG_WSPACE(d) ((d) >> 16) /* Write space avail */ +/* Write fifo size. FIXME: this should be extracted with sopc2dts */ +#define ALTERA_JTAG_WRITE_DEPTH 64 struct altera_jtaguart_regs { u32 data; /* Data register */ @@ -21,18 +32,6 @@ struct altera_jtaguart_platdata { struct altera_jtaguart_regs *regs; }; -/* data register */ -#define ALTERA_JTAG_RVALID (1<<15) /* Read valid */ - -/* control register */ -#define ALTERA_JTAG_AC (1 << 10) /* activity indicator */ -#define ALTERA_JTAG_RRDY (1 << 12) /* read available */ -#define ALTERA_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ -/* Write fifo size. FIXME: this should be extracted with sopc2dts */ -#define ALTERA_JTAG_WRITE_DEPTH 64 - -DECLARE_GLOBAL_DATA_PTR; - static int altera_jtaguart_setbrg(struct udevice *dev, int baudrate) { return 0; @@ -112,8 +111,8 @@ static const struct dm_serial_ops altera_jtaguart_ops = { }; static const struct udevice_id altera_jtaguart_ids[] = { - { .compatible = "altr,juart-1.0", }, - { } + { .compatible = "altr,juart-1.0" }, + {} }; U_BOOT_DRIVER(altera_jtaguart) = { @@ -131,7 +130,7 @@ U_BOOT_DRIVER(altera_jtaguart) = { #include <debug_uart.h> -void debug_uart_init(void) +static inline void _debug_uart_init(void) { } diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index 4ff9fe27a8..5d76c3359b 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -8,9 +8,15 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <asm/io.h> -#include <linux/compiler.h> #include <serial.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* status register */ +#define ALTERA_UART_TMT BIT(5) /* tx empty */ +#define ALTERA_UART_TRDY BIT(6) /* tx ready */ +#define ALTERA_UART_RRDY BIT(7) /* rx ready */ struct altera_uart_regs { u32 rxdata; /* Rx data reg */ @@ -26,13 +32,6 @@ struct altera_uart_platdata { unsigned int uartclk; }; -/* status register */ -#define ALTERA_UART_TMT (1 << 5) /* tx empty */ -#define ALTERA_UART_TRDY (1 << 6) /* tx ready */ -#define ALTERA_UART_RRDY (1 << 7) /* rx ready */ - -DECLARE_GLOBAL_DATA_PTR; - static int altera_uart_setbrg(struct udevice *dev, int baudrate) { struct altera_uart_platdata *plat = dev->platdata; @@ -106,8 +105,8 @@ static const struct dm_serial_ops altera_uart_ops = { }; static const struct udevice_id altera_uart_ids[] = { - { .compatible = "altr,uart-1.0", }, - { } + { .compatible = "altr,uart-1.0" }, + {} }; U_BOOT_DRIVER(altera_uart) = { @@ -125,7 +124,7 @@ U_BOOT_DRIVER(altera_uart) = { #include <debug_uart.h> -void debug_uart_init(void) +static inline void _debug_uart_init(void) { struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; u32 div; diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 55011cc4b9..842f78bff3 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -29,14 +29,34 @@ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; static void serial_find_console_or_panic(void) { + const void *blob = gd->fdt_blob; struct udevice *dev; int node; - if (CONFIG_IS_ENABLED(OF_CONTROL) && gd->fdt_blob) { + if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) { /* Check for a chosen console */ - node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); + node = fdtdec_get_chosen_node(blob, "stdout-path"); + if (node < 0) { + const char *str, *p, *name; + + /* + * Deal with things like + * stdout-path = "serial0:115200n8"; + * + * We need to look up the alias and then follow it to + * the correct node. + */ + str = fdtdec_get_chosen_prop(blob, "stdout-path"); + if (str) { + p = strchr(str, ':'); + name = fdt_get_alias_namelen(blob, str, + p ? p - str : strlen(str)); + if (name) + node = fdt_path_offset(blob, name); + } + } if (node < 0) - node = fdt_path_offset(gd->fdt_blob, "console"); + node = fdt_path_offset(blob, "console"); if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) { gd->cur_serial_dev = dev; @@ -48,14 +68,14 @@ static void serial_find_console_or_panic(void) * bind it anyway. */ if (node > 0 && - !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) { + !lists_bind_fdt(gd->dm_root, blob, node, &dev)) { if (!device_probe(dev)) { gd->cur_serial_dev = dev; return; } } } - if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !gd->fdt_blob) { + if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) { /* * Try to use CONFIG_CONS_INDEX if available (it is numbered * from 1!). diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 9d84290196..88bebed236 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -6,6 +6,9 @@ */ #include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <errno.h> #include <fdtdec.h> #include <watchdog.h> #include <asm/io.h> @@ -17,6 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ @@ -37,26 +41,21 @@ struct uart_zynq { u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ }; -static struct uart_zynq *uart_zynq_ports[2] = { - [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, - [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, +struct zynq_uart_priv { + struct uart_zynq *regs; }; /* Set up the baud rate in gd struct */ -static void uart_zynq_serial_setbrg(const int port) +static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, + unsigned long clock, unsigned long baud) { /* Calculation results. */ unsigned int calc_bauderror, bdiv, bgen; unsigned long calc_baud = 0; - unsigned long baud; - unsigned long clock = get_uart_clk(port); - struct uart_zynq *regs = uart_zynq_ports[port]; /* Covering case where input clock is so slow */ - if (clock < 1000000 && gd->baudrate > 4800) - gd->baudrate = 4800; - - baud = gd->baudrate; + if (clock < 1000000 && baud > 4800) + baud = 4800; /* master clock * Baud rate = ------------------ @@ -88,133 +87,131 @@ static void uart_zynq_serial_setbrg(const int port) } /* Initialize the UART, with...some settings. */ -static int uart_zynq_serial_init(const int port) +static void _uart_zynq_serial_init(struct uart_zynq *regs) { - struct uart_zynq *regs = uart_zynq_ports[port]; - - if (!regs) - return -1; - /* RX/TX enabled & reset */ writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ ZYNQ_UART_CR_RXRST, ®s->control); writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ - uart_zynq_serial_setbrg(port); - - return 0; } -static void uart_zynq_serial_putc(const char c, const int port) +static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - struct uart_zynq *regs = uart_zynq_ports[port]; + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) + return -EAGAIN; - while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) - WATCHDOG_RESET(); - - if (c == '\n') { - writel('\r', ®s->tx_rx_fifo); - while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) - WATCHDOG_RESET(); - } writel(c, ®s->tx_rx_fifo); + + return 0; } -static void uart_zynq_serial_puts(const char *s, const int port) +int zynq_serial_setbrg(struct udevice *dev, int baudrate) { - while (*s) - uart_zynq_serial_putc(*s++, port); + struct zynq_uart_priv *priv = dev_get_priv(dev); + unsigned long clock = get_uart_clk(0); + + _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); + + return 0; } -static int uart_zynq_serial_tstc(const int port) +static int zynq_serial_probe(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_priv *priv = dev_get_priv(dev); + + _uart_zynq_serial_init(priv->regs); - return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; + return 0; } -static int uart_zynq_serial_getc(const int port) +static int zynq_serial_getc(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_priv *priv = dev_get_priv(dev); + struct uart_zynq *regs = priv->regs; + + if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) + return -EAGAIN; - while (!uart_zynq_serial_tstc(port)) - WATCHDOG_RESET(); return readl(®s->tx_rx_fifo); } -/* Multi serial device functions */ -#define DECLARE_PSSERIAL_FUNCTIONS(port) \ - static int uart_zynq##port##_init(void) \ - { return uart_zynq_serial_init(port); } \ - static void uart_zynq##port##_setbrg(void) \ - { return uart_zynq_serial_setbrg(port); } \ - static int uart_zynq##port##_getc(void) \ - { return uart_zynq_serial_getc(port); } \ - static int uart_zynq##port##_tstc(void) \ - { return uart_zynq_serial_tstc(port); } \ - static void uart_zynq##port##_putc(const char c) \ - { uart_zynq_serial_putc(c, port); } \ - static void uart_zynq##port##_puts(const char *s) \ - { uart_zynq_serial_puts(s, port); } - -/* Serial device descriptor */ -#define INIT_PSSERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = uart_zynq##port##_init, \ - .stop = NULL, \ - .setbrg = uart_zynq##port##_setbrg, \ - .getc = uart_zynq##port##_getc, \ - .tstc = uart_zynq##port##_tstc, \ - .putc = uart_zynq##port##_putc, \ - .puts = uart_zynq##port##_puts, \ -} +static int zynq_serial_putc(struct udevice *dev, const char ch) +{ + struct zynq_uart_priv *priv = dev_get_priv(dev); -DECLARE_PSSERIAL_FUNCTIONS(0); -static struct serial_device uart_zynq_serial0_device = - INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); -DECLARE_PSSERIAL_FUNCTIONS(1); -static struct serial_device uart_zynq_serial1_device = - INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); + return _uart_zynq_serial_putc(priv->regs, ch); +} -#if CONFIG_IS_ENABLED(OF_CONTROL) -__weak struct serial_device *default_serial_console(void) +static int zynq_serial_pending(struct udevice *dev, bool input) { - const void *blob = gd->fdt_blob; - int node; - unsigned int base_addr; + struct zynq_uart_priv *priv = dev_get_priv(dev); + struct uart_zynq *regs = priv->regs; - node = fdt_path_offset(blob, "serial0"); - if (node < 0) - return NULL; + if (input) + return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); + else + return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); +} - base_addr = fdtdec_get_addr(blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) - return NULL; +static int zynq_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct zynq_uart_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; - if (base_addr == ZYNQ_SERIAL_BASEADDR0) - return &uart_zynq_serial0_device; + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; - if (base_addr == ZYNQ_SERIAL_BASEADDR1) - return &uart_zynq_serial1_device; + priv->regs = (struct uart_zynq *)addr; - return NULL; + return 0; } -#else -__weak struct serial_device *default_serial_console(void) + +static const struct dm_serial_ops zynq_serial_ops = { + .putc = zynq_serial_putc, + .pending = zynq_serial_pending, + .getc = zynq_serial_getc, + .setbrg = zynq_serial_setbrg, +}; + +static const struct udevice_id zynq_serial_ids[] = { + { .compatible = "xlnx,xuartps" }, + { .compatible = "cdns,uart-r1p8" }, + { } +}; + +U_BOOT_DRIVER(serial_s5p) = { + .name = "serial_zynq", + .id = UCLASS_SERIAL, + .of_match = zynq_serial_ids, + .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), + .probe = zynq_serial_probe, + .ops = &zynq_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_ZYNQ + +#include <debug_uart.h> + +void _debug_uart_init(void) { -#if defined(CONFIG_ZYNQ_SERIAL_UART0) - if (uart_zynq_ports[0]) - return &uart_zynq_serial0_device; -#endif -#if defined(CONFIG_ZYNQ_SERIAL_UART1) - if (uart_zynq_ports[1]) - return &uart_zynq_serial1_device; -#endif - return NULL; + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; + + _uart_zynq_serial_init(regs); + _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); } -#endif -void zynq_serial_initialize(void) +static inline void _debug_uart_putc(int ch) { - serial_register(&uart_zynq_serial0_device); - serial_register(&uart_zynq_serial1_device); + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; + + while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); } + +DEBUG_UART_FUNCS + +#endif diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3d4baa51d6..99345eb9a0 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -1,5 +1,7 @@ # # Makefile for the U-boot SOC specific device drivers. # +# SPDX-License-Identifier: GPL-2.0+ +# obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ diff --git a/drivers/soc/keystone/Makefile b/drivers/soc/keystone/Makefile index c000ecac76..1334fa49bc 100644 --- a/drivers/soc/keystone/Makefile +++ b/drivers/soc/keystone/Makefile @@ -1 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index e49949b4a2..3e09592ac6 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -193,8 +193,8 @@ static const struct dm_spi_ops altera_spi_ops = { }; static const struct udevice_id altera_spi_ids[] = { - { .compatible = "altr,spi-1.0", }, - { } + { .compatible = "altr,spi-1.0" }, + {} }; U_BOOT_DRIVER(altera_spi) = { diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46a1a..4f7fd52532 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { - struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; u8 opcode_rdid = 0x9F; @@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -123,17 +122,25 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); int err; + if (hz > plat->max_hz) + hz = plat->max_hz; + /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); - cadence_spi_write_speed(bus, hz); - - /* Calibration required for different SCLK speed or chip select */ - if (priv->qspi_calibrated_hz != plat->max_hz || + /* + * Calibration required for different current SCLK speed, requested + * SCLK speed or chip select + */ + if (priv->previous_hz != hz || + priv->qspi_calibrated_hz != hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; + + /* prevent calibration run when same as previous request */ + priv->previous_hz = hz; } /* Enable QSPI */ @@ -291,10 +298,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; - /* Use 500KHz as a suitable default */ - plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); if (subnode < 0) { @@ -302,6 +305,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) return -ENODEV; } + /* Use 500 KHz as a suitable default */ + plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", + 500000); + /* Read other parameters from DT */ plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa5bc..2912e36a53 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -38,6 +38,7 @@ struct cadence_spi_priv { int qspi_is_init; unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; + unsigned int previous_hz; }; /* Functions call declaration */ diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c index 2ef9ad6934..46a598ae9f 100644 --- a/drivers/timer/altera_timer.c +++ b/drivers/timer/altera_timer.c @@ -16,6 +16,11 @@ DECLARE_GLOBAL_DATA_PTR; +/* control register */ +#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */ +#define ALTERA_TIMER_START BIT(2) /* Start timer */ +#define ALTERA_TIMER_STOP BIT(3) /* Stop timer */ + struct altera_timer_regs { u32 status; /* Timer status reg */ u32 control; /* Timer control reg */ @@ -30,11 +35,6 @@ struct altera_timer_platdata { unsigned long clock_rate; }; -/* control register */ -#define ALTERA_TIMER_CONT (1 << 1) /* Continuous mode */ -#define ALTERA_TIMER_START (1 << 2) /* Start timer */ -#define ALTERA_TIMER_STOP (1 << 3) /* Stop timer */ - static int altera_timer_get_count(struct udevice *dev, unsigned long *count) { struct altera_timer_platdata *plat = dev->platdata; @@ -88,8 +88,8 @@ static const struct timer_ops altera_timer_ops = { }; static const struct udevice_id altera_timer_ids[] = { - { .compatible = "altr,timer-1.0", }, - { } + { .compatible = "altr,timer-1.0" }, + {} }; U_BOOT_DRIVER(altera_timer) = { diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 02bb216db7..0cd73020a7 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_USB_DWC3) += dwc3.o dwc3-y := core.o diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index ab3c94e512..0ae3de5c27 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -281,7 +281,7 @@ static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) return 0; err1: - dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch * + dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); err0: @@ -296,7 +296,7 @@ static void dwc3_free_scratch_buffers(struct dwc3 *dwc) if (!dwc->nr_scratch) return; - dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch * + dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); kfree(dwc->scratchbuf); } @@ -629,7 +629,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); dwc->mem = mem; - dwc->regs = (int *)(dwc3_dev->base + DWC3_GLOBALS_REGS_START); + dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + + DWC3_GLOBALS_REGS_START); /* default to highest possible threshold */ lpm_nyet_threshold = 0xff; diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index aba614fb4e..12b133f93e 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -81,8 +81,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, trb->ctrl |= (DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_LST); - dwc3_flush_cache((int)buf_dma, len); - dwc3_flush_cache((int)trb, sizeof(*trb)); + dwc3_flush_cache((long)buf_dma, len); + dwc3_flush_cache((long)trb, sizeof(*trb)); if (chain) return 0; @@ -790,7 +790,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, if (!r) return; - dwc3_flush_cache((int)trb, sizeof(*trb)); + dwc3_flush_cache((long)trb, sizeof(*trb)); status = DWC3_TRB_SIZE_TRBSTS(trb->size); if (status == DWC3_TRBSTS_SETUP_PENDING) { @@ -821,7 +821,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, ur->actual += transferred; trb++; - dwc3_flush_cache((int)trb, sizeof(*trb)); + dwc3_flush_cache((long)trb, sizeof(*trb)); length = trb->size & DWC3_TRB_SIZE_MASK; ep0->free_slot = 0; @@ -831,7 +831,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, maxp); transferred = min_t(u32, ur->length - transferred, transfer_size - length); - dwc3_flush_cache((int)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE); + dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE); memcpy(buf, dwc->ep0_bounce, transferred); } else { transferred = ur->length - length; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index f3d649a5ee..8ff949d241 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -244,7 +244,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, list_del(&req->list); req->trb = NULL; - dwc3_flush_cache((int)req->request.dma, req->request.length); + dwc3_flush_cache((long)req->request.dma, req->request.length); if (req->request.status == -EINPROGRESS) req->request.status = status; @@ -771,8 +771,8 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep, trb->ctrl |= DWC3_TRB_CTRL_HWO; - dwc3_flush_cache((int)dma, length); - dwc3_flush_cache((int)trb, sizeof(*trb)); + dwc3_flush_cache((long)dma, length); + dwc3_flush_cache((long)trb, sizeof(*trb)); } /* @@ -1769,7 +1769,7 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, slot %= DWC3_TRB_NUM; trb = &dep->trb_pool[slot]; - dwc3_flush_cache((int)trb, sizeof(*trb)); + dwc3_flush_cache((long)trb, sizeof(*trb)); __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status); dwc3_gadget_giveback(dep, req, status); @@ -2670,7 +2670,7 @@ void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc) for (i = 0; i < dwc->num_event_buffers; i++) { evt = dwc->ev_buffs[i]; - dwc3_flush_cache((int)evt->buf, evt->length); + dwc3_flush_cache((long)evt->buf, evt->length); } dwc3_thread_interrupt(0, dwc); diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 5042a24193..0d9fa220e9 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -23,7 +23,7 @@ #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE static inline u32 dwc3_readl(void __iomem *base, u32 offset) { - u32 offs = offset - DWC3_GLOBALS_REGS_START; + unsigned long offs = offset - DWC3_GLOBALS_REGS_START; u32 value; /* @@ -38,7 +38,7 @@ static inline u32 dwc3_readl(void __iomem *base, u32 offset) static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) { - u32 offs = offset - DWC3_GLOBALS_REGS_START; + unsigned long offs = offset - DWC3_GLOBALS_REGS_START; /* * We requested the mem region starting from the Globals address diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index ff1481ba37..9ed0ce3d31 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -569,7 +569,7 @@ static void thor_tx_data(unsigned char *data, int len) dev->in_req->length = len; - debug("%s: dev->in_req->length:%d to_cpy:%d\n", __func__, + debug("%s: dev->in_req->length:%d to_cpy:%zd\n", __func__, dev->in_req->length, sizeof(data)); status = usb_ep_queue(dev->in_ep, dev->in_req, 0); diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile index 12380f4e4e..1699ccdf94 100644 --- a/drivers/usb/gadget/udc/Makefile +++ b/drivers/usb/gadget/udc/Makefile @@ -1,4 +1,7 @@ # # USB peripheral controller drivers # +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 875e998a82..326757b547 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -65,7 +65,7 @@ void usb_gadget_unmap_request(struct usb_gadget *gadget, if (req->length == 0) return; - dma_unmap_single((void *)req->dma, req->length, + dma_unmap_single((void *)(uintptr_t)req->dma, req->length, is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE); } EXPORT_SYMBOL_GPL(usb_gadget_unmap_request); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 9bde2b252c..ccbfc0265a 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -2205,6 +2205,7 @@ int ohci_register(struct udevice *dev, struct ohci_regs *regs) if (!ohci->hcca) return -ENOMEM; memset(ohci->hcca, 0, sizeof(struct ohci_hcca)); + flush_dcache_hcca(ohci->hcca); if (hc_reset(ohci) < 0) return -EIO; diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile index fd9df72ed4..072d516a03 100644 --- a/drivers/usb/musb-new/Makefile +++ b/drivers/usb/musb-new/Makefile @@ -1,6 +1,8 @@ # # for USB OTG silicon based on Mentor Graphics INVENTRA designs # +# SPDX-License-Identifier: GPL-2.0+ +# obj-$(CONFIG_USB_MUSB_GADGET) += musb_gadget.o musb_gadget_ep0.o musb_core.o obj-$(CONFIG_USB_MUSB_GADGET) += musb_uboot.o diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 0ce237094d..960b474b76 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -162,6 +162,10 @@ void lcd_ctrl_init(void *lcdbase) lcdc_writel(®s->lcdc_basecfg1, LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); break; + case 32: + lcdc_writel(®s->lcdc_basecfg1, + LCDC_BASECFG1_RGBMODE_24BPP_RGB_888); + break; default: BUG(); break; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index aa7ca8646d..556a55f65c 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -2280,8 +2280,7 @@ int drv_video_init(void) /* Init vga device */ memset(&console_dev, 0, sizeof(console_dev)); strcpy(console_dev.name, "vga"); - console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ - console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; + console_dev.flags = DEV_FLAGS_OUTPUT; console_dev.putc = video_putc; /* 'putc' function */ console_dev.puts = video_puts; /* 'puts' function */ diff --git a/examples/Makefile b/examples/Makefile index 18d008e7b5..8e329d7cd5 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + ifndef CONFIG_SANDBOX ifdef FTRACE diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 0863a8cda2..5a6ae0013c 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -73,3 +73,13 @@ $(obj)/%.srec: $(obj)/% FORCE $(obj)/%.bin: OBJCOPYFLAGS := -O binary $(obj)/%.bin: $(obj)/% FORCE $(call if_changed,objcopy) + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_stubs.o := -marm + +endif +endif diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index c4743135fc..abe861a976 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -31,7 +31,7 @@ #include <common.h> #include <malloc.h> #include <memalign.h> -#include <linux/compat.h> +#include <linux/log2.h> #include <linux/stat.h> #include <linux/err.h> #include "ubifs.h" diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile index 45ff7458c6..b69ea73f6e 100644 --- a/fs/yaffs2/Makefile +++ b/fs/yaffs2/Makefile @@ -8,13 +8,8 @@ # # Created by Charles Manning <charles@aleph1.co.uk> # -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License version 2 as -# published by the Free Software Foundation. +# SPDX-License-Identifier: GPL-2.0 # -# NB Warning this Makefile does not include header dependencies. -# -# $Id: Makefile,v 1.15 2007/07/18 19:40:38 charles Exp $ obj-y := \ yaffs_allocator.o yaffs_attribs.o yaffs_bitmap.o yaffs_uboot_glue.o\ diff --git a/include/adc.h b/include/adc.h new file mode 100644 index 0000000000..4b14017849 --- /dev/null +++ b/include/adc.h @@ -0,0 +1,288 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ADC_H_ +#define _ADC_H_ + +/* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */ +#define ADC_CHANNEL(x) (1 << x) + +/* The last possible selected channel with 32-bit mask */ +#define ADC_MAX_CHANNEL 31 + +/** + * adc_data_format: define the ADC output data format, can be useful when + * the device's input Voltage range is bipolar. + * - ADC_DATA_FORMAT_BIN - binary offset + * - ADC_DATA_FORMAT_2S - two's complement + * + * Note: Device's driver should fill the 'data_format' field of its uclass's + * platform data using one of the above data format types. + */ +enum adc_data_format { + ADC_DATA_FORMAT_BIN, + ADC_DATA_FORMAT_2S, +}; + +/** + * struct adc_channel - structure to hold channel conversion data. + * Useful to keep the result of a multi-channel conversion output. + * + * @id - channel id + * @data - channel conversion data + */ +struct adc_channel { + int id; + unsigned int data; +}; + +/** + * struct adc_uclass_platdata - basic ADC info + * + * Note: The positive/negative reference Voltage is only a name and it doesn't + * provide an information about the value polarity. It is possible, for both + * values to be a negative or positive. For this purpose the uclass's platform + * data provides a bool fields: 'vdd/vss_supply_is_negative'. This is useful, + * since the regulator API returns only a positive Voltage values. + * + * To get the reference Voltage values with polarity, use functions: + * - adc_vdd_value() + * - adc_vss_value() + * Those are useful for some cases of ADC's references, e.g.: + * * Vdd: +3.3V; Vss: -3.3V -> 6.6 Vdiff + * * Vdd: +3.3V; Vss: +0.3V -> 3.0 Vdiff + * * Vdd: +3.3V; Vss: 0.0V -> 3.3 Vdiff + * The last one is usually standard and doesn't require the fdt polarity info. + * + * For more informations read binding info: + * - doc/device-tree-bindings/adc/adc.txt + * + * @data_mask - conversion output data mask + * @data_timeout_us - single channel conversion timeout + * @multidata_timeout_us - multi channel conversion timeout + * @channel_mask - bit mask of available channels [0:31] + * @vdd_supply - positive reference Voltage supply (regulator) + * @vss_supply - negative reference Voltage supply (regulator) + * @vdd_polarity_negative - positive reference Voltage has negative polarity + * @vss_polarity_negative - negative reference Voltage has negative polarity + * @vdd_microvolts - positive reference Voltage value + * @vss_microvolts - negative reference Voltage value + */ +struct adc_uclass_platdata { + int data_format; + unsigned int data_mask; + unsigned int data_timeout_us; + unsigned int multidata_timeout_us; + unsigned int channel_mask; + struct udevice *vdd_supply; + struct udevice *vss_supply; + bool vdd_polarity_negative; + bool vss_polarity_negative; + int vdd_microvolts; + int vss_microvolts; +}; + +/** + * struct adc_ops - ADC device operations for single/multi-channel operation. + */ +struct adc_ops { + /** + * start_channel() - start conversion with its default parameters + * for the given channel number. + * + * @dev: ADC device to init + * @channel: analog channel number + * @return: 0 if OK, -ve on error + */ + int (*start_channel)(struct udevice *dev, int channel); + + /** + * start_channels() - start conversion with its default parameters + * for the channel numbers selected by the bit mask. + * + * This is optional, useful when the hardware supports multichannel + * conversion by the single software trigger. + * + * @dev: ADC device to init + * @channel_mask: bit mask of selected analog channels + * @return: 0 if OK, -ve on error + */ + int (*start_channels)(struct udevice *dev, unsigned int channel_mask); + + /** + * channel_data() - get conversion output data for the given channel. + * + * Note: The implementation of this function should only check, that + * the conversion data is available at the call time. If the hardware + * requires some delay to get the data, then this function should + * return with -EBUSY value. The ADC API will call it in a loop, + * until the data is available or the timeout expires. The maximum + * timeout for this operation is defined by the field 'data_timeout_us' + * in ADC uclasses platform data structure. + * + * @dev: ADC device to trigger + * @channel: selected analog channel number + * @data: returned pointer to selected channel's output data + * @return: 0 if OK, -EBUSY if busy, and other negative on error + */ + int (*channel_data)(struct udevice *dev, int channel, + unsigned int *data); + + /** + * channels_data() - get conversion data for the selected channels. + * + * This is optional, useful when multichannel conversion is supported + * by the hardware, by the single software trigger. + * + * For the proper implementation, please look at the 'Note' for the + * above method. The only difference is in used timeout value, which + * is defined by field 'multidata_timeout_us'. + * + * @dev: ADC device to trigger + * @channel_mask: bit mask of selected analog channels + * @channels: returned pointer to array of output data for channels + * selected by the given mask + * @return: 0 if OK, -ve on error + */ + int (*channels_data)(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels); + + /** + * stop() - stop conversion of the given ADC device + * + * @dev: ADC device to stop + * @return: 0 if OK, -ve on error + */ + int (*stop)(struct udevice *dev); +}; + +/** + * adc_start_channel() - start conversion for given device/channel and exit. + * + * @dev: ADC device + * @channel: analog channel number + * @return: 0 if OK, -ve on error + */ +int adc_start_channel(struct udevice *dev, int channel); + +/** + * adc_start_channels() - start conversion for given device/channels and exit. + * + * Note: + * To use this function, device must implement method: start_channels(). + * + * @dev: ADC device to start + * @channel_mask: channel selection - a bit mask + * @channel_mask: bit mask of analog channels + * @return: 0 if OK, -ve on error + */ +int adc_start_channels(struct udevice *dev, unsigned int channel_mask); + +/** + * adc_channel_data() - get conversion data for the given device channel number. + * + * @dev: ADC device to read + * @channel: analog channel number + * @data: pointer to returned channel's data + * @return: 0 if OK, -ve on error + */ +int adc_channel_data(struct udevice *dev, int channel, unsigned int *data); + +/** + * adc_channels_data() - get conversion data for the channels selected by mask + * + * Note: + * To use this function, device must implement methods: + * - start_channels() + * - channels_data() + * + * @dev: ADC device to read + * @channel_mask: channel selection - a bit mask + * @channels: pointer to structure array of returned data for each channel + * @return: 0 if OK, -ve on error + */ +int adc_channels_data(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels); + +/** + * adc_data_mask() - get data mask (ADC resolution bitmask) for given ADC device + * + * This can be used if adc uclass platform data is filled. + * + * @dev: ADC device to check + * @data_mask: pointer to the returned data bitmask + * @return: 0 if OK, -ve on error + */ +int adc_data_mask(struct udevice *dev, unsigned int *data_mask); + +/** + * adc_channel_single_shot() - get output data of conversion for the ADC + * device's channel. This function searches for the device with the given name, + * starts the given channel conversion and returns the output data. + * + * Note: To use this function, device must implement metods: + * - start_channel() + * - channel_data() + * + * @name: device's name to search + * @channel: device's input channel to init + * @data: pointer to conversion output data + * @return: 0 if OK, -ve on error + */ +int adc_channel_single_shot(const char *name, int channel, unsigned int *data); + +/** + * adc_channels_single_shot() - get ADC conversion output data for the selected + * device's channels. This function searches for the device by the given name, + * starts the selected channels conversion and returns the output data as array + * of type 'struct adc_channel'. + * + * Note: This function can be used if device implements one of ADC's single + * or multi-channel operation API. If multi-channel operation is not supported, + * then each selected channel is triggered by the sequence start/data in a loop. + * + * @name: device's name to search + * @channel_mask: channel selection - a bit mask + * @channels: pointer to conversion output data for the selected channels + * @return: 0 if OK, -ve on error + */ +int adc_channels_single_shot(const char *name, unsigned int channel_mask, + struct adc_channel *channels); + +/** + * adc_vdd_value() - get the ADC device's positive reference Voltage value + * + * Note: Depending on bool value 'vdd_supply_is_negative' of platform data, + * the returned uV value can be negative, and it's not an error. + * + * @dev: ADC device to check + * @uV: Voltage value with polarization sign (uV) + * @return: 0 on success or -ve on error +*/ +int adc_vdd_value(struct udevice *dev, int *uV); + +/** + * adc_vss_value() - get the ADC device's negative reference Voltage value + * + * Note: Depending on bool value 'vdd_supply_is_negative' of platform data, + * the returned uV value can be negative, and it's not an error. + * + * @dev: ADC device to check + * @uV: Voltage value with polarization sign (uV) + * @return: 0 on success or -ve on error +*/ +int adc_vss_value(struct udevice *dev, int *uV); + +/** + * adc_stop() - stop operation for given ADC device. + * + * @dev: ADC device to stop + * @return: 0 if OK, -ve on error + */ +int adc_stop(struct udevice *dev); + +#endif diff --git a/include/asm-generic/bitops/__ffs.h b/include/asm-generic/bitops/__ffs.h new file mode 100644 index 0000000000..937d7c4355 --- /dev/null +++ b/include/asm-generic/bitops/__ffs.h @@ -0,0 +1,43 @@ +#ifndef _ASM_GENERIC_BITOPS___FFS_H_ +#define _ASM_GENERIC_BITOPS___FFS_H_ + +#include <asm/types.h> + +/** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static __always_inline unsigned long __ffs(unsigned long word) +{ + int num = 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +#endif /* _ASM_GENERIC_BITOPS___FFS_H_ */ diff --git a/include/asm-generic/bitops/__fls.h b/include/asm-generic/bitops/__fls.h new file mode 100644 index 0000000000..a60a7ccb67 --- /dev/null +++ b/include/asm-generic/bitops/__fls.h @@ -0,0 +1,43 @@ +#ifndef _ASM_GENERIC_BITOPS___FLS_H_ +#define _ASM_GENERIC_BITOPS___FLS_H_ + +#include <asm/types.h> + +/** + * __fls - find last (most-significant) set bit in a long word + * @word: the word to search + * + * Undefined if no set bit exists, so code should check against 0 first. + */ +static __always_inline unsigned long __fls(unsigned long word) +{ + int num = BITS_PER_LONG - 1; + +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; +} + +#endif /* _ASM_GENERIC_BITOPS___FLS_H_ */ diff --git a/include/asm-generic/bitops/fls.h b/include/asm-generic/bitops/fls.h new file mode 100644 index 0000000000..0576d1f42f --- /dev/null +++ b/include/asm-generic/bitops/fls.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS_H_ +#define _ASM_GENERIC_BITOPS_FLS_H_ + +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ + +static __always_inline int fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FLS_H_ */ diff --git a/include/asm-generic/bitops/fls64.h b/include/asm-generic/bitops/fls64.h new file mode 100644 index 0000000000..b097cf8444 --- /dev/null +++ b/include/asm-generic/bitops/fls64.h @@ -0,0 +1,36 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS64_H_ +#define _ASM_GENERIC_BITOPS_FLS64_H_ + +#include <asm/types.h> + +/** + * fls64 - find last set bit in a 64-bit word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffsll, but returns the position of the most significant set bit. + * + * fls64(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 64. + */ +#if BITS_PER_LONG == 32 +static __always_inline int fls64(__u64 x) +{ + __u32 h = x >> 32; + if (h) + return fls(h) + 32; + return fls(x); +} +#elif BITS_PER_LONG == 64 +static __always_inline int fls64(__u64 x) +{ + if (x == 0) + return 0; + return __fls(x) + 1; +} +#else +#error BITS_PER_LONG not 32 or 64 +#endif + +#endif /* _ASM_GENERIC_BITOPS_FLS64_H_ */ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 458952fb58..328bc62948 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -71,6 +71,7 @@ extern char __bss_start[]; extern char __bss_end[]; extern char __image_copy_start[]; extern char __image_copy_end[]; +extern char _image_binary_end[]; extern char __rel_dyn_start[]; extern char __rel_dyn_end[]; diff --git a/include/common.h b/include/common.h index ecb1f0682e..09a131da0b 100644 --- a/include/common.h +++ b/include/common.h @@ -76,6 +76,12 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_SOC_DA8XX #include <asm/arch/hardware.h> #endif +#ifdef CONFIG_FSL_LSCH3 +#include <asm/arch/immap_lsch3.h> +#endif +#ifdef CONFIG_FSL_LSCH2 +#include <asm/arch/immap_lsch2.h> +#endif #include <part.h> #include <flash.h> diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h new file mode 100644 index 0000000000..ab7dd08914 --- /dev/null +++ b/include/configs/10m50_devboard.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * SERIAL + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ + +/* + * Flash + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_MTD_DEVICE + +/* + * NET options + */ +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHY_MARVELL + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * FDT options + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR 0xf4040000 + +/* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). + */ +#define CONFIG_SYS_SDRAM_BASE 0xc8000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN 0x20000 + +/* + * MISC + */ +#define CONFIG_SYS_LONGHELP /* Provide extended help */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ +#define CONFIG_SYS_MAXARGS 16 /* Max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print buf size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + 0x10000) +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_GPIO + +#endif /* __CONFIG_H */ diff --git a/include/configs/nios2-generic.h b/include/configs/3c120_devboard.h index b38513e99b..856c836385 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/3c120_devboard.h @@ -24,22 +24,22 @@ /* * CFI Flash */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* - * MII/PHY + * NET options */ -#define CONFIG_CMD_MII 1 -#define CONFIG_PHY_GIGE 1 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -#define CONFIG_PHY_MARVELL 1 +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHY_MARVELL /* * BOOTP options @@ -77,15 +77,13 @@ */ #define CONFIG_SYS_SDRAM_BASE 0xD0000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_MONITOR_IS_IN_RAM #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000) -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_MALLOC_BASE +#define CONFIG_SYS_MALLOC_LEN 0x20000 /* * MISC @@ -99,7 +97,10 @@ 16) /* Print buf size */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - 0x20000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + 0x10000) #define CONFIG_CMDLINE_EDITING #define CONFIG_CMD_GPIO diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index a006dcebaa..54dcf3b954 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -17,7 +17,6 @@ #define CONFIG_BSC9132 #endif -#define CONFIG_FSL_CLK #define CONFIG_MISC_INIT_R #ifdef CONFIG_SDCARD diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index cfa5931311..551b72d153 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -10,7 +10,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK /* * High Level Configuration Options diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 990fc04e87..7d1262d510 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK /* * High Level Configuration Options diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index fcc531b600..ab68e63881 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -16,7 +16,6 @@ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index af8eb8c0d2..29c27fa9a7 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -12,7 +12,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_36BIT diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9f784e0adb..6f614b0cbe 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -12,7 +12,6 @@ #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9e40730395..81b085572d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -15,7 +15,6 @@ #define CONFIG_PHYS_64BIT #endif #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index c571fac666..a9d825baf5 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -12,7 +12,6 @@ #include "../board/freescale/common/ics307_clk.h" #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0cd990477b..2c4c8b5a02 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -15,7 +15,6 @@ #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_PPC_P2041 -#define CONFIG_FSL_CLK #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 4f22657703..52942edbd4 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -20,7 +20,6 @@ #define CONFIG_MP /* support multiple processors */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_FSL_CLK #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP 1 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index d412d0b2b7..39fa5e2b18 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -20,7 +20,6 @@ #define CONFIG_MP /* support multiple processors */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_FSL_CLK #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP 1 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 18df2372a4..fc263dfcb6 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -29,7 +29,6 @@ #define CONFIG_T1040QDS #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE @@ -593,12 +592,14 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC_ADAPTER_IDENT #endif /* Qman/Bman */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 2091015638..840be047cd 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -13,7 +13,6 @@ #define CONFIG_T104xRDB #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> @@ -742,7 +741,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_T1040D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#elif defined(CONFIG_T1042D4RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index d35b9d2d90..a81f1e66f3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -13,7 +13,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_CLK #define CONFIG_MMC #define CONFIG_USB_EHCI #if defined(CONFIG_PPC_T2080) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index c632b8e328..8b762346ac 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -14,7 +14,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_T2080RDB #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_CLK #define CONFIG_MMC #define CONFIG_USB_EHCI #define CONFIG_FSL_SATA_V2 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index dd8dd73f98..4edb3cb91f 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -12,7 +12,6 @@ #define CONFIG_T4240QDS #define CONFIG_PHYS_64BIT -#define CONFIG_FSL_CLK #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2c5f800cbd..2e875d2fc1 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -13,7 +13,6 @@ #define CONFIG_T4240RDB #define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 0b609af2c9..8611473773 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -15,7 +15,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #define CONFIG_FSL_ELBC #define CONFIG_PCI diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index f9385349ae..9db4a4ff27 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -97,8 +97,8 @@ #elif CONFIG_SYS_USE_SERIALFLASH /* u-boot env in serial flash, by default is bus 0 and cs 0 */ #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_OFFSET 0x6000 +#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x1000 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ "sf read 0x21000000 0x60000 0xc000; " \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 9fa8f817f2..7658e61367 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -18,7 +18,7 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_USE_ARCH_MEMCPY #define CONFIG_USE_ARCH_MEMSET -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_ARCH_MISC_INIT #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 77c2edcbb3..600bb835ce 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -44,7 +44,6 @@ #define CONFIG_P1022 #define CONFIG_CONTROLCENTERD #define CONFIG_MP /* support multiple processors */ -#define CONFIG_FSL_CLK #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3c9a529162..921021634d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #include "../board/freescale/common/ics307_clk.h" diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h new file mode 100644 index 0000000000..5d25fb1400 --- /dev/null +++ b/include/configs/cyrus.h @@ -0,0 +1,587 @@ +/* + * Based on corenet_ds.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CYRUS + +#define CONFIG_PHYS_64BIT + +#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) +#error Must call Cyrus CONFIG with a specific CPU enabled. +#endif + + +#define CONFIG_MMC +#define CONFIG_SDCARD +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 +#define CONFIG_PCIE4 +#ifdef CONFIG_PPC_P5020 +#define CONFIG_SYS_FSL_RAID_ENGINE +#define CONFIG_SYS_DPAA_RMAN +#endif +#define CONFIG_SYS_DPAA_PME + +/* + * Corenet DS style board configuration file + */ +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg +#if defined(CONFIG_PPC_P5020) +#define CONFIG_SYS_CLK_FREQ 133000000 +#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg +#elif defined(CONFIG_PPC_P5040) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg +#endif + + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + + +#define CONFIG_SYS_MMC_MAX_DEVICE 1 + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_NO_FLASH + +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +/* test POST memory test */ +#undef CONFIG_POST +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * Local Bus Definitions + */ + +#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE +#endif + +#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull +#else +#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE +#endif + +/* Set the local bus clock 1/16 of platform clock */ +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) + +#define CONFIG_SYS_BR0_PRELIM \ +(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM \ +(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) + +#define CONFIG_SYS_OR0_PRELIM 0xfff00010 +#define CONFIG_SYS_OR1_PRELIM 0xfff00010 + + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ +{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 + +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 + +#define CONFIG_SYS_I2C_GENERIC_MAC +#define CONFIG_SYS_I2C_MAC1_BUS 3 +#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 +#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 +#define CONFIG_SYS_I2C_MAC2_BUS 0 +#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 +#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa + +#define CONFIG_CMD_DATE 1 +#define CONFIG_RTC_MCP79411 1 +#define CONFIG_SYS_RTC_BUS_NUM 3 +#define CONFIG_SYS_I2C_RTC_ADDR 0x6f + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +/* Default address of microcode for the Linux Fman driver */ +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) + +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#endif + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_NET_MULTI + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#endif + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + /* _VIA_CONTROL_EP */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ +"bank_intlv=cs0_cs1;" \ +"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ +"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ +"netdev=eth0\0" \ +"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ +"consoledev=ttyS0\0" \ +"ramdiskaddr=2000000\0" \ +"fdtaddr=c00000\0" \ +"bdev=sda3\0" + +#define CONFIG_HDBOOT \ +"setenv bootargs root=/dev/$bdev rw " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ +"setenv bootargs root=/dev/nfs rw " \ +"nfsroot=$serverip:$rootpath " \ +"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $ramdiskaddr $ramdiskfile;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#include <asm/fsl_secure_boot.h> + +#ifdef CONFIG_SECURE_BOOT +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6e32de8546..cb9544b49e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -82,11 +82,24 @@ "fdt ram 0x80f80000 0x80000;" \ "ramdisk ram 0x81000000 0x4000000\0" +#define DFU_ALT_INFO_QSPI \ + "dfu_alt_info_qspi=" \ + "MLO raw 0x0 0x010000;" \ + "MLO.backup1 raw 0x010000 0x010000;" \ + "MLO.backup2 raw 0x020000 0x010000;" \ + "MLO.backup3 raw 0x030000 0x010000;" \ + "u-boot.img raw 0x040000 0x0100000;" \ + "u-boot-spl-os raw 0x140000 0x080000;" \ + "u-boot-env raw 0x1C0000 0x010000;" \ + "u-boot-env.backup raw 0x1D0000 0x010000;" \ + "kernel raw 0x1E0000 0x800000\0" + #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_QSPI /* Fastboot */ #define CONFIG_USB_FUNCTION_FASTBOOT @@ -207,6 +220,7 @@ #define CONFIG_DFU_MMC #define CONFIG_DFU_RAM +#define CONFIG_DFU_SF /* SATA */ #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index e2b9deba9e..3cb279a912 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -23,7 +23,6 @@ #define CONFIG_IDENT_STRING " hrcon 0.01" -#define CONFIG_FSL_CLK #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_LAST_STAGE_INIT diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b8477e89d2..562e78f0a5 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,7 +11,7 @@ #define CONFIG_ARMV7_PSCI -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -69,7 +69,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -82,7 +82,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xc0000 #endif #ifdef CONFIG_QSPI_BOOT @@ -563,7 +563,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 @@ -574,7 +574,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 -#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 +#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -658,6 +658,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS #define CONFIG_CMD_BOOTZ #define CONFIG_MISC_INIT_R diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 784331ff8e..fdbbfc1196 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,7 +11,7 @@ #define CONFIG_ARMV7_PSCI -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -109,7 +109,13 @@ #endif #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg +#endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -139,6 +145,9 @@ #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NO_FLASH #endif @@ -165,7 +174,7 @@ /* * IFC Definitions */ -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -280,7 +289,6 @@ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ -#ifndef CONFIG_SD_BOOT #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 @@ -288,7 +296,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#endif /* * MMC @@ -302,7 +309,7 @@ #define CONFIG_DOS_PARTITION /* SPI */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ #define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 @@ -412,10 +419,14 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#undef CONFIG_CMD_IMLS +#endif + #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 @@ -429,13 +440,13 @@ #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "initrd_high=0xcfffffff\0" \ - "fdt_high=0xcfffffff\0" + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "initrd_high=0xcfffffff\0" \ - "fdt_high=0xcfffffff\0" + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" #endif /* @@ -478,7 +489,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif -#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 +#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 /* * Environment @@ -504,6 +515,7 @@ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS #define CONFIG_CMD_BOOTZ #define CONFIG_MISC_INIT_R diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h new file mode 100644 index 0000000000..1f22dd34df --- /dev/null +++ b/include/configs/ls1043a_common.h @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043A_COMMON_H +#define __LS1043A_COMMON_H + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_FSL_LSCH2 +#define CONFIG_LS1043A +#define CONFIG_MP +#define CONFIG_SYS_FSL_CLK +#define CONFIG_GICV2 + +#include <asm/arch/config.h> +#ifdef CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_HAS_SERDES +#endif + +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#endif + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* SD boot SPL */ +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1d000 +#define CONFIG_SPL_STACK 0x1001e000 +#define CONFIG_SPL_PAD_TO 0x1d000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + +/* NAND SPL */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + +/* IFC */ +#define CONFIG_FSL_IFC +/* + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting + */ +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#endif + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_MXC_I2C4 + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" + +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#endif + +/* Command line configuration */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_PING + +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#endif + +/* FMan ucode */ +#define CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 + +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* FMan fireware Pre-load address */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x61200000\0" \ + "kernel_load=0x807f0000\0" \ + "kernel_size=0x1000000\0" \ + "console=ttyAMA0,38400n8\0" + +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ + "earlycon=uart8250,0x21c0500,115200" +#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#define CONFIG_BOOTDELAY 10 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h new file mode 100644 index 0000000000..307d947405 --- /dev/null +++ b/include/configs/ls1043ardb.h @@ -0,0 +1,271 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043ARDB_H__ +#define __LS1043ARDB_H__ + +#include "ls1043a_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x82000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_MISC_INIT_R + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_FSL_DDR_BIST +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +#endif + +/* + * NOR Flash Definitions + */ +#define CONFIG_SYS_NOR_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0xc)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ + FTIM1_NOR_TRAD_NOR(0xb) | \ + FTIM1_NOR_TSEQRAD_NOR(0x9)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x8) | \ + FTIM2_NOR_TWP(0x10)) +#define CONFIG_SYS_NOR_FTIM3 0 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#endif + +/* + * CPLD + */ +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) +#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CONFIG_SYS_CPLD_FTIM3 0x0 + +/* IFC Timing Params */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_AQUANTIA + +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 + +#define QSGMII_PORT1_PHY_ADDR 0x4 +#define QSGMII_PORT2_PHY_ADDR 0x5 +#define QSGMII_PORT3_PHY_ADDR 0x6 +#define QSGMII_PORT4_PHY_ADDR 0x7 + +#define FM1_10GEC1_PHY_ADDR 0x1 + +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#endif + +#endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 9c8a8642e5..0011e720ea 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -9,8 +9,10 @@ #define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH3 #define CONFIG_LS2085A +#define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 @@ -18,12 +20,15 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 -#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h> -#include <asm/arch-fsl-lsch3/config.h> +#include <asm/arch/ls2085a_stream_id.h> +#include <asm/arch/config.h> #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) #define CONFIG_SYS_HAS_SERDES #endif +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT @@ -46,6 +51,7 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS /* new uImage format support */ #define CONFIG_FIT @@ -61,6 +67,7 @@ #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index 4cfcf98094..406d0e6d47 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -16,7 +16,7 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index 583fed574a..f95d7b2732 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -18,7 +18,7 @@ unsigned long get_board_sys_clk(void); #endif -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) @@ -331,6 +331,7 @@ unsigned long get_board_sys_clk(void); /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_PHYLIB_10G +#define CONFIG_PHY_AQUANTIA #define CONFIG_PHY_CORTINA #define CONFIG_PHYLIB #define CONFIG_SYS_CORTINA_FW_IN_NOR diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 152e295778..fbaa6000bc 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -17,7 +17,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_REVISION_TAG #define CONFIG_SYS_NO_FLASH -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_FIT diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 9c53fb4ad8..10a6ce995f 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -3,7 +3,7 @@ * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009-2011 + * (C) Copyright 2009-2015 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -27,7 +27,7 @@ * Since the linker has to swallow that define, we must use a pure * hex number here! */ -#define CONFIG_SYS_TEXT_BASE 0x20002000 +#define CONFIG_SYS_TEXT_BASE 0x21F00000 /* * since a number of boards are not being listed in linux @@ -56,14 +56,13 @@ #define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* * Hardware drivers */ -/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* general purpose I/O */ #define CONFIG_AT91_GPIO @@ -87,10 +86,17 @@ /* * Command line configuration. */ +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP + +#ifdef CONFIG_SYS_USE_NANDFLASH #define CONFIG_CMD_NAND -#define CONFIG_CMD_USB +#endif /* LED */ #define CONFIG_AT91_LED @@ -99,9 +105,12 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ +#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ +#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ + #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ -#define CONFIG_SYS_SDRAM_SIZE 0x02000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) @@ -133,7 +142,7 @@ #ifdef CONFIG_CMD_NAND # define CONFIG_NAND_ATMEL # define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ +# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ # define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) @@ -148,19 +157,6 @@ #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_RESET_PHY_R -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -/* CAN */ -#define CONFIG_AT91_CAN - /* hw-controller addresses */ #define CONFIG_ET1100_BASE 0x70000000 @@ -190,6 +186,8 @@ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER /* * Size of malloc() pool diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 0ee8e0d97c..f113302695 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -14,7 +14,7 @@ #define CONFIG_MX25 #define CONFIG_SYS_TEXT_BASE 0x81200000 #define CONFIG_MXC_GPIO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_TIMER_RATE 32768 #define CONFIG_SYS_TIMER_COUNTER \ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 41f518e49b..1b2f952975 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -19,7 +19,7 @@ #define CONFIG_MX35 #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA0000000 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 35c9346638..32cd58ef44 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -18,7 +18,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_TEXT_BASE 0x97800000 #include <asm/arch/imx-regs.h> diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index be37ce5342..fdb4134b13 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -23,7 +23,7 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 81af248696..37430f0a2a 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -23,7 +23,7 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_OF_LIBFDT diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 53fb4f79ef..54d3e3edd5 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -22,7 +22,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index f5fcd838ed..d915b883ce 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -23,7 +23,7 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index ba13178384..29bfbde3c5 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -45,7 +45,7 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK /* ATAGs */ #define CONFIG_CMDLINE_TAG diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index fc6aa9da2c..ffe4d81656 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -21,6 +21,7 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SYSCOUNTER_TIMER #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define CONFIG_SYS_FSL_CLK /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 3c701587bf..648e48bcf4 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -94,6 +94,8 @@ "boot.scr fat 0 1;" \ "boot.cmd fat 0 1;" \ "exynos5422-odroidxu3.dtb fat 0 1;" \ + "exynos5422-odroidxu3-lite.dtb fat 0 1;" \ + "exynos5422-odroidxu4.dtb fat 0 1;" \ "boot part 0 1;" \ "root part 0 2\0" @@ -113,9 +115,19 @@ /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ #define CONFIG_MISC_COMMON +#define CONFIG_MISC_INIT_R #define CONFIG_SET_DFU_ALT_INFO #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) +/* Set soc_rev, soc_id, board_rev, boardname, fdtfile */ +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_ODROID_REV_AIN 9 +#define CONFIG_REVISION_TAG +#define CONFIG_BOARD_TYPES + +#undef CONFIG_SYS_BOARD +#define CONFIG_SYS_BOARD "odroid" + /* Define new extra env settings, including DFU settings */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/openrd.h b/include/configs/openrd.h new file mode 100644 index 0000000000..62f15b7688 --- /dev/null +++ b/include/configs/openrd.h @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_OPENRD_H +#define _CONFIG_OPENRD_H + +/* + * Version number information + */ +#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" +#else +# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT +# define CONFIG_IDENT_STRING "\nOpenRD-Client" +# else +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_IDENT_STRING "\nOpenRD-Base" +# else +# error Unknown OpenRD board specified +# endif +# endif +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_THUMB_BUILD + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_IDE + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x60000 +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define MTDIDS_DEFAULT "nand0=nand_mtd" +#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ + "0x400000@0x100000(uImage),"\ + "0x1fb00000@0x500000(rootfs)" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +# else +# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +# endif +# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_PHY_BASE_ADR 0x0 +# define PHY_NO "88E1121" +# else +# define CONFIG_PHY_BASE_ADR 0x8 +# define PHY_NO "88E1116" +# endif +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MVEBU_MMC +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE +#endif /* CONFIG_CMD_MMC */ + +#endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 03eb185e16..433c409336 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 46f5f0f70e..d83daa0255 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK #if defined(CONFIG_TWR_P1025) #define CONFIG_BOARDNAME "TWR-P1025" #define CONFIG_P1025 diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 17969952d1..8191fb2b8a 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -9,6 +9,7 @@ #define __CONFIG_H #define CONFIG_STM32F4 +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_STM32F4DISCOVERY #define CONFIG_OF_LIBFDT diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 651c4c4935..68da23e8b7 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif -#ifndef CONFIG_ARM64 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#endif #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 02b0e6351f..0ab69e665a 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -17,6 +17,7 @@ #define __CONFIG_H /* High Level Configuration Options */ +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_COMMON /* Common ARM Erratas */ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 6735055a61..6f6666281a 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -14,7 +14,7 @@ #define CONFIG_MX53 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_OF_LIBFDT #define CONFIG_MXC_GPIO diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index abd1e98d9b..a3ea2e0a1f 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -15,7 +15,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_MACH_TYPE 4146 diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index e6f3e28fe1..2acebf1a56 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -16,7 +16,7 @@ /* High Level Configuration Options */ #define CONFIG_MX35 #define CONFIG_MX35_HCLK_FREQ 24000000 -#define CONFIG_FSL_CLK +#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 32ee0fc149..36c11009fc 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -55,9 +55,7 @@ # define CONFIG_ARM_DCC # define CONFIG_CPU_ARMV8 #else -# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) -# define CONFIG_ZYNQ_SERIAL -# endif +# define CONFIG_ZYNQ_SERIAL #endif #define CONFIG_CONS_INDEX 0 diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index e476eb1b49..ed6023a7bf 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -18,7 +18,6 @@ #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 -#define CONFIG_ZYNQ_SERIAL_UART0 #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_I2C0 #define CONFIG_SYS_I2C_ZYNQ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index ca5ef04302..f98101fc27 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -179,7 +179,10 @@ # define CONFIG_CMD_FS_GENERIC #endif +#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) #define CONFIG_SYS_I2C_ZYNQ +#endif + /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) # define CONFIG_CMD_I2C @@ -329,7 +332,11 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#ifdef CONFIG_OF_CONTROL +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif #endif /* Disable dcache for SPL just for sure */ diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index 549a664ef5..b5ffafb561 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h index d116e05ac7..ffc73bd0e3 100644 --- a/include/configs/zynq_picozed.h +++ b/include/configs/zynq_picozed.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index b6590547a9..468a6bc7bf 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 7a1b8729e5..63224dd744 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -15,26 +15,20 @@ #define CONFIG_SYS_NO_FLASH #if defined(CONFIG_ZC770_XM010) -# define CONFIG_ZYNQ_SERIAL_UART1 # define CONFIG_ZYNQ_GEM0 # define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 # define CONFIG_ZYNQ_SDHCI0 # define CONFIG_ZYNQ_SPI #elif defined(CONFIG_ZC770_XM011) -# define CONFIG_ZYNQ_SERIAL_UART1 #elif defined(CONFIG_ZC770_XM012) -# define CONFIG_ZYNQ_SERIAL_UART1 # undef CONFIG_SYS_NO_FLASH #elif defined(CONFIG_ZC770_XM013) -# define CONFIG_ZYNQ_SERIAL_UART0 # define CONFIG_ZYNQ_GEM1 # define CONFIG_ZYNQ_GEM_PHY_ADDR1 7 -#else -# define CONFIG_ZYNQ_SERIAL_UART0 #endif #include <configs/zynq-common.h> diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 946de953e4..6ec6117f17 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 191f2a5f30..e2270cd2ea 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 886a44c134..327de3486b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -25,6 +25,7 @@ enum uclass_id { UCLASS_SIMPLE_BUS, /* bus with child devices */ /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_ADC, /* Analog-to-digital converter */ UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ @@ -42,6 +43,7 @@ enum uclass_id { UCLASS_MISC, /* Miscellaneous device */ UCLASS_MMC, /* SD / MMC card or chip */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ + UCLASS_MTD, /* Memory Technology Device (MTD) device */ UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 2de6dda04c..0e36664dca 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -490,6 +490,19 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, s32 default_val); /** + * Unsigned version of fdtdec_get_int. The property must have at least + * 4 bytes of data. The value of the first cell is returned. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param default_val default value to return if the property is not found + * @return unsigned integer value, if found, or default_val if not + */ +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val); + +/** * Get a variable-sized number from a property * * This reads a number from one or more cells. @@ -628,7 +641,16 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int node, int *seqp); /** - * Get the offset of the given chosen node + * Get a property from the /chosen node + * + * @param blob Device tree blob (if NULL, then NULL is returned) + * @param name Property name to look up + * @return Value of property, or NULL if it does not exist + */ +const char *fdtdec_get_chosen_prop(const void *blob, const char *name); + +/** + * Get the offset of the given /chosen node * * This looks up a property in /chosen containing the path to another node, * then finds the offset of that node. diff --git a/include/flash.h b/include/flash.h index 5754cf9773..13e03842c8 100644 --- a/include/flash.h +++ b/include/flash.h @@ -41,6 +41,9 @@ typedef struct { ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ const char *name; /* human-readable name */ #endif +#ifdef CONFIG_MTD + struct mtd_info *mtd; +#endif } flash_info_t; extern flash_info_t flash_info[]; /* info for FLASH chips */ diff --git a/include/fm_eth.h b/include/fm_eth.h index 3e1b9f4281..d43f801fdc 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -45,8 +45,10 @@ enum fm_eth_type { #ifdef CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) +#endif #else #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) @@ -89,6 +91,7 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } #else +#if (CONFIG_SYS_NUM_FMAN == 2) #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -101,6 +104,20 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } +#else +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1+8]),\ +} +#endif #endif #if (CONFIG_SYS_NUM_FM1_10GEC >= 3) diff --git a/include/fsl_csu.h b/include/fsl_csu.h new file mode 100644 index 0000000000..f4d97fb605 --- /dev/null +++ b/include/fsl_csu.h @@ -0,0 +1,34 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __FSL_CSU_H__ +#define __FSL_CSU_H__ + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +void enable_layerscape_ns_access(void); + +#endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index e5b6e03c8f..c79fce0898 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -324,6 +324,8 @@ typedef struct memctl_options_s { unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ /* SREN - self-refresh during sleep */ unsigned int self_refresh_in_sleep; + /* SR_IE - Self-refresh interrupt enable */ + unsigned int self_refresh_interrupt_en; unsigned int dynamic_power; /* DYN_PWR */ /* memory data width to use (16-bit, 32-bit, 64-bit) */ unsigned int data_bus_width; diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/include/fsl_dtsec.h index 41b8398ecd..41b8398ecd 100644 --- a/arch/powerpc/include/asm/fsl_dtsec.h +++ b/include/fsl_dtsec.h diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 0d00b7dfdb..aa1b4cf1e4 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -166,7 +166,7 @@ #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ struct fsl_esdhc_cfg { -#ifdef CONFIG_LS2085A +#ifdef CONFIG_FSL_LAYERSCAPE u64 esdhc_base; #else u32 esdhc_base; diff --git a/arch/powerpc/include/asm/fsl_fman.h b/include/fsl_fman.h index 4d04415ba8..4d04415ba8 100644 --- a/arch/powerpc/include/asm/fsl_fman.h +++ b/include/fsl_fman.h diff --git a/include/fsl_sec.h b/include/fsl_sec.h index abc62da992..2ddced34ab 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -194,11 +194,9 @@ struct jr_regs { struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) uint32_t addr_lo; /* Memory Address - lo */ - uint16_t addr_hi; /* Memory Address of start of buffer - hi */ - uint16_t reserved_zero; + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else - uint16_t reserved_zero; - uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ uint32_t addr_lo; /* Memory Address - lo */ #endif diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/include/fsl_tgec.h index 92fb777c25..92fb777c25 100644 --- a/arch/powerpc/include/asm/fsl_tgec.h +++ b/include/fsl_tgec.h diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c4605349a6..92dd98bb61 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr { u32 psign; /* signature offset */ u32 sign_len; /* length of the signature in bytes */ union { - struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */ - u8 *pimg; /* ptr to ESBC client image */ + u32 psgtable; /* ptr to SG table */ + u32 pimg; /* ptr to ESBC client image */ }; union { u32 sg_entries; /* no of entries in SG table */ u32 img_size; /* ESBC client image size in bytes */ }; - ulong img_start; /* ESBC client entry point */ + u32 img_start; /* ESBC client entry point */ u32 sg_flag; /* Scatter gather flag */ u32 uid_flag; u32 fsl_uid_0; @@ -133,7 +133,7 @@ struct srk_table { */ struct fsl_secboot_sg_table { u32 len; /* length of the segment in bytes */ - ulong src_addr; /* ptr to the data segment */ + u32 src_addr; /* ptr to the data segment */ }; #else /* @@ -146,8 +146,8 @@ struct fsl_secboot_sg_table { struct fsl_secboot_sg_table { u32 len; u32 trgt_id; - ulong src_addr; - ulong dst_addr; + u32 src_addr; + u32 dst_addr; }; #endif @@ -162,7 +162,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - ulong ie_addr; + u32 ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7b4011f0a3..1b2e4915a0 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,6 +2,7 @@ #define _LINUX_BITOPS_H #include <asm/types.h> +#include <linux/compiler.h> #define BIT(nr) (1UL << (nr)) #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) @@ -139,6 +140,32 @@ static inline unsigned int generic_hweight8(unsigned int w) # define fls generic_fls #endif +static inline unsigned fls_long(unsigned long l) +{ + if (sizeof(l) == 4) + return fls(l); + return fls64(l); +} + +/** + * __ffs64 - find first set bit in a 64 bit word + * @word: The 64 bit word + * + * On 64 bit arches this is a synomyn for __ffs + * The result is not defined if no bits are set, so check that @word + * is non-zero before calling this. + */ +static inline unsigned long __ffs64(u64 word) +{ +#if BITS_PER_LONG == 32 + if (((u32)word) == 0UL) + return __ffs((u32)(word >> 32)) + 32; +#elif BITS_PER_LONG != 64 +#error BITS_PER_LONG not 32 or 64 +#endif + return __ffs((unsigned long)word); +} + /** * __set_bit - Set a bit in memory * @nr: the bit to set diff --git a/include/linux/compat.h b/include/linux/compat.h index 59937de960..e561ee311a 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -130,12 +130,6 @@ static inline void led_trigger_unregister_simple(struct led_trigger *trigger) {} static inline void led_trigger_event(struct led_trigger *trigger, enum led_brightness event) {} -/* include/linux/log2.h */ -static inline int is_power_of_2(unsigned long n) -{ - return (n != 0 && ((n & (n - 1)) == 0)); -} - /* uapi/linux/limits.h */ #define XATTR_LIST_MAX 65536 /* size of extended attribute namelist (64k) */ diff --git a/include/linux/log2.h b/include/linux/log2.h new file mode 100644 index 0000000000..aa1de63090 --- /dev/null +++ b/include/linux/log2.h @@ -0,0 +1,205 @@ +/* Integer base 2 logarithm calculation + * + * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LINUX_LOG2_H +#define _LINUX_LOG2_H + +#include <linux/types.h> +#include <linux/bitops.h> + +/* + * deal with unrepresentable constant logarithms + */ +extern __attribute__((const, noreturn)) +int ____ilog2_NaN(void); + +/* + * non-constant log of base 2 calculators + * - the arch may override these in asm/bitops.h if they can be implemented + * more efficiently than using fls() and fls64() + * - the arch is not required to handle n==0 if implementing the fallback + */ +#ifndef CONFIG_ARCH_HAS_ILOG2_U32 +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + return fls(n) - 1; +} +#endif + +#ifndef CONFIG_ARCH_HAS_ILOG2_U64 +static inline __attribute__((const)) +int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} +#endif + +/* + * Determine whether some value is a power of two, where zero is + * *not* considered a power of two. + */ + +static inline __attribute__((const)) +bool is_power_of_2(unsigned long n) +{ + return (n != 0 && ((n & (n - 1)) == 0)); +} + +/* + * round up to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __roundup_pow_of_two(unsigned long n) +{ + return 1UL << fls_long(n - 1); +} + +/* + * round down to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __rounddown_pow_of_two(unsigned long n) +{ + return 1UL << (fls_long(n) - 1); +} + +/** + * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value + * @n - parameter + * + * constant-capable log of base 2 calculation + * - this can be used to initialise global variables from constant data, hence + * the massive ternary operator construction + * + * selects the appropriately-sized optimised version depending on sizeof(n) + */ +#define ilog2(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n) < 1 ? ____ilog2_NaN() : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + (n) & (1ULL << 1) ? 1 : \ + (n) & (1ULL << 0) ? 0 : \ + ____ilog2_NaN() \ + ) : \ + (sizeof(n) <= 4) ? \ + __ilog2_u32(n) : \ + __ilog2_u64(n) \ + ) + +/** + * roundup_pow_of_two - round the given value up to nearest power of two + * @n - parameter + * + * round the given value up to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define roundup_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n == 1) ? 1 : \ + (1UL << (ilog2((n) - 1) + 1)) \ + ) : \ + __roundup_pow_of_two(n) \ + ) + +/** + * rounddown_pow_of_two - round the given value down to nearest power of two + * @n - parameter + * + * round the given value down to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define rounddown_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (1UL << ilog2(n))) : \ + __rounddown_pow_of_two(n) \ + ) + +/** + * order_base_2 - calculate the (rounded up) base 2 order of the argument + * @n: parameter + * + * The first few values calculated by this routine: + * ob2(0) = 0 + * ob2(1) = 0 + * ob2(2) = 1 + * ob2(3) = 2 + * ob2(4) = 2 + * ob2(5) = 3 + * ... and so on. + */ + +#define order_base_2(n) ilog2(roundup_pow_of_two(n)) + +#endif /* _LINUX_LOG2_H */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index e3d3fc73fd..c2cd3df1fa 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -272,6 +272,8 @@ struct mtd_info { struct module *owner; #ifndef __UBOOT__ struct device dev; +#else + struct udevice *dev; #endif int usecount; }; diff --git a/include/mpc8260.h b/include/mpc8260.h index 9980c74b51..75f1b0c9df 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -892,7 +892,7 @@ #define UPMC 3 #if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG) -extern __inline__ void +static __inline__ void reset_8260_watchdog(volatile immap_t *immr) { immr->im_siu_conf.sc_swsr = 0x556c; diff --git a/include/mtd.h b/include/mtd.h new file mode 100644 index 0000000000..3f8c293b00 --- /dev/null +++ b/include/mtd.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MTD_H_ +#define _MTD_H_ + +#include <linux/mtd/mtd.h> + +/* + * Get mtd_info structure of the dev, which is stored as uclass private. + * + * @dev: The MTD device + * @return: pointer to mtd_info, NULL on error + */ +static inline struct mtd_info *mtd_get_info(struct udevice *dev) +{ + return dev_get_uclass_priv(dev); +} + +#endif /* _MTD_H_ */ diff --git a/include/netdev.h b/include/netdev.h index 3d5a54f2ab..28eab46407 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -25,9 +25,6 @@ int board_eth_init(bd_t *bis); int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ -int altera_tse_initialize(u8 dev_num, int mac_base, - int sgdma_rx_base, int sgdma_tx_base, - u32 sgdma_desc_base, u32 sgdma_desc_size); int at91emac_register(bd_t *bis, unsigned long iobase); int au1x00_enet_initialize(bd_t*); int ax88180_initialize(bd_t *bis); diff --git a/include/power/regulator.h b/include/power/regulator.h index 1a51c3f07b..63c0814fe8 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -419,4 +419,20 @@ int regulator_get_by_devname(const char *devname, struct udevice **devp); */ int regulator_get_by_platname(const char *platname, struct udevice **devp); +/** + * device_get_supply_regulator: returns the pointer to the supply regulator. + * Search by phandle, found in device's node. + * + * Note: Please pay attention to proper order of device bind sequence. + * The regulator device searched by the phandle, must be binded before + * this function call. + * + * @dev - device with supply phandle + * @supply_name - phandle name of regulator + * @devp - returned pointer to the supply device + * @return 0 on success or negative value of errno. + */ +int device_get_supply_regulator(struct udevice *dev, const char *supply_name, + struct udevice **devp); + #endif /* _INCLUDE_REGULATOR_H_ */ diff --git a/include/power/s2mps11.h b/include/power/s2mps11.h new file mode 100644 index 0000000000..5da47198a4 --- /dev/null +++ b/include/power/s2mps11.h @@ -0,0 +1,109 @@ +#ifndef __S2MPS11__H__ +#define __S2MPS11__H__ + +enum s2mps11_reg { + S2MPS11_REG_ID = 0, + S2MPS11_REG_INT1, + S2MPS11_REG_INT2, + S2MPS11_REG_INT3, + S2MPS11_REG_INT1M, + S2MPS11_REG_INT2M, + S2MPS11_REG_INT3M, + S2MPS11_REG_STATUS1, + S2MPS11_REG_STATUS2, + S2MPS11_REG_OFFSRC, + S2MPS11_REG_PWRONSRC, + S2MPS11_REG_RTC_CTRL, + S2MPS11_REG_CTRL1, + S2MPS11_REG_ETC_TEST, + S2MPS11_REG_RSVD3, + S2MPS11_REG_BU_CHG, + S2MPS11_REG_RAMP, + S2MPS11_REG_RAMP_BUCK, + S2MPS11_REG_LDO1_8, + S2MPS11_REG_LDO9_16, + S2MPS11_REG_LDO17_24, + S2MPS11_REG_LDO25_32, + S2MPS11_REG_LDO33_38, + S2MPS11_REG_LDO1_8_OVC, + S2MPS11_REG_LDO9_16_OVC, + S2MPS11_REG_LDO17_24_OVC, + S2MPS11_REG_LDO25_32_OVC, + S2MPS11_REG_LDO33_38_OVC, + S2MPS11_REG_RESERVED1, + S2MPS11_REG_RESERVED2, + S2MPS11_REG_RESERVED3, + S2MPS11_REG_RESERVED4, + S2MPS11_REG_RESERVED5, + S2MPS11_REG_RESERVED6, + S2MPS11_REG_RESERVED7, + S2MPS11_REG_RESERVED8, + S2MPS11_REG_WDRSTEN_CTRL, + S2MPS11_REG_B1CTRL1, + S2MPS11_REG_B1CTRL2, + S2MPS11_REG_B2CTRL1, + S2MPS11_REG_B2CTRL2, + S2MPS11_REG_B3CTRL1, + S2MPS11_REG_B3CTRL2, + S2MPS11_REG_B4CTRL1, + S2MPS11_REG_B4CTRL2, + S2MPS11_REG_B5CTRL1, + S2MPS11_REG_BUCK5_SW, + S2MPS11_REG_B5CTRL2, + S2MPS11_REG_B5CTRL3, + S2MPS11_REG_B5CTRL4, + S2MPS11_REG_B5CTRL5, + S2MPS11_REG_B6CTRL1, + S2MPS11_REG_B6CTRL2, + S2MPS11_REG_B7CTRL1, + S2MPS11_REG_B7CTRL2, + S2MPS11_REG_B8CTRL1, + S2MPS11_REG_B8CTRL2, + S2MPS11_REG_B9CTRL1, + S2MPS11_REG_B9CTRL2, + S2MPS11_REG_B10CTRL1, + S2MPS11_REG_B10CTRL2, + S2MPS11_REG_L1CTRL, + S2MPS11_REG_L2CTRL, + S2MPS11_REG_L3CTRL, + S2MPS11_REG_L4CTRL, + S2MPS11_REG_L5CTRL, + S2MPS11_REG_L6CTRL, + S2MPS11_REG_L7CTRL, + S2MPS11_REG_L8CTRL, + S2MPS11_REG_L9CTRL, + S2MPS11_REG_L10CTRL, + S2MPS11_REG_L11CTRL, + S2MPS11_REG_L12CTRL, + S2MPS11_REG_L13CTRL, + S2MPS11_REG_L14CTRL, + S2MPS11_REG_L15CTRL, + S2MPS11_REG_L16CTRL, + S2MPS11_REG_L17CTRL, + S2MPS11_REG_L18CTRL, + S2MPS11_REG_L19CTRL, + S2MPS11_REG_L20CTRL, + S2MPS11_REG_L21CTRL, + S2MPS11_REG_L22CTRL, + S2MPS11_REG_L23CTRL, + S2MPS11_REG_L24CTRL, + S2MPS11_REG_L25CTRL, + S2MPS11_REG_L26CTRL, + S2MPS11_REG_L27CTRL, + S2MPS11_REG_L28CTRL, + S2MPS11_REG_L29CTRL, + S2MPS11_REG_L30CTRL, + S2MPS11_REG_L31CTRL, + S2MPS11_REG_L32CTRL, + S2MPS11_REG_L33CTRL, + S2MPS11_REG_L34CTRL, + S2MPS11_REG_L35CTRL, + S2MPS11_REG_L36CTRL, + S2MPS11_REG_L37CTRL, + S2MPS11_REG_L38CTRL, + S2MPS11_REG_COUNT, +}; + +#define S2MPS11_LDO26_ENABLE 0xec + +#endif diff --git a/include/power/sandbox_pmic.h b/include/power/sandbox_pmic.h index 8547674971..7fdbfb9fc6 100644 --- a/include/power/sandbox_pmic.h +++ b/include/power/sandbox_pmic.h @@ -126,6 +126,10 @@ enum { #define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA 200000 #define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE true +/* BUCK2: for testing sandbox ADC's supply */ +#define SANDBOX_BUCK2_INITIAL_EXPECTED_UV 3000000 +#define SANDBOX_BUCK2_SET_UV 3300000 + /* LDO1/2 for testing regulator_list_autoset() */ #define SANDBOX_LDO1_AUTOSET_EXPECTED_UV 1800000 #define SANDBOX_LDO1_AUTOSET_EXPECTED_UA 100000 diff --git a/include/samsung/exynos5-dt-types.h b/include/samsung/exynos5-dt-types.h new file mode 100644 index 0000000000..479e2e793d --- /dev/null +++ b/include/samsung/exynos5-dt-types.h @@ -0,0 +1,27 @@ +#ifndef _EXYNOS5_DT_H_ +#define _EXYNOS5_DT_H_ + +enum { + EXYNOS5_BOARD_GENERIC, + + EXYNOS5_BOARD_ODROID_XU3, + EXYNOS5_BOARD_ODROID_XU3_REV01, + EXYNOS5_BOARD_ODROID_XU3_REV02, + EXYNOS5_BOARD_ODROID_XU4_REV01, + EXYNOS5_BOARD_ODROID_UNKNOWN, + + EXYNOS5_BOARD_COUNT, +}; + +struct odroid_rev_info { + int board_type; + int board_rev; + int adc_val; + const char *name; +}; + +bool board_is_generic(void); +bool board_is_odroidxu3(void); +bool board_is_odroidxu4(void); + +#endif diff --git a/include/sandbox-adc.h b/include/sandbox-adc.h new file mode 100644 index 0000000000..79ff01c6ab --- /dev/null +++ b/include/sandbox-adc.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SANDBOX_ADC_H_ +#define _SANDBOX_ADC_H_ + +#define SANDBOX_ADC_DEVNAME "adc@0" +#define SANDBOX_ADC_DATA_MASK 0xffff /* 16-bits resolution */ +#define SANDBOX_ADC_CHANNELS 4 +#define SANDBOX_ADC_CHANNEL0_DATA 0x0 +#define SANDBOX_ADC_CHANNEL1_DATA 0x1000 +#define SANDBOX_ADC_CHANNEL2_DATA 0x2000 +#define SANDBOX_ADC_CHANNEL3_DATA 0x3000 + +enum sandbox_adc_mode { + SANDBOX_ADC_MODE_SINGLE_CHANNEL = 0, + SANDBOX_ADC_MODE_MULTI_CHANNEL, +}; + +enum sandbox_adc_status { + SANDBOX_ADC_INACTIVE = 0, + SANDBOX_ADC_ACTIVE, +}; + +#define SANDBOX_ADC_VSS_VALUE 0 + +#endif diff --git a/include/spi_flash.h b/include/spi_flash.h index 4312d3d691..0ae0062d12 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -54,6 +54,9 @@ struct spi_slave; * @write_cmd: Write cmd - page and quad program. * @dummy_byte: Dummy cycles for read operation. * @memory_map: Address of read-only SPI flash access + * @flash_lock: lock a region of the SPI Flash + * @flash_unlock: unlock a region of the SPI Flash + * @flash_is_locked: check if a region of the SPI Flash is completely locked * @read: Flash read ops: Read len bytes at offset into buf * Supported cmds: Fast Array Read * @write: Flash write ops: Write len bytes from buf into offset @@ -87,6 +90,10 @@ struct spi_flash { u8 dummy_byte; void *memory_map; + + int (*flash_lock)(struct spi_flash *flash, u32 ofs, size_t len); + int (*flash_unlock)(struct spi_flash *flash, u32 ofs, size_t len); + int (*flash_is_locked)(struct spi_flash *flash, u32 ofs, size_t len); #ifndef CONFIG_DM_SPI_FLASH /* * These are not strictly needed for driver model, but keep them here @@ -227,6 +234,18 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, } #endif +static inline int spi_flash_protect(struct spi_flash *flash, u32 ofs, u32 len, + bool prot) +{ + if (!flash->flash_lock) + return -EOPNOTSUPP; + + if (prot) + return flash->flash_lock(flash, ofs, len); + else + return flash->flash_unlock(flash, ofs, len); +} + void spi_boot(void) __noreturn; void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 95d6246f59..13f76be7c2 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -16,8 +16,6 @@ #define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */ #define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */ -#define DEV_FLAGS_SYSTEM 0x80000000 /* Device is a system device */ -#define DEV_EXT_VIDEO 0x00000001 /* Video extensions supported */ /* Device information */ struct stdio_dev { diff --git a/lib/bzip2/Makefile b/lib/bzip2/Makefile index 929c24e228..f0b81ad2c2 100644 --- a/lib/bzip2/Makefile +++ b/lib/bzip2/Makefile @@ -1,2 +1,6 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += bzlib.o bzlib_crctable.o bzlib_decompress.o \ bzlib_randtable.o bzlib_huffman.o diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9db033ae73..c1b517706d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -601,16 +601,21 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int offset, return -ENOENT; } -int fdtdec_get_chosen_node(const void *blob, const char *name) +const char *fdtdec_get_chosen_prop(const void *blob, const char *name) { - const char *prop; int chosen_node; - int len; if (!blob) - return -FDT_ERR_NOTFOUND; + return NULL; chosen_node = fdt_path_offset(blob, "/chosen"); - prop = fdt_getprop(blob, chosen_node, name, &len); + return fdt_getprop(blob, chosen_node, name, NULL); +} + +int fdtdec_get_chosen_node(const void *blob, const char *name) +{ + const char *prop; + + prop = fdtdec_get_chosen_prop(blob, name); if (!prop) return -FDT_ERR_NOTFOUND; return fdt_path_offset(blob, prop); @@ -1217,8 +1222,11 @@ int fdtdec_setup(void) gd->fdt_blob = __dtb_dt_begin; # elif defined CONFIG_OF_SEPARATE # ifdef CONFIG_SPL_BUILD - /* FDT is at end of BSS */ - gd->fdt_blob = (ulong *)&__bss_end; + /* FDT is at end of BSS unless it is in a different memory region */ + if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) + gd->fdt_blob = (ulong *)&_image_binary_end; + else + gd->fdt_blob = (ulong *)&__bss_end; # else /* FDT is at end of image */ gd->fdt_blob = (ulong *)&_end; diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c index 757931a9cb..63b704a3d7 100644 --- a/lib/fdtdec_common.c +++ b/lib/fdtdec_common.c @@ -36,3 +36,21 @@ int fdtdec_get_int(const void *blob, int node, const char *prop_name, debug("(not found)\n"); return default_val; } + +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val) +{ + const int *cell; + int len; + + debug("%s: %s: ", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (cell && len >= sizeof(unsigned int)) { + unsigned int val = fdt32_to_cpu(cell[0]); + + debug("%#x (%d)\n", val, val); + return val; + } + debug("(not found)\n"); + return default_val; +} diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c index 9fea775a97..747d8bb86a 100644 --- a/lib/libfdt/fdt_region.c +++ b/lib/libfdt/fdt_region.c @@ -101,7 +101,7 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, continue; next = fdt_next_property_offset(fdt, offset); if (next < 0) - next = node_end - sizeof(fdt32_t); + next = node_end; if (!did_alias_header) { fdt_add_region(info, base + node, 12); diff --git a/scripts/Makefile b/scripts/Makefile index efe25bfc6e..2f081f7104 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -3,6 +3,9 @@ # the kernel for the build process. # --------------------------------------------------------------------------- # docproc: Used in Documentation/DocBook +# +# SPDX-License-Identifier: GPL-2.0 +# # The following hostprogs-y programs are only build on demand hostprogs-y += docproc diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 2df93c8a09..dd235b9d7a 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -129,7 +129,9 @@ boot.bin: $(obj)/u-boot-spl.bin ALL-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).cfg +ifdef CONFIG_SPL_OF_CONTROL ALL-$(CONFIG_OF_SEPARATE) += $(obj)/$(SPL_BIN)-pad.bin $(obj)/$(SPL_BIN)-dtb.bin +endif ifdef CONFIG_SAMSUNG ALL-y += $(obj)/$(BOARD)-spl.bin diff --git a/scripts/basic/Makefile b/scripts/basic/Makefile index 4fcef87bb8..f883857b54 100644 --- a/scripts/basic/Makefile +++ b/scripts/basic/Makefile @@ -7,6 +7,9 @@ # .config is included by main Makefile. # --------------------------------------------------------------------------- # fixdep: Used to generate dependency information during build process +# +# SPDX-License-Identifier: GPL-2.0 +# hostprogs-y := fixdep always := $(hostprogs-y) diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index 46ddf2d6bd..14285b15a8 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -1,6 +1,9 @@ # =========================================================================== # Kernel configuration targets # These targets are used from top-level makefile +# +# SPDX-License-Identifier: GPL-2.0 +# PHONY += xconfig gconfig menuconfig config silentoldconfig update-po-config \ localmodconfig localyesconfig diff --git a/test/dm/Makefile b/test/dm/Makefile index 7b3626cb32..39630f68c8 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -33,4 +33,5 @@ obj-y += syscon.o obj-$(CONFIG_DM_USB) += usb.o obj-$(CONFIG_DM_PMIC) += pmic.o obj-$(CONFIG_DM_REGULATOR) += regulator.o +obj-$(CONFIG_ADC) += adc.o endif diff --git a/test/dm/adc.c b/test/dm/adc.c new file mode 100644 index 0000000000..b0d4fe5b23 --- /dev/null +++ b/test/dm/adc.c @@ -0,0 +1,165 @@ +/* + * Tests for the driver model ADC API + * + * Copyright (c) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <adc.h> +#include <dm.h> +#include <dm/root.h> +#include <dm/util.h> +#include <dm/test.h> +#include <errno.h> +#include <fdtdec.h> +#include <power/regulator.h> +#include <power/sandbox_pmic.h> +#include <sandbox-adc.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int dm_test_adc_bind(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); + ut_asserteq_str(SANDBOX_ADC_DEVNAME, dev->name); + + return 0; +} +DM_TEST(dm_test_adc_bind, DM_TESTF_SCAN_FDT); + +static int dm_test_adc_wrong_channel_selection(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); + ut_asserteq(-EINVAL, adc_start_channel(dev, SANDBOX_ADC_CHANNELS)); + + return 0; +} +DM_TEST(dm_test_adc_wrong_channel_selection, DM_TESTF_SCAN_FDT); + +static int dm_test_adc_supply(struct unit_test_state *uts) +{ + struct udevice *supply; + struct udevice *dev; + int uV; + + ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); + + /* Test Vss value - predefined 0 uV */ + ut_assertok(adc_vss_value(dev, &uV)); + ut_asserteq(SANDBOX_ADC_VSS_VALUE, uV); + + /* Test Vdd initial value - buck2 */ + ut_assertok(adc_vdd_value(dev, &uV)); + ut_asserteq(SANDBOX_BUCK2_INITIAL_EXPECTED_UV, uV); + + /* Change Vdd value - buck2 manual preset */ + ut_assertok(regulator_get_by_devname(SANDBOX_BUCK2_DEVNAME, &supply)); + ut_assertok(regulator_set_value(supply, SANDBOX_BUCK2_SET_UV)); + ut_asserteq(SANDBOX_BUCK2_SET_UV, regulator_get_value(supply)); + + /* Update ADC platdata and get new Vdd value */ + ut_assertok(adc_vdd_value(dev, &uV)); + ut_asserteq(SANDBOX_BUCK2_SET_UV, uV); + + /* Disable buck2 and test ADC supply enable function */ + ut_assertok(regulator_set_enable(supply, false)); + ut_asserteq(false, regulator_get_enable(supply)); + /* adc_start_channel() should enable the supply regulator */ + ut_assertok(adc_start_channel(dev, 0)); + ut_asserteq(true, regulator_get_enable(supply)); + + return 0; +} +DM_TEST(dm_test_adc_supply, DM_TESTF_SCAN_FDT); + +struct adc_channel adc_channel_test_data[] = { + { 0, SANDBOX_ADC_CHANNEL0_DATA }, + { 1, SANDBOX_ADC_CHANNEL1_DATA }, + { 2, SANDBOX_ADC_CHANNEL2_DATA }, + { 3, SANDBOX_ADC_CHANNEL3_DATA }, +}; + +static int dm_test_adc_single_channel_conversion(struct unit_test_state *uts) +{ + struct adc_channel *tdata = adc_channel_test_data; + unsigned int i, data; + struct udevice *dev; + + ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); + /* Test each ADC channel's value */ + for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) { + ut_assertok(adc_start_channel(dev, tdata->id)); + ut_assertok(adc_channel_data(dev, tdata->id, &data)); + ut_asserteq(tdata->data, data); + } + + return 0; +} +DM_TEST(dm_test_adc_single_channel_conversion, DM_TESTF_SCAN_FDT); + +static int dm_test_adc_multi_channel_conversion(struct unit_test_state *uts) +{ + struct adc_channel channels[SANDBOX_ADC_CHANNELS]; + struct udevice *dev; + struct adc_channel *tdata = adc_channel_test_data; + unsigned int i, channel_mask; + + channel_mask = ADC_CHANNEL(0) | ADC_CHANNEL(1) | + ADC_CHANNEL(2) | ADC_CHANNEL(3); + + /* Start multi channel conversion */ + ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); + ut_assertok(adc_start_channels(dev, channel_mask)); + ut_assertok(adc_channels_data(dev, channel_mask, channels)); + + /* Compare the expected and returned conversion data. */ + for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) + ut_asserteq(tdata->data, channels[i].data); + + return 0; +} +DM_TEST(dm_test_adc_multi_channel_conversion, DM_TESTF_SCAN_FDT); + +static int dm_test_adc_single_channel_shot(struct unit_test_state *uts) +{ + struct adc_channel *tdata = adc_channel_test_data; + unsigned int i, data; + + for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) { + /* Start single channel conversion */ + ut_assertok(adc_channel_single_shot("adc", tdata->id, &data)); + /* Compare the expected and returned conversion data. */ + ut_asserteq(tdata->data, data); + } + + return 0; +} +DM_TEST(dm_test_adc_single_channel_shot, DM_TESTF_SCAN_FDT); + +static int dm_test_adc_multi_channel_shot(struct unit_test_state *uts) +{ + struct adc_channel channels[SANDBOX_ADC_CHANNELS]; + struct adc_channel *tdata = adc_channel_test_data; + unsigned int i, channel_mask; + + channel_mask = ADC_CHANNEL(0) | ADC_CHANNEL(1) | + ADC_CHANNEL(2) | ADC_CHANNEL(3); + + /* Start single call and multi channel conversion */ + ut_assertok(adc_channels_single_shot("adc", channel_mask, channels)); + + /* Compare the expected and returned conversion data. */ + for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) + ut_asserteq(tdata->data, channels[i].data); + + return 0; +} +DM_TEST(dm_test_adc_multi_channel_shot, DM_TESTF_SCAN_FDT); diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile index 10aba2ba66..3c3e69f014 100644 --- a/tools/easylogo/Makefile +++ b/tools/easylogo/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + hostprogs-y := easylogo always := $(hostprogs-y) diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index caaf6006a5..67aa41a24d 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -667,28 +667,16 @@ static int fdtgrep_find_regions(const void *fdt, new_count = fdt_add_alias_regions(fdt, region, count, max_regions, &state); - if (new_count > max_regions) { - region = malloc(new_count * sizeof(struct fdt_region)); - if (!region) { - fprintf(stderr, - "Out of memory for %d regions\n", - count); - return -1; - } - memcpy(region, state.region, - count * sizeof(struct fdt_region)); - free(state.region); - new_count = fdt_add_alias_regions(fdt, region, count, - max_regions, &state); + if (new_count <= max_regions) { + /* + * The alias regions will now be at the end of the list. + * Sort the regions by offset to get things into the + * right order + */ + count = new_count; + qsort(region, count, sizeof(struct fdt_region), + h_cmp_region); } - - /* - * The alias regions will now be at the end of the list. Sort - * the regions by offset to get things into the right order - */ - qsort(region, new_count, sizeof(struct fdt_region), - h_cmp_region); - count = new_count; } if (ret != -FDT_ERR_NOTFOUND) @@ -805,7 +793,7 @@ static int do_fdtgrep(struct display_info *disp, const char *filename) * The first pass will count the regions, but if it is too many, * we do another pass to actually record them. */ - for (i = 0; i < 2; i++) { + for (i = 0; i < 3; i++) { region = malloc(count * sizeof(struct fdt_region)); if (!region) { fprintf(stderr, "Out of memory for %d regions\n", |
