Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

71 files changed, 3917 insertions, 245 deletions

diff --git a/MAKEALL b/MAKEALL
index 2133559e82..b34ae33288 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -428,6 +428,7 @@ LIST_85xx="		\
 	P2020RDB_NAND	\
 	P2020RDB_SDCARD	\
 	P2020RDB_SPIFLASH	\
+	P4080DS		\
 	PM854		\
 	PM856		\
 	sbc8540		\
diff --git a/Makefile b/Makefile
index 9cea069980..4f1cb1b4d1 100644
--- a/Makefile
+++ b/Makefile
@@ -1788,6 +1788,7 @@ P2010RDB_config \
 P2010RDB_NAND_config \
 P2010RDB_SDCARD_config \
 P2010RDB_SPIFLASH_config \
+P2020DS_DDR2_config \
 P2020RDB_config \
 P2020RDB_NAND_config \
 P2020RDB_SDCARD_config \
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index fe851f15db..b7c0272105 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -64,12 +64,20 @@ COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-$(CONFIG_FSL_CORENET) += liodn.o
 COBJS-$(CONFIG_MP)	+= mp.o
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
 COBJS-$(CONFIG_P1022)	+= p1022_serdes.o
 COBJS-$(CONFIG_PCI)	+= pci.o
+COBJS-$(CONFIG_FSL_CORENET) += portals.o
+
+# various SoC specific assignments
+COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
+
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
+COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 
 COBJS	= $(COBJS-y)
 COBJS	+= cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index d7835c8d69..d73f3d7f14 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -41,6 +41,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 #endif
 
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
+	puts("Work-around for Erratum SERDES8 enabled\n");
+#endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+	puts("Work-around for Erratum CPU22 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 5d5b4c2963..2c3be6dd09 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -32,6 +32,7 @@
 #include <ioports.h>
 #include <sata.h>
 #include <asm/io.h>
+#include <asm/cache.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
@@ -127,6 +128,44 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_CPC
+static void enable_cpc(void)
+{
+	int i;
+	u32 size = 0;
+
+	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+		size += CPC_CFG0_SZ_K(cpccfg0);
+
+		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
+		/* Read back to sync write */
+		in_be32(&cpc->cpccsr0);
+
+	}
+
+	printf("Corenet Platform Cache: %d KB enabled\n", size);
+}
+
+void invalidate_cpc(void)
+{
+	int i;
+	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+		/* Flash invalidate the CPC and clear all the locks */
+		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
+		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
+			;
+	}
+}
+#else
+#define enable_cpc()
+#define invalidate_cpc()
+#endif /* CONFIG_SYS_FSL_CPC */
+
 /*
  * Breathe some life into the CPU...
  *
@@ -188,6 +227,9 @@ void cpu_init_f (void)
 	corenet_tb_init();
 #endif
 	init_used_tlb_cams();
+
+	/* Invalidate the CPC before DDR gets enabled */
+	invalidate_cpc();
 }
 
 
@@ -198,13 +240,18 @@ void cpu_init_f (void)
  * use the same bit-encoding as the older 8555, etc, parts.
  *
  */
-
 int cpu_init_r(void)
 {
 #ifdef CONFIG_SYS_LBC_LCRR
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
 
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+	flush_dcache();
+	mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+	sync();
+#endif
+
 	puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
@@ -319,6 +366,9 @@ int cpu_init_r(void)
 #else
 	puts("disabled\n");
 #endif
+
+	enable_cpc();
+
 #ifdef CONFIG_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 	qe_init(qe_base);
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 0691ca455a..e46dcb7047 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -33,6 +33,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		return;
 	}
 
+	out_be32(&ddr->eor, regs->ddr_eor);
+
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (i == 0) {
 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 932466e883..8e7b827ffb 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -28,6 +28,8 @@
 #include <fdt_support.h>
 #include <asm/processor.h>
 #include <linux/ctype.h>
+#include <asm/io.h>
+#include <asm/fsl_portals.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
@@ -80,7 +82,30 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_CPC
+static inline void ft_fixup_l3cache(void *blob, int off)
+{
+	u32 line_size, num_ways, size, num_sets;
+	cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
+	u32 cfg0 = in_be32(&cpc->cpccfg0);
+
+	size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
+	num_ways = CPC_CFG0_NUM_WAYS(cfg0);
+	line_size = CPC_CFG0_LINE_SZ(cfg0);
+	num_sets = size / (line_size * num_ways);
+
+	fdt_setprop(blob, off, "cache-unified", NULL, 0);
+	fdt_setprop_cell(blob, off, "cache-block-size", line_size);
+	fdt_setprop_cell(blob, off, "cache-size", size);
+	fdt_setprop_cell(blob, off, "cache-sets", num_sets);
+	fdt_setprop_cell(blob, off, "cache-level", 3);
+#ifdef CONFIG_SYS_CACHE_STASHING
+	fdt_setprop_cell(blob, off, "cache-stash-id", 1);
+#endif
+}
+#else
 #define ft_fixup_l3cache(x, y)
+#endif
 
 #if defined(CONFIG_L2_CACHE)
 /* return size in kilobytes */
@@ -422,4 +447,18 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
 
 	ft_fixup_dpaa_clks(blob);
+
+#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
+	fdt_portal(blob, "fsl,bman-portal", "bman-portals",
+			(u64)CONFIG_SYS_BMAN_MEM_PHYS,
+			CONFIG_SYS_BMAN_MEM_SIZE);
+#endif
+
+#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
+	fdt_portal(blob, "fsl,qman-portal", "qman-portals",
+			(u64)CONFIG_SYS_QMAN_MEM_PHYS,
+			CONFIG_SYS_QMAN_MEM_SIZE);
+
+	fdt_fixup_qportals(blob);
+#endif
 }
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
new file mode 100644
index 0000000000..5bcf91abf2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -0,0 +1,495 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+#include <hwconfig.h>
+#endif
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/fsl_law.h>
+#include "fsl_corenet_serdes.h"
+
+static u32 serdes_prtcl_map;
+
+#ifdef DEBUG
+static const char *serdes_prtcl_str[] = {
+	[NONE] = "NA",
+	[PCIE1] = "PCIE1",
+	[PCIE2] = "PCIE2",
+	[PCIE3] = "PCIE3",
+	[PCIE4] = "PCIE4",
+	[SATA1] = "SATA1",
+	[SATA2] = "SATA2",
+	[SRIO1] = "SRIO1",
+	[SRIO2] = "SRIO2",
+	[SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
+	[SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
+	[SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
+	[SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
+	[SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
+	[SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
+	[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
+	[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
+	[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+	[XAUI_FM1] = "XAUI_FM1",
+	[XAUI_FM2] = "XAUI_FM2",
+	[AURORA] = "DEBUG",
+};
+#endif
+
+static const struct {
+	int idx;
+	unsigned int lpd; /* RCW lane powerdown bit */
+	int bank;
+} lanes[SRDS_MAX_LANES] = {
+	{ 0, 152, FSL_SRDS_BANK_1 },
+	{ 1, 153, FSL_SRDS_BANK_1 },
+	{ 2, 154, FSL_SRDS_BANK_1 },
+	{ 3, 155, FSL_SRDS_BANK_1 },
+	{ 4, 156, FSL_SRDS_BANK_1 },
+	{ 5, 157, FSL_SRDS_BANK_1 },
+	{ 6, 158, FSL_SRDS_BANK_1 },
+	{ 7, 159, FSL_SRDS_BANK_1 },
+	{ 8, 160, FSL_SRDS_BANK_1 },
+	{ 9, 161, FSL_SRDS_BANK_1 },
+	{ 16, 162, FSL_SRDS_BANK_2 },
+	{ 17, 163, FSL_SRDS_BANK_2 },
+	{ 18, 164, FSL_SRDS_BANK_2 },
+	{ 19, 165, FSL_SRDS_BANK_2 },
+	{ 20, 170, FSL_SRDS_BANK_3 },
+	{ 21, 171, FSL_SRDS_BANK_3 },
+	{ 22, 172, FSL_SRDS_BANK_3 },
+	{ 23, 173, FSL_SRDS_BANK_3 },
+};
+
+int serdes_get_lane_idx(int lane)
+{
+	return lanes[lane].idx;
+}
+
+int serdes_get_bank(int lane)
+{
+	return lanes[lane].bank;
+}
+
+int serdes_lane_enabled(int lane)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+
+	int bank = lanes[lane].bank;
+	int word = lanes[lane].lpd / 32;
+	int bit = lanes[lane].lpd % 32;
+
+	if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
+		return 0;
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+	if (!IS_SVR_REV(get_svr(), 1, 0))
+		if (bank > 0)
+			return !(srds_lpd_b[bank] &
+					(8 >> (lane - (6 + 4 * bank))));
+#endif
+
+	return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
+}
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* Is serdes enabled at all? */
+	if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
+		return 0;
+
+	return (1 << device) & serdes_prtcl_map;
+}
+
+#ifndef CONFIG_SYS_DCSRBAR_PHYS
+#define CONFIG_SYS_DCSRBAR_PHYS	0x80000000 /* Must be 1GB-aligned for rev1.0 */
+#define CONFIG_SYS_DCSRBAR	0x80000000
+#define __DCSR_NOT_DEFINED_BY_CONFIG
+#endif
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+static void enable_bank(ccsr_gur_t *gur, int bank)
+{
+	u32 rcw5;
+
+	/*
+	 * Enable the lanes SRDS_LPD_Bn.  The RCW bits are read-only in
+	 * CCSR, and read/write in DSCR.
+	 */
+	rcw5 = in_be32(gur->rcwsr + 5);
+	if (bank == FSL_SRDS_BANK_2) {
+		rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
+		rcw5 |= srds_lpd_b[bank] << 26;
+	} else if (bank == FSL_SRDS_BANK_3) {
+		rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
+		rcw5 |= srds_lpd_b[bank] << 18;
+	} else {
+		printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
+		return;
+	}
+
+	/* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
+	 * of the DCSR mapping.
+	 */
+	{
+#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
+		struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
+		int law_index;
+		if (law.index == -1)
+			law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
+						 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
+		else
+			set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
+				LAW_TRGT_IF_DCSR);
+#endif
+		u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
+		out_be32(p, rcw5);
+#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
+		if (law.index == -1)
+			disable_law(law_index);
+		else
+			set_law(law.index, law.addr, law.size, law.trgt_id);
+#endif
+	}
+}
+
+/*
+ * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
+ * bank 3 to clock banks 2 and 3, as well as a limited selection of
+ * protocol configurations.  This requires that banks 2 and 3's lanes be
+ * disabled in the RCW, and enabled with some fixup here to re-enable
+ * them, and to configure bank 2's clock parameters in bank 3's pll in
+ * cases where they differ.
+ */
+static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
+				  u32 devdisr, u32 devdisr2, int cfg)
+{
+	int srds_ratio_b2;
+	int rfck_sel;
+
+	/*
+	 * The disabled lanes of bank 2 will cause the associated
+	 * logic blocks to be disabled in DEVDISR.  We reverse that here.
+	 *
+	 * Note that normally it is not permitted to clear DEVDISR bits
+	 * once the device has been disabled, but the hardware people
+	 * say that this special case is OK.
+	 */
+	clrbits_be32(&gur->devdisr, devdisr);
+	clrbits_be32(&gur->devdisr2, devdisr2);
+
+	/*
+	 * Some protocols require special handling.  There are a few
+	 * additional protocol configurations that can be used, which are
+	 * not listed here.  See app note 4065 for supported protocol
+	 * configurations.
+	 */
+	switch (cfg) {
+	case 0x19:
+		/*
+		 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
+		 * SGMII on bank 3 should still be usable.
+		 */
+		setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
+			     SRDS_PLLCR1_PLL_BWSEL);
+
+		enable_bank(gur, FSL_SRDS_BANK_3);
+		break;
+
+	case 0x0f:
+	case 0x10:
+		/*
+		 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
+		 * requirements in these configurations.  Bank 3 cannot
+		 * be used and should have its lanes (but not the bank
+		 * itself) disabled in the RCW.  We set up bank 3's pll
+		 * for bank 2's needs here.
+		 */
+		srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
+
+		/* Determine refclock from XAUI ratio */
+		switch (srds_ratio_b2) {
+		case 1: /* 20:1 */
+			rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		case 2: /* 25:1 */
+			rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		default:
+			printf("SERDES: bad SRDS_RATIO_B2 %d\n",
+			       srds_ratio_b2);
+			return;
+		}
+
+		clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
+				SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
+
+		clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
+				SRDS_PLLCR0_FRATE_SEL_MASK,
+				SRDS_PLLCR0_FRATE_SEL_6_25);
+		break;
+	default:
+		enable_bank(gur, FSL_SRDS_BANK_3);
+	}
+
+}
+#endif
+
+void fsl_serdes_init(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int cfg;
+	serdes_corenet_t *srds_regs;
+	int lane, bank, idx;
+	enum srds_prtcl lane_prtcl;
+	long long end_tick;
+	int have_bank[SRDS_MAX_BANK] = {};
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+	u32 serdes8_devdisr = 0;
+	u32 serdes8_devdisr2 = 0;
+	char srds_lpd_opt[16];
+	const char *srds_lpd_arg;
+	size_t arglen;
+#endif
+
+	/* Is serdes enabled at all? */
+	if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
+		return;
+
+	srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+	cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+	debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
+
+	if (!is_serdes_prtcl_valid(cfg)) {
+		printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
+		return;
+	}
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+	if (!IS_SVR_REV(get_svr(), 1, 0))
+		for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
+			sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
+			srds_lpd_arg = hwconfig_subarg("serdes", srds_lpd_opt,
+						       &arglen);
+			if (srds_lpd_arg)
+				srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg,
+								  NULL, 0);
+		}
+#endif
+
+	/* Look for banks with all lanes disabled, and power down the bank. */
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
+		if (serdes_lane_enabled(lane)) {
+			have_bank[serdes_get_bank(lane)] = 1;
+			serdes_prtcl_map |= (1 << lane_prtcl);
+		}
+	}
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+	if (IS_SVR_REV(get_svr(), 1, 0)) {
+		/* At least one bank must be disabled due to SERDES8.  If
+		 * no bank is found to be disabled based on lane
+		 * disables, disable bank 3 because we can't turn off its
+		 * lanes in the RCW without disabling MDIO due to erratum
+		 * GEN8.
+		 *
+		 * This means that if you are relying on bank 3 being
+		 * disabled to avoid SERDES8, in some cases you cannot
+		 * also disable all lanes of another bank, or else bank
+		 * 3 won't be disabled, leaving you with a configuration
+		 * that isn't valid according to SERDES8 (e.g. if banks
+		 * 2 and 3 have the same clock, and bank 1 is disabled
+		 * instead of 3).
+		 */
+		for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
+			if (!have_bank[bank])
+				break;
+		}
+
+		if (bank == SRDS_MAX_BANK)
+			have_bank[FSL_SRDS_BANK_3] = 0;
+	} else {
+		if (have_bank[FSL_SRDS_BANK_2])
+			have_bank[FSL_SRDS_BANK_3] = 1;
+	}
+#endif
+
+	for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
+		if (!have_bank[bank]) {
+			printf("SERDES: bank %d disabled\n", bank + 1);
+			setbits_be32(&srds_regs->bank[bank].rstctl,
+				     SRDS_RSTCTL_SDPD);
+		}
+	}
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		idx = serdes_get_lane_idx(lane);
+		lane_prtcl = serdes_get_prtcl(cfg, lane);
+
+#ifdef DEBUG
+		switch (lane) {
+		case 0:
+			puts("Bank1: ");
+			break;
+		case 10:
+			puts("\nBank2: ");
+			break;
+		case 14:
+			puts("\nBank3: ");
+			break;
+		default:
+			break;
+		}
+
+		printf("%s ", serdes_prtcl_str[lane_prtcl]);
+#endif
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+		switch (lane_prtcl) {
+		case PCIE1:
+		case PCIE2:
+		case PCIE3:
+			serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
+					   (lane_prtcl - PCIE1);
+			break;
+		case SRIO1:
+		case SRIO2:
+			serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
+					   (lane_prtcl - SRIO1);
+			break;
+		case SGMII_FM1_DTSEC1:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
+					    FSL_CORENET_DEVDISR2_DTSEC1_1;
+			break;
+		case SGMII_FM1_DTSEC2:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
+					    FSL_CORENET_DEVDISR2_DTSEC1_2;
+			break;
+		case SGMII_FM1_DTSEC3:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
+					    FSL_CORENET_DEVDISR2_DTSEC1_3;
+			break;
+		case SGMII_FM1_DTSEC4:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
+					    FSL_CORENET_DEVDISR2_DTSEC1_4;
+			break;
+		case SGMII_FM2_DTSEC1:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+					    FSL_CORENET_DEVDISR2_DTSEC2_1;
+			break;
+		case SGMII_FM2_DTSEC2:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+					    FSL_CORENET_DEVDISR2_DTSEC2_2;
+			break;
+		case SGMII_FM2_DTSEC3:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+					    FSL_CORENET_DEVDISR2_DTSEC2_3;
+			break;
+		case SGMII_FM2_DTSEC4:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+					    FSL_CORENET_DEVDISR2_DTSEC2_4;
+			break;
+		case XAUI_FM1:
+		case XAUI_FM2:
+			if (lane_prtcl == XAUI_FM1)
+				serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1	|
+						    FSL_CORENET_DEVDISR2_10GEC1;
+			else
+				serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2	|
+						    FSL_CORENET_DEVDISR2_10GEC2;
+			break;
+		case AURORA:
+			break;
+		default:
+			break;
+		}
+
+#endif
+	}
+
+#ifdef DEBUG
+	puts("\n");
+#endif
+
+	for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
+		u32 rstctl;
+
+		bank = idx;
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+		if (!IS_SVR_REV(get_svr(), 1, 0)) {
+			/*
+			 * Change bank init order to 0, 2, 1, so that the
+			 * third bank's PLL is established before we
+			 * start the second bank which shares the third
+			 * bank's PLL.
+			 */
+
+			if (idx == 1)
+				bank = FSL_SRDS_BANK_3;
+			else if (idx == 2)
+				bank = FSL_SRDS_BANK_2;
+		}
+#endif
+
+		/* Skip disabled banks */
+		if (!have_bank[bank])
+			continue;
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+		if (!IS_SVR_REV(get_svr(), 1, 0)) {
+			if (idx == 1) {
+				p4080_erratum_serdes8(srds_regs, gur,
+						      serdes8_devdisr,
+						      serdes8_devdisr2, cfg);
+			} else if (idx == 2) {
+				enable_bank(gur, FSL_SRDS_BANK_2);
+			}
+		}
+#endif
+
+		/* reset banks for errata */
+		setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
+
+		/* wait for reset complete or 1-second timeout */
+		end_tick = usec2ticks(1000000) + get_ticks();
+		do {
+			rstctl = in_be32(&srds_regs->bank[bank].rstctl);
+			if (rstctl & SRDS_RSTCTL_RSTDONE)
+				break;
+		} while (end_tick > get_ticks());
+
+		if (!(rstctl & SRDS_RSTCTL_RSTDONE)) {
+			printf("SERDES: timeout resetting bank %d\n",
+			       bank + 1);
+			continue;
+		}
+	}
+}
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
new file mode 100644
index 0000000000..42d771e096
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_CORENET_SERDES_H
+#define __FSL_CORENET_SERDES_H
+
+#define SRDS_MAX_LANES		18
+#define SRDS_MAX_BANK		3
+
+enum srds_bank {
+	FSL_SRDS_BANK_1  = 0,
+	FSL_SRDS_BANK_2  = 1,
+	FSL_SRDS_BANK_3  = 2,
+};
+
+int is_serdes_prtcl_valid(u32 prtcl);
+int serdes_get_lane_idx(int lane);
+int serdes_get_bank(int lane);
+int serdes_lane_enabled(int lane);
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+extern uint16_t srds_lpd_b[SRDS_MAX_BANK];
+#endif
+
+#endif /* __FSL_CORENET_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
new file mode 100644
index 0000000000..bd1909471c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset)
+{
+	liodns[0] = liodn_bases[dpaa_dev].id[0] + liodn_offset;
+
+	if (liodn_bases[dpaa_dev].num_ids == 2)
+		liodns[1] = liodn_bases[dpaa_dev].id[1] + liodn_offset;
+
+	return liodn_bases[dpaa_dev].num_ids;
+}
+
+static void set_liodn(struct liodn_id_table *tbl, int size)
+{
+	int i;
+
+	for (i = 0; i < size; i++) {
+		u32 liodn;
+		if (tbl[i].num_ids == 2) {
+			liodn = (tbl[i].id[0] << 16) | tbl[i].id[1];
+		} else {
+			liodn = tbl[i].id[0];
+		}
+
+		out_be32((volatile u32 *)(tbl[i].reg_offset), liodn);
+	}
+}
+
+static void setup_sec_liodn_base(void)
+{
+	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	u32 base;
+
+	if (!IS_E_PROCESSOR(get_svr()))
+		return;
+
+	/* QILCR[QSLOM] */
+	out_be32(&sec->qilcr_ms, 0x3ff<<16);
+
+	base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) |
+		liodn_bases[FSL_HW_PORTAL_SEC].id[1];
+
+	out_be32(&sec->qilcr_ls, base);
+}
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
+				  struct liodn_id_table *tbl, int size)
+{
+	int i;
+	ccsr_fman_t *fm;
+	u32 base;
+
+	switch(dev) {
+	case FSL_HW_PORTAL_FMAN1:
+		fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+		break;
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	case FSL_HW_PORTAL_FMAN2:
+		fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+		break;
+#endif
+	default:
+		printf("Error: Invalid device type to %s\n", __FUNCTION__);
+		return ;
+	}
+
+	base = (liodn_bases[dev].id[0] << 16) | liodn_bases[dev].id[0];
+
+	/* setup all bases the same */
+	for (i = 0; i < 32; i++) {
+		out_be32(&fm->fm_dma.fmdmplr[i], base);
+	}
+
+	/* update tbl to ... */
+	for (i = 0; i < size; i++)
+		tbl[i].id[0] += liodn_bases[dev].id[0];
+}
+#endif
+
+static void setup_pme_liodn_base(void)
+{
+#ifdef CONFIG_SYS_DPAA_PME
+	ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+	u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
+			liodn_bases[FSL_HW_PORTAL_PME].id[1];
+
+	out_be32(&pme->liodnbr, base);
+#endif
+}
+
+void set_liodns(void)
+{
+	/* setup general liodn offsets */
+	set_liodn(liodn_tbl, liodn_tbl_sz);
+
+	/* setup SEC block liodn bases & offsets if we have one */
+	if (IS_E_PROCESSOR(get_svr())) {
+		set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz);
+		setup_sec_liodn_base();
+	}
+
+	/* setup FMAN block(s) liodn bases & offsets if we have one */
+#ifdef CONFIG_SYS_DPAA_FMAN
+	set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz);
+	setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl,
+				fman1_liodn_tbl_sz);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz);
+	setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl,
+				fman2_liodn_tbl_sz);
+#endif
+#endif
+	/* setup PME liodn base */
+	setup_pme_liodn_base();
+}
+
+static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
+{
+	int i;
+
+	for (i = 0; i < sz; i++) {
+		int off;
+
+		if (tbl[i].compat == NULL)
+			continue;
+
+		off = fdt_node_offset_by_compat_reg(blob,
+				tbl[i].compat, tbl[i].compat_offset);
+		if (off >= 0) {
+			off = fdt_setprop(blob, off, "fsl,liodn",
+				&tbl[i].id[0],
+				sizeof(u32) * tbl[i].num_ids);
+			if (off > 0)
+				printf("WARNING unable to set fsl,liodn for "
+					"%s: %s\n",
+					tbl[i].compat, fdt_strerror(off));
+		} else {
+			debug("WARNING: could not set fsl,liodn for %s: %s.\n",
+					tbl[i].compat, fdt_strerror(off));
+		}
+	}
+}
+
+void fdt_fixup_liodn(void *blob)
+{
+	fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_liodn_tbl(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz);
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	fdt_fixup_liodn_tbl(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz);
+#endif
+#endif
+	fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz);
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
new file mode 100644
index 0000000000..3861146b8b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO( 1,  2,  1, 0),
+	SET_QP_INFO( 3,  4,  2, 1),
+	SET_QP_INFO( 5,  6,  3, 2),
+	SET_QP_INFO( 7,  8,  4, 3),
+	SET_QP_INFO( 9, 10,  5, 4),
+	SET_QP_INFO(11, 12,  6, 5),
+	SET_QP_INFO(13, 14,  7, 6),
+	SET_QP_INFO(15, 16,  8, 7),
+	SET_QP_INFO(17, 18,  9, 0), /* for now sdest to 0 */
+	SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
+};
+
+struct liodn_id_table liodn_tbl[] = {
+	SET_USB_LIODN(1, "fsl-usb2-mph", 127),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 157),
+
+	SET_SDHC_LIODN(1, 156),
+
+	SET_PCI_LIODN(1, 193),
+	SET_PCI_LIODN(2, 194),
+	SET_PCI_LIODN(3, 195),
+
+	SET_DMA_LIODN(1, 196),
+	SET_DMA_LIODN(2, 197),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0),
+
+	SET_QMAN_LIODN(31),
+	SET_BMAN_LIODN(32),
+	SET_PME_LIODN(128),
+};
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 11),
+	SET_FMAN_RX_1G_LIODN(1, 1, 12),
+	SET_FMAN_RX_1G_LIODN(1, 2, 13),
+	SET_FMAN_RX_1G_LIODN(1, 3, 14),
+	SET_FMAN_RX_10G_LIODN(1, 0, 15),
+};
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(2, 0, 16),
+	SET_FMAN_RX_1G_LIODN(2, 1, 17),
+	SET_FMAN_RX_1G_LIODN(2, 2, 18),
+	SET_FMAN_RX_1G_LIODN(2, 3, 19),
+	SET_FMAN_RX_10G_LIODN(2, 0, 20),
+};
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JQ_LIODN_ENTRY(0, 146, 154),
+	SET_SEC_JQ_LIODN_ENTRY(1, 147, 155),
+	SET_SEC_JQ_LIODN_ENTRY(2, 178, 186),
+	SET_SEC_JQ_LIODN_ENTRY(3, 179, 187),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 144),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 145),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 176),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 177),
+	SET_SEC_DECO_LIODN_ENTRY(0, 129, 161),
+	SET_SEC_DECO_LIODN_ENTRY(1, 130, 162),
+	SET_SEC_DECO_LIODN_ENTRY(2, 131, 163),
+	SET_SEC_DECO_LIODN_ENTRY(3, 132, 164),
+	SET_SEC_DECO_LIODN_ENTRY(4, 133, 165),
+};
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(96, 106),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(116, 133),
+#endif
+};
+
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
new file mode 100644
index 0000000000..87bd795293
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
+		SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
+		SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
+		XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
+	[0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
+		SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		NONE, NONE, NONE, NONE},
+	[0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+		AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
+	[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+		AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
+	[0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+	[0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+		AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+};
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
+uint16_t srds_lpd_b[SRDS_MAX_BANK];
+#endif
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+	if (!serdes_lane_enabled(lane))
+		return NONE;
+
+	return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl) {
+	int i;
+
+	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_cfg_tbl[prtcl][i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
new file mode 100644
index 0000000000..01aec6e794
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR;
+
+void setup_portals(void)
+{
+	int i;
+
+	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+
+	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+		u8 sdest = qp_info[i].sdest;
+		u16 fliodn = qp_info[i].fliodn;
+		u16 dliodn = qp_info[i].dliodn;
+		u16 liodn_off = qp_info[i].liodn_offset;
+
+		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
+					dliodn);
+		/* set frame liodn */
+		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
+	}
+}
+
+/* Update portal containter to match LAW setup of portal in phy map */
+void fdt_portal(void *blob, const char *compat, const char *container,
+			u64 addr, u32 size)
+{
+	int off;
+
+	off = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (off < 0)
+		return ;
+
+	off = fdt_parent_offset(blob, off);
+	/* if non-zero assume we have a container */
+	if (off > 0) {
+		char buf[60];
+		const char *p, *name;
+		u32 *range;
+		int len;
+
+		/* fixup ranges */
+		range = fdt_getprop_w(blob, off, "ranges", &len);
+		if (range == NULL) {
+			printf("ERROR: container for %s has no ranges", compat);
+			return ;
+		}
+
+		range[0] = 0;
+		if (len == 16) {
+			range[1] = addr >> 32;
+			range[2] = addr & 0xffffffff;
+			range[3] = size;
+		} else {
+			range[1] = addr & 0xffffffff;
+			range[2] = size;
+		}
+		fdt_setprop_inplace(blob, off, "ranges", range, len);
+
+		/* fixup the name */
+		name = fdt_get_name(blob, off, &len);
+		p = memchr(name, '@', len);
+
+		if (p)
+			len = p - name;
+
+		/* if we are given a container name check it
+		 * against what we found, if it doesnt match exit out */
+		if (container && (memcmp(container, name, len))) {
+			printf("WARNING: container names didn't match %s %s\n",
+				container, name);
+			return ;
+		}
+
+		memcpy(&buf, name, len);
+		len += sprintf(&buf[len], "@%llx", addr);
+		fdt_set_name(blob, off, buf);
+		return ;
+	}
+
+	printf("ERROR: %s isn't in a container.  Not supported\n", compat);
+}
+
+static int fdt_qportal(void *blob, int off, int id, char *name,
+		       enum fsl_dpaa_dev dev, int create)
+{
+	int childoff, dev_off, num, ret = 0;
+	uint32_t dev_handle;
+	u32 liodns[2];
+
+	childoff = fdt_subnode_offset(blob, off, name);
+	if (create) {
+		if (childoff <= 0)
+			childoff = fdt_add_subnode(blob, off, name);
+
+		if (childoff > 0) {
+			char handle[64], *p;
+
+			strncpy(handle, name, sizeof(handle));
+			p = strchr(handle, '@');
+			if (!strncmp(name, "fman", 4)) {
+				*p = *(p + 1);
+				p++;
+			}
+			*p = '\0';
+
+			dev_off = fdt_path_offset(blob, handle);
+			if (dev_off < 0)
+				return dev_off;
+
+			dev_handle = fdt_get_phandle(blob, dev_off);
+			if (dev_handle <= 0) {
+				dev_handle = fdt_alloc_phandle(blob);
+				fdt_setprop_cell(blob, dev_off,
+					"linux,phandle", dev_handle);
+			}
+
+			ret = fdt_setprop(blob, childoff, "dev-handle",
+					  &dev_handle, sizeof(dev_handle));
+			if (ret < 0)
+				return ret;
+
+			num = get_dpaa_liodn(dev, &liodns[0], id);
+			ret = fdt_setprop(blob, childoff, "fsl,liodn",
+					  &liodns[0], sizeof(u32) * num);
+		} else {
+			return childoff;
+		}
+	} else {
+		if (childoff > 0)
+			ret = fdt_del_node(blob, childoff);
+	}
+
+	return ret;
+}
+
+void fdt_fixup_qportals(void *blob)
+{
+	int off, err;
+	unsigned int maj, min;
+	u32 rev_1 = in_be32(&qman->ip_rev_1);
+	char compat[64];
+	int compat_len;
+
+	maj = (rev_1 >> 8) & 0xff;
+	min = rev_1 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1;
+	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
+	while (off != -FDT_ERR_NOTFOUND) {
+		u32 liodns[2];
+		const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
+		int j, i = *ci;
+
+		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+		if (err < 0)
+			goto err;
+
+		liodns[0] = qp_info[i].dliodn;
+		liodns[1] = qp_info[i].fliodn;
+
+		err = fdt_setprop(blob, off, "fsl,liodn",
+				  &liodns, sizeof(u32) * 2);
+		if (err < 0)
+			goto err;
+
+		i++;
+
+		err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
+				  IS_E_PROCESSOR(get_svr()));
+		if (err < 0)
+			goto err;
+
+#ifdef CONFIG_SYS_DPAA_PME
+		err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
+		if (err < 0)
+			goto err;
+#else
+		fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
+#endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+			char name[] = "fman@0";
+
+			name[sizeof(name) - 2] = '0' + j;
+			err = fdt_qportal(blob, off, i, name,
+					  FSL_HW_PORTAL_FMAN1 + j, 1);
+			if (err < 0)
+				goto err;
+		}
+#endif
+
+err:
+		if (err < 0) {
+			printf("ERROR: unable to create props for %s: %s\n",
+				fdt_get_name(blob, off, NULL), fdt_strerror(err));
+			return;
+		}
+
+		off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
+	}
+}
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 0b5b9da032..53cefaf002 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -136,6 +136,12 @@ __secondary_start_page:
 	mtspr	L1CSR2,r8
 #endif
 
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+	mfspr	r8,L1CSR2
+	oris	r8,r8,(L1CSR2_DCWS)@h
+	mtspr	L1CSR2,r8
+#endif
+
 #ifdef CONFIG_BACKSIDE_L2_CACHE
 	/* Enable/invalidate the L2 cache */
 	msync
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index b3cb56a5b0..3278b109fe 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -330,8 +330,18 @@ _start_e500:
 	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
 	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
 
+#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
+    defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
+	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
+				(MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
+				(MAS3_SX|MAS3_SW|MAS3_SR))@l
+	li      r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
+	mtspr	MAS7,r10
+#else
 	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
 
 	mtspr   MAS0,r6
 	mtspr   MAS1,r7
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index dc3da1689f..97a94f4cd0 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -110,8 +110,14 @@ struct cpu_type *identify_cpu(u32 ver)
 }
 
 int cpu_numcores() {
-	struct cpu_type *cpu;
-	cpu = gd->cpu;
+	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
+	struct cpu_type *cpu = gd->cpu;
+
+	/* better to query feature reporting register than just assume 1 */
+	if (cpu == &cpu_type_unknown)
+		return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >>
+			MPC85xx_PICFRR_NCPU_SHIFT) + 1;
+
 	return cpu->num_cores;
 }
 
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
index 5aea517f25..06706ed78c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
@@ -48,6 +48,9 @@ typedef struct {
 
 	unsigned long long total_mem;
 	unsigned long long base_address;
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
 } common_timing_params_t;
 
 #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 4a282bc52d..dccb7aa14b 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -93,7 +93,7 @@ static inline unsigned int compute_cas_write_latency(void)
 }
 
 /* Chip Select Configuration (CSn_CONFIG) */
-static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
+static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const dimm_params_t *dimm_params)
 {
@@ -106,28 +106,49 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
 	unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 	unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 	unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
+	int go_config = 0;
 
 	/* Compute CS_CONFIG only for existing ranks of each DIMM.  */
-	if ((((i&1) == 0)
-	    && (dimm_params[i/2].n_ranks == 1))
-	    || (dimm_params[i/2].n_ranks == 2)) {
-		unsigned int n_banks_per_sdram_device;
-		cs_n_en = 1;
-		if (i == 0) {
+	switch (i) {
+	case 0:
+		if (dimm_params[dimm_number].n_ranks > 0) {
+			go_config = 1;
 			/* These fields only available in CS0_CONFIG */
 			intlv_en = popts->memctl_interleaving;
 			intlv_ctl = popts->memctl_interleaving_mode;
 		}
+		break;
+	case 1:
+		if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
+		    (dimm_number == 1 && dimm_params[1].n_ranks > 0))
+			go_config = 1;
+		break;
+	case 2:
+		if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
+		   (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
+			go_config = 1;
+		break;
+	case 3:
+		if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
+		    (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
+		    (dimm_number == 3 && dimm_params[3].n_ranks > 0))
+			go_config = 1;
+		break;
+	default:
+		break;
+	}
+	if (go_config) {
+		unsigned int n_banks_per_sdram_device;
+		cs_n_en = 1;
 		ap_n_en = popts->cs_local_opts[i].auto_precharge;
 		odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 		odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 		n_banks_per_sdram_device
-			= dimm_params[i/2].n_banks_per_sdram_device;
+			= dimm_params[dimm_number].n_banks_per_sdram_device;
 		ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
-		row_bits_cs_n = dimm_params[i/2].n_row_addr - 12;
-		col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
+		row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
+		col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 	}
-
 	ddr->cs[i].config = (0
 		| ((cs_n_en & 0x1) << 31)
 		| ((intlv_en & 0x3) << 29)
@@ -178,7 +199,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 	unsigned char act_pd_exit_mclk;
 	/* Precharge powerdown exit timing (tXP). */
 	unsigned char pre_pd_exit_mclk;
-	/* Precharge powerdown exit timing (tAXPD). */
+	/* ODT powerdown exit timing (tAXPD). */
 	unsigned char taxpd_mclk;
 	/* Mode register set cycle time (tMRD). */
 	unsigned char tmrd_mclk;
@@ -190,13 +211,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 	 * we use the tXP instead of it.
 	 * tXP=max(3nCK, 7.5ns) for DDR3.
 	 * spec has not the tAXPD, we use
-	 * tAXPD=8, need design to confirm.
+	 * tAXPD=1, need design to confirm.
 	 */
 	int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 	act_pd_exit_mclk = picos_to_mclk(tXP);
 	/* Mode register MR0[A12] is '1' - fast exit */
 	pre_pd_exit_mclk = act_pd_exit_mclk;
-	taxpd_mclk = 8;
+	taxpd_mclk = 1;
 	tmrd_mclk = 4;
 	/* set the turnaround time */
 	trwt_mclk = 1;
@@ -427,6 +448,35 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 }
 
+/* DDR SDRAM Register Control Word */
+static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
+			       const common_timing_params_t *common_dimm)
+{
+	if (common_dimm->all_DIMMs_registered
+		&& !common_dimm->all_DIMMs_unbuffered) {
+		ddr->ddr_sdram_rcw_1 =
+			common_dimm->rcw[0] << 28 | \
+			common_dimm->rcw[1] << 24 | \
+			common_dimm->rcw[2] << 20 | \
+			common_dimm->rcw[3] << 16 | \
+			common_dimm->rcw[4] << 12 | \
+			common_dimm->rcw[5] << 8 | \
+			common_dimm->rcw[6] << 4 | \
+			common_dimm->rcw[7];
+		ddr->ddr_sdram_rcw_2 =
+			common_dimm->rcw[8] << 28 | \
+			common_dimm->rcw[9] << 24 | \
+			common_dimm->rcw[10] << 20 | \
+			common_dimm->rcw[11] << 16 | \
+			common_dimm->rcw[12] << 12 | \
+			common_dimm->rcw[13] << 8 | \
+			common_dimm->rcw[14] << 4 | \
+			common_dimm->rcw[15];
+		debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
+		debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
+	}
+}
+
 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
@@ -521,6 +571,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int d_init;		/* DRAM data initialization */
 	unsigned int rcw_en = 0;	/* Register Control Word Enable */
 	unsigned int md_en = 0;		/* Mirrored DIMM Enable */
+	unsigned int qd_en = 0;		/* quad-rank DIMM Enable */
 
 	dll_rst_dis = 1;	/* Make this configurable */
 	dqs_cfg = popts->DQS_config;
@@ -562,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR3)
 	md_en = popts->mirrored_dimm;
 #endif
+	qd_en = popts->quad_rank_present ? 1 : 0;
 	ddr->ddr_sdram_cfg_2 = (0
 		| ((frc_sr & 0x1) << 31)
 		| ((sr_ie & 0x1) << 30)
@@ -569,6 +621,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((dqs_cfg & 0x3) << 26)
 		| ((odt_cfg & 0x3) << 21)
 		| ((num_pr & 0xf) << 12)
+		| (qd_en << 9)
 		| ((obc_cfg & 0x1) << 6)
 		| ((ap_en & 0x1) << 5)
 		| ((d_init & 0x1) << 4)
@@ -914,6 +967,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 
 	clk_adjust = popts->clk_adjust;
 	ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
+	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
 
 /* DDR Initialization Address (DDR_INIT_ADDR) */
@@ -977,9 +1031,9 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
 	unsigned int wodt_off = 0;	/* Write to ODT off */
 
 #if defined(CONFIG_FSL_DDR3)
-	rodt_on = 3;	/*  2 clocks */
+	rodt_on = 2;	/*  2 clocks */
 	rodt_off = 4;	/*  4 clocks */
-	wodt_on = 2;	/*  1 clocks */
+	wodt_on = 1;	/*  1 clocks */
 	wodt_off = 4;	/*  4 clocks */
 #endif
 
@@ -1052,9 +1106,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
 		/*
 		 * Write leveling repetition time
 		 * at least tWLO + 6 clocks clocks
-		 * we set it 32
+		 * we set it 64
 		 */
-		wrlvl_wlr = 0x5;
+		wrlvl_wlr = 0x6;
 		/*
 		 * Write leveling start time
 		 * The value use for the DQS_ADJUST for the first sample
@@ -1089,52 +1143,12 @@ static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
 	ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
 }
 
-/* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
-static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
-{
-	unsigned int rcw0 = 0;	/* RCW0: Register Control Word 0 */
-	unsigned int rcw1 = 0;	/* RCW1: Register Control Word 1 */
-	unsigned int rcw2 = 0;	/* RCW2: Register Control Word 2 */
-	unsigned int rcw3 = 0;	/* RCW3: Register Control Word 3 */
-	unsigned int rcw4 = 0;	/* RCW4: Register Control Word 4 */
-	unsigned int rcw5 = 0;	/* RCW5: Register Control Word 5 */
-	unsigned int rcw6 = 0;	/* RCW6: Register Control Word 6 */
-	unsigned int rcw7 = 0;	/* RCW7: Register Control Word 7 */
-
-	ddr->ddr_sdram_rcw_1 = (0
-				| ((rcw0 & 0xF) << 28)
-				| ((rcw1 & 0xF) << 24)
-				| ((rcw2 & 0xF) << 20)
-				| ((rcw3 & 0xF) << 16)
-				| ((rcw4 & 0xF) << 12)
-				| ((rcw5 & 0xF) << 8)
-				| ((rcw6 & 0xF) << 4)
-				| ((rcw7 & 0xF) << 0)
-				);
-}
-
-/* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
-static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
 {
-	unsigned int rcw8 = 0;	/* RCW0: Register Control Word 8 */
-	unsigned int rcw9 = 0;	/* RCW1: Register Control Word 9 */
-	unsigned int rcw10 = 0;	/* RCW2: Register Control Word 10 */
-	unsigned int rcw11 = 0;	/* RCW3: Register Control Word 11 */
-	unsigned int rcw12 = 0;	/* RCW4: Register Control Word 12 */
-	unsigned int rcw13 = 0;	/* RCW5: Register Control Word 13 */
-	unsigned int rcw14 = 0;	/* RCW6: Register Control Word 14 */
-	unsigned int rcw15 = 0;	/* RCW7: Register Control Word 15 */
-
-	ddr->ddr_sdram_rcw_2 = (0
-				| ((rcw8 & 0xF) << 28)
-				| ((rcw9 & 0xF) << 24)
-				| ((rcw10 & 0xF) << 20)
-				| ((rcw11 & 0xF) << 16)
-				| ((rcw12 & 0xF) << 12)
-				| ((rcw13 & 0xF) << 8)
-				| ((rcw14 & 0xF) << 4)
-				| ((rcw15 & 0xF) << 0)
-				);
+	if (popts->addr_hash) {
+		ddr->ddr_eor = 0x40000000;	/* address hash enable */
+		puts("Addess hashing enabled.\n");
+	}
 }
 
 unsigned int
@@ -1201,37 +1215,63 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	/* Chip Select Memory Bounds (CSn_BNDS) */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		unsigned long long ea = 0, sa = 0;
-
-		if (popts->ba_intlv_ctl && (i > 0) &&
-			((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
-			/* Don't set up boundaries for other CS
-			 * other than CS0, if bank interleaving
-			 * is enabled and not CS2+CS3 interleaved.
+		unsigned int cs_per_dimm
+			= CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
+		unsigned int dimm_number
+			= i / cs_per_dimm;
+		unsigned long long rank_density
+			= dimm_params[dimm_number].rank_density;
+
+		if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
+			((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
+			((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
+			/*
+			 * Don't set up boundaries for unused CS
+			 * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
+			 * cs2 for cs0_cs1_cs2_cs3
+			 * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
 			 * But we need to set the ODT_RD_CFG and
 			 * ODT_WR_CFG for CS1_CONFIG here.
 			 */
-			set_csn_config(i, ddr, popts, dimm_params);
-			break;
+			set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+			continue;
 		}
-
-		if (dimm_params[i/2].n_ranks == 0) {
+		if (dimm_params[dimm_number].n_ranks == 0) {
 			debug("Skipping setup of CS%u "
-				"because n_ranks on DIMM %u is 0\n", i, i/2);
+				"because n_ranks on DIMM %u is 0\n", i, dimm_number);
 			continue;
 		}
 		if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
 			/*
 			 * This works superbank 2CS
-			 * There are 2 memory controllers configured
+			 * There are 2 or more memory controllers configured
 			 * identically, memory is interleaved between them,
 			 * and each controller uses rank interleaving within
 			 * itself. Therefore the starting and ending address
 			 * on each controller is twice the amount present on
 			 * each controller.
 			 */
-			unsigned long long rank_density
-					= dimm_params[0].capacity;
-			ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
+			unsigned long long ctlr_density = 0;
+			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+			case FSL_DDR_CS0_CS1:
+			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+				ctlr_density = dimm_params[0].rank_density * 2;
+				break;
+			case FSL_DDR_CS2_CS3:
+				ctlr_density = dimm_params[0].rank_density;
+				break;
+			case FSL_DDR_CS0_CS1_CS2_CS3:
+				/*
+				 * The four CS interleaving should have been verified by
+				 * populate_memctl_options()
+				 */
+				ctlr_density = dimm_params[0].rank_density * 4;
+				break;
+			default:
+				break;
+			}
+			ea = (CONFIG_NUM_DDR_CONTROLLERS *
+				(ctlr_density >> dbw_cap_adj)) - 1;
 		}
 		else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
 			/*
@@ -1243,8 +1283,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			 * controller needs to be programmed into its
 			 * respective CS0_BNDS.
 			 */
-			unsigned long long rank_density
-						= dimm_params[i/2].rank_density;
 			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 			case FSL_DDR_CS0_CS1_CS2_CS3:
 				/* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
@@ -1257,9 +1295,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 				/* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
 				 * and CS2_CNDS need to be set.
 				 */
-				if (!(i&1)) {
-					sa = dimm_params[i/2].base_address;
-					ea = sa + (i * (rank_density >>
+				if ((i == 2) && (dimm_number == 0)) {
+					sa = dimm_params[dimm_number].base_address +
+					      2 * (rank_density >> dbw_cap_adj);
+					ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
+				} else {
+					sa = dimm_params[dimm_number].base_address;
+					ea = sa + (2 * (rank_density >>
 						dbw_cap_adj)) - 1;
 				}
 				break;
@@ -1267,16 +1309,31 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 				/* CS0+CS1 interleaving, CS0_CNDS needs
 				 * to be set
 				 */
-				sa = common_dimm->base_address;
-				ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
+				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
+					sa = dimm_params[dimm_number].base_address;
+					ea = sa + (rank_density >> dbw_cap_adj) - 1;
+					sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
+					ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
+				} else {
+					sa = 0;
+					ea = 0;
+				}
+				if (i == 0)
+					ea += (rank_density >> dbw_cap_adj);
 				break;
 			case FSL_DDR_CS2_CS3:
 				/* CS2+CS3 interleaving*/
-				if (i == 2) {
-					sa = dimm_params[i/2].base_address;
-					ea = sa + (2 * (rank_density >>
-						dbw_cap_adj)) - 1;
+				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
+					sa = dimm_params[dimm_number].base_address;
+					ea = sa + (rank_density >> dbw_cap_adj) - 1;
+					sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
+					ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
+				} else {
+					sa = 0;
+					ea = 0;
 				}
+				if (i == 2)
+					ea += (rank_density >> dbw_cap_adj);
 				break;
 			default:  /* No bank(chip-select) interleaving */
 				break;
@@ -1292,8 +1349,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			 * memory in the two CS0 ranks.
 			 */
 			if (i == 0) {
-				unsigned long long rank_density
-						= dimm_params[0].rank_density;
 				ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
 			}
 
@@ -1303,20 +1358,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			 * No rank interleaving and no memory controller
 			 * interleaving.
 			 */
-			unsigned long long rank_density
-						= dimm_params[i/2].rank_density;
-			sa = dimm_params[i/2].base_address;
+			sa = dimm_params[dimm_number].base_address;
 			ea = sa + (rank_density >> dbw_cap_adj) - 1;
-			if (i&1) {
-				if ((dimm_params[i/2].n_ranks == 1)) {
-					/* Odd chip select, single-rank dimm */
-					sa = 0;
-					ea = 0;
-				} else {
-					/* Odd chip select, dual-rank DIMM */
-					sa += rank_density >> dbw_cap_adj;
-					ea += rank_density >> dbw_cap_adj;
-				}
+			if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
+				sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
+				ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
+			} else {
+				sa = 0;
+				ea = 0;
 			}
 		}
 
@@ -1329,10 +1378,12 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			);
 
 		debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
-		set_csn_config(i, ddr, popts, dimm_params);
+		set_csn_config(dimm_number, i, ddr, popts, dimm_params);
 		set_csn_config_2(i, ddr);
 	}
 
+	set_ddr_eor(ddr, popts);
+
 #if !defined(CONFIG_FSL_DDR1)
 	set_timing_cfg_0(ddr);
 #endif
@@ -1361,8 +1412,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 
 	set_ddr_sr_cntr(ddr, sr_it);
 
-	set_ddr_sdram_rcw_1(ddr);
-	set_ddr_sdram_rcw_2(ddr);
+	set_ddr_sdram_rcw(ddr, common_dimm);
 
 	return check_fsl_memctl_config_regs(ddr);
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index f1220750df..98acb8dd52 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -73,6 +73,7 @@ extern unsigned int populate_memctl_options(int all_DIMMs_registered,
 				memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num);
+extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
 
 extern unsigned int mclk_to_picos(unsigned int mclk);
 extern unsigned int get_memory_clk_period_ps(void);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index d4199baa82..29cea53266 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -90,6 +90,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 {
 	unsigned int retval;
 	unsigned int mtb_ps;
+	int i;
 
 	if (spd->mem_type) {
 		if (spd->mem_type != SPD_MEMTYPE_DDR3) {
@@ -131,8 +132,11 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	case 0x01:	/* RDIMM */
 	case 0x05:	/* Mini-RDIMM */
 		pdimm->registered_dimm = 1; /* register buffered */
+		for (i = 0; i < 16; i += 2) {
+			pdimm->rcw[i] = spd->mod_section.registered.rcw[i/2] & 0x0F;
+			pdimm->rcw[i+1] = (spd->mod_section.registered.rcw[i/2] >> 4) & 0x0F;
+		}
 		break;
-
 	case 0x02:	/* UDIMM */
 	case 0x03:	/* SO-DIMM */
 	case 0x04:	/* Micro-DIMM */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index e888e3ea56..029e566b6b 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -76,7 +76,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 				      common_timing_params_t *outpdimm,
 				      unsigned int number_of_dimms)
 {
-	unsigned int i;
+	unsigned int i, j;
 
 	unsigned int tCKmin_X_ps = 0;
 	unsigned int tCKmax_ps = 0xFFFFFFFF;
@@ -98,7 +98,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	unsigned int tDQSQ_max_ps = 0;
 	unsigned int tQHS_ps = 0;
 
-	unsigned int temp1, temp2;
+	unsigned int temp1, temp2, temp3;
 	unsigned int additive_latency = 0;
 #if !defined(CONFIG_FSL_DDR3)
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
@@ -118,6 +118,18 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 			temp1++;
 			continue;
 		}
+		if (dimm_params[i].n_ranks == 4 && i != 0) {
+			printf("Found Quad-rank DIMM in wrong bank, ignored."
+				" Software may not run as expected.\n");
+			temp1++;
+			continue;
+		}
+		if (dimm_params[i].n_ranks == 4 && \
+		  CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
+			printf("Found Quad-rank DIMM, not able to support.");
+			temp1++;
+			continue;
+		}
 
 		/*
 		 * Find minimum tCKmax_ps to find fastest slow speed,
@@ -219,6 +231,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 				"DIMMs detected!\n");
 	}
 
+	temp1 = 0;
+	if (outpdimm->all_DIMMs_registered)
+		for (j = 0; j < 16; j++) {
+			outpdimm->rcw[j] = dimm_params[0].rcw[j];
+			for (i = 1; i < number_of_dimms; i++)
+				if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
+					temp3 = 1;
+					break;
+				}
+		}
+
+	if (temp1 != 0)
+		printf("ERROR: Mix different RDIMM detected!\n");
+
 #if defined(CONFIG_FSL_DDR3)
 	if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
 		return 1;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index faa1af95ef..6d582e97d4 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -100,8 +100,8 @@ const char * step_to_string(unsigned int step) {
 
 int step_assign_addresses(fsl_ddr_info_t *pinfo,
 			  unsigned int dbw_cap_adj[],
-			  unsigned int *memctl_interleaving,
-			  unsigned int *rank_interleaving)
+			  unsigned int *all_memctl_interleaving,
+			  unsigned int *all_ctlr_rank_interleaving)
 {
 	int i, j;
 
@@ -152,30 +152,30 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 		}
 	}
 
-	/*
-	 * Check if all controllers are configured for memory
-	 * controller interleaving.
-	 */
 	j = 0;
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (pinfo->memctl_opts[i].memctl_interleaving) {
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+		if (pinfo->memctl_opts[i].memctl_interleaving)
 			j++;
-		}
-	}
-	if (j == 2)
-		*memctl_interleaving = 1;
+	/*
+	 * Not support less than all memory controllers interleaving
+	 * if more than two controllers
+	 */
+	if (j == CONFIG_NUM_DDR_CONTROLLERS)
+		*all_memctl_interleaving = 1;
 
 	/* Check that all controllers are rank interleaving. */
 	j = 0;
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (pinfo->memctl_opts[i].ba_intlv_ctl) {
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+		if (pinfo->memctl_opts[i].ba_intlv_ctl)
 			j++;
-		}
-	}
-	if (j == 2)
-		*rank_interleaving = 1;
+	/*
+	 * All memory controllers must be populated to qualify for
+	 * all controller rank interleaving
+	 */
+	 if (j == CONFIG_NUM_DDR_CONTROLLERS)
+		*all_ctlr_rank_interleaving = 1;
 
-	if (*memctl_interleaving) {
+	if (*all_memctl_interleaving) {
 		unsigned long long addr, total_mem_per_ctlr = 0;
 		/*
 		 * If interleaving between memory controllers,
@@ -316,7 +316,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
 					&pinfo->memctl_opts[i],
 					pinfo->dimm_params[i], i);
 		}
-
+		check_interleaving_options(pinfo);
 	case STEP_ASSIGN_ADDRESSES:
 		/* STEP 5:  Assign addresses to chip selects */
 		step_assign_addresses(pinfo,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 46731c8153..774c0e4b42 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <hwconfig.h>
 #include <asm/fsl_ddr_sdram.h>
 
 #include "ddr.h"
@@ -23,7 +24,6 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			unsigned int ctrl_num)
 {
 	unsigned int i;
-	const char *p;
 
 	/* Chip select options. */
 
@@ -204,6 +204,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * meet the tQDSS under different loading.
 	 */
 	popts->wrlvl_en = 1;
+	popts->zq_en = 1;
 	popts->wrlvl_override = 0;
 #endif
 
@@ -212,78 +213,128 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * Please refer to doc/README.fsl-ddr for the detail.
 	 *
 	 * If memory controller interleaving is enabled, then the data
-	 * bus widths must be programmed identically for the 2 memory
-	 * controllers.
+	 * bus widths must be programmed identically for all memory controllers.
 	 *
-	 * XXX: Attempt to set both controllers to the same chip select
+	 * XXX: Attempt to set all controllers to the same chip select
 	 * interleaving mode. It will do a best effort to get the
 	 * requested ranks interleaved together such that the result
 	 * should be a subset of the requested configuration.
 	 */
 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
-	if ((p = getenv("memctl_intlv_ctl")) != NULL) {
+	if (hwconfig_sub("fsl_ddr", "ctlr_intlv")) {
 		if (pdimm[0].n_ranks == 0) {
-			printf("There is no rank on CS0. Because only rank on "
-				"CS0 and ranks chip-select interleaved with CS0"
+			printf("There is no rank on CS0 for controller %d. Because only"
+				" rank on CS0 and ranks chip-select interleaved with CS0"
 				" are controller interleaved, force non memory "
-				"controller interleaving\n");
+				"controller interleaving\n", ctrl_num);
 			popts->memctl_interleaving = 0;
 		} else {
 			popts->memctl_interleaving = 1;
-			if (strcmp(p, "cacheline") == 0)
+			/*
+			 * test null first. if CONFIG_HWCONFIG is not defined
+			 * hwconfig_arg_cmp returns non-zero
+			 */
+			if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "null")) {
+				popts->memctl_interleaving = 0;
+				debug("memory controller interleaving disabled.\n");
+			} else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "cacheline"))
 				popts->memctl_interleaving_mode =
 					FSL_DDR_CACHE_LINE_INTERLEAVING;
-			else if (strcmp(p, "page") == 0)
+			else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "page"))
 				popts->memctl_interleaving_mode =
 					FSL_DDR_PAGE_INTERLEAVING;
-			else if (strcmp(p, "bank") == 0)
+			else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "bank"))
 				popts->memctl_interleaving_mode =
 					FSL_DDR_BANK_INTERLEAVING;
-			else if (strcmp(p, "superbank") == 0)
+			else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "superbank"))
 				popts->memctl_interleaving_mode =
 					FSL_DDR_SUPERBANK_INTERLEAVING;
-			else
-				popts->memctl_interleaving_mode =
-						simple_strtoul(p, NULL, 0);
+			else {
+				popts->memctl_interleaving = 0;
+				printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
+			}
 		}
 	}
 #endif
-
-	if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
+	if ((hwconfig_sub("fsl_ddr", "bank_intlv")) &&
 		(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
-		if (strcmp(p, "cs0_cs1") == 0)
+		/* test null first. if CONFIG_HWCONFIG is not defined,
+		 * hwconfig_arg_cmp returns non-zero */
+		if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "null"))
+			debug("bank interleaving disabled.\n");
+		else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1"))
 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
-		else if (strcmp(p, "cs2_cs3") == 0)
+		else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs2_cs3"))
 			popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
-		else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
+		else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3"))
 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
-		else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
+		else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3"))
 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 		else
-			popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
-
+			printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 		case FSL_DDR_CS0_CS1_CS2_CS3:
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+			if (pdimm[0].n_ranks < 4) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for "
+					"CS0+CS1+CS2+CS3 on controller %d, "
+					"force non-interleaving!\n", ctrl_num);
+			}
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for "
+					"CS0+CS1+CS2+CS3 on controller %d, "
+					"force non-interleaving!\n", ctrl_num);
+			}
+			if (pdimm[0].capacity != pdimm[1].capacity) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not identical DIMM size for "
+					"CS0+CS1+CS2+CS3 on controller %d, "
+					"force non-interleaving!\n", ctrl_num);
+			}
+#endif
+			break;
 		case FSL_DDR_CS0_CS1:
-			if (pdimm[0].n_ranks != 2) {
+			if (pdimm[0].n_ranks < 2) {
 				popts->ba_intlv_ctl = 0;
 				printf("Not enough bank(chip-select) for "
-					"CS0+CS1, force non-interleaving!\n");
+					"CS0+CS1 on controller %d, "
+					"force non-interleaving!\n", ctrl_num);
 			}
 			break;
 		case FSL_DDR_CS2_CS3:
-			if (pdimm[1].n_ranks !=2){
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+			if (pdimm[0].n_ranks < 4) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for CS2+CS3 "
+					"on controller %d, force non-interleaving!\n", ctrl_num);
+			}
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if (pdimm[1].n_ranks < 2) {
 				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(CS) for CS2+CS3, "
-					"force non-interleaving!\n");
+				printf("Not enough bank(chip-select) for CS2+CS3 "
+					"on controller %d, force non-interleaving!\n", ctrl_num);
 			}
+#endif
 			break;
 		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-			if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+			if (pdimm[0].n_ranks < 4) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(CS) for CS0+CS1 and "
+					"CS2+CS3 on controller %d, "
+					"force non-interleaving!\n", ctrl_num);
+			}
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
 				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(CS) for CS0+CS1 or "
-					"CS2+CS3, force non-interleaving!\n");
+				printf("Not enough bank(CS) for CS0+CS1 and "
+					"CS2+CS3 on controller %d, "
+					"force non-interleaving!\n", ctrl_num);
 			}
+#endif
 			break;
 		default:
 			popts->ba_intlv_ctl = 0;
@@ -291,7 +342,48 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 		}
 	}
 
+	if (hwconfig_sub("fsl_ddr", "addr_hash")) {
+		if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null"))
+			popts->addr_hash = 0;
+		else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true"))
+			popts->addr_hash = 1;
+	}
+
+	if (pdimm[0].n_ranks == 4)
+		popts->quad_rank_present = 1;
+
 	fsl_ddr_board_options(popts, pdimm, ctrl_num);
 
 	return 0;
 }
+
+void check_interleaving_options(fsl_ddr_info_t *pinfo)
+{
+	int i, j, check_n_ranks, intlv_fixed = 0;
+	unsigned long long check_rank_density;
+	/*
+	 * Check if all controllers are configured for memory
+	 * controller interleaving. Identical dimms are recommended. At least
+	 * the size should be checked.
+	 */
+	j = 0;
+	check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
+	check_rank_density = pinfo->dimm_params[0][0].rank_density;
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		if ((pinfo->memctl_opts[i].memctl_interleaving) && \
+		    (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
+		    (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
+			j++;
+		}
+	}
+	if (j != CONFIG_NUM_DDR_CONTROLLERS) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+			if (pinfo->memctl_opts[i].memctl_interleaving) {
+				pinfo->memctl_opts[i].memctl_interleaving = 0;
+				intlv_fixed = 1;
+			}
+		if (intlv_fixed)
+			printf("Not all DIMMs are identical in size. "
+				"Memory controller interleaving disabled.\n");
+	}
+}
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index 55923e09b3..be8260277b 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -81,6 +81,9 @@ typedef struct dimm_params_s {
 	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
 	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
 	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
 } dimm_params_t;
 
 extern unsigned int ddr_compute_dimm_parameters(
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 02920dbfd7..d576eb85e3 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -119,6 +119,7 @@ typedef struct fsl_ddr_cfg_regs_s {
 	unsigned int ddr_sr_cntr;
 	unsigned int ddr_sdram_rcw_1;
 	unsigned int ddr_sdram_rcw_2;
+	unsigned int ddr_eor;
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
@@ -156,6 +157,7 @@ typedef struct memctl_options_s {
 	unsigned int memctl_interleaving;
 	unsigned int memctl_interleaving_mode;
 	unsigned int ba_intlv_ctl;
+	unsigned int addr_hash;
 
 	/* Operational mode parameters */
 	unsigned int ECC_mode;	 /* Use ECC? */
@@ -172,6 +174,7 @@ typedef struct memctl_options_s {
 	unsigned int OTF_burst_chop_en;
 	/* mirrior DIMMs for DDR3 */
 	unsigned int mirrored_dimm;
+	unsigned int quad_rank_present;
 
 	/* Global Timing Parameters */
 	unsigned int cas_latency_override;
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
new file mode 100644
index 0000000000..6c01ffc41b
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_fman.h
@@ -0,0 +1,212 @@
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_FMAN_H__
+#define __FSL_FMAN_H__
+
+#include <asm/types.h>
+
+typedef struct fm_bmi_common {
+	u32	fmbm_init;	/* BMI initialization */
+	u32	fmbm_cfg1;	/* BMI configuration1 */
+	u32	fmbm_cfg2;	/* BMI configuration2 */
+	u32	res0[0x5];
+	u32	fmbm_ievr;	/* interrupt event register */
+	u32	fmbm_ier;	/* interrupt enable register */
+	u32	fmbm_ifr;	/* interrupt force register */
+	u32	res1[0x5];
+	u32	fmbm_arb[0x8];	/* BMI arbitration */
+	u32	res2[0x28];
+	u32	fmbm_gde;	/* global debug enable */
+	u32	fmbm_pp[0x3f];	/* BMI port parameters */
+	u32	res3;
+	u32	fmbm_pfs[0x3f];	/* BMI port FIFO size */
+	u32	res4;
+	u32	fmbm_ppid[0x3f];/* port partition ID */
+} fm_bmi_common_t;
+
+typedef struct fm_qmi_common {
+	u32	fmqm_gc;	/* general configuration register */
+	u32	res0;
+	u32	fmqm_eie;	/* error interrupt event register */
+	u32	fmqm_eien;	/* error interrupt enable register */
+	u32	fmqm_eif;	/* error interrupt force register */
+	u32	fmqm_ie;	/* interrupt event register */
+	u32	fmqm_ien;	/* interrupt enable register */
+	u32	fmqm_if;	/* interrupt force register */
+	u32	fmqm_gs;	/* global status register */
+	u32	fmqm_ts;	/* task status register */
+	u32	fmqm_etfc;	/* enqueue total frame counter */
+	u32	fmqm_dtfc;	/* dequeue total frame counter */
+	u32	fmqm_dc0;	/* dequeue counter 0 */
+	u32	fmqm_dc1;	/* dequeue counter 1 */
+	u32	fmqm_dc2;	/* dequeue counter 2 */
+	u32	fmqm_dc3;	/* dequeue counter 3 */
+	u32	fmqm_dfnoc;	/* dequeue FQID not override counter */
+	u32	fmqm_dfcc;	/* dequeue FQID from context counter */
+	u32	fmqm_dffc;	/* dequeue FQID from FD counter */
+	u32	fmqm_dcc;	/* dequeue confirm counter */
+	u32	res1[0xc];
+	u32	fmqm_dtrc;	/* debug trap configuration register */
+	u32	fmqm_efddd;	/* enqueue frame descriptor dynamic debug */
+	u32	res3[0x2];
+	u32	res4[0xdc];	/* missing debug regs */
+} fm_qmi_common_t;
+
+typedef struct fm_bmi {
+	u8	res[1024];
+} fm_bmi_t;
+
+typedef struct fm_qmi {
+	u8	res[1024];
+} fm_qmi_t;
+
+typedef struct fm_parser {
+	u8	res[1024];
+} fm_parser_t;
+
+typedef struct fm_policer {
+	u8	res[4*1024];
+} fm_policer_t;
+
+typedef struct fm_keygen {
+	u8	res[4*1024];
+} fm_keygen_t;
+
+typedef struct fm_dma {
+	u32	fmdmsr;		/* status register */
+	u32	fmdmmr;		/* mode register */
+	u32	fmdmtr;		/* bus threshold register */
+	u32	fmdmhy;		/* bus hysteresis register */
+	u32	fmdmsetr;	/* SOS emergency threshold register */
+	u32	fmdmtah;	/* transfer bus address high register */
+	u32	fmdmtal;	/* transfer bus address low register */
+	u32	fmdmtcid;	/* transfer bus communication ID register */
+	u32	fmdmra;		/* DMA bus internal ram address register */
+	u32	fmdmrd;		/* DMA bus internal ram data register */
+	u32	res0[0xb];
+	u32	fmdmdcr;	/* debug counter */
+	u32	fmdmemsr;	/* emrgency smoother register */
+	u32	res1;
+	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
+	u32	res[0x3c8];
+} fm_dma_t;
+
+typedef struct fm_fpm {
+	u32	fpmtnc;		/* TNUM control */
+	u32	fpmprc;		/* Port_ID control */
+	u32	res0;
+	u32	fpmflc;		/* flush control */
+	u32	fpmdis1;	/* dispatch thresholds1 */
+	u32	fpmdis2;	/* dispatch thresholds2 */
+	u32	fmepi;		/* error pending interrupts */
+	u32	fmrie;		/* rams interrupt enable */
+	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
+	u32	res1[0x4];
+	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
+	u32	res2[0x4];
+	u32	fpmtsc1;	/* timestamp control1 */
+	u32	fpmtsc2;	/* timestamp control2 */
+	u32	fpmtsp;		/* time stamp */
+	u32	fpmtsf;		/* time stamp fraction */
+	u32	fpmrcr;		/* rams control and event */
+	u32	res3[0x3];
+	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
+	u32	res4[0xc];
+	u32	fpmdra;		/* data ram access */
+	u32	fm_ip_rev_1;	/* IP block revision 1 */
+	u32	fm_ip_rev_2;	/* IP block revision 2 */
+	u32	fmrstc;		/* reset command */
+	u32	fmcld;		/* classifier debug control */
+	u32	fmnpi;		/* normal pending interrupts */
+	u32	res5;
+	u32	fmnee;		/* event and enable */
+	u32	fpmcev[0x4];	/* CPU event 0-3 */
+	u32	res6[0x4];
+	u32	fmfp_ps[0x40];	/* port status */
+	u32	res7[0x260];
+	u32	fpmts[0x80];	/* task status */
+	u32	res8[0xa0];
+} fm_fpm_t;
+
+typedef struct fm_imem {
+	u8	res[4*1024];
+} fm_imem_t;
+
+typedef struct fm_soft_parser {
+	u8	res[4*1024];
+} fm_soft_parser_t;
+
+typedef struct fm_dtesc {
+	u8	res[4*1024];
+} fm_dtsec_t;
+
+typedef struct fm_mdio {
+	u8	res[4*1024];
+} fm_mdio_t;
+
+typedef struct fm_10gec {
+	u8	res[4*1024];
+} fm_10gec_t;
+
+typedef struct fm_10gec_mdio {
+	u8	res[4*1024];
+} fm_10gec_mdio_t;
+
+typedef struct fm_1588 {
+	u8	res[4*1024];
+} fm_1588_t;
+
+typedef struct ccsr_fman {
+	u8			muram[0x80000];
+	fm_bmi_common_t		fm_bmi_common;
+	fm_qmi_common_t		fm_qmi_common;
+	u8			res0[2048];
+	struct {
+		fm_bmi_t	fm_bmi;
+		fm_qmi_t	fm_qmi;
+		fm_parser_t	fm_parser;
+		u8		res[1024];
+	} port[63];
+	fm_policer_t		fm_policer;
+	fm_keygen_t		fm_keygen;
+	fm_dma_t		fm_dma;
+	fm_fpm_t		fm_fpm;
+	fm_imem_t		fm_imem;
+	u8			res1[8*1024];
+	fm_soft_parser_t	fm_soft_parser;
+	u8			res2[96*1024];
+	struct {
+		fm_dtsec_t	fm_dtesc;
+		fm_mdio_t	fm_mdio;
+	} mac[4];
+	u8			res3[32*1024];
+	fm_10gec_t		fm_10gec;
+	fm_10gec_mdio_t		fm_10gec_mdio;
+	u8			res4[48*1024];
+	fm_1588_t		fm_1588;
+	u8			res5[4*1024];
+} ccsr_fman_t;
+
+#endif /*__FSL_FMAN_H__*/
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 12ba1a6a04..0e255ffce8 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -54,6 +54,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_PCIE_1 = 0x00,
 	LAW_TRGT_IF_PCIE_2 = 0x01,
 	LAW_TRGT_IF_PCIE_3 = 0x02,
+	LAW_TRGT_IF_PCIE_4 = 0x03,
 	LAW_TRGT_IF_RIO_1 = 0x08,
 	LAW_TRGT_IF_RIO_2 = 0x09,
 
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
new file mode 100644
index 0000000000..acdc99aee5
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FSL_LIODN_H_
+#define _FSL_LIODN_H_
+
+#include <asm/types.h>
+
+struct liodn_id_table {
+	const char * compat;
+	u32 id[2];
+	u8 num_ids;
+	phys_addr_t compat_offset;
+	unsigned long reg_offset;
+};
+
+extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid);
+extern void set_liodns(void);
+extern void fdt_fixup_liodn(void *blob);
+
+#define SET_LIODN_BASE_1(idA) \
+	{ .id = { idA }, .num_ids = 1, }
+
+#define SET_LIODN_BASE_2(idA, idB) \
+	{ .id = { idA, idB }, .num_ids = 2 }
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA }, .num_ids = 1, \
+	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA, idB }, .num_ids = 2, \
+	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
+	SET_LIODN_ENTRY_1(compat, liodn, \
+		offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+		compatoff)
+
+#define SET_USB_LIODN(usbNum, compat, liodn) \
+	SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
+		CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+
+#define SET_SATA_LIODN(sataNum, liodn) \
+	SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
+		CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+
+#define SET_PCI_LIODN(pciNum, liodn) \
+	SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\
+		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
+/* reg nodes for DMA start @ 0x300 */
+#define SET_DMA_LIODN(dmaNum, liodn) \
+	SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
+		CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+
+#define SET_SDHC_LIODN(sdhcNum, liodn) \
+	SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
+		CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+
+#define SET_QMAN_LIODN(liodn) \
+	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
+		CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
+
+#define SET_BMAN_LIODN(liodn) \
+	SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
+		CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+
+#define SET_PME_LIODN(liodn) \
+	SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
+		CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+
+/* -1 from portID due to how immap has the registers */
+#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
+	CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
+	offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
+
+/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
+#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
+	SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \
+		FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \
+
+/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
+	SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \
+		FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
+
+#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\
+		offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum)
+
+/* This is a bit evil since we treat rtic param as both a string & hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+
+#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
+		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, 0)
+
+extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
+extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+extern int liodn_tbl_sz, sec_liodn_tbl_sz;
+extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
new file mode 100644
index 0000000000..cb32927a83
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FSL_PORTALS_H_
+#define _FSL_PORTALS_H_
+
+/* entries must be in order and contiguous */
+enum fsl_dpaa_dev {
+	FSL_HW_PORTAL_SEC,
+#ifdef CONFIG_SYS_DPAA_FMAN
+	FSL_HW_PORTAL_FMAN1,
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	FSL_HW_PORTAL_FMAN2,
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	FSL_HW_PORTAL_PME,
+#endif
+};
+
+struct qportal_info {
+	u16	dliodn;	/* DQRR LIODN */
+	u16	fliodn;	/* frame data LIODN */
+	u16	liodn_offset;
+	u8	sdest;
+};
+
+#define SET_QP_INFO(dqrr, fdata, off, dest) \
+	{ .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }
+
+extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
+			  u32 *liodns, int liodn_offset);
+extern void setup_portals(void);
+extern void fdt_fixup_qportals(void *blob);
+
+extern struct qportal_info qp_info[];
+extern void fdt_portal(void *blob, const char *compat, const char *container,
+			u64 addr, u32 size);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index c7877b91a1..85518eb6e7 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -32,8 +32,15 @@ enum srds_prtcl {
 	SATA2,
 	SRIO1,
 	SRIO2,
-	SGMII_FM1,
-	SGMII_FM2,
+	SGMII_FM1_DTSEC1,
+	SGMII_FM1_DTSEC2,
+	SGMII_FM1_DTSEC3,
+	SGMII_FM1_DTSEC4,
+	SGMII_FM1_DTSEC5,
+	SGMII_FM2_DTSEC1,
+	SGMII_FM2_DTSEC2,
+	SGMII_FM2_DTSEC3,
+	SGMII_FM2_DTSEC4,
 	SGMII_TSEC1,
 	SGMII_TSEC2,
 	SGMII_TSEC3,
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b1d219b7aa..c1382c8c5e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -32,6 +32,7 @@
 #include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 #include <asm/fsl_lbc.h>
+#include <asm/fsl_fman.h>
 
 typedef struct ccsr_local {
 	u32	ccsrbarh;	/* CCSR Base Addr High */
@@ -172,7 +173,17 @@ typedef struct ccsr_ddr {
 	u32	ddr_sr_cntr;		/* self refresh counter */
 	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
 	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
-	u8	res8_1b[2456];
+	u8	reg_1ab[8];
+	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
+	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
+	u8	res8_1b[104];
+	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
+	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
+	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
+	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
+	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
+	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
+	u8	res8_1ba[0x908];
 	u32	ddr_dsr1;		/* Debug Status 1 */
 	u32	ddr_dsr2;		/* Debug Status 2 */
 	u32	ddr_cdr1;		/* Control Driver 1 */
@@ -180,7 +191,21 @@ typedef struct ccsr_ddr {
 	u8	res8_1c[200];
 	u32	ip_rev1;		/* IP Block Revision 1 */
 	u32	ip_rev2;		/* IP Block Revision 2 */
-	u8	res8_2[512];
+	u32	eor;			/* Enhanced Optimization Register */
+	u8	res8_2[252];
+	u32	mtcr;			/* Memory Test Control Register */
+	u8	res8_3[28];
+	u32	mtp1;			/* Memory Test Pattern 1 */
+	u32	mtp2;			/* Memory Test Pattern 2 */
+	u32	mtp3;			/* Memory Test Pattern 3 */
+	u32	mtp4;			/* Memory Test Pattern 4 */
+	u32	mtp5;			/* Memory Test Pattern 5 */
+	u32	mtp6;			/* Memory Test Pattern 6 */
+	u32	mtp7;			/* Memory Test Pattern 7 */
+	u32	mtp8;			/* Memory Test Pattern 8 */
+	u32	mtp9;			/* Memory Test Pattern 9 */
+	u32	mtp10;			/* Memory Test Pattern 10 */
+	u8	res8_4[184];
 	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
 	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
 	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
@@ -218,6 +243,9 @@ typedef struct ccsr_ddr {
 	u8	res12[184];
 } ccsr_ddr_t;
 
+#define DDR_EOR_RD_BDW_OPT_DIS	0x80000000 /* Read BDW Opt. disable */
+#define DDR_EOR_ADDR_HASH_EN	0x40000000 /* Address hash enabled */
+
 /* I2C Registers */
 typedef struct ccsr_i2c {
 	struct fsl_i2c	i2c[1];
@@ -732,6 +760,8 @@ typedef struct ccsr_pic {
 	u32	eoi;		/* End Of IRQ */
 	u8	res9[3916];
 	u32	frr;		/* Feature Reporting */
+#define MPC85xx_PICFRR_NCPU_MASK	0x00001f00
+#define MPC85xx_PICFRR_NCPU_SHIFT	8
 	u8	res10[28];
 	u32	gcr;		/* Global Configuration */
 #define MPC85xx_PICGCR_RST	0x80000000
@@ -1609,6 +1639,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR_PCIE1	0x80000000
 #define FSL_CORENET_DEVDISR_PCIE2	0x40000000
 #define FSL_CORENET_DEVDISR_PCIE3	0x20000000
+#define FSL_CORENET_DEVDISR_PCIE4	0x10000000
 #define FSL_CORENET_DEVDISR_RMU		0x08000000
 #define FSL_CORENET_DEVDISR_SRIO1	0x04000000
 #define FSL_CORENET_DEVDISR_SRIO2	0x02000000
@@ -1618,6 +1649,8 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR_DDR2	0x00080000
 #define FSL_CORENET_DEVDISR_DBG		0x00010000
 #define FSL_CORENET_DEVDISR_NAL		0x00008000
+#define FSL_CORENET_DEVDISR_SATA1	0x00004000
+#define FSL_CORENET_DEVDISR_SATA2	0x00002000
 #define FSL_CORENET_DEVDISR_ELBC	0x00001000
 #define FSL_CORENET_DEVDISR_USB1	0x00000800
 #define FSL_CORENET_DEVDISR_USB2	0x00000400
@@ -1638,12 +1671,14 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC1_2	0x00400000
 #define FSL_CORENET_DEVDISR2_DTSEC1_3	0x00200000
 #define FSL_CORENET_DEVDISR2_DTSEC1_4	0x00100000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5	0x00080000
 #define FSL_CORENET_DEVDISR2_FM2	0x00020000
 #define FSL_CORENET_DEVDISR2_10GEC2	0x00010000
 #define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00008000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00002000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
+#define FSL_CORENET_NUM_DEVDISR		2
 	u8	res7[8];
 	u32	powmgtcsr;	/* Power management status & control */
 	u8	res8[12];
@@ -1672,9 +1707,18 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
 #define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
+#define FSL_CORENET_RCWSR11_EC1			0x00c00000 /* bits 360..361 */
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1	0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_USB1	0x00800000
+#define FSL_CORENET_RCWSR11_EC2			0x001c0000 /* bits 363..365 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1	0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2	0x00080000
+#define FSL_CORENET_RCWSR11_EC2_USB2		0x00100000
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
@@ -1698,10 +1742,15 @@ typedef struct ccsr_gur {
 	u32	sdmmc2liodnr;	/* SD/MMC 2 LIODN */
 	u32	sdmmc3liodnr;	/* SD/MMC 3 LIODN */
 	u32	sdmmc4liodnr;	/* SD/MMC 4 LIODN */
-	u32	rmuliodnr;	/* RIO Message Unit LIODN */
-	u32	rduliodnr;	/* RIO Doorbell Unit LIODN */
-	u32	rpwuliodnr;	/* RIO Port Write Unit LIODN */
-	u8	res22[52];
+	u32	rio1maintliodnr;/* RIO 1 Maintenance LIODN */
+	u32	rio2maintliodnr;/* RIO 2 Maintenance LIODN */
+	u32	rio3maintliodnr;/* RIO 3 Maintenance LIODN */
+	u32	rio4maintliodnr;/* RIO 4 Maintenance LIODN */
+	u32	sata1liodnr;	/* SATA 1 LIODN */
+	u32	sata2liodnr;	/* SATA 2 LIODN */
+	u32	sata3liodnr;	/* SATA 3 LIODN */
+	u32	sata4liodnr;	/* SATA 4 LIODN */
+	u8	res22[32];
 	u32	dma1liodnr;	/* DMA 1 LIODN */
 	u32	dma2liodnr;	/* DMA 2 LIODN */
 	u32	dma3liodnr;	/* DMA 3 LIODN */
@@ -1736,6 +1785,12 @@ typedef struct ccsr_gur {
 	u8	res37[380];
 } ccsr_gur_t;
 
+/*
+ * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
+ * everything after has RMan thus msg unit LIODN is used for maintenance
+ */
+#define rmuliodnr rio1maintliodnr
+
 typedef struct ccsr_clk {
 	u32	clkc0csr;	/* Core 0 Clock control/status */
 	u8	res1[0x1c];
@@ -2004,38 +2059,125 @@ enum {
 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 typedef struct ccsr_sec {
-	u8	res1[0xfa0];
+	u32	res0;
+	u32	mcfgr;		/* Master CFG Register */
+	u8	res1[0x8];
+	struct {
+		u32	ms;	/* Job Ring LIODN Register, MS */
+		u32	ls;	/* Job Ring LIODN Register, LS */
+	} jqliodnr[4];
+	u8	res2[0x30];
+	struct {
+		u32	ms;	/* RTIC LIODN Register, MS */
+		u32	ls;	/* RTIC LIODN Register, LS */
+	} rticliodnr[4];
+	u8	res3[0x1c];
+	u32	decorr;		/* DECO Request Register */
+	struct {
+		u32	ms;	/* DECO LIODN Register, MS */
+		u32	ls;	/* DECO LIODN Register, LS */
+	} decoliodnr[5];
+	u8	res4[0x58];
+	u32	dar;		/* DECO Avail Register */
+	u32	drr;		/* DECO Reset Register */
+	u8	res5[0xe78];
 	u32	crnr_ms;	/* CHA Revision Number Register, MS */
 	u32	crnr_ls;	/* CHA Revision Number Register, LS */
 	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
-#define SEC_CTPR_MS_AXI_LIODN		0x08000000
-#define SEC_CTPR_MS_QI			0x02000000
 	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
-	u8	res2[0x10];
+	u8	res6[0x10];
 	u32	far_ms;		/* Fault Address Register, MS */
 	u32	far_ls;		/* Fault Address Register, LS */
 	u32	falr;		/* Fault Address LIODN Register */
 	u32	fadr;		/* Fault Address Detail Register */
-	u8	res3[0x4];
+	u8	res7[0x4];
 	u32	csta;		/* CAAM Status Register */
-	u8	res4[0x8];
+	u8	res8[0x8];
 	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
-#define SEC_RVID_MA			0x0f000000
 	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
 	u32	chavid_ms;	/* CHA Version ID Register, MS */
 	u32	chavid_ls;	/* CHA Version ID Register, LS */
 	u32	chanum_ms;	/* CHA Number Register, MS */
+	u32	chanum_ls;	/* CHA Number Register, LS */
+	u32	secvid_ms;	/* SEC Version ID Register, MS */
+	u32	secvid_ls;	/* SEC Version ID Register, LS */
+	u8	res9[0x6020];
+	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
+	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
+	u8	res10[0x8fd8];
+} ccsr_sec_t;
+
+#define SEC_CTPR_MS_AXI_LIODN		0x08000000
+#define SEC_CTPR_MS_QI			0x02000000
+#define SEC_RVID_MA			0x0f000000
 #define SEC_CHANUM_MS_JQNUM_MASK	0xf0000000
 #define SEC_CHANUM_MS_JQNUM_SHIFT	28
 #define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
 #define SEC_CHANUM_MS_DECONUM_SHIFT	24
-	u32	chanum_ls;	/* CHA Number Register, LS */
-	u32	caamvid_ms;	/* CAAM Version ID Register, MS */
-	u32	caamvid_ls;	/* CAAM Version ID Register, LS */
-	u8	res5[0xf000];
-} ccsr_sec_t;
 #endif
 
+typedef struct ccsr_qman {
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
+	} qcsp[32];
+
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8 - 0x200];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fqd_bare;	/* FQD Extended Base Addr Register */
+	u32	fqd_bar;	/* FQD Base Addr Register */
+	u8	res1[0x8];
+	u32	fqd_ar;		/* FQD Attributes Register */
+	u8	res2[0xc];
+	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
+	u32	pfdr_bar;	/* PFDR Base Addr Register */
+	u8	res3[0x8];
+	u32	pfdr_ar;	/* PFDR Attributes Register */
+	u8	res4[0x4c];
+	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
+	u32	qcsp_bar;	/* QCSP Base Addr Register */
+	u8	res5[0x78];
+	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res6[4];
+	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
+	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
+	u8	res7[0x2e8];
+} ccsr_qman_t;
+
+typedef struct ccsr_bman {
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
+	u32	fbpr_bar;	/* FBPR Base Addr Register */
+	u8	res1[0x8];
+	u32	fbpr_ar;	/* FBPR Attributes Register */
+	u8	res2[0xf0];
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res7[0x2f4];
+} ccsr_bman_t;
+
+typedef struct ccsr_pme {
+	u8	res0[0x804];
+	u32	liodnbr;	/* LIODN Base Register */
+	u8	res1[0x1f8];
+	u32	srcidr;		/* Source ID Register */
+	u8	res2[8];
+	u32	liodnr;		/* LIODN Register */
+	u8	res3[0x1e8];
+	u32	pm_ip_rev_1;	/* PME IP Block Revision Reg 1*/
+	u32	pm_ip_rev_2;	/* PME IP Block Revision Reg 1*/
+	u8	res4[0x400];
+} ccsr_pme_t;
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000
@@ -2044,16 +2186,41 @@ typedef struct ccsr_sec {
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x100000
+#define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
+#define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET		0x210000
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
+#define CONFIG_SYS_MPC85xx_USB_OFFSET		CONFIG_SYS_MPC85xx_USB1_OFFSET
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
+#define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET	0x318000
 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET	0x31a000
-#define CONFIG_SYS_TSEC1_OFFSET			0x4e0000 /* FM1@DTSEC0 */
+#define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
+#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
+#define CONFIG_SYS_FSL_FM2_OFFSET		0x500000
+#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
+#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET	0x589000
+#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
+#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
+#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
+#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x2000
@@ -2098,6 +2265,8 @@ typedef struct ccsr_sec {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
@@ -2146,6 +2315,12 @@ typedef struct ccsr_sec {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_FM1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CONFIG_SYS_FSL_FM2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
@@ -2157,6 +2332,8 @@ typedef struct ccsr_sec {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
 #define CONFIG_SYS_PCIE3_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+#define CONFIG_SYS_PCIE4_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
 
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 89f283a6c5..84a1e2ec0d 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -495,6 +495,7 @@
 #define   L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
 #define SPRN_L1CSR2	0x25e	/* L1 Data Cache Control and Status Register 2 */
+#define   L1CSR2_DCWS		0x40000000	/* Data Cache Write Shadow */
 #define SPRN_L2CSR0	0x3f9	/* L2 Data Cache Control and Status Register 0 */
 #define   L2CSR0_L2E		0x80000000	/* L2 Cache Enable */
 #define   L2CSR0_L2PE		0x40000000	/* L2 Cache Parity/ECC Enable */
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 2d48d7ea32..f93045ff98 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -46,6 +46,7 @@ COBJS-$(CONFIG_MPC8536DS)	+= ics307_clk.o
 COBJS-$(CONFIG_MPC8572DS)	+= ics307_clk.o
 COBJS-$(CONFIG_P1022DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
+COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
new file mode 100644
index 0000000000..8aa725523a
--- /dev/null
+++ b/board/freescale/corenet_ds/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-$(CONFIG_DDR_SPD)	+= ddr.o
+COBJS-$(CONFIG_PCI)	+= pci.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk
new file mode 100644
index 0000000000..72db24ebd2
--- /dev/null
+++ b/board/freescale/corenet_ds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# P4080DS board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+RESET_VECTOR_ADDRESS = 0xeffffffc
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
new file mode 100644
index 0000000000..3cdefb34ef
--- /dev/null
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+extern void pci_of_setup(void *blob, bd_t *bd);
+
+#include "../common/ngpixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+int checkboard (void)
+{
+	u8 sw;
+	struct cpu_type *cpu = gd->cpu;
+
+	printf("Board: %sDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+	sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
+
+#ifdef CONFIG_PHYS_64BIT
+	puts("36-bit Addressing\n");
+#endif
+
+	/* Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+	sw = in_8(&PIXIS_SW(3));
+	printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
+	printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
+	printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/*
+	 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
+	 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
+	 * the noise introduced by these unterminated and unused clock pairs.
+	 */
+	setbits_be32(&gur->ddrclkdr, 0x001B001B);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
+
+	set_liodns();
+	setup_portals();
+
+#ifdef CONFIG_SRIO1
+	if (is_serdes_configured(SRIO1)) {
+		set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
+				LAW_TRGT_IF_RIO_1);
+	} else {
+		printf ("    SRIO1: disabled\n");
+	}
+#else
+	setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
+#endif
+
+#ifdef CONFIG_SRIO2
+	if (is_serdes_configured(SRIO2)) {
+		set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
+				LAW_TRGT_IF_RIO_2);
+	} else {
+		printf ("    SRIO2: disabled\n");
+	}
+#else
+	setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
+#endif
+
+	return 0;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch(clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	default:
+		return "???";
+	}
+}
+
+#define NUM_SRDS_BANKS	3
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS];
+	unsigned int i;
+	u8 sw3;
+
+	/* Warn if the expected SERDES reference clocks don't match the
+	 * actual reference clocks.  This needs to be done after calling
+	 * p4080_erratum_serdes8(), since that function may modify the clocks.
+	 */
+	sw3 = in_8(&PIXIS_SW(3));
+	actual[0] = (sw3 & 0x40) ?
+		SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
+	actual[1] = (sw3 & 0x20) ?
+		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+	actual[2] = (sw3 & 0x10) ?
+		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES bank %u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	setup_ddr_tlbs(dram_size / 0x100000);
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
+
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+	if (!is_serdes_configured(SRIO1)) {
+		fdt_del_node_and_alias(blob, "rio0");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+	if (!is_serdes_configured(SRIO2)) {
+		fdt_del_node_and_alias(blob, "rio1");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	ft_srio_setup(blob);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
new file mode 100644
index 0000000000..82b2b4f550
--- /dev/null
+++ b/board/freescale/corenet_ds/ddr.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	int ret;
+
+	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+	if (ret) {
+		debug("DDR: failed to read SPD from address %u\n", i2c_address);
+		memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		else if (ctrl_num == 1 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS2;
+
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
+ *      seem reliable, but errors will appear when memory intensive
+ *      program is run. */
+/* XXX: Single rank at 800 MHz is OK.  */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+	/* 	memory controller 0 			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+		{  0, 333,    2,    6,   7,    3,  0},
+		{334, 400,    2,    6,   9,    3,  0},
+		{401, 549,    2,    6,  11,    3,  0},
+		{550, 680,    2,    1,  10,    5,  0},
+		{681, 850,    2,    1,  12,    5,  0},
+		{851, 1050,   2,    1,  12,    5,  0},
+		{1051, 1250,  2,    1,  15,    4,  0},
+		{1251, 1350,  2,    1,  15,    4,  0},
+		{  0, 333,    1,    6,   7,    3,  0},
+		{334, 400,    1,    6,   9,    3,  0},
+		{401, 549,    1,    6,  11,    3,  0},
+		{550, 680,    1,    1,  10,    5,  0},
+		{681, 850,    1,    1,  12,    5,  0}
+	},
+
+	{
+	/*	memory controller 1			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+		{  0, 333,    2,     6,  7,    3,  0},
+		{334, 400,    2,     6,  9,    3,  0},
+		{401, 549,    2,     6, 11,    3,  0},
+		{550, 680,    2,     1, 11,    6,  0},
+		{681, 850,    2,     1, 13,    6,  0},
+		{851, 1050,   2,     1, 13,    6,  0},
+		{1051, 1250,  2,     1, 15,    4,  0},
+		{1251, 1350,  2,     1, 15,    4,  0},
+		{  0, 333,    1,     6,  7,    3,  0},
+		{334, 400,    1,     6,  9,    3,  0},
+		{401, 549,    1,     6, 11,    3,  0},
+		{550, 680,    1,     1, 11,    6,  0},
+		{681, 850,    1,     1, 13,    6,  0}
+	}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 1;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 1;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+			popts->cs_local_opts[i].odt_rd_cfg = 3;
+			popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high &&
+		    pdimm->n_ranks == pbsp->n_ranks) {
+			popts->cpo_override = 0xff; /* force auto CPO calibration */
+			popts->write_data_delay = 2;
+			popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */
+			popts->twoT_en = pbsp->force_2T;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xa;
+	popts->wrlvl_start = 0x7;
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = DDR3_RTT_120_OHM;
+	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+}
diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c
new file mode 100644
index 0000000000..43b4b97de1
--- /dev/null
+++ b/board/freescale/corenet_ds/law.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c
new file mode 100644
index 0000000000..2994e366c2
--- /dev/null
+++ b/board/freescale/corenet_ds/pci.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+void pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info[3];
+	u32 devdisr;
+	int first_free_busno = 0;
+	int num = 0;
+
+	int pcie_ep, pcie_configured;
+
+	devdisr = in_be32(&gur->devdisr);
+
+	debug ("   pci_init_board: devdisr=%x\n", devdisr);
+
+#ifdef CONFIG_PCIE1
+	pcie_configured = is_serdes_configured(PCIE1);
+
+	if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
+		set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
+				LAW_TRGT_IF_PCIE_1);
+		set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_1);
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+		printf("    PCIE1 connected to Slot 1 as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+				&pcie1_hose, first_free_busno);
+	} else {
+		printf ("    PCIE1: disabled\n");
+	}
+#else
+	setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+	pcie_configured = is_serdes_configured(PCIE2);
+
+	if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
+		set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
+				LAW_TRGT_IF_PCIE_2);
+		set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_2);
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+		printf("    PCIE2 connected to Slot 3 as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+				&pcie2_hose, first_free_busno);
+	} else {
+		printf ("    PCIE2: disabled\n");
+	}
+#else
+	setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+	pcie_configured = is_serdes_configured(PCIE3);
+
+	if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
+		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
+				LAW_TRGT_IF_PCIE_3);
+		set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_3);
+		SET_STD_PCIE_INFO(pci_info[num], 3);
+		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+		printf("    PCIE3 connected to Slot 2 as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+				&pcie3_hose, first_free_busno);
+	} else {
+		printf ("    PCIE3: disabled\n");
+	}
+#else
+	setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
+#endif
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
new file mode 100644
index 0000000000..1ae0416248
--- /dev/null
+++ b/board/freescale/corenet_ds/tlb.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_1M, 1),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index d86ca12aaf..fee310a67f 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -60,6 +60,8 @@ int checkboard(void)
 	return 0;
 }
 
+const char *board_hwconfig = "foo:bar=baz";
+const char *cpu_hwconfig = "foo:bar=baz";
 
 phys_size_t
 initdram(int board_type)
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index b9c0cb2576..30d640fa31 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -12,7 +12,7 @@
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 
-static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
 {
 	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
 }
@@ -22,7 +22,7 @@ unsigned int fsl_ddr_get_mem_data_rate(void)
 	return get_ddr_freq(0);
 }
 
-void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 		      unsigned int ctrl_num)
 {
 	unsigned int i;
@@ -51,27 +51,26 @@ typedef struct {
  *  cpo 2-0x1E (30)
  */
 
-
-/* XXX: these values need to be checked for all interleaving modes.  */
-/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
- *      seem reliable, but errors will appear when memory intensive
- *      program is run. */
-/* XXX: Single rank at 800 MHz is OK.  */
 const board_specific_parameters_t board_specific_parameters[][20] = {
 	{
 	/* 	memory controller 0 			*/
 	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
 	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
-		{  0, 333,    2,    6,   7,    3,  0},
-		{334, 400,    2,    6,   9,    3,  0},
-		{401, 549,    2,    6,  11,    3,  0},
-		{550, 680,    2,    1,  10,    5,  0},
-		{681, 850,    2,    1,  12,    5,  1},
-		{  0, 333,    1,    6,   7,    3,  0},
-		{334, 400,    1,    6,   9,    3,  0},
-		{401, 549,    1,    6,  11,    3,  0},
-		{550, 680,    1,    1,  10,    5,  0},
-		{681, 850,    1,    1,  12,    5,  0}
+#ifdef CONFIG_FSL_DDR2
+		{  0, 333,    2,    4,   0x1f,    2,  0},
+		{334, 400,    2,    4,   0x1f,    2,  0},
+		{401, 549,    2,    4,   0x1f,    2,  0},
+		{550, 680,    2,    4,   0x1f,    3,  0},
+		{681, 850,    2,    4,   0x1f,    4,  0},
+		{  0, 333,    1,    4,   0x1f,    2,  0},
+		{334, 400,    1,    4,   0x1f,    2,  0},
+		{401, 549,    1,    4,   0x1f,    2,  0},
+		{550, 680,    1,    4,   0x1f,    3,  0},
+		{681, 850,    1,    4,   0x1f,    4,  0}
+#else
+		{  0, 850,    2,    4,   0x1f,    4,  0},
+		{  0, 850,    1,    4,   0x1f,    4,  0}
+#endif
 	},
 };
 
@@ -92,18 +91,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
 	 */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i&1) {	/* odd CS */
 			popts->cs_local_opts[i].odt_rd_cfg = 0;
-			popts->cs_local_opts[i].odt_wr_cfg = 0;
-		} else {	/* even CS */
-			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-				popts->cs_local_opts[i].odt_rd_cfg = 0;
-				popts->cs_local_opts[i].odt_wr_cfg = 4;
-			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-				popts->cs_local_opts[i].odt_rd_cfg = 3;
-				popts->cs_local_opts[i].odt_wr_cfg = 3;
-			}
-		}
+			popts->cs_local_opts[i].odt_wr_cfg = 1;
 	}
 
 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
@@ -127,4 +116,13 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 *	- number of DIMMs installed
 	 */
 	popts->half_strength_driver_enable = 0;
+	popts->wrlvl_en = 1;
+	/* Write leveling override */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xa;
+	popts->wrlvl_start = 0x7;
+	/* Rtt and Rtt_WR override */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = DDR3_RTT_120_OHM;
+	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
 }
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 3fd1b347ab..608ff916da 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -69,13 +69,16 @@ int checkboard(void)
 	return 0;
 }
 
+const char *board_hwconfig = "foo:bar=baz";
+const char *cpu_hwconfig = "foo:bar=baz";
+
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size = 0;
 
 	puts("Initializing....");
 
-#ifdef CONFIG_SPD_EEPROM
+#ifdef CONFIG_DDR_SPD
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
@@ -94,7 +97,7 @@ phys_size_t initdram(int board_type)
 	return dram_size;
 }
 
-#if !defined(CONFIG_SPD_EEPROM)
+#if !defined(CONFIG_DDR_SPD)
 /*
  * Fixed sdram init -- doesn't use serial presence detect.
  */
diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
index 36ad086d08..824b3b29f0 100644
--- a/board/freescale/p2020ds/tlb.c
+++ b/board/freescale/p2020ds/tlb.c
@@ -28,19 +28,19 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
diff --git a/boards.cfg b/boards.cfg
index b82f530f46..a70f541bd4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -343,6 +343,7 @@ MPC8540ADS	powerpc	mpc85xx		mpc8540ads	freescale
 MPC8544DS	powerpc	mpc85xx		mpc8544ds	freescale
 MPC8560ADS	powerpc	mpc85xx		mpc8560ads	freescale
 MPC8568MDS	powerpc	mpc85xx		mpc8568mds	freescale
+P4080DS		powerpc	mpc85xx		corenet_ds	freescale
 XPEDITE5200	powerpc	mpc85xx		xpedite5200	xes
 XPEDITE5370	powerpc	mpc85xx		xpedite5370	xes
 P1022DS		powerpc	mpc85xx		p1022ds		freescale
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 718b635d99..166f5e145d 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1151,4 +1151,22 @@ int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
 	return -FDT_ERR_NOTFOUND;
 }
 
+/**
+ * fdt_alloc_phandle: Return next free phandle value
+ *
+ * @blob: ptr to device tree
+ */
+int fdt_alloc_phandle(void *blob)
+{
+	int offset, len, phandle = 0;
+	const u32 *val;
+
+	for (offset = fdt_next_node(blob, -1, NULL); offset >= 0;
+	     offset = fdt_next_node(blob, offset, NULL)) {
+		val = fdt_getprop(blob, offset, "linux,phandle", &len);
+		if (val)
+			phandle = max(*val, phandle);
+	}
 
+	return phandle + 1;
+}
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 9c2224fea1..e108a0d50c 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -27,43 +27,60 @@ Table of interleaving modes supported in cpu/8xxx/ddr/
  from each controller. {CS2+CS3} on each controller are only rank
  interleaved on that controller.
 
+ For memory controller interleaving, identical DIMMs are suggested. Software
+ doesn't check the size or organization of interleaved DIMMs.
+
 The ways to configure the ddr interleaving mode
 ==============================================
 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
    under "CONFIG_EXTRA_ENV_SETTINGS", like:
 	#define CONFIG_EXTRA_ENV_SETTINGS				\
-	 "memctl_intlv_ctl=2\0"						\
+	 "hwconfig=fsl_ddr:ctlr_intlv=bank"			\
 	 ......
 
 2. Run u-boot "setenv" command to configure the memory interleaving mode.
    Either numerical or string value is accepted.
 
   # disable memory controller interleaving
-  setenv memctl_intlv_ctl
+  setenv hwconfig "fsl_ddr:ctlr_intlv=null"
 
   # cacheline interleaving
-  setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline
+  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
 
   # page interleaving
-  setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page
+  setenv hwconfig "fsl_ddr:ctlr_intlv=page"
 
   # bank interleaving
-  setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank
+  setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
 
   # superbank
-  setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank
+  setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
 
   # disable bank (chip-select) interleaving
-  setenv ba_intlv_ctl
+  setenv hwconfig "fsl_ddr:bank_intlv=null"
 
   # bank(chip-select) interleaving cs0+cs1
-  setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1
+  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
 
   # bank(chip-select) interleaving cs2+cs3
-  setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3
+  setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
 
   # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
-  setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3
+  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
 
   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
-  setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3
+  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
+
+Memory controller address hashing
+==================================
+If the DDR controller supports address hashing, it can be enabled by hwconfig.
+
+Syntax is:
+hwconfig=fsl_ddr:addr_hash=true
+
+Combination of hwconfig
+=======================
+Hwconfig can be combined with multiple parameters, for example, on a supported
+platform
+
+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 890a6c9bc4..2a3c058619 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -687,6 +687,7 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 78bb74bdc1..577c276107 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -398,7 +398,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index ae4fba8014..8797b3099d 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -416,7 +416,8 @@ extern unsigned long get_clock_freq(void);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 96fd0241ca..d1ac32f4ad 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -431,7 +431,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 23594a74cb..33f49f5f08 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -471,7 +471,8 @@ extern unsigned long get_clock_freq(void);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 5011e5a8bf..0f71f11c65 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -414,7 +414,8 @@ extern unsigned long get_clock_freq(void);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 98677e5f1b..31740fdb25 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -438,7 +438,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index bc6c5c7b46..ea7a134b8d 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -431,7 +431,8 @@ extern unsigned long get_clock_freq(void);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 92c2b49c1f..f69b650185 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -560,8 +560,9 @@ extern unsigned long get_clock_freq(void);
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 51e5d06db9..081661e6b3 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -581,7 +581,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 0d1f7799cf..974cb6ba7d 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -122,6 +122,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
 #endif
 
+#define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
+
 /*
  * DDR Setup
  */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index f9d12f55f9..dcaca2b617 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -366,6 +366,7 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index fca3cddf11..7e901e17cc 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -518,6 +518,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index bf2acbf4c4..79ce2c0a8b 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -92,7 +92,11 @@
 
 /* DDR Setup */
 #define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_MK_DDR2
+#define CONFIG_FSL_DDR2
+#else
 #define CONFIG_FSL_DDR3		1
+#endif
 #undef CONFIG_FSL_DDR_INTERACTIVE
 
 /* ECC will be enabled based on perf_mode environment variable */
@@ -109,6 +113,7 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
 /* I2C addresses of SPD EEPROMs */
+#define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD EEPROM located on I2C bus 0 */
 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
 
@@ -228,6 +233,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 
+#define CONFIG_HWCONFIG			/* enable hwconfig */
 #define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
 
 #ifdef CONFIG_FSL_NGPIXIS
@@ -249,6 +255,18 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
 
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
@@ -567,7 +585,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
new file mode 100644
index 0000000000..87703c98b3
--- /dev/null
+++ b/include/configs/P4080DS.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P4080 DS board configuration file
+ */
+#define CONFIG_P4080DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P4080
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM2_DTSEC	4
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+
+#define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_P4080_ERRATUM_SERDES8
+
+#include "corenet_ds.h"
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index d8f2602e59..abbaf383c7 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -280,6 +280,7 @@
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support */
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 83aeffd29f..1fbe4fbab4 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -351,6 +351,7 @@
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index fc4a986039..8225ffff55 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -409,6 +409,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
new file mode 100644
index 0000000000..dd609da8f0
--- /dev/null
+++ b/include/configs/corenet_ds.h
@@ -0,0 +1,653 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_MP			/* support multiple processors */
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+#define CONFIG_SYS_HAS_SERDES		/* has SERDES */
+
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+//#define	CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xfe000000	/* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS		0xffe000000ull	/* physical addr of CCSRBAR */
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#endif
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+
+#ifdef CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM	1
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#else
+#define CONFIG_SYS_SDRAM_SIZE		4096
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_TIMING_3		0x01031000
+#define CONFIG_SYS_DDR_TIMING_0		0x55440804
+#define CONFIG_SYS_DDR_TIMING_1		0x74713a66
+#define CONFIG_SYS_DDR_TIMING_2		0x0fb8911b
+#define CONFIG_SYS_DDR_MODE_1		0x00421850
+#define CONFIG_SYS_DDR_MODE_2		0x00100000
+#define CONFIG_SYS_DDR_MODE_CTRL	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x10400100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03401500
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8655a608
+#define CONFIG_SYS_DDR_CONTROL		0xc7048000
+#define CONFIG_SYS_DDR_CONTROL2		0x24400011
+#define CONFIG_SYS_DDR_CDR1		0x00000000
+#define CONFIG_SYS_DDR_CDR2		0x00000000
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
+#define CONFIG_SYS_DDR_DEBUG_18		0x40100400
+
+#define CONFIG_SYS_DDR2_CS0_BNDS	0x008000bf
+#define CONFIG_SYS_DDR2_CS1_BNDS	0x00C000ff
+#define CONFIG_SYS_DDR2_CS0_CONFIG	CONFIG_SYS_DDR_CS0_CONFIG
+#define CONFIG_SYS_DDR2_CS1_CONFIG	CONFIG_SYS_DDR_CS1_CONFIG
+#define CONFIG_SYS_DDR2_TIMING_3	CONFIG_SYS_DDR_TIMING_3
+#define CONFIG_SYS_DDR2_TIMING_0	CONFIG_SYS_DDR_TIMING_0
+#define CONFIG_SYS_DDR2_TIMING_1	CONFIG_SYS_DDR_TIMING_1
+#define CONFIG_SYS_DDR2_TIMING_2	CONFIG_SYS_DDR_TIMING_2
+#define CONFIG_SYS_DDR2_MODE_1		CONFIG_SYS_DDR_MODE_1
+#define CONFIG_SYS_DDR2_MODE_2		CONFIG_SYS_DDR_MODE_2
+#define CONFIG_SYS_DDR2_MODE_CTRL	CONFIG_SYS_DDR_MODE_CTRL
+#define CONFIG_SYS_DDR2_INTERVAL	CONFIG_SYS_DDR_INTERVAL
+#define CONFIG_SYS_DDR2_DATA_INIT	CONFIG_SYS_DDR_DATA_INIT
+#define CONFIG_SYS_DDR2_CLK_CTRL	CONFIG_SYS_DDR_CLK_CTRL
+#define CONFIG_SYS_DDR2_TIMING_4	CONFIG_SYS_DDR_TIMING_4
+#define CONFIG_SYS_DDR2_TIMING_5	CONFIG_SYS_DDR_TIMING_5
+#define CONFIG_SYS_DDR2_ZQ_CNTL		CONFIG_SYS_DDR_ZQ_CNTL
+#define CONFIG_SYS_DDR2_WRLVL_CNTL	CONFIG_SYS_DDR_WRLVL_CNTL
+#define CONFIG_SYS_DDR2_CONTROL		CONFIG_SYS_DDR_CONTROL
+#define CONFIG_SYS_DDR2_CONTROL2	CONFIG_SYS_DDR_CONTROL2
+#define CONFIG_SYS_DDR2_CDR1		CONFIG_SYS_DDR_CDR1
+#define CONFIG_SYS_DDR2_CDR2		CONFIG_SYS_DDR_CDR2
+#define CONFIG_SYS_DDR2_ERR_INT_EN	CONFIG_SYS_DDR_ERR_INT_EN
+#define CONFIG_SYS_DDR2_ERR_DIS		CONFIG_SYS_DDR_ERR_DIS
+#define CONFIG_SYS_DDR2_SBE		CONFIG_SYS_DDR_SBE
+#define CONFIG_SYS_DDR2_DEBUG_18	CONFIG_SYS_DDR_DEBUG_18
+
+#endif
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of platform clock */
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* Start of PromJet */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_BR0_PRELIM \
+	(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
+	 BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+					| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_SYS_BR1_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+#define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS		0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS		PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x40
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_END		0x00004000	/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x118000
+#define CONFIG_SYS_I2C2_OFFSET		0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_RIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_RIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_RIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_RIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_RIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_RIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver */
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEF000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FMAN_FW_ADDR_PHYS	0xFEF000000ULL
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR_PHYS	CONFIG_SYS_FMAN_FW_ADDR
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#endif
+
+#ifdef CONFIG_PCI
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
+
+/* video */
+#define CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#ifndef CONFIG_PCI_PNP
+#define PCI_ENET0_IOADDR		CONFIG_SYS_PCI1_IO_BUS
+#define PCI_ENET0_MEMADDR		CONFIG_SYS_PCI1_IO_BUS
+#define PCI_IDSEL_NUMBER		0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1f
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR	0x1f
+#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR	0
+#endif
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=p4080ds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=p4080ds/p4080ds.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"						\
+	"fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index c8b8d0d80d..564f661bcb 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -496,6 +496,7 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_CMDLINE_EDITING			/* undef to save memory */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index ad7010900d..af1e19ee0a 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -233,6 +233,7 @@
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support */
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 363f7b473a..57bb8d1a38 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -189,6 +189,7 @@
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support   */
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index 10402c5bbb..710e5289c7 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -243,6 +243,20 @@ typedef struct ddr3_spd_eeprom_s {
 			unsigned char mod_thickness;
 			/* 62 (Registered) Reference Raw Card Used */
 			unsigned char ref_raw_card;
+			/* 63 DIMM Module Attributes */
+			unsigned char modu_attr;
+			/* 64 RDIMM Thermal Heat Spreader Solution */
+			unsigned char thermal;
+			/* 65 Register Manufacturer ID Code, Least Significant Byte */
+			unsigned char reg_id_lo;
+			/* 66 Register Manufacturer ID Code, Most Significant Byte */
+			unsigned char reg_id_hi;
+			/* 67 Register Revision Number */
+			unsigned char reg_rev;
+			/* 68 Register Type */
+			unsigned char reg_type;
+			/* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
+			unsigned char rcw[8];
 		} registered;
 		unsigned char uc[57]; /* 60-116 Module-Specific Section */
 	} mod_section;
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 54af9fe712..871ef4524b 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -86,6 +86,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias);
 u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
 int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
 					phys_addr_t compat_off);
+int fdt_alloc_phandle(void *blob);
 
 #endif /* ifdef CONFIG_OF_LIBFDT */
 #endif /* ifndef __FDT_SUPPORT_H */