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/*
* MPC8572 DS Core0 Device Tree Source in CAMP mode.
*
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
* can be shared, all the other devices must be assigned to one core only.
* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
* eth1, crypto, pci0, pci1.
*
* Copyright 2007-2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "mpc8572ds.dts"
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
cpus {
PowerPC,8572@0 {
};
PowerPC,8572@1 {
status = "disabled";
};
};
localbus@ffe05000 {
status = "disabled";
};
soc8572@ffe00000 {
serial@4600 {
status = "disabled";
};
dma@c300 {
status = "disabled";
};
gpio-controller@f000 {
};
l2-cache-controller@20000 {
cache-size = <0x80000>; // L2, 512K
};
ethernet@26000 {
status = "disabled";
};
mdio@26520 {
status = "disabled";
};
ethernet@27000 {
status = "disabled";
};
mdio@27520 {
status = "disabled";
};
pic@40000 {
protected-sources = <
31 32 33 37 38 39 /* enet2 enet3 */
76 77 78 79 26 42 /* dma2 pci2 serial*/
0xe4 0xe5 0xe6 0xe7 /* msi */
>;
};
msi@41600 {
msi-available-ranges = <0 0x80>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0>;
};
timer@42100 {
status = "disabled";
};
};
pcie@ffe0a000 {
status = "disabled";
};
};
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