blob: 9632436d74d7a74b3d584ab6e87a1fc7e55827cc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2011 Wind River Systems,
* written by Ralf Baechle (ralf@linux-mips.org)
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/of_address.h>
#include <asm/cpu-info.h>
unsigned long PCIBIOS_MIN_IO;
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
unsigned long PCIBIOS_MIN_MEM;
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
static int __init pcibios_set_cache_line_size(void)
{
unsigned int lsize;
/*
* Set PCI cacheline size to that of the highest level in the
* cache hierarchy.
*/
lsize = cpu_dcache_line_size();
lsize = cpu_scache_line_size() ? : lsize;
lsize = cpu_tcache_line_size() ? : lsize;
BUG_ON(!lsize);
pci_dfl_cache_line_size = lsize >> 2;
pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
return 0;
}
arch_initcall(pcibios_set_cache_line_size);
void pci_resource_to_user(const struct pci_dev *dev, int bar,
const struct resource *rsrc, resource_size_t *start,
resource_size_t *end)
{
phys_addr_t size = resource_size(rsrc);
*start = fixup_bigphys_addr(rsrc->start, size);
*end = rsrc->start + size;
}
|
