blob: 20446a846a98f45ce3c286cdb1d2eb58e62d3e2a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Device tree source file for Samsung's ARTIK5 evaluation board
* which is based on Samsung Exynos3250 SoC.
*/
/dts-v1/;
#include "exynos3250-artik5.dtsi"
/ {
model = "Samsung ARTIK5 evaluation board";
compatible = "samsung,artik5-eval", "samsung,artik5",
"samsung,exynos3250", "samsung,exynos3";
};
&mshc_2 {
cap-sd-highspeed;
disable-wp;
vqmmc-supply = <&ldo3_reg>;
card-detect-delay = <200>;
clock-frequency = <100000000>;
max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
status = "okay";
};
&serial_2 {
status = "okay";
};
|
