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/*
* Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "skeleton_hs_idu.dtsi"
/ {
model = "snps,zebu_hs-smp";
compatible = "snps,zebu_hs";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 */
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>; /* 50 MHZ */
};
core_intc: interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/* <hwirq distribution>
distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */
#interrupt-cells = <2>;
interrupts = <24 25 26 27 28 29 30 31>;
};
uart0: serial@f0000000 {
/* compatible = "ns8250"; Doesn't use FIFOs */
compatible = "ns16550a";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
/* interrupts = <0 1>; DEST=1*/
/* interrupts = <0 2>; DEST=2*/
interrupts = <0 0>; /* RR*/
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupts = <20>;
};
};
};
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