blob: 6f1c7b4e4d2ca8419db996e105b86fd855cce173 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
* NXP LPC1850 CREG clocks
The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
control registers for two low speed clocks. One of the clocks is a
32 kHz oscillator driver with power up/down and clock gating. Next
is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
These clocks are used by the RTC and the Event Router peripherials.
The 32 kHz can also be routed to other peripherials to enable low
power modes.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible:
Should be "nxp,lpc1850-creg-clk"
- #clock-cells:
Shall have value <1>.
- clocks:
Shall contain a phandle to the fixed 32 kHz crystal.
The creg-clk node must be a child of the creg syscon node.
The following clocks are available from the clock node.
Clock ID Name
0 1 kHz clock
1 32 kHz Oscillator
Example:
soc {
creg: syscon@40043000 {
compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
reg = <0x40043000 0x1000>;
creg_clk: clock-controller {
compatible = "nxp,lpc1850-creg-clk";
clocks = <&xtal32>;
#clock-cells = <1>;
};
...
};
rtc: rtc@40046000 {
...
clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
clock-names = "rtc", "reg";
...
};
};
|
