summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/clock/axi-clkgen.txt
blob: aca94fe9416f009ef387e9f7b7880bc5b6b5127e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Binding for the axi-clkgen clock generator

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
- #clock-cells : from common clock binding; Should always be set to 0.
- reg : Address and length of the axi-clkgen register set.
- clocks : Phandle and clock specifier for the parent clock(s). This must
	either reference one clock if only the first clock input is connected or two
	if both clock inputs are connected. For the later case the clock connected
	to the first input must be specified first.

Optional properties:
- clock-output-names : From common clock binding.

Example:
	clock@ff000000 {
		compatible = "adi,axi-clkgen";
		#clock-cells = <0>;
		reg = <0xff000000 0x1000>;
		clocks = <&osc 1>;
	};
OpenPOWER on IntegriCloud