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path: root/drivers/gpu/drm/i915/intel_dsi_pll.c
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* drm/i915: Changes required to enable DSI Video Mode on CHTGaurav K Singh2015-07-031-6/+20
* drm/i915: Support for higher DSI clkGaurav K Singh2015-07-031-2/+2
* drm/i915/dsi: abstract dsi bpp derivation from pixel formatJani Nikula2015-07-031-43/+24
* drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä2015-05-281-7/+7
* drm/i915/dsi: add support for DSI PLL N1 divisor valuesJani Nikula2015-05-201-6/+11
* drm/i915: clean up dsi pll calculationJani Nikula2015-05-201-36/+17
* drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port CGaurav K Singh2014-12-101-2/+3
* drm/i915: cck reg used for checking DSI Pll lockedGaurav K Singh2014-12-051-2/+4
* drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual linkGaurav K Singh2014-12-051-0/+3
* drm/i915: Align intel_dsi*.c files a bitDaniel Vetter2014-08-081-4/+4
* drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar2014-08-081-6/+3
* drm/i915: Add correct hw/sw config check for DSI encoderShobhit Kumar2014-08-071-0/+81
* drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar2013-12-111-10/+20
* drm/i915: Compute dsi_clk from pixel clockShobhit Kumar2013-12-111-58/+31
* drm/i915: Use adjusted_mode in DSI PLL calculationsVille Syrjälä2013-09-161-2/+2
* drm/i915: add VLV DSI PLL Calculationsymohanma2013-09-041-0/+317
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