summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_drv.h
Commit message (Collapse)AuthorAgeFilesLines
...
* drm/i915/skl: Unexport skl_pw1_misc_io_initImre Deak2016-04-151-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | On Broxton we need to enable/disable power well 1 during the init/unit display sequence similarly to Skylake/Kabylake. The code for this will be added in a follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's a simple function called only from a single place and having it inlined in the Skylake display core init/unit functions will make it easier to compare it with its Broxton counterpart. This also flips the order of Misc IO and power well 1 disabling which matches the enabling order. The specification doesn't prescribe the disabling order, so this should be fine. v2: - Fix incorrect enable vs. disable power well call in skl_display_core_uninit() (Patrik) - Add commit comment about chaning the order of PW1 and Misc IO power well disabling (Patrik) CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459773777-10701-1-git-send-email-imre.deak@intel.com
* drm/i915: Use GPLL ref clock to calculate GPU freqs on VLV/CHVVille Syrjälä2016-04-051-0/+2
| | | | | | | | | | | | | | | | | | | | | Extract the GPLL reference frequency from CCK and use it in the GPU freq<->opcode conversions on VLV/CHV. This eliminates all the assumptions we have about which divider is used for which czclk frequency. Note that unlike most clocks from CCK, the GPLL ref clock is a divided down version of the CZ clock rather than the HPLL clock. CZ clock itself is a divided down version of the HPLL clock though, so in effect it just gets divided down twice. While at it, throw in a few comments explaining the remaining constants for anyone who later wants to compare this to the spreadsheets. v2: Add slow/fast notes for CHV clocks (Imre) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457120584-26080-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com> (v1)
* drm/i915: Read sink_count dpcd alwaysShubhangi Shrivastava2016-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sink count can change between short pulse hpd hence this patch adds a member variable to intel_dp so we can track any changes between short pulse interrupts. This patch reads sink_count dpcd always and removes its read operation based on values in downstream port dpcd. SINK_COUNT dpcd is not dependent on DOWNSTREAM_PORT_PRESENT dpcd. SINK_COUNT denotes if a display is attached, while DOWNSTREAM_PORT_PRESET indicates how many ports are available in the dongle where display can be attached. so it is possible for sink count to change irrespective of value in downstream port dpcd. Here is a table of possible values and scenarios sink_count downstream_port present 0 0 no display is attached 0 1 dongle is connected without display 1 0 display connected directly 1 1 display connected through dongle v2: Storing value of intel_dp->sink_count that is ready for consumption. (Ander) Squashing two commits into one. (Ander) v3: Added comment to explain the need of early return when sink count is 0. (Ander) Tested-by: Nathan D Ciobanu <nathan.d.ciobanu@intel.com> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459341326-13142-4-git-send-email-shubhangi.shrivastava@intel.com
* drm/i915: Cleaning up intel_dp_hpd_pulseShubhangi Shrivastava2016-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Current DP detection has DPCD operations split across intel_dp_hpd_pulse and intel_dp_detect which contains duplicates as well. Also intel_dp_detect is called during modes enumeration as well which will result in multiple dpcd operations. So this patch tries to solve both these by bringing all DPCD operations in one single function and make intel_dp_detect use existing values instead of repeating same steps. v2: Pulled in a hunk from last patch of the series to this patch. (Ander) v3: Added MST hotplug handling. (Ander) v4: Added a flag to check if detect is performed to prevent multiple detects on hotplug. (Ander) Tested-by: Nathan D Ciobanu <nathan.d.ciobanu@intel.com> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> [anderco: fix parenthesis aligment] Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459341326-13142-2-git-send-email-shubhangi.shrivastava@intel.com
* drm/i915: Pass crtc_state to color management functions.Maarten Lankhorst2016-03-311-2/+2
| | | | | | Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459350996-4957-2-git-send-email-maarten.lankhorst@linux.intel.com
* drm/i915: Implement color management on bdw/skl/bxt/kblLionel Landwerlin2016-03-211-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Patch based on a previous series by Shashank Sharma. v2: Do not read GAMMA_MODE register to figure what mode we're in v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0 Add documentation on how the Broadcast RGB property is affected by CTM v4: Update contributors v5: Refactor degamma/gamma LUTs load into a single function v6: Fix missing intel_crtc variable (bisect issue) v7: Fix & simplify limited range matrix multiplication (Matt Roper's comment) Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Kumar, Kiran S <kiran.s.kumar@intel.com> Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acknowledged-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458125837-2576-4-git-send-email-lionel.g.landwerlin@intel.com
* drm/i915: Do not read GAMMA_MODE registerLionel Landwerlin2016-03-211-0/+3
| | | | | | | | | | | | | | | | | Implement Daniel Stone's recommendation to not read registers to infer the hardware's state. v2: Read GAMMA_MODE register value at init (Matt Roper's comment) v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along with other registers (Matt Roper's comment). v4: Mask GAMMA_MODE register with interesting bits when reading Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458125837-2576-3-git-send-email-lionel.g.landwerlin@intel.com
* drm/i915: Extract out gamma table and CSC to their own fileLionel Landwerlin2016-03-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | The moves a couple of functions programming the gamma LUT and CSC units into their own file. On generations prior to Haswell there is only a gamma LUT. From haswell on there is also a new enhanced color correction unit that isn't used yet. This is why we need to set the GAMMA_MODE register, either we're using the legacy 8bits LUT or enhanced LUTs (of 10 or 12bits). The CSC unit is only available from Haswell on. We also need to make a special case for CherryView which is recognized as a gen 8 but doesn't have the same enhanced color correction unit from Haswell on. v2: Fix access to GAMMA_MODE register on older generations than Haswell (from Matt Roper's comments) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1458125837-2576-2-git-send-email-lionel.g.landwerlin@intel.com
* drm/i915/bxt: add dsi transcodersJani Nikula2016-03-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | The BXT display connections have DSI transcoders A and C that can be muxed to any pipe, not unlike the eDP transcoder. Add the notion of DSI transcoders. The "normal" transcoders A, B and C are not used with BXT DSI, so care must be taken to avoid accessing those registers with DSI transcoders in the hardware state readout, modeset, and generally everywhere. v2: addressing comments by Ville: - rename the dsi get config function to hsw_get_dsi_transcoder_state - rebase onto the higher level split of pipe/transcoder functions - use more has_dsi_encoder as we can now because of the above, with no need to look at the transcoder so much - rename IS_DSI_TRANSCODER to transcoder_is_dsi - use the above a bit more instead of comparing to < TRANSCODER_EDP Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/299740536b7941e31b2744f3ce34f7afe936a771.1458313400.git.jani.nikula@intel.com
* drm/i915: Move load time init of clock gating hooks earlierImre Deak2016-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Split out the part initing the clock gating hooks and move it earlier. Add a new NOP hook for platforms without the need to apply clockgating or workaround settings, so that the hook can be called unconditionally. Also add a WARN for future platforms that forget to add a hook. The rest of the hooks in intel_init_pm() should be inited in the same way, but atm some of the hooks are set only conditionally, so before doing this we need to make the setup unconditional and use instead some flags. v2: - add a NOP hook and WARN if no hook is set for the platform (Chris) - use the term hook instead of callback for these functions (Jani) v3: - remove the GEN4() check it's already covered by earlier platform checks (Chris) CC: Jani Nikula <jani.nikula@intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1458128348-15730-6-git-send-email-imre.deak@intel.com
* drm/i915: Move load time init of display/audio hooks earlierImre Deak2016-03-171-1/+2
| | | | | | | | | | | | | | All of this is SW only initialization so we can move them earlier. Move the mutex init where the rest of the locks are inited. While at it also convert dev to dev_priv. v2: - use the term hook instead of callback for these functions (Jani) CC: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1458128348-15730-5-git-send-email-imre.deak@intel.com
* drm/i915: Nuke fbc members from intel_crtc->atomic, v4.Maarten Lankhorst2016-03-161-15/+0
| | | | | | | | | | | | | | | | | | | Whenever there's an update to the primary plane, fbc_pre_update and fbc_post_update are called. Kill off intel_crtc->atomic.update_fbc and now that intel_crtc->atomic is empty, kill it off too. Changes since v1: - Add a intel_fbc_supports_rotation helper. Changes since v2: - Remove intel_fbc_supports_rotation_helper. - Remove unrelated changes. Changes since v3: - Rebase Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457516145-32117-2-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
* drm/i915: Remove some post-commit members from intel_crtc->atomic, v3.Maarten Lankhorst2016-03-161-4/+1
| | | | | | | | | | | | | | | | fb_bits is useful to have in the crtc_state for cs flips when the code is updated to use intel_frontbuffer_flip_prepare/complete. So calculate it in advance and move it to crtc_state. The other stuff can be calculated in post_plane_update, and aren't useful elsewhere. Changes since v1: - Changing wording, remove comment about loop. Changes since v2: - Rebase. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457516145-32117-1-git-send-email-maarten.lankhorst@linux.intel.com
* drm/i915: Fix watermarks for VLV/CHVVille Syrjälä2016-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.") broke thigns by removing the pre vs. post wm update distinction. We also lost the pre plane wm update entirely for VLV/CHV from the crtc enable path. This caused underruns on modeset and plane enable/disable on CHV, and often those can lead to a dead pipe. So let's bring back the pre vs. post thing, and let's toss in an explicit wm update to valleyview_crtc_enable() to avoid having to put it into the common code. This is more or less a partial revert of the offending commit. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: drm-intel-fixes@lists.freedesktop.org Fixes: 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457543247-13987-4-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
* drm/i915: Manage HSW/BDW LCPLLs with the shared dpll interfaceAnder Conselvan de Oliveira2016-03-091-1/+0
| | | | | | | | | | | | | Manage the LCPLLs used with DisplayPort, so that all the HSW/BDW DPLLs are managed by the shared dpll code. v2: Introduce INTEL_DPLL_ALWAYS_ON flag to please state checker. (Ander) v3: Initialize pll->flags in intel_shared_dpll_init(). (Ander) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-13-git-send-email-ander.conselvan.de.oliveira@intel.com
* drm/i915: Move shared dpll function prototypes to intel_dpll_mgr.hAnder Conselvan de Oliveira2016-03-091-28/+0
| | | | | | | | | Move shared dpll function prototype together with other shared dpll definitions. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-7-git-send-email-ander.conselvan.de.oliveira@intel.com
* drm/i915: Store a direct pointer to shared dpll in intel_crtc_stateAnder Conselvan de Oliveira2016-03-091-3/+16
| | | | | | | | | | | | | | Change the type of intel_crtc_state->shared_dpll to be a pointer to a shared dpll. With this there is no need to first convert the id stored in the crtc state to a pointer in order to use it. It does introduce a bit of hassle on doing the opposite. The long term objective is to hide details about dpll ids behind the shared dpll interface. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-5-git-send-email-ander.conselvan.de.oliveira@intel.com
* drm/i915: Move ddi shared dpll code to intel_dpll_mgr.cAnder Conselvan de Oliveira2016-03-091-1/+0
| | | | | | | | No functional changes. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-3-git-send-email-ander.conselvan.de.oliveira@intel.com
* drm/i915: Move shared dpll code to a new fileAnder Conselvan de Oliveira2016-03-091-0/+8
| | | | | | | | | | | | Create the new file intel_dpll_mgr.c and move the shared dpll code to it. Follow up patches that reorganize pll handling will move more code there and tweak the interface. No functional changes. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-2-git-send-email-ander.conselvan.de.oliveira@intel.com
* drm/i915: Only use sanitized values for ILK watermarksMaarten Lankhorst2016-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The raw watermark values are needed when planes are not part of the state, but this introduced a regression and possibly an overflow when merging the watermarks because invalid values may end up used. Solve this by calculating raw watermarks for all levels, and only setting non-zero values when the level is valid. Fixes the SNB warning: WARNING: CPU: 1 PID: 25405 at drivers/gpu/drm/i915/intel_pm.c:2580 ilk_program_watermarks+0x7b2/0x9d0 [i915]() WARN_ON(wm_lp != 1) Modules linked in: i915 drm_kms_helper drm bluetooth fuse iTCO_wdt iTCO_vendor_support syscopyarea sysfillrect sysimgblt fb_sys_fops tpm_tis mei_me e1000e snd_hda_codec_hdmi pcspkr tpm mei i2c_i801 lpc_ich snd_hda_codec snd_hda_core CPU: 1 PID: 25405 Comm: kms_universal_p Tainted: G U W 4.5.0-rc6apollolake+ #462 Hardware name: /DH67GD, BIOS BLH6710H.86A.0160.2012.1204.1156 12/04/2012 0000000000000000 ffff88009d42b918 ffffffff8143cfab ffff88009d42b960 ffffffffa0363580 ffff88009d42b950 ffffffff81082746 ffff8800b9a24928 ffff88009d42ba00 ffff88009d4a0000 0000000000000000 ffff88009d42ba6c Call Trace: [<ffffffff8143cfab>] dump_stack+0x4d/0x72 [<ffffffff81082746>] warn_slowpath_common+0x86/0xc0 [<ffffffff810827cc>] warn_slowpath_fmt+0x4c/0x50 [<ffffffffa0292862>] ilk_program_watermarks+0x7b2/0x9d0 [i915] [<ffffffffa0292cb7>] ilk_initial_watermarks+0x107/0x120 [i915] [<ffffffffa02feffa>] intel_pre_plane_update+0x12a/0x190 [i915] [<ffffffffa02ffb36>] intel_atomic_commit+0x546/0xd50 [i915] [<ffffffffa012c9e7>] drm_atomic_commit+0x37/0x60 [drm] [<ffffffffa0217361>] drm_atomic_helper_disable_plane+0xb1/0xf0 [drm_kms_helper] [<ffffffffa011cdb4>] __setplane_internal+0x184/0x280 [drm] [<ffffffffa012b57a>] ? drm_modeset_lock_all_ctx+0x9a/0xb0 [drm] [<ffffffffa012010f>] drm_mode_setplane+0x13f/0x1c0 [drm] [<ffffffffa0111b52>] drm_ioctl+0x142/0x590 [drm] [<ffffffffa011ffd0>] ? drm_plane_check_pixel_format+0x50/0x50 [drm] [<ffffffff811f2744>] ? mntput+0x24/0x40 [<ffffffff811d28d4>] ? __fput+0x194/0x200 [<ffffffffa012dec3>] drm_compat_ioctl+0x33/0x40 [drm] [<ffffffffa029e1c2>] i915_compat_ioctl+0x32/0x40 [i915] [<ffffffff81228d72>] compat_SyS_ioctl+0xc2/0x330 [<ffffffff810021d5>] ? exit_to_usermode_loop+0x95/0xb0 [<ffffffff81002d2e>] do_fast_syscall_32+0x9e/0x210 [<ffffffff8197faf2>] entry_SYSENTER_compat+0x52/0x70 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Testcase: kms_universal_plane Fixes: d81f04c5ef ("drm/i915: Allow preservation of watermarks, v2.") Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/56DEA1FC.8080703@linux.intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
* drm/i915/gen9: Fix DMC firmware initializationImre Deak2016-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | In commit 1e657ad7 we moved the last step of firmware initialization to skl_display_core_init(), where it will be run only during system resume, but not during driver loading. Since this init step needs to be done whenever we program the firmware fix this by moving the initialization to the end of intel_csr_load_program(). While at it simplify a bit csr_load_work_fn(). This issue prevented DC5/6 transitions, this change will re-enable those. v2: - remove debugging left-over and redundant comment in csr_load_work_fn() Fixes: 1e657ad7a48f ("drm/i915/gen9: Write dc state debugmask bits only once") CC: Mika Kuoppala <mika.kuoppala@intel.com> CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457121461-16729-1-git-send-email-imre.deak@intel.com
* drm/i915: Store rawclk_freq in dev_privVille Syrjälä2016-03-041-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generalize rawclk handling by storing it in dev_priv. Presumably our hrawclk readout works at least for CTG and ELK since we've been using it for DP AUX on those platforms. There are no real docs anymore after configdb vanished, so the only reference is the public CTG GMCH spec. What bits are listed in that doc match our code. The ELK GMCH spec have no relevant details unfortunately. The PNV situation is less clear. Starting from commit aa17cdb4f836 ("drm/i915: initialize backlight max from VBT") we assume that the CTG/ELK hrawclk readout works for PNV as well. At least the results *seem* reasonable for one PNV machine (Lenovo Ideapad S10-3t). Sadly the PNV GMCH spec doesn't have the goods on the relevant register either. So let's keep assuming it works for PNV,ELK,CTG and read it out on those platforms. G33 also has hrawclk according to some notes in BSpec, but we don't actually need it for anything, so let's not even try to read it out there. v2: Rebase due to IS_VALLYVIEW vs. IS_CHERRYVIEW split Use KHz() all over, and kill off a few useless temp variables Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456932138-14004-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Do not lie about atomic timeout granularityTvrtko Ursulin2016-03-031-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the wait_for_atomic_us only allows for a jiffie timeout granularity which is not nice towards callers requesting small micro-second timeouts. Re-implement it so micro-second timeout granularity is really supported and not just in the name of the macro. This has another beneficial side effect that it improves "gem_latency -n 100" results by approximately 2.5% (throughput and latencies) and 3% (CPU usage). (Note this improvement is relative to not yet merged execlist lock uncontention patch which moves the CSB MMIO outside this lock.) It also shrinks some hot functions like fw_domains_get by a tiny 3%. v2: * Warn when used from non-atomic context (if possible). * Warn on too long atomic waits. v3: * Added comment explaining CONFIG_PREEMPT_COUNT. * Fixed pre-processor indentation. (Chris Wilson) v4: * Commit msg update (gem_latency) and rebase. v5: * Commit message re-wording. * Added comment about no need for double cond check. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Add wait_for_usTvrtko Ursulin2016-03-031-7/+8
| | | | | | | | | | | | | | This is for callers who want micro-second precision but are not waiting from the atomic context. v2: * Fix atomic waits. (Dave Gordon) * Use USEC_PER_SEC and USEC_PER_MSEC. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Dave Gordon <david.s.gordon@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only recalculate wm's for planes part of the state, v2.Maarten Lankhorst2016-03-031-0/+12
| | | | | | | | | | | | | | | | | Only planes that are part of the state should be used for recalculating watermarks. For planes not part of the state the previous patch allows us to re-use the old values since they're calculated even for levels that are not actively used. Changes since v1: - Remove big if from intel_crtc_atomic_check. - Remove extra newline. - Remove memset in ilk_compute_pipe_wm. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456826842-32553-2-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
* drm/i915: Read out VGA dotclock properly on LPTVille Syrjälä2016-03-011-0/+1
| | | | | | | | | | | | Rather than assume the VGA dotclock is really the FDI based thing, let's read out the real thing via iclkip, and after readout it'll get to compare it with the FDI based number to make sure they're in sync. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-6-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config()Ville Syrjälä2016-03-011-3/+0
| | | | | | | | | | | | | | | | | Currently we check if the encoder's idea of dotclock agrees with what we calculated based on the FDI parameters. We do this in the encoder .get_config() hooks, which isn't so nice in case the BIOS (or some other outside party) made a mess of the state and we're just trying to take over. So as a prep step to being able sanitize such a bogus state, move the the sanity check to just after we've read out the entire state. If we then need to sanitize a bad state, it should be easier to move the sanity check to occur after sanitation instead of before it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-3-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* drm/i915: Embed rotation_info under intel_framebufferVille Syrjälä2016-03-011-0/+1
| | | | | | | | | | Instead of repopulatin the rotation_info struct for the fb every time we try to use the fb, we can just populate it once when creating the fb, and later we can just copy the pre-populate struct into the gtt_view. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-10-git-send-email-ville.syrjala@linux.intel.com
* drm/i915: Reorganize intel_rotation_infoVille Syrjälä2016-03-011-0/+1
| | | | | | | | | | | | | | | Throw out a bunch of unnecessary stuff from struct intel_rotation_info, and pull most of the remaining stuff to live under an array of per-color plane sub-structures. What still remains outside the sub-structure will be reorgranized later as well, but that requires more work elsewhere so leave it be for now. v2: Split the vma size == luma+chroma size fix to prep patch (Daniel) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-8-git-send-email-ville.syrjala@linux.intel.com
* drm/i915: Pass drm_frambuffer to intel_compute_page_offset()Ville Syrjälä2016-03-011-4/+2
| | | | | | | | | | | | | | | intel_compute_page_offsets() gets passed a bunch of the framebuffer metadate sepearately. Just pass the framebuffer itself to make life simpler for the caller, and make it less likely they would make a mistake in the order of the arguments (as most as just unsigned ints and such). We still pass the pitch explicitly since for 90/270 degree rotation the caller has to pass in the right thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-7-git-send-email-ville.syrjala@linux.intel.com
* drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj()Ville Syrjälä2016-03-011-3/+2
| | | | | | | | | | | | | | | intel_pin_and_fence_fb_obj() only needs the framebuffer, and the desird rotation (to find the right GTT view for it), so no need to pass all kinds of plane stuff. The main motivation is to get rid of the uggy NULL plane_state handling due to fbdev. v2: Add a note why I really want this Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Grumpily-Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-6-git-send-email-ville.syrjala@linux.intel.com
* drm/i915: Pass 90/270 vs. 0/180 rotation info for ↵Ville Syrjälä2016-03-011-1/+2
| | | | | | | | | | | | | | | | | | | intel_gen4_compute_page_offset() The page aligned surface address calculation needs to know which way things are rotated. The contract now says that the caller must pass the rotate x/y coordinates, as well as the tile_height aligned stride in the tile_height direction. This will make it fairly simple to deal with 90/270 degree rotation on SKL+ where we have to deal with the rotated view into the GTT. v2: Pass rotation instead of bool even thoughwe only care about 0/180 vs. 90/270 v3: Introduce intel_tile_dims(), and don't mix up different units so much v4: Unconfuse bytes vs. pixels even more Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-4-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add two-stage ILK-style watermark programming (v11)Matt Roper2016-02-291-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to calculating final watermarks, let's also pre-calculate a set of intermediate watermark values at atomic check time. These intermediate watermarks are a combination of the watermarks for the old state and the new state; they should satisfy the requirements of both states which means they can be programmed immediately when we commit the atomic state (without waiting for a vblank). Once the vblank does happen, we can then re-program watermarks to the more optimal final value. v2: Significant rebasing/rewriting. v3: - Move 'need_postvbl_update' flag to CRTC state (Daniel) - Don't forget to check intermediate watermark values for validity (Maarten) - Don't due async watermark optimization; just do it at the end of the atomic transaction, after waiting for vblanks. We do want it to be async eventually, but adding that now will cause more trouble for Maarten's in-progress work. (Maarten) - Don't allocate space in crtc_state for intermediate watermarks on platforms that don't need it (gen9+). - Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit now that ilk_update_wm is gone. v4: - Add a wm_mutex to cover updates to intel_crtc->active and the need_postvbl_update flag. Since we don't have async yet it isn't terribly important yet, but might as well add it now. - Change interface to program watermarks. Platforms will now expose .initial_watermarks() and .optimize_watermarks() functions to do watermark programming. These should lock wm_mutex, copy the appropriate state values into intel_crtc->active, and then call the internal program watermarks function. v5: - Skip intermediate watermark calculation/check during initial hardware readout since we don't trust the existing HW values (and don't have valid values of our own yet). - Don't try to call .optimize_watermarks() on platforms that don't have atomic watermarks yet. (Maarten) v6: - Rebase v7: - Further rebase v8: - A few minor indentation and line length fixes v9: - Yet another rebase since Maarten's patches reworked a bunch of the code (wm_pre, wm_post, etc.) that this was previously based on. v10: - Move wm_mutex to dev_priv to protect against racing commits against disjoint CRTC sets. (Maarten) - Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten) v11: - Now that we've moved to atomic watermark updates, make sure we call the proper function to program watermarks in {ironlake,haswell}_crtc_enable(); the failure to do so on the previous patch iteration led to us not actually programming the watermarks before turning on the CRTC, which was the cause of the underruns that the CI system was seeing. - Fix inverted logic for determining when to optimize watermarks. We were needlessly optimizing when the intermediate/optimal values were the same (harmless), but not actually optimizing when they differed (also harmless, but wasteful from a power/bandwidth perspective). Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
* drm/i915: Remove update_sprite_watermarks.Maarten Lankhorst2016-02-251-1/+0
| | | | | | | | | Commit 791a32be6eb2 ("drm/i915: Drop intel_update_sprite_watermarks") removes the use of this variable, but forgot to remove it. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455108583-29227-5-git-send-email-maarten.lankhorst@linux.intel.com
* drm/i915: Kill off intel_crtc->atomic.wait_vblank, v6.Maarten Lankhorst2016-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we perform our own wait in post_plane_update, but the atomic core performs another one in wait_for_vblanks. This means that 2 vblanks are done when a fb is changed, which is a bit overkill. Merge them by creating a helper function that takes a crtc mask for the planes to wait on. The broadwell vblank workaround may look gone entirely but this is not the case. pipe_config->wm_changed is set to true when any plane is turned on, which forces a vblank wait. Changes since v1: - Removing the double vblank wait on broadwell moved to its own commit. Changes since v2: - Move out POWER_DOMAIN_MODESET handling to its own commit. Changes since v3: - Do not wait for vblank on legacy cursor updates. (Ville) - Move broadwell vblank workaround comment to page_flip_finished. (Ville) Changes since v4: - Compile fix, legacy_cursor_flip -> *_update. Changes since v5: - Kill brackets. - Add WARN_ON when wait_for_vblanks fails. - Remove extra newlines. - Split the checks whether vblank is needed to a separate function, with comments why a vblank is needed. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/56CD84DA.5030507@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
* drm/i915: Make sure pipe interrupts are processed before turning off power ↵Ville Syrjälä2016-02-221-0/+2
| | | | | | | | | | | | | | | | well on BDW+ Starting from BDW the DE_PIPE interrupts for pipe B and C belong to the relevant display power well. So we should make sure we've finished processing them before turning off the power well. The pipe interrupts shouldn't really happen at this point anymore since we've already shut down the planes/pipes/whatnot, but being a bit paranoid shouldn't hurt. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455907651-16397-1-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* drm/i915/gen9: Write dc state debugmask bits only onceMika Kuoppala2016-02-221-1/+1
| | | | | | | | | | | | DMC debugmask bits should stick so no need to write them everytime dc state is changed. v2: Write after firmware has been successfully loaded (Ville) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455808874-22089-5-git-send-email-mika.kuoppala@intel.com
* drm/i915: Use atomic state to obtain load detection crtc, v3.Maarten Lankhorst2016-02-181-3/+1
| | | | | | | | | | | | | | | Instead of restoring dpms and a flag for whether a temp fb is allocated duplicate an atomic state before the new state is committed, and commit it the old state in intel_release_load_detect_pipe. Changes since v1: - Use a real atomic state. (Ville) Changes since v2: - Do not preserve shared_dpll any more, no need to do so. (Ville) Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455697119-31416-2-git-send-email-maarten.lankhorst@linux.intel.com
* drm/i915: Add helper to get a display power ref if it was already enabledImre Deak2016-02-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | We have many places in the code where we check if a given display power domain is enabled and if so access registers backed by this power domain. We assumed that some modeset lock will prevent the power reference from vanishing in the middle of the HW access, but this assumption doesn't always hold. In such cases we get either the wakeref not held, or an unclaimed register access error message. To fix this in a future-proof way that's independent of other locks wrap any such access with a get_ref_if_enabled()/put_ref() pair. Kudos to Ville and Joonas for the ideas of this new interface. v2: - init the power_domains ptr when declaring it everywhere (Joonas) v3: - don't report the device to be powered if runtime PM is disabled CC: Mika Kuoppala <mika.kuoppala@intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455711462-7442-1-git-send-email-imre.deak@intel.com
* drm/i915: edp resume/On time optimization.Abhay Kumar2016-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12) if this time is already spent in suspend/poweron time. v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle delay calculation(Ville). v3: Addressed below comments 1. Tracking time from where last powercycle is initiated. 2. Used ktime_get_bootime() wrapper for boottime clock. 3. Used ktime_ms_delta() to get time difference. v4: Updated v3 change log in detail. v5: Removed static from panel_power_on_time(Stéphane). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1453513144-14135-1-git-send-email-abhay.kumar@intel.com
* Merge tag 'topic/drm-misc-2016-02-12' into drm-intel-next-queuedDaniel Vetter2016-02-121-1/+0
|\ | | | | | | | | | | Backmerge to get at the new encoder_mask support in atomic helpers. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
| * Merge tag 'topic/drm-misc-2016-02-08' of ↵Dave Airlie2016-02-091-1/+0
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next First drm-misc pull req for 4.6. Big one is the drm_event cleanup, which is also prep work for adding android fence support to kms (Gustavo is planning to do that). Otherwise random small bits all over. * tag 'topic/drm-misc-2016-02-08' of git://anongit.freedesktop.org/drm-intel: (33 commits) gma500: clean up an excessive and confusing helper drm/gma500: remove helper function drm/vmwgfx: Nuke preclose hook drm/vc4: Nuke preclose hook drm/tilcdc: Nuke preclose hook drm/tegra: Stop cancelling page flip events drm/shmob: Nuke preclose hook drm/rcar: Nuke preclose hook drm/omap: Nuke close hooks drm/msm: Nuke preclose hooks drm/imx: Unconfuse preclose logic drm/exynos: Remove event cancelling from postclose drm/atmel: Nuke preclose drm/i915: Nuke intel_modeset_preclose drm: Nuke vblank event file cleanup code drm: Clean up pending events in the core drm/vblank: Use drm_event_reserve_init drm/vmwgfx: fix a NULL dereference drm/crtc-helper: Add caveat to disable_unused_functions doc drm/gma500: Remove empty preclose hook ...
| | * drm/i915: Nuke intel_modeset_precloseDaniel Vetter2016-02-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the drm core unlinks/disarms events there's no need to do so ourselves anymore. Nuke the code. Acked-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453756616-28942-4-git-send-email-daniel.vetter@ffwll.ch
| | * drm/i915: Tune down rpm wakelock debug checksDaniel Vetter2016-01-131-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | They're causing massive amounts of dmesg noise and hence CI noise all over the place. Enabling them for a bit was good enough to refresh our task list of what's still needed to enable rpm by default. To make sure we're not forgetting to make this noisy again add a FIXME comment. Fixes: da5827c36607 ("drm/i915: add assert_rpm_wakelock_held helper") Cc: Imre Deak <imre.deak@intel.com> Cc: drm-intel-fixes@lists.freedesktop.org Cc: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1452012847-4737-1-git-send-email-daniel.vetter@ffwll.ch Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> (cherry picked from commit becd9ca2de656ccd8d02c434742388aead336147) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* | | drm/i915: Remove atomic.pre_disable_primary.Maarten Lankhorst2016-02-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This can be derived from the atomic state in pre_plane_update, which makes it more clear when it's supposed to be called. Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1454514805-10595-3-git-send-email-maarten.lankhorst@linux.intel.com
* | | drm/i915: Remove intel_crtc->atomic.disable_ips.Maarten Lankhorst2016-02-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a revert of commit 066cf55b9ce3 "drm/i915: Fix IPS related flicker". intel_pre_disable_primary already handles this, and now everything goes through the atomic path there's no need to try to disable ips twice. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Link: http://patchwork.freedesktop.org/patch/msgid/1454514805-10595-2-git-send-email-maarten.lankhorst@linux.intel.com
* | | drm/i915/bxt: Check BIOS RC6 setup before enabling RC6Sagar Arun Kamble2016-02-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RC6 setup is shared between BIOS and Driver. BIOS sets up subset of RC6 setup registers. If those are not setup Driver should not enable RC6. For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values to know if BIOS has enabled HW/SW RC6. This will also enable user to control RC6 using BIOS settings alone. RC6 related instability can be avoided by disabling via BIOS settings till driver fixes it. v2: Had placed logic in gen8 function by mistake. Fixed it. Ensuring RPM is not enabled in case BIOS disabled RC6. v3: Need to disable RPM if RC6 is disabled due to BIOS settings. (Daniel) Runtime PM enabling happens before gen9_enable_rc6. Moved the updation of enable_rc6 parameter in intel_uncore_sanitize. v4: Added elaborate check for BIOS RC6 setup. Prepared check_pctx for bxt. (Imre) v5: Caching reserved stolen base and size in the driver private data. Reorganized RC6 setup check. Moved from gen9_enable_rc6 to intel_uncore_sanitize. (Imre) v6: Rebasing on the patch submitted by Imre that moves gem_init_stolen earlier in the load. v7: Removed PWRCTX_MAXCNT_VCSUNIT1 check as it applies to SKL. (Imre) v8: Fixed formatting and checkpatch issues. Fixed functional issue where RC6 ctx size check was missing. (Imre) Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1454697809-22113-1-git-send-email-sagar.a.kamble@intel.com
* | | drm/i915/fbc: choose the new FBC CRTC during atomic checkPaulo Zanoni2016-01-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This opens the possibility of implementing nicer schemes to choose the CRTC, such as checking the amount of stolen memory available, or choosing the best pipe on platforms that don't die FBC to pipe or plane A. This code was written for another refactor that I ended up discarding, so I don't actually need it, but I figured this patch would be an improvement on its own so I kept it on the series. Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-18-git-send-email-paulo.r.zanoni@intel.com
* | | drm/i915/fbc: rewrite the multiple_pipes_ok() code for lockingPaulo Zanoni2016-01-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Older FBC platforms have this restriction where FBC can't be enabled if multiple pipes are enabled. In the current code, we disable FBC before the second pipe becomes visible. One of the problems with this code is that the current multiple_pipes_ok() implementation just iterates through all CRTCs looking at their states, but it doesn't make sure that the state locks are grabbed. It also can't just grab the locks for every CRTC since this would kill one of the biggest advantages of atomic modesetting. After the recent FBC changes, we now have the appropriate locks for the given CRTC, so we can just try to maintain the state of each CRTC and update it once intel_fbc_pre_update is called. As a last note, I don't have gen 2/3 machines to test this code. My current plan is to enable FBC on just the newer platforms, so this patch is just an attempt to get the gen 2/3 code at least looking sane, so if one day someone decide to fix FBC on these platforms, they may have less work to do. Not-tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (only on HSW+) Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-16-git-send-email-paulo.r.zanoni@intel.com
* | | drm/i915/fbc: rename the FBC disable functionsPaulo Zanoni2016-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of: - intel_fbc_disable_crtc(crtc) - intel_fbc_disable(dev_priv) we now have: - intel_fbc_disable(crtc) - intel_fbc_global_disable(dev_priv) This is because all the other functions that take a CRTC are called - intel_fbc_something(crtc) Instead of: - intel_fbc_something_crtc(crtc) And I also hope that the word "global" is going to help make it more explicit that "global" is the unusual case, not the opposite. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-14-git-send-email-paulo.r.zanoni@intel.com
OpenPOWER on IntegriCloud