Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | fpga zynq: Check the bitstream for validity | Jason Gunthorpe | 2017-02-10 | 1 | -0/+21 |
* | fpga zynq: Check for errors after completing DMA | Jason Gunthorpe | 2017-02-10 | 1 | -22/+32 |
* | fpga zynq: Fix incorrect ISR state on bootup | Jason Gunthorpe | 2016-11-29 | 1 | -7/+10 |
* | fpga zynq: Remove priv->dev | Jason Gunthorpe | 2016-11-29 | 1 | -11/+8 |
* | fpga zynq: Add missing \n to messages | Jason Gunthorpe | 2016-11-29 | 1 | -11/+11 |
* | fpga-mgr: add fpga image information struct | Alan Tull | 2016-11-10 | 1 | -4/+6 |
* | fpga: zynq-fpga: Fix issue with drvdata being overwritten. | Moritz Fischer | 2015-10-23 | 1 | -3/+4 |
* | fpga: zynq-fpga: Change fw format to handle bin instead of bit. | Moritz Fischer | 2015-10-23 | 1 | -22/+2 |
* | fpga: zynq-fpga: Fix unbalanced clock handling | Moritz Fischer | 2015-10-23 | 1 | -2/+2 |
* | fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000 | Moritz Fischer | 2015-10-17 | 1 | -0/+533 |