summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
* clk: aspeed: Support HPLL strapping on ast2400Joel Stanley2018-07-111-13/+29
* clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHzGregory CLEMENT2018-07-091-0/+38
* clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as criticalJoel Stanley2018-07-061-2/+2
* clk/mmcc-msm8996: Make mmagic_bimc_gdsc ALWAYS_ONVivek Gautam2018-07-061-0/+1
* Merge tag 'meson-clk-fixes-4.18-1' of https://github.com/BayLibre/clk-meson i...Stephen Boyd2018-07-062-1/+2
|\
| * clk: meson: audio-divider is one basedJerome Brunet2018-06-211-1/+1
| * clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong2018-06-191-0/+1
* | clk: aspeed: Treat a gate in reset as disabledBenjamin Herrenschmidt2018-07-061-0/+13
* | clk: Really show symbolic clock flags in debugfsGeert Uytterhoeven2018-07-061-2/+1
* | clk: qcom: gcc-msm8996: Disable halt check on UFS tx clockVinod Koul2018-07-061-0/+1
* | Merge tag 'clk-davinci-fixes-4.18' of https://github.com/dlech/linux into clk...Stephen Boyd2018-06-272-2/+2
|\ \
| * | clk: davinci: fix a typo (which leads to build failures)Bartosz Golaszewski2018-06-251-1/+1
| * | clk: davinci: cfgchip: testing the wrong variableDan Carpenter2018-06-251-1/+1
| |/
* | clk: sunxi-ng: replace lib-y with obj-yMasahiro Yamada2018-06-212-25/+16
|/
* docs: Fix some broken referencesMauro Carvalho Chehab2018-06-152-3/+3
* treewide: devm_kzalloc() -> devm_kcalloc()Kees Cook2018-06-122-4/+6
* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-1211-14/+15
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-09138-1156/+12576
|\
| * Merge branch 'clk-imx6ul' into clk-nextStephen Boyd2018-06-041-1/+1
| |\
| | * clk: imx6ul: fix periph clk2 clock mux selectionStefan Agner2018-05-041-1/+1
| | |
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *-------. \ Merge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'cl...Stephen Boyd2018-06-0450-502/+1545
| |\ \ \ \ \ \
| | | | | | * | clk: meson: axg: let mpll clocks round closestJerome Brunet2018-05-211-0/+4
| | | | | | * | clk: meson: mpll: add round closest supportJerome Brunet2018-05-212-5/+22
| | | | | | * | clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl2018-05-211-0/+7
| | | | | | * | clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-1813-238/+20
| | | | | | * | clk: meson: drop CLK_SET_RATE_PARENT flagYixun Lan2018-05-151-1/+1
| | | | | | * | clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai2018-05-154-1/+195
| | | | | | * | clk: meson: aoclk: refactor common code into dedicated fileYixun Lan2018-05-156-62/+160
| | | | | | * | clk: meson: migrate to devm_of_clk_add_hw_provider APIYixun Lan2018-05-151-1/+1
| | | | | | * | clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2018-05-152-1/+119
| | | | | | * | clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl2018-05-152-1/+58
| | | | | | |/
| | | | | * | clk: davinci: Fix link errors when not all SoCs are enabledDavid Lechner2018-05-304-3/+50
| | | | | * | clk: davinci: psc: allow for dev == NULLDavid Lechner2018-05-305-18/+52
| | | | | * | clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLAREDavid Lechner2018-05-303-6/+21
| | | | | * | clk: davinci: pll: allow dev == NULLDavid Lechner2018-05-308-137/+235
| | | | | * | clk: davinci: psc-dm365: fix few clocksSekhar Nori2018-05-301-3/+16
| | | | | * | clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabledSekhar Nori2018-05-301-1/+1
| | | | | * | clk: davinci: psc-dm355: fix ASP0/1 clkdev lookupsDavid Lechner2018-05-301-2/+2
| | | | | * | clk: davinci: pll-dm355: fix SYSCLKn parent namesDavid Lechner2018-05-301-5/+5
| | | | | * | clk: davinci: pll-dm355: drop pll2_sysclk2David Lechner2018-05-301-4/+1
| | | | | |/
| | | | * | clk: at91: PLL recalc_rate() now using cached MUL and DIV valuesMarcin Ziemianowicz2018-05-151-12/+1
| | | | |/
| | | * | clk: renesas: cpg-mssr: Add support for R-Car E3Yoshihiro Shimoda2018-05-095-0/+302
| | | * | clk: renesas: rcar-gen2: Centralize quirks handlingGeert Uytterhoeven2018-04-161-4/+16
| | | * | clk: renesas: r8a77980: Correct parent clock of PCIEC0Geert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7794: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7792: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7791/r8a7793: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7745: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7743: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: cpg-mssr: Add r8a77470 supportBiju Das2018-04-166-0/+254
OpenPOWER on IntegriCloud