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path: root/drivers/clk/meson/clk-mpll.c
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* clk: meson: mpll: add round closest supportJerome Brunet2018-05-211-5/+19
* clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-181-51/+1
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-131-44/+0
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-131-65/+37
* clk: meson: add axg misc bit to the mpll driverJerome Brunet2018-02-121-0/+7
* clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl2017-12-231-1/+1
* clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet2017-08-011-0/+7
* clk: meson: mpll: use 64bit math in rate_from_paramsMartin Blumenstingl2017-04-071-1/+1
* clk: meson: mpll: fix division by zero in rate_from_paramsMartin Blumenstingl2017-04-071-11/+15
* clk: meson: mpll: correct N2 maximum valueJerome Brunet2017-03-271-1/+1
* clk: meson: mpll: add rw operationJerome Brunet2017-03-271-5/+147
* clk: meson: add mpll supportMichael Turquette2016-06-221-0/+94
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