Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | clk: meson: clk-pll: remove od parameters | Jerome Brunet | 2018-09-26 | 1 | -1/+7 |
* | clk: meson: add gen_clk | Jerome Brunet | 2018-07-09 | 1 | -1/+3 |
* | clk: meson-axg: add clocks required by pcie driver | Yixun Lan | 2018-07-09 | 1 | -1/+5 |
* | clk: meson: add fdiv clock gates | Jerome Brunet | 2018-03-13 | 1 | -1/+6 |
* | clk: meson: add mpll pre-divider | Jerome Brunet | 2018-03-13 | 1 | -1/+2 |
* | clk: meson: axg: add hifi pll clock | Jerome Brunet | 2018-03-13 | 1 | -1/+1 |
* | clk: meson: split divider and gate part of mpll | Jerome Brunet | 2018-03-13 | 1 | -1/+5 |
* | clk: meson-axg: add clock controller drivers | Qiufang Dai | 2017-12-14 | 1 | -0/+126 |