diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index ad151fefa41f..e1c2b4e9c7b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -26,6 +26,7 @@ #include "amdgpu.h" #include "gmc_v6_0.h" #include "amdgpu_ucode.h" +#include "amdgpu_gem.h" #include "bif/bif_3_0_d.h" #include "bif/bif_3_0_sh_mask.h" @@ -223,8 +224,8 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_device_vram_location(adev, &adev->gmc, base); - amdgpu_device_gart_location(adev, mc); + amdgpu_gmc_vram_location(adev, &adev->gmc, base); + amdgpu_gmc_gart_location(adev, mc); } static void gmc_v6_0_mc_program(struct amdgpu_device *adev) @@ -493,16 +494,20 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) { + uint64_t table_addr; int r, i; u32 field; - if (adev->gart.robj == NULL) { + if (adev->gart.bo == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } r = amdgpu_gart_table_vram_pin(adev); if (r) return r; + + table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); + /* Setup TLB control */ WREG32(mmMC_VM_MX_L1_TLB_CNTL, (0xA << 7) | @@ -531,7 +536,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) /* setup context0 */ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); - WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(adev->dummy_page_addr >> 12)); WREG32(mmVM_CONTEXT0_CNTL2, 0); @@ -555,10 +560,10 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) for (i = 1; i < 16; i++) { if (i < 8) WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, - adev->gart.table_addr >> 12); + table_addr >> 12); else WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, - adev->gart.table_addr >> 12); + table_addr >> 12); } /* enable context1-15 */ @@ -578,7 +583,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) gmc_v6_0_flush_gpu_tlb(adev, 0); dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned)(adev->gmc.gart_size >> 20), - (unsigned long long)adev->gart.table_addr); + (unsigned long long)table_addr); adev->gart.ready = true; return 0; } @@ -587,7 +592,7 @@ static int gmc_v6_0_gart_init(struct amdgpu_device *adev) { int r; - if (adev->gart.robj) { + if (adev->gart.bo) { dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); return 0; } @@ -854,11 +859,11 @@ static int gmc_v6_0_sw_init(void *handle) adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); } - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); if (r) return r; - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); if (r) return r; @@ -1175,8 +1180,7 @@ static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) { - if (adev->gmc.gmc_funcs == NULL) - adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; + adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; } static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) |
