diff options
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk.c | 504 | ||||
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 516 | ||||
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.h | 35 | ||||
| -rw-r--r-- | drivers/clk/qcom/gcc-ipq8074.c | 2 | ||||
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8994.c | 4 | ||||
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8996.c | 4 | ||||
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8996.c | 16 | ||||
| -rw-r--r-- | drivers/clk/ti/Makefile | 4 | ||||
| -rw-r--r-- | drivers/clk/ti/clk-3xxx-legacy.c | 4656 | ||||
| -rw-r--r-- | drivers/clk/ti/clk.c | 135 | ||||
| -rw-r--r-- | drivers/clk/ti/clock.h | 68 | ||||
| -rw-r--r-- | drivers/clk/ti/composite.c | 45 | ||||
| -rw-r--r-- | drivers/clk/ti/dpll.c | 90 | ||||
| -rw-r--r-- | drivers/clk/ti/gate.c | 48 | ||||
| -rw-r--r-- | drivers/clk/ti/interface.c | 32 |
15 files changed, 918 insertions, 5241 deletions
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8a1860a36c77..3526bc068f30 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -62,6 +62,7 @@ struct clk_core { bool orphan; unsigned int enable_count; unsigned int prepare_count; + unsigned int protect_count; unsigned long min_rate; unsigned long max_rate; unsigned long accuracy; @@ -86,6 +87,7 @@ struct clk { const char *con_id; unsigned long min_rate; unsigned long max_rate; + unsigned int exclusive_count; struct hlist_node clks_node; }; @@ -170,6 +172,11 @@ static void clk_enable_unlock(unsigned long flags) spin_unlock_irqrestore(&enable_lock, flags); } +static bool clk_core_rate_is_protected(struct clk_core *core) +{ + return core->protect_count; +} + static bool clk_core_is_prepared(struct clk_core *core) { bool ret = false; @@ -381,6 +388,11 @@ bool clk_hw_is_prepared(const struct clk_hw *hw) return clk_core_is_prepared(hw->core); } +bool clk_hw_rate_is_protected(const struct clk_hw *hw) +{ + return clk_core_rate_is_protected(hw->core); +} + bool clk_hw_is_enabled(const struct clk_hw *hw) { return clk_core_is_enabled(hw->core); @@ -519,6 +531,139 @@ EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest); /*** clk api ***/ +static void clk_core_rate_unprotect(struct clk_core *core) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return; + + if (WARN_ON(core->protect_count == 0)) + return; + + if (--core->protect_count > 0) + return; + + clk_core_rate_unprotect(core->parent); +} + +static int clk_core_rate_nuke_protect(struct clk_core *core) +{ + int ret; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return -EINVAL; + + if (core->protect_count == 0) + return 0; + + ret = core->protect_count; + core->protect_count = 1; + clk_core_rate_unprotect(core); + + return ret; +} + +/** + * clk_rate_exclusive_put - release exclusivity over clock rate control + * @clk: the clk over which the exclusivity is released + * + * clk_rate_exclusive_put() completes a critical section during which a clock + * consumer cannot tolerate any other consumer making any operation on the + * clock which could result in a rate change or rate glitch. Exclusive clocks + * cannot have their rate changed, either directly or indirectly due to changes + * further up the parent chain of clocks. As a result, clocks up parent chain + * also get under exclusive control of the calling consumer. + * + * If exlusivity is claimed more than once on clock, even by the same consumer, + * the rate effectively gets locked as exclusivity can't be preempted. + * + * Calls to clk_rate_exclusive_put() must be balanced with calls to + * clk_rate_exclusive_get(). Calls to this function may sleep, and do not return + * error status. + */ +void clk_rate_exclusive_put(struct clk *clk) +{ + if (!clk) + return; + + clk_prepare_lock(); + + /* + * if there is something wrong with this consumer protect count, stop + * here before messing with the provider + */ + if (WARN_ON(clk->exclusive_count <= 0)) + goto out; + + clk_core_rate_unprotect(clk->core); + clk->exclusive_count--; +out: + clk_prepare_unlock(); +} +EXPORT_SYMBOL_GPL(clk_rate_exclusive_put); + +static void clk_core_rate_protect(struct clk_core *core) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return; + + if (core->protect_count == 0) + clk_core_rate_protect(core->parent); + + core->protect_count++; +} + +static void clk_core_rate_restore_protect(struct clk_core *core, int count) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return; + + if (count == 0) + return; + + clk_core_rate_protect(core); + core->protect_count = count; +} + +/** + * clk_rate_exclusive_get - get exclusivity over the clk rate control + * @clk: the clk over which the exclusity of rate control is requested + * + * clk_rate_exlusive_get() begins a critical section during which a clock + * consumer cannot tolerate any other consumer making any operation on the + * clock which could result in a rate change or rate glitch. Exclusive clocks + * cannot have their rate changed, either directly or indirectly due to changes + * further up the parent chain of clocks. As a result, clocks up parent chain + * also get under exclusive control of the calling consumer. + * + * If exlusivity is claimed more than once on clock, even by the same consumer, + * the rate effectively gets locked as exclusivity can't be preempted. + * + * Calls to clk_rate_exclusive_get() should be balanced with calls to + * clk_rate_exclusive_put(). Calls to this function may sleep. + * Returns 0 on success, -EERROR otherwise + */ +int clk_rate_exclusive_get(struct clk *clk) +{ + if (!clk) + return 0; + + clk_prepare_lock(); + clk_core_rate_protect(clk->core); + clk->exclusive_count++; + clk_prepare_unlock(); + + return 0; +} +EXPORT_SYMBOL_GPL(clk_rate_exclusive_get); + static void clk_core_unprepare(struct clk_core *core) { lockdep_assert_held(&prepare_lock); @@ -905,10 +1050,9 @@ static int clk_disable_unused(void) } late_initcall_sync(clk_disable_unused); -static int clk_core_round_rate_nolock(struct clk_core *core, - struct clk_rate_request *req) +static int clk_core_determine_round_nolock(struct clk_core *core, + struct clk_rate_request *req) { - struct clk_core *parent; long rate; lockdep_assert_held(&prepare_lock); @@ -916,16 +1060,15 @@ static int clk_core_round_rate_nolock(struct clk_core *core, if (!core) return 0; - parent = core->parent; - if (parent) { - req->best_parent_hw = parent->hw; - req->best_parent_rate = parent->rate; - } else { - req->best_parent_hw = NULL; - req->best_parent_rate = 0; - } - - if (core->ops->determine_rate) { + /* + * At this point, core protection will be disabled if + * - if the provider is not protected at all + * - if the calling consumer is the only one which has exclusivity + * over the provider + */ + if (clk_core_rate_is_protected(core)) { + req->rate = core->rate; + } else if (core->ops->determine_rate) { return core->ops->determine_rate(core->hw, req); } else if (core->ops->round_rate) { rate = core->ops->round_rate(core->hw, req->rate, @@ -934,15 +1077,58 @@ static int clk_core_round_rate_nolock(struct clk_core *core, return rate; req->rate = rate; - } else if (core->flags & CLK_SET_RATE_PARENT) { - return clk_core_round_rate_nolock(parent, req); } else { - req->rate = core->rate; + return -EINVAL; } return 0; } +static void clk_core_init_rate_req(struct clk_core * const core, + struct clk_rate_request *req) +{ + struct clk_core *parent; + + if (WARN_ON(!core || !req)) + return; + + parent = core->parent; + if (parent) { + req->best_parent_hw = parent->hw; + req->best_parent_rate = parent->rate; + } else { + req->best_parent_hw = NULL; + req->best_parent_rate = 0; + } +} + +static bool clk_core_can_round(struct clk_core * const core) +{ + if (core->ops->determine_rate || core->ops->round_rate) + return true; + + return false; +} + +static int clk_core_round_rate_nolock(struct clk_core *core, + struct clk_rate_request *req) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + clk_core_init_rate_req(core, req); + + if (clk_core_can_round(core)) + return clk_core_determine_round_nolock(core, req); + else if (core->flags & CLK_SET_RATE_PARENT) + return clk_core_round_rate_nolock(core->parent, req); + + req->rate = core->rate; + return 0; +} + /** * __clk_determine_rate - get the closest rate actually supported by a clock * @hw: determine the rate of this clock @@ -996,10 +1182,17 @@ long clk_round_rate(struct clk *clk, unsigned long rate) clk_prepare_lock(); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate); req.rate = rate; ret = clk_core_round_rate_nolock(clk->core, &req); + + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + clk_prepare_unlock(); if (ret) @@ -1432,34 +1625,23 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, clk_core_get_boundaries(core, &min_rate, &max_rate); /* find the closest rate and parent clk/rate */ - if (core->ops->determine_rate) { + if (clk_core_can_round(core)) { struct clk_rate_request req; req.rate = rate; req.min_rate = min_rate; req.max_rate = max_rate; - if (parent) { - req.best_parent_hw = parent->hw; - req.best_parent_rate = parent->rate; - } else { - req.best_parent_hw = NULL; - req.best_parent_rate = 0; - } - ret = core->ops->determine_rate(core->hw, &req); + clk_core_init_rate_req(core, &req); + + ret = clk_core_determine_round_nolock(core, &req); if (ret < 0) return NULL; best_parent_rate = req.best_parent_rate; new_rate = req.rate; parent = req.best_parent_hw ? req.best_parent_hw->core : NULL; - } else if (core->ops->round_rate) { - ret = core->ops->round_rate(core->hw, rate, - &best_parent_rate); - if (ret < 0) - return NULL; - new_rate = ret; if (new_rate < min_rate || new_rate > max_rate) return NULL; } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) { @@ -1641,25 +1823,58 @@ static void clk_change_rate(struct clk_core *core) clk_pm_runtime_put(core); } +static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core, + unsigned long req_rate) +{ + int ret, cnt; + struct clk_rate_request req; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + /* simulate what the rate would be if it could be freely set */ + cnt = clk_core_rate_nuke_protect(core); + if (cnt < 0) + return cnt; + + clk_core_get_boundaries(core, &req.min_rate, &req.max_rate); + req.rate = req_rate; + + ret = clk_core_round_rate_nolock(core, &req); + + /* restore the protection */ + clk_core_rate_restore_protect(core, cnt); + + return ret ? 0 : req.rate; +} + static int clk_core_set_rate_nolock(struct clk_core *core, unsigned long req_rate) { struct clk_core *top, *fail_clk; - unsigned long rate = req_rate; + unsigned long rate; int ret = 0; if (!core) return 0; + rate = clk_core_req_round_rate_nolock(core, req_rate); + /* bail early if nothing to do */ if (rate == clk_core_get_rate_nolock(core)) return 0; + /* fail on a direct rate set of a protected provider */ + if (clk_core_rate_is_protected(core)) + return -EBUSY; + if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count) return -EBUSY; /* calculate new rates and get the topmost changed clock */ - top = clk_calc_new_rates(core, rate); + top = clk_calc_new_rates(core, req_rate); if (!top) return -EINVAL; @@ -1718,8 +1933,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate) /* prevent racing with updates to the clock topology */ clk_prepare_lock(); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + ret = clk_core_set_rate_nolock(clk->core, rate); + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + clk_prepare_unlock(); return ret; @@ -1727,6 +1948,53 @@ int clk_set_rate(struct clk *clk, unsigned long rate) EXPORT_SYMBOL_GPL(clk_set_rate); /** + * clk_set_rate_exclusive - specify a new rate get exclusive control + * @clk: the clk whose rate is being changed + * @rate: the new rate for clk + * + * This is a combination of clk_set_rate() and clk_rate_exclusive_get() + * within a critical section + * + * This can be used initially to ensure that at least 1 consumer is + * statisfied when several consumers are competing for exclusivity over the + * same clock provider. + * + * The exclusivity is not applied if setting the rate failed. + * + * Calls to clk_rate_exclusive_get() should be balanced with calls to + * clk_rate_exclusive_put(). + * + * Returns 0 on success, -EERROR otherwise. + */ +int clk_set_rate_exclusive(struct clk *clk, unsigned long rate) +{ + int ret; + + if (!clk) + return 0; + + /* prevent racing with updates to the clock topology */ + clk_prepare_lock(); + + /* + * The temporary protection removal is not here, on purpose + * This function is meant to be used instead of clk_rate_protect, + * so before the consumer code path protect the clock provider + */ + + ret = clk_core_set_rate_nolock(clk->core, rate); + if (!ret) { + clk_core_rate_protect(clk->core); + clk->exclusive_count++; + } + + clk_prepare_unlock(); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_set_rate_exclusive); + +/** * clk_set_rate_range - set a rate range for a clock source * @clk: clock source * @min: desired minimum clock rate in Hz, inclusive @@ -1737,6 +2005,7 @@ EXPORT_SYMBOL_GPL(clk_set_rate); int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) { int ret = 0; + unsigned long old_min, old_max, rate; if (!clk) return 0; @@ -1750,12 +2019,46 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) clk_prepare_lock(); - if (min != clk->min_rate || max != clk->max_rate) { - clk->min_rate = min; - clk->max_rate = max; - ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + + /* Save the current values in case we need to rollback the change */ + old_min = clk->min_rate; + old_max = clk->max_rate; + clk->min_rate = min; + clk->max_rate = max; + + rate = clk_core_get_rate_nolock(clk->core); + if (rate < min || rate > max) { + /* + * FIXME: + * We are in bit of trouble here, current rate is outside the + * the requested range. We are going try to request appropriate + * range boundary but there is a catch. It may fail for the + * usual reason (clock broken, clock protected, etc) but also + * because: + * - round_rate() was not favorable and fell on the wrong + * side of the boundary + * - the determine_rate() callback does not really check for + * this corner case when determining the rate + */ + + if (rate < min) + rate = min; + else + rate = max; + + ret = clk_core_set_rate_nolock(clk->core, rate); + if (ret) { + /* rollback the changes */ + clk->min_rate = old_min; + clk->max_rate = old_max; + } } + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + clk_prepare_unlock(); return ret; @@ -1876,32 +2179,31 @@ bool clk_has_parent(struct clk *clk, struct clk *parent) } EXPORT_SYMBOL_GPL(clk_has_parent); -static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent) +static int clk_core_set_parent_nolock(struct clk_core *core, + struct clk_core *parent) { int ret = 0; int p_index = 0; unsigned long p_rate = 0; + lockdep_assert_held(&prepare_lock); + if (!core) return 0; - /* prevent racing with updates to the clock topology */ - clk_prepare_lock(); - if (core->parent == parent) - goto out; + return 0; /* verify ops for for multi-parent clks */ - if ((core->num_parents > 1) && (!core->ops->set_parent)) { - ret = -ENOSYS; - goto out; - } + if (core->num_parents > 1 && !core->ops->set_parent) + return -EPERM; /* check that we are allowed to re-parent if the clock is in use */ - if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) { - ret = -EBUSY; - goto out; - } + if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) + return -EBUSY; + + if (clk_core_rate_is_protected(core)) + return -EBUSY; /* try finding the new parent index */ if (parent) { @@ -1909,15 +2211,14 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent) if (p_index < 0) { pr_debug("%s: clk %s can not be parent of clk %s\n", __func__, parent->name, core->name); - ret = p_index; - goto out; + return p_index; } p_rate = parent->rate; } ret = clk_pm_runtime_get(core); if (ret) - goto out; + return ret; /* propagate PRE_RATE_CHANGE notifications */ ret = __clk_speculate_rates(core, p_rate); @@ -1939,8 +2240,6 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent) runtime_put: clk_pm_runtime_put(core); -out: - clk_prepare_unlock(); return ret; } @@ -1964,13 +2263,50 @@ out: */ int clk_set_parent(struct clk *clk, struct clk *parent) { + int ret; + if (!clk) return 0; - return clk_core_set_parent(clk->core, parent ? parent->core : NULL); + clk_prepare_lock(); + + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + + ret = clk_core_set_parent_nolock(clk->core, + parent ? parent->core : NULL); + + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + + clk_prepare_unlock(); + + return ret; } EXPORT_SYMBOL_GPL(clk_set_parent); +static int clk_core_set_phase_nolock(struct clk_core *core, int degrees) +{ + int ret = -EINVAL; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + if (clk_core_rate_is_protected(core)) + return -EBUSY; + + trace_clk_set_phase(core, degrees); + + if (core->ops->set_phase) + ret = core->ops->set_phase(core->hw, degrees); + + trace_clk_set_phase_complete(core, degrees); + + return ret; +} + /** * clk_set_phase - adjust the phase shift of a clock signal * @clk: clock signal source @@ -1993,7 +2329,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent); */ int clk_set_phase(struct clk *clk, int degrees) { - int ret = -EINVAL; + int ret; if (!clk) return 0; @@ -2005,15 +2341,13 @@ int clk_set_phase(struct clk *clk, int degrees) clk_prepare_lock(); - trace_clk_set_phase(clk->core, degrees); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); - if (clk->core->ops->set_phase) - ret = clk->core->ops->set_phase(clk->core->hw, degrees); + ret = clk_core_set_phase_nolock(clk->core, degrees); - trace_clk_set_phase_complete(clk->core, degrees); - - if (!ret) - clk->core->phase = degrees; + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); clk_prepare_unlock(); @@ -2101,11 +2435,12 @@ static void clk_summary_show_one(struct seq_file *s, struct clk_core *c, if (!c) return; - seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n", + seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %-3d\n", level * 3 + 1, "", 30 - level * 3, c->name, - c->enable_count, c->prepare_count, clk_core_get_rate(c), - clk_core_get_accuracy(c), clk_core_get_phase(c)); + c->enable_count, c->prepare_count, c->protect_count, + clk_core_get_rate(c), clk_core_get_accuracy(c), + clk_core_get_phase(c)); } static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c, @@ -2127,7 +2462,8 @@ static int clk_summary_show(struct seq_file *s, void *data) struct clk_core *c; struct hlist_head **lists = (struct hlist_head **)s->private; - seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n"); + seq_puts(s, " enable prepare protect \n"); + seq_puts(s, " clock count count count rate accuracy phase\n"); seq_puts(s, "----------------------------------------------------------------------------------------\n"); clk_prepare_lock(); @@ -2163,6 +2499,7 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level) seq_printf(s, "\"%s\": { ", c->name); seq_printf(s, "\"enable_count\": %d,", c->enable_count); seq_printf(s, "\"prepare_count\": %d,", c->prepare_count); + seq_printf(s, "\"protect_count\": %d,", c->protect_count); seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c)); seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c)); seq_printf(s, "\"phase\": %d", clk_core_get_phase(c)); @@ -2293,6 +2630,11 @@ static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) if (!d) goto err_out; + d = debugfs_create_u32("clk_protect_count", S_IRUGO, core->dentry, + (u32 *)&core->protect_count); + if (!d) + goto err_out; + d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry, (u32 *)&core->notifier_count); if (!d) @@ -2683,7 +3025,13 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw) ret = -ENOMEM; goto fail_name; } + + if (WARN_ON(!hw->init->ops)) { + ret = -EINVAL; + goto fail_ops; + } core->ops = hw->init->ops; + if (dev && pm_runtime_enabled(dev)) core->dev = dev; if (dev && dev->driver) @@ -2745,6 +3093,7 @@ fail_parent_names_copy: kfree_const(core->parent_names[i]); kfree(core->parent_names); fail_parent_names: +fail_ops: kfree_const(core->name); fail_name: kfree(core); @@ -2856,7 +3205,7 @@ void clk_unregister(struct clk *clk) /* Reparent all children to the orphan list. */ hlist_for_each_entry_safe(child, t, &clk->core->children, child_node) - clk_core_set_parent(child, NULL); + clk_core_set_parent_nolock(child, NULL); } hlist_del_init(&clk->core->child_node); @@ -2864,6 +3213,11 @@ void clk_unregister(struct clk *clk) if (clk->core->prepare_count) pr_warn("%s: unregistering prepared clock: %s\n", __func__, clk->core->name); + + if (clk->core->protect_count) + pr_warn("%s: unregistering protected clock: %s\n", + __func__, clk->core->name); + kref_put(&clk->core->ref, __clk_release); unlock: clk_prepare_unlock(); @@ -3022,6 +3376,18 @@ void __clk_put(struct clk *clk) clk_prepare_lock(); + /* + * Before calling clk_put, all calls to clk_rate_exclusive_get() from a + * given user should be balanced with calls to clk_rate_exclusive_put() + * and by that same consumer + */ + if (WARN_ON(clk->exclusive_count)) { + /* We voiced our concern, let's sanitize the situation */ + clk->core->protect_count -= (clk->exclusive_count - 1); + clk_core_rate_unprotect(clk->core); + clk->exclusive_count = 0; + } + hlist_del(&clk->clks_node); if (clk->min_rate > clk->core->req_rate || clk->max_rate < clk->core->req_rate) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 47a1da3739ce..6d04cd96482a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -20,7 +20,7 @@ #include "clk-alpha-pll.h" #include "common.h" -#define PLL_MODE 0x00 +#define PLL_MODE(p) ((p)->offset + 0x0) # define PLL_OUTCTRL BIT(0) # define PLL_BYPASSNL BIT(1) # define PLL_RESET_N BIT(2) @@ -32,35 +32,87 @@ # define PLL_VOTE_FSM_ENA BIT(20) # define PLL_FSM_ENA BIT(20) # define PLL_VOTE_FSM_RESET BIT(21) +# define PLL_UPDATE BIT(22) +# define PLL_UPDATE_BYPASS BIT(23) # define PLL_OFFLINE_ACK BIT(28) +# define ALPHA_PLL_ACK_LATCH BIT(29) # define PLL_ACTIVE_FLAG BIT(30) # define PLL_LOCK_DET BIT(31) -#define PLL_L_VAL 0x04 -#define PLL_ALPHA_VAL 0x08 -#define PLL_ALPHA_VAL_U 0x0c +#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) +#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) +#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) -#define PLL_USER_CTL 0x10 +#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK 0xf +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) # define PLL_ALPHA_EN BIT(24) +# define PLL_ALPHA_MODE BIT(25) # define PLL_VCO_SHIFT 20 # define PLL_VCO_MASK 0x3 -#define PLL_USER_CTL_U 0x14 - -#define PLL_CONFIG_CTL 0x18 -#define PLL_CONFIG_CTL_U 0x20 -#define PLL_TEST_CTL 0x1c -#define PLL_TEST_CTL_U 0x20 -#define PLL_STATUS 0x24 +#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) + +#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) +#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) +#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) +#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) +#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) + +const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { + [CLK_ALPHA_PLL_TYPE_DEFAULT] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL_U] = 0x0c, + [PLL_OFF_USER_CTL] = 0x10, + [PLL_OFF_USER_CTL_U] = 0x14, + [PLL_OFF_CONFIG_CTL] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_STATUS] = 0x24, + }, + [CLK_ALPHA_PLL_TYPE_HUAYRA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL] = 0x14, + [PLL_OFF_CONFIG_CTL_U] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_STATUS] = 0x24, + }, + [CLK_ALPHA_PLL_TYPE_BRAMMO] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL_U] = 0x0c, + [PLL_OFF_USER_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_STATUS] = 0x24, + }, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); /* * Even though 40 bits are present, use only 32 for ease of calculation. */ #define ALPHA_REG_BITWIDTH 40 -#define ALPHA_BITWIDTH 32 -#define ALPHA_16BIT_MASK 0xffff +#define ALPHA_REG_16BIT_WIDTH 16 +#define ALPHA_BITWIDTH 32U +#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) + +#define PLL_HUAYRA_M_WIDTH 8 +#define PLL_HUAYRA_M_SHIFT 8 +#define PLL_HUAYRA_M_MASK 0xff +#define PLL_HUAYRA_N_SHIFT 0 +#define PLL_HUAYRA_N_MASK 0xff +#define PLL_HUAYRA_ALPHA_WIDTH 16 + +#define pll_alpha_width(p) \ + ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ + ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) + +#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ struct clk_alpha_pll, clkr) @@ -71,18 +123,17 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, const char *action) { - u32 val, off; + u32 val; int count; int ret; const char *name = clk_hw_get_name(&pll->clkr.hw); - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; for (count = 100; count > 0; count--) { - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; if (inverse && !(val & mask)) @@ -109,16 +160,30 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, #define wait_for_pll_offline(pll) \ wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") +#define wait_for_pll_update(pll) \ + wait_for_pll(pll, PLL_UPDATE, 1, "update") + +#define wait_for_pll_update_ack_set(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") + +#define wait_for_pll_update_ack_clear(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { u32 val, mask; - u32 off = pll->offset; - regmap_write(regmap, off + PLL_L_VAL, config->l); - regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha); - regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val); - regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val); + regmap_write(regmap, PLL_L_VAL(pll), config->l); + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); + regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + + if (pll_has_64bit_config(pll)) + regmap_write(regmap, PLL_CONFIG_CTL_U(pll), + config->config_ctl_hi_val); + + if (pll_alpha_width(pll) > 32) + regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); val = config->main_output_mask; val |= config->aux_output_mask; @@ -127,6 +192,8 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, val |= config->pre_div_val; val |= config->post_div_val; val |= config->vco_val; + val |= config->alpha_en_mask; + val |= config->alpha_mode_mask; mask = config->main_output_mask; mask |= config->aux_output_mask; @@ -136,20 +203,19 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, mask |= config->post_div_mask; mask |= config->vco_mask; - regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val); + regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); if (pll->flags & SUPPORTS_FSM_MODE) - qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0); + qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); } static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) { int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; @@ -158,7 +224,7 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) if (pll->flags & SUPPORTS_OFFLINE_REQ) val &= ~PLL_OFFLINE_REQ; - ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val); + ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); if (ret) return ret; @@ -171,16 +237,15 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) { int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return; if (pll->flags & SUPPORTS_OFFLINE_REQ) { - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); if (ret) return; @@ -191,7 +256,7 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) } /* Disable hwfsm */ - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_FSM_ENA, 0); if (ret) return; @@ -202,11 +267,10 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) static int pll_is_enabled(struct clk_hw *hw, u32 mask) { int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; @@ -227,12 +291,10 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 val, mask, off; - - off = pll->offset; + u32 val, mask; mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; @@ -248,7 +310,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) if ((val & mask) == mask) return 0; - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); if (ret) return ret; @@ -260,7 +322,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) mb(); udelay(5); - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); if (ret) return ret; @@ -269,7 +331,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) if (ret) return ret; - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); /* Ensure that the write above goes through before returning. */ @@ -281,11 +343,9 @@ static void clk_alpha_pll_disable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 val, mask, off; - - off = pll->offset; + u32 val, mask; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return; @@ -296,23 +356,25 @@ static void clk_alpha_pll_disable(struct clk_hw *hw) } mask = PLL_OUTCTRL; - regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0); + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); /* Delay of 2 output clock ticks required until output is disabled */ mb(); udelay(1); mask = PLL_RESET_N | PLL_BYPASSNL; - regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0); + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); } -static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a) +static unsigned long +alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) { - return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH); + return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); } static unsigned long -alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a) +alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, + u32 alpha_width) { u64 remainder; u64 quotient; @@ -327,14 +389,15 @@ alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a) } /* Upper ALPHA_BITWIDTH bits of Alpha */ - quotient = remainder << ALPHA_BITWIDTH; + quotient = remainder << ALPHA_SHIFT(alpha_width); + remainder = do_div(quotient, prate); if (remainder) quotient++; *a = quotient; - return alpha_pll_calc_rate(prate, *l, *a); + return alpha_pll_calc_rate(prate, *l, *a, alpha_width); } static const struct pll_vco * @@ -356,71 +419,138 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) u32 l, low, high, ctl; u64 a = 0, prate = parent_rate; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 off = pll->offset; + u32 alpha_width = pll_alpha_width(pll); - regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l); + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); - regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl); + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); if (ctl & PLL_ALPHA_EN) { - regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low); - if (pll->flags & SUPPORTS_16BIT_ALPHA) { - a = low & ALPHA_16BIT_MASK; - } else { - regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); + if (alpha_width > 32) { + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), &high); a = (u64)high << 32 | low; - a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; + } else { + a = low & GENMASK(alpha_width - 1, 0); } + + if (alpha_width > ALPHA_BITWIDTH) + a >>= alpha_width - ALPHA_BITWIDTH; } - return alpha_pll_calc_rate(prate, l, a); + return alpha_pll_calc_rate(prate, l, a, alpha_width); } -static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) +static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, + int (*is_enabled)(struct clk_hw *)) +{ + int ret; + u32 mode; + + if (!is_enabled(&pll->clkr.hw) || + !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) + return 0; + + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); + + /* Latch the input to the PLL */ + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, + PLL_UPDATE); + + /* Wait for 2 reference cycle before checking ACK bit */ + udelay(1); + + /* + * PLL will latch the new L, Alpha and freq control word. + * PLL will respond by raising PLL_ACK_LATCH output when new programming + * has been latched in and PLL is being updated. When + * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared + * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. + */ + if (mode & PLL_UPDATE_BYPASS) { + ret = wait_for_pll_update_ack_set(pll); + if (ret) + return ret; + + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); + } else { + ret = wait_for_pll_update(pll); + if (ret) + return ret; + } + + ret = wait_for_pll_update_ack_clear(pll); + if (ret) + return ret; + + /* Wait for PLL output to stabilize */ + udelay(10); + + return 0; +} + +static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate, + int (*is_enabled)(struct clk_hw *)) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); const struct pll_vco *vco; - u32 l, off = pll->offset; + u32 l, alpha_width = pll_alpha_width(pll); u64 a; - rate = alpha_pll_round_rate(rate, prate, &l, &a); + rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); vco = alpha_pll_find_vco(pll, rate); - if (!vco) { + if (pll->vco_table && !vco) { pr_err("alpha pll not in a valid vco range\n"); return -EINVAL; } - regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); - if (pll->flags & SUPPORTS_16BIT_ALPHA) { - regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, - a & ALPHA_16BIT_MASK); - } else { - a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); - regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32); + if (alpha_width > ALPHA_BITWIDTH) + a <<= alpha_width - ALPHA_BITWIDTH; + + if (alpha_width > 32) + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); + + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + + if (vco) { + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_VCO_MASK << PLL_VCO_SHIFT, + vco->val << PLL_VCO_SHIFT); } - regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, - PLL_VCO_MASK << PLL_VCO_SHIFT, - vco->val << PLL_VCO_SHIFT); + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN, PLL_ALPHA_EN); - regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN, - PLL_ALPHA_EN); + return clk_alpha_pll_update_latch(pll, is_enabled); +} - return 0; +static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __clk_alpha_pll_set_rate(hw, rate, prate, + clk_alpha_pll_is_enabled); +} + +static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __clk_alpha_pll_set_rate(hw, rate, prate, + clk_alpha_pll_hwfsm_is_enabled); } static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 l; + u32 l, alpha_width = pll_alpha_width(pll); u64 a; unsigned long min_freq, max_freq; - rate = alpha_pll_round_rate(rate, *prate, &l, &a); - if (alpha_pll_find_vco(pll, rate)) + rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); + if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) return rate; min_freq = pll->vco_table[0].min_freq; @@ -429,6 +559,158 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, return clamp(rate, min_freq, max_freq); } +static unsigned long +alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) +{ + /* + * a contains 16 bit alpha_val in two’s compliment number in the range + * of [-0.5, 0.5). + */ + if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) + l -= 1; + + return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); +} + +static unsigned long +alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, + u32 *l, u32 *a) +{ + u64 remainder; + u64 quotient; + + quotient = rate; + remainder = do_div(quotient, prate); + *l = quotient; + + if (!remainder) { + *a = 0; + return rate; + } + + quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; + remainder = do_div(quotient, prate); + + if (remainder) + quotient++; + + /* + * alpha_val should be in two’s compliment number in the range + * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value + * since alpha value will be subtracted in this case. + */ + if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) + *l += 1; + + *a = quotient; + return alpha_huayra_pll_calc_rate(prate, *l, *a); +} + +static unsigned long +alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + u64 rate = parent_rate, tmp; + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l, alpha = 0, ctl, alpha_m, alpha_n; + + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + + if (ctl & PLL_ALPHA_EN) { + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); + /* + * Depending upon alpha_mode, it can be treated as M/N value or + * as a two’s compliment number. When alpha_mode=1, + * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N + * + * Fout=FIN*(L+(M/N)) + * + * M is a signed number (-128 to 127) and N is unsigned + * (0 to 255). M/N has to be within +/-0.5. + * + * When alpha_mode=0, it is a two’s compliment number in the + * range [-0.5, 0.5). + * + * Fout=FIN*(L+(alpha_val)/2^16) + * + * where alpha_val is two’s compliment number. + */ + if (!(ctl & PLL_ALPHA_MODE)) + return alpha_huayra_pll_calc_rate(rate, l, alpha); + + alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; + alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; + + rate *= l; + tmp = parent_rate; + if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { + alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; + tmp *= alpha_m; + do_div(tmp, alpha_n); + rate -= tmp; + } else { + tmp *= alpha_m; + do_div(tmp, alpha_n); + rate += tmp; + } + + return rate; + } + + return alpha_huayra_pll_calc_rate(rate, l, alpha); +} + +static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l, a, ctl, cur_alpha = 0; + + rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); + + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + + if (ctl & PLL_ALPHA_EN) + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); + + /* + * Huayra PLL supports PLL dynamic programming. User can change L_VAL, + * without having to go through the power on sequence. + */ + if (clk_alpha_pll_is_enabled(hw)) { + if (cur_alpha != a) { + pr_err("clock needs to be gated %s\n", + clk_hw_get_name(hw)); + return -EBUSY; + } + + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + /* Ensure that the write above goes to detect L val change. */ + mb(); + return wait_for_pll_enable_lock(pll); + } + + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + + if (a == 0) + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN, 0x0); + else + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); + + return 0; +} + +static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u32 l, a; + + return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); +} + const struct clk_ops clk_alpha_pll_ops = { .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, @@ -439,13 +721,23 @@ const struct clk_ops clk_alpha_pll_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); +const struct clk_ops clk_alpha_pll_huayra_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = alpha_pll_huayra_recalc_rate, + .round_rate = alpha_pll_huayra_round_rate, + .set_rate = alpha_pll_huayra_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); + const struct clk_ops clk_alpha_pll_hwfsm_ops = { .enable = clk_alpha_pll_hwfsm_enable, .disable = clk_alpha_pll_hwfsm_disable, .is_enabled = clk_alpha_pll_hwfsm_is_enabled, .recalc_rate = clk_alpha_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, - .set_rate = clk_alpha_pll_set_rate, + .set_rate = clk_alpha_pll_hwfsm_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); @@ -455,10 +747,10 @@ clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); u32 ctl; - regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl); + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); ctl >>= PLL_POST_DIV_SHIFT; - ctl &= PLL_POST_DIV_MASK; + ctl &= PLL_POST_DIV_MASK(pll); return parent_rate >> fls(ctl); } @@ -472,16 +764,48 @@ static const struct clk_div_table clk_alpha_div_table[] = { { } }; +static const struct clk_div_table clk_alpha_2bit_div_table[] = { + { 0x0, 1 }, + { 0x1, 2 }, + { 0x3, 4 }, + { } +}; + static long clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + const struct clk_div_table *table; - return divider_round_rate(hw, rate, prate, clk_alpha_div_table, + if (pll->width == 2) + table = clk_alpha_2bit_div_table; + else + table = clk_alpha_div_table; + + return divider_round_rate(hw, rate, prate, table, pll->width, CLK_DIVIDER_POWER_OF_TWO); } +static long +clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + u32 ctl, div; + + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + + ctl >>= PLL_POST_DIV_SHIFT; + ctl &= BIT(pll->width) - 1; + div = 1 << fls(ctl); + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) + *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); + + return DIV_ROUND_UP_ULL((u64)*prate, div); +} + static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -491,8 +815,8 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; - return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL, - PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT, + return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, div << PLL_POST_DIV_SHIFT); } @@ -502,3 +826,9 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = { .set_rate = clk_alpha_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); + +const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { + .round_rate = clk_alpha_pll_postdiv_round_ro_rate, + .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index d6e1ee2c7348..7593e8a56cf2 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -17,6 +17,30 @@ #include <linux/clk-provider.h> #include "clk-regmap.h" +/* Alpha PLL types */ +enum { + CLK_ALPHA_PLL_TYPE_DEFAULT, + CLK_ALPHA_PLL_TYPE_HUAYRA, + CLK_ALPHA_PLL_TYPE_BRAMMO, + CLK_ALPHA_PLL_TYPE_MAX, +}; + +enum { + PLL_OFF_L_VAL, + PLL_OFF_ALPHA_VAL, + PLL_OFF_ALPHA_VAL_U, + PLL_OFF_USER_CTL, + PLL_OFF_USER_CTL_U, + PLL_OFF_CONFIG_CTL, + PLL_OFF_CONFIG_CTL_U, + PLL_OFF_TEST_CTL, + PLL_OFF_TEST_CTL_U, + PLL_OFF_STATUS, + PLL_OFF_MAX_REGS +}; + +extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; + struct pll_vco { unsigned long min_freq; unsigned long max_freq; @@ -27,16 +51,18 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @vco_table: array of VCO settings + * @regs: alpha pll register map (see @clk_alpha_pll_regs) * @clkr: regmap clock handle */ struct clk_alpha_pll { u32 offset; + const u8 *regs; const struct pll_vco *vco_table; size_t num_vco; #define SUPPORTS_OFFLINE_REQ BIT(0) -#define SUPPORTS_16BIT_ALPHA BIT(1) #define SUPPORTS_FSM_MODE BIT(2) +#define SUPPORTS_DYNAMIC_UPDATE BIT(3) u8 flags; struct clk_regmap clkr; @@ -45,12 +71,14 @@ struct clk_alpha_pll { /** * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider * @offset: base address of registers + * @regs: alpha pll register map (see @clk_alpha_pll_regs) * @width: width of post-divider * @clkr: regmap clock handle */ struct clk_alpha_pll_postdiv { u32 offset; u8 width; + const u8 *regs; struct clk_regmap clkr; }; @@ -58,12 +86,15 @@ struct clk_alpha_pll_postdiv { struct alpha_pll_config { u32 l; u32 alpha; + u32 alpha_hi; u32 config_ctl_val; u32 config_ctl_hi_val; u32 main_output_mask; u32 aux_output_mask; u32 aux2_output_mask; u32 early_output_mask; + u32 alpha_en_mask; + u32 alpha_mode_mask; u32 pre_div_val; u32 pre_div_mask; u32 post_div_val; @@ -75,6 +106,8 @@ struct alpha_pll_config { extern const struct clk_ops clk_alpha_pll_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ops; +extern const struct clk_ops clk_alpha_pll_huayra_ops; +extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 0f735d37690f..ed2d00f55378 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -52,6 +52,7 @@ static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { static struct clk_alpha_pll gpll0_main = { .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x0b000, .enable_mask = BIT(0), @@ -82,6 +83,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){ diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 7983288d9141..1e38efc37180 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -73,6 +73,7 @@ static struct clk_fixed_factor xo = { static struct clk_alpha_pll gpll0_early = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x1480, .enable_mask = BIT(0), @@ -88,6 +89,7 @@ static struct clk_alpha_pll gpll0_early = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data) { .name = "gpll0", @@ -99,6 +101,7 @@ static struct clk_alpha_pll_postdiv gpll0 = { static struct clk_alpha_pll gpll4_early = { .offset = 0x1dc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x1480, .enable_mask = BIT(4), @@ -114,6 +117,7 @@ static struct clk_alpha_pll gpll4_early = { static struct clk_alpha_pll_postdiv gpll4 = { .offset = 0x1dc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data) { .name = "gpll4", diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 7ddec886fcd3..5d7451209206 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -227,6 +227,7 @@ static struct clk_fixed_factor xo = { static struct clk_alpha_pll gpll0_early = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(0), @@ -252,6 +253,7 @@ static struct clk_fixed_factor gpll0_early_div = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){ "gpll0_early" }, @@ -262,6 +264,7 @@ static struct clk_alpha_pll_postdiv gpll0 = { static struct clk_alpha_pll gpll4_early = { .offset = 0x77000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(4), @@ -276,6 +279,7 @@ static struct clk_alpha_pll gpll4_early = { static struct clk_alpha_pll_postdiv gpll4 = { .offset = 0x77000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", .parent_names = (const char *[]){ "gpll4_early" }, diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 352394d8fd8c..66a2fa4ec93c 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -267,6 +267,7 @@ static struct pll_vco mmpll_t_vco[] = { static struct clk_alpha_pll mmpll0_early = { .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr = { @@ -283,6 +284,7 @@ static struct clk_alpha_pll mmpll0_early = { static struct clk_alpha_pll_postdiv mmpll0 = { .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll0", @@ -295,6 +297,7 @@ static struct clk_alpha_pll_postdiv mmpll0 = { static struct clk_alpha_pll mmpll1_early = { .offset = 0x30, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr = { @@ -311,6 +314,7 @@ static struct clk_alpha_pll mmpll1_early = { static struct clk_alpha_pll_postdiv mmpll1 = { .offset = 0x30, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll1", @@ -323,6 +327,7 @@ static struct clk_alpha_pll_postdiv mmpll1 = { static struct clk_alpha_pll mmpll2_early = { .offset = 0x4100, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_gfx_vco, .num_vco = ARRAY_SIZE(mmpll_gfx_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -335,6 +340,7 @@ static struct clk_alpha_pll mmpll2_early = { static struct clk_alpha_pll_postdiv mmpll2 = { .offset = 0x4100, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll2", @@ -347,6 +353,7 @@ static struct clk_alpha_pll_postdiv mmpll2 = { static struct clk_alpha_pll mmpll3_early = { .offset = 0x60, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -359,6 +366,7 @@ static struct clk_alpha_pll mmpll3_early = { static struct clk_alpha_pll_postdiv mmpll3 = { .offset = 0x60, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll3", @@ -371,6 +379,7 @@ static struct clk_alpha_pll_postdiv mmpll3 = { static struct clk_alpha_pll mmpll4_early = { .offset = 0x90, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_t_vco, .num_vco = ARRAY_SIZE(mmpll_t_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -383,6 +392,7 @@ static struct clk_alpha_pll mmpll4_early = { static struct clk_alpha_pll_postdiv mmpll4 = { .offset = 0x90, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll4", @@ -395,6 +405,7 @@ static struct clk_alpha_pll_postdiv mmpll4 = { static struct clk_alpha_pll mmpll5_early = { .offset = 0xc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -407,6 +418,7 @@ static struct clk_alpha_pll mmpll5_early = { static struct clk_alpha_pll_postdiv mmpll5 = { .offset = 0xc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll5", @@ -419,6 +431,7 @@ static struct clk_alpha_pll_postdiv mmpll5 = { static struct clk_alpha_pll mmpll8_early = { .offset = 0x4130, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_gfx_vco, .num_vco = ARRAY_SIZE(mmpll_gfx_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -431,6 +444,7 @@ static struct clk_alpha_pll mmpll8_early = { static struct clk_alpha_pll_postdiv mmpll8 = { .offset = 0x4130, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll8", @@ -443,6 +457,7 @@ static struct clk_alpha_pll_postdiv mmpll8 = { static struct clk_alpha_pll mmpll9_early = { .offset = 0x4200, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_t_vco, .num_vco = ARRAY_SIZE(mmpll_t_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -455,6 +470,7 @@ static struct clk_alpha_pll mmpll9_early = { static struct clk_alpha_pll_postdiv mmpll9 = { .offset = 0x4200, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll9", diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index a2293ee09440..5ab295d2a3cb 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -19,10 +19,6 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ clk-dra7-atl.o dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o -ifdef CONFIG_ATAGS -obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o -endif - endif # CONFIG_ARCH_OMAP2PLUS obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c deleted file mode 100644 index 0fbf8a917955..000000000000 --- a/drivers/clk/ti/clk-3xxx-legacy.c +++ /dev/null @@ -1,4656 +0,0 @@ -/* - * OMAP3 Legacy clock data - * - * Copyright (C) 2014 Texas Instruments, Inc - * Tero Kristo (t-kristo@ti.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/clk/ti.h> - -#include "clock.h" - -static struct ti_clk_fixed virt_12m_ck_data = { - .frequency = 12000000, -}; - -static struct ti_clk virt_12m_ck = { - .name = "virt_12m_ck", - .type = TI_CLK_FIXED, - .data = &virt_12m_ck_data, -}; - -static struct ti_clk_fixed virt_13m_ck_data = { - .frequency = 13000000, -}; - -static struct ti_clk virt_13m_ck = { - .name = "virt_13m_ck", - .type = TI_CLK_FIXED, - .data = &virt_13m_ck_data, -}; - -static struct ti_clk_fixed virt_19200000_ck_data = { - .frequency = 19200000, -}; - -static struct ti_clk virt_19200000_ck = { - .name = "virt_19200000_ck", - .type = TI_CLK_FIXED, - .data = &virt_19200000_ck_data, -}; - -static struct ti_clk_fixed virt_26000000_ck_data = { - .frequency = 26000000, -}; - -static struct ti_clk virt_26000000_ck = { - .name = "virt_26000000_ck", - .type = TI_CLK_FIXED, - .data = &virt_26000000_ck_data, -}; - -static struct ti_clk_fixed virt_38_4m_ck_data = { - .frequency = 38400000, -}; - -static struct ti_clk virt_38_4m_ck = { - .name = "virt_38_4m_ck", - .type = TI_CLK_FIXED, - .data = &virt_38_4m_ck_data, -}; - -static struct ti_clk_fixed virt_16_8m_ck_data = { - .frequency = 16800000, -}; - -static struct ti_clk virt_16_8m_ck = { - .name = "virt_16_8m_ck", - .type = TI_CLK_FIXED, - .data = &virt_16_8m_ck_data, -}; - -static const char *osc_sys_ck_parents[] = { - "virt_12m_ck", - "virt_13m_ck", - "virt_19200000_ck", - "virt_26000000_ck", - "virt_38_4m_ck", - "virt_16_8m_ck", -}; - -static struct ti_clk_mux osc_sys_ck_data = { - .num_parents = ARRAY_SIZE(osc_sys_ck_parents), - .reg = 0xd40, - .module = TI_CLKM_PRM, - .parents = osc_sys_ck_parents, -}; - -static struct ti_clk osc_sys_ck = { - .name = "osc_sys_ck", - .type = TI_CLK_MUX, - .data = &osc_sys_ck_data, -}; - -static struct ti_clk_divider sys_ck_data = { - .parent = "osc_sys_ck", - .bit_shift = 6, - .max_div = 3, - .reg = 0x1270, - .module = TI_CLKM_PRM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk sys_ck = { - .name = "sys_ck", - .type = TI_CLK_DIVIDER, - .data = &sys_ck_data, -}; - -static const char *dpll3_ck_parents[] = { - "sys_ck", - "sys_ck", -}; - -static struct ti_clk_dpll dpll3_ck_data = { - .num_parents = ARRAY_SIZE(dpll3_ck_parents), - .control_reg = 0xd00, - .idlest_reg = 0xd20, - .mult_div1_reg = 0xd40, - .autoidle_reg = 0xd30, - .module = TI_CLKM_CM, - .parents = dpll3_ck_parents, - .flags = CLKF_CORE, - .freqsel_mask = 0xf0, - .div1_mask = 0x7f00, - .idlest_mask = 0x1, - .auto_recal_bit = 0x3, - .max_divider = 0x80, - .min_divider = 0x1, - .recal_en_bit = 0x5, - .max_multiplier = 0x7ff, - .enable_mask = 0x7, - .mult_mask = 0x7ff0000, - .recal_st_bit = 0x5, - .autoidle_mask = 0x7, -}; - -static struct ti_clk dpll3_ck = { - .name = "dpll3_ck", - .clkdm_name = "dpll3_clkdm", - .type = TI_CLK_DPLL, - .data = &dpll3_ck_data, -}; - -static struct ti_clk_divider dpll3_m2_ck_data = { - .parent = "dpll3_ck", - .bit_shift = 27, - .max_div = 31, - .reg = 0xd40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll3_m2_ck = { - .name = "dpll3_m2_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll3_m2_ck_data, -}; - -static struct ti_clk_fixed_factor core_ck_data = { - .parent = "dpll3_m2_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk core_ck = { - .name = "core_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_ck_data, -}; - -static struct ti_clk_divider l3_ick_data = { - .parent = "core_ck", - .max_div = 3, - .reg = 0xa40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk l3_ick = { - .name = "l3_ick", - .type = TI_CLK_DIVIDER, - .data = &l3_ick_data, -}; - -static struct ti_clk_fixed_factor security_l3_ick_data = { - .parent = "l3_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk security_l3_ick = { - .name = "security_l3_ick", - .type = TI_CLK_FIXED_FACTOR, - .data = &security_l3_ick_data, -}; - -static struct ti_clk_fixed_factor wkup_l4_ick_data = { - .parent = "sys_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk wkup_l4_ick = { - .name = "wkup_l4_ick", - .type = TI_CLK_FIXED_FACTOR, - .data = &wkup_l4_ick_data, -}; - -static struct ti_clk_gate usim_ick_data = { - .parent = "wkup_l4_ick", - .bit_shift = 9, - .reg = 0xc10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk usim_ick = { - .name = "usim_ick", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &usim_ick_data, -}; - -static struct ti_clk_gate dss2_alwon_fck_data = { - .parent = "sys_ck", - .bit_shift = 1, - .reg = 0xe00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk dss2_alwon_fck = { - .name = "dss2_alwon_fck", - .clkdm_name = "dss_clkdm", - .type = TI_CLK_GATE, - .data = &dss2_alwon_fck_data, -}; - -static struct ti_clk_divider l4_ick_data = { - .parent = "l3_ick", - .bit_shift = 2, - .max_div = 3, - .reg = 0xa40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk l4_ick = { - .name = "l4_ick", - .type = TI_CLK_DIVIDER, - .data = &l4_ick_data, -}; - -static struct ti_clk_fixed_factor core_l4_ick_data = { - .parent = "l4_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk core_l4_ick = { - .name = "core_l4_ick", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_l4_ick_data, -}; - -static struct ti_clk_gate mmchs2_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 25, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mmchs2_ick = { - .name = "mmchs2_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mmchs2_ick_data, -}; - -static const char *dpll4_ck_parents[] = { - "sys_ck", - "sys_ck", -}; - -static struct ti_clk_dpll dpll4_ck_data = { - .num_parents = ARRAY_SIZE(dpll4_ck_parents), - .control_reg = 0xd00, - .idlest_reg = 0xd20, - .mult_div1_reg = 0xd44, - .autoidle_reg = 0xd30, - .module = TI_CLKM_CM, - .parents = dpll4_ck_parents, - .flags = CLKF_PER, - .freqsel_mask = 0xf00000, - .modes = 0x82, - .div1_mask = 0x7f, - .idlest_mask = 0x2, - .auto_recal_bit = 0x13, - .max_divider = 0x80, - .min_divider = 0x1, - .recal_en_bit = 0x6, - .max_multiplier = 0x7ff, - .enable_mask = 0x70000, - .mult_mask = 0x7ff00, - .recal_st_bit = 0x6, - .autoidle_mask = 0x38, -}; - -static struct ti_clk dpll4_ck = { - .name = "dpll4_ck", - .clkdm_name = "dpll4_clkdm", - .type = TI_CLK_DPLL, - .data = &dpll4_ck_data, -}; - -static struct ti_clk_divider dpll4_m2_ck_data = { - .parent = "dpll4_ck", - .max_div = 63, - .reg = 0xd48, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll4_m2_ck = { - .name = "dpll4_m2_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll4_m2_ck_data, -}; - -static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = { - .parent = "dpll4_m2_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll4_m2x2_mul_ck = { - .name = "dpll4_m2x2_mul_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll4_m2x2_mul_ck_data, -}; - -static struct ti_clk_gate dpll4_m2x2_ck_data = { - .parent = "dpll4_m2x2_mul_ck", - .bit_shift = 0x1b, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m2x2_ck = { - .name = "dpll4_m2x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m2x2_ck_data, -}; - -static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = { - .parent = "dpll4_m2x2_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk omap_96m_alwon_fck = { - .name = "omap_96m_alwon_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &omap_96m_alwon_fck_data, -}; - -static struct ti_clk_fixed_factor cm_96m_fck_data = { - .parent = "omap_96m_alwon_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk cm_96m_fck = { - .name = "cm_96m_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &cm_96m_fck_data, -}; - -static const char *omap_96m_fck_parents[] = { - "cm_96m_fck", - "sys_ck", -}; - -static struct ti_clk_mux omap_96m_fck_data = { - .bit_shift = 6, - .num_parents = ARRAY_SIZE(omap_96m_fck_parents), - .reg = 0xd40, - .module = TI_CLKM_CM, - .parents = omap_96m_fck_parents, -}; - -static struct ti_clk omap_96m_fck = { - .name = "omap_96m_fck", - .type = TI_CLK_MUX, - .data = &omap_96m_fck_data, -}; - -static struct ti_clk_fixed_factor core_96m_fck_data = { - .parent = "omap_96m_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk core_96m_fck = { - .name = "core_96m_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_96m_fck_data, -}; - -static struct ti_clk_gate mspro_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 23, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mspro_fck = { - .name = "mspro_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mspro_fck_data, -}; - -static struct ti_clk_gate dss_ick_3430es2_data = { - .parent = "l4_ick", - .bit_shift = 0, - .reg = 0xe10, - .module = TI_CLKM_CM, - .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk dss_ick_3430es2 = { - .name = "dss_ick", - .clkdm_name = "dss_clkdm", - .type = TI_CLK_GATE, - .data = &dss_ick_3430es2_data, -}; - -static struct ti_clk_gate uart4_ick_am35xx_data = { - .parent = "core_l4_ick", - .bit_shift = 23, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk uart4_ick_am35xx = { - .name = "uart4_ick_am35xx", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &uart4_ick_am35xx_data, -}; - -static struct ti_clk_fixed_factor security_l4_ick2_data = { - .parent = "l4_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk security_l4_ick2 = { - .name = "security_l4_ick2", - .type = TI_CLK_FIXED_FACTOR, - .data = &security_l4_ick2_data, -}; - -static struct ti_clk_gate aes1_ick_data = { - .parent = "security_l4_ick2", - .bit_shift = 3, - .reg = 0xa14, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk aes1_ick = { - .name = "aes1_ick", - .type = TI_CLK_GATE, - .data = &aes1_ick_data, -}; - -static const char *dpll5_ck_parents[] = { - "sys_ck", - "sys_ck", -}; - -static struct ti_clk_dpll dpll5_ck_data = { - .num_parents = ARRAY_SIZE(dpll5_ck_parents), - .control_reg = 0xd04, - .idlest_reg = 0xd24, - .mult_div1_reg = 0xd4c, - .autoidle_reg = 0xd34, - .module = TI_CLKM_CM, - .parents = dpll5_ck_parents, - .freqsel_mask = 0xf0, - .modes = 0x82, - .div1_mask = 0x7f, - .idlest_mask = 0x1, - .auto_recal_bit = 0x3, - .max_divider = 0x80, - .min_divider = 0x1, - .recal_en_bit = 0x19, - .max_multiplier = 0x7ff, - .enable_mask = 0x7, - .mult_mask = 0x7ff00, - .recal_st_bit = 0x19, - .autoidle_mask = 0x7, -}; - -static struct ti_clk dpll5_ck = { - .name = "dpll5_ck", - .clkdm_name = "dpll5_clkdm", - .type = TI_CLK_DPLL, - .data = &dpll5_ck_data, -}; - -static struct ti_clk_divider dpll5_m2_ck_data = { - .parent = "dpll5_ck", - .max_div = 31, - .reg = 0xd50, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll5_m2_ck = { - .name = "dpll5_m2_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll5_m2_ck_data, -}; - -static struct ti_clk_gate usbhost_120m_fck_data = { - .parent = "dpll5_m2_ck", - .bit_shift = 1, - .reg = 0x1400, - .module = TI_CLKM_CM, -}; - -static struct ti_clk usbhost_120m_fck = { - .name = "usbhost_120m_fck", - .clkdm_name = "usbhost_clkdm", - .type = TI_CLK_GATE, - .data = &usbhost_120m_fck_data, -}; - -static struct ti_clk_fixed_factor cm_96m_d2_fck_data = { - .parent = "cm_96m_fck", - .div = 2, - .mult = 1, -}; - -static struct ti_clk cm_96m_d2_fck = { - .name = "cm_96m_d2_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &cm_96m_d2_fck_data, -}; - -static struct ti_clk_fixed sys_altclk_data = { - .frequency = 0x0, -}; - -static struct ti_clk sys_altclk = { - .name = "sys_altclk", - .type = TI_CLK_FIXED, - .data = &sys_altclk_data, -}; - -static const char *omap_48m_fck_parents[] = { - "cm_96m_d2_fck", - "sys_altclk", -}; - -static struct ti_clk_mux omap_48m_fck_data = { - .bit_shift = 3, - .num_parents = ARRAY_SIZE(omap_48m_fck_parents), - .reg = 0xd40, - .module = TI_CLKM_CM, - .parents = omap_48m_fck_parents, -}; - -static struct ti_clk omap_48m_fck = { - .name = "omap_48m_fck", - .type = TI_CLK_MUX, - .data = &omap_48m_fck_data, -}; - -static struct ti_clk_fixed_factor core_48m_fck_data = { - .parent = "omap_48m_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk core_48m_fck = { - .name = "core_48m_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_48m_fck_data, -}; - -static struct ti_clk_fixed mcbsp_clks_data = { - .frequency = 0x0, -}; - -static struct ti_clk mcbsp_clks = { - .name = "mcbsp_clks", - .type = TI_CLK_FIXED, - .data = &mcbsp_clks_data, -}; - -static struct ti_clk_gate mcbsp2_gate_fck_data = { - .parent = "mcbsp_clks", - .bit_shift = 0, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_fixed_factor per_96m_fck_data = { - .parent = "omap_96m_alwon_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk per_96m_fck = { - .name = "per_96m_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &per_96m_fck_data, -}; - -static const char *mcbsp2_mux_fck_parents[] = { - "per_96m_fck", - "mcbsp_clks", -}; - -static struct ti_clk_mux mcbsp2_mux_fck_data = { - .bit_shift = 6, - .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents), - .reg = 0x274, - .module = TI_CLKM_SCRM, - .parents = mcbsp2_mux_fck_parents, -}; - -static struct ti_clk_composite mcbsp2_fck_data = { - .mux = &mcbsp2_mux_fck_data, - .gate = &mcbsp2_gate_fck_data, -}; - -static struct ti_clk mcbsp2_fck = { - .name = "mcbsp2_fck", - .type = TI_CLK_COMPOSITE, - .data = &mcbsp2_fck_data, -}; - -static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = { - .parent = "dpll3_m2_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll3_m2x2_ck = { - .name = "dpll3_m2x2_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll3_m2x2_ck_data, -}; - -static struct ti_clk_fixed_factor corex2_fck_data = { - .parent = "dpll3_m2x2_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk corex2_fck = { - .name = "corex2_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &corex2_fck_data, -}; - -static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = { - .parent = "corex2_fck", - .bit_shift = 0, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_NO_WAIT, -}; - -static int ssi_ssr_div_fck_3430es1_divs[] = { - 0, - 1, - 2, - 3, - 4, - 0, - 6, - 0, - 8, -}; - -static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = { - .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs), - .parent = "corex2_fck", - .bit_shift = 8, - .dividers = ssi_ssr_div_fck_3430es1_divs, - .reg = 0xa40, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_composite ssi_ssr_fck_3430es1_data = { - .gate = &ssi_ssr_gate_fck_3430es1_data, - .divider = &ssi_ssr_div_fck_3430es1_data, -}; - -static struct ti_clk ssi_ssr_fck_3430es1 = { - .name = "ssi_ssr_fck", - .type = TI_CLK_COMPOSITE, - .data = &ssi_ssr_fck_3430es1_data, -}; - -static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = { - .parent = "ssi_ssr_fck", - .div = 2, - .mult = 1, -}; - -static struct ti_clk ssi_sst_fck_3430es1 = { - .name = "ssi_sst_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &ssi_sst_fck_3430es1_data, -}; - -static struct ti_clk_fixed omap_32k_fck_data = { - .frequency = 32768, -}; - -static struct ti_clk omap_32k_fck = { - .name = "omap_32k_fck", - .type = TI_CLK_FIXED, - .data = &omap_32k_fck_data, -}; - -static struct ti_clk_fixed_factor per_32k_alwon_fck_data = { - .parent = "omap_32k_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk per_32k_alwon_fck = { - .name = "per_32k_alwon_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &per_32k_alwon_fck_data, -}; - -static struct ti_clk_gate gpio5_dbck_data = { - .parent = "per_32k_alwon_fck", - .bit_shift = 16, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk gpio5_dbck = { - .name = "gpio5_dbck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio5_dbck_data, -}; - -static struct ti_clk_gate gpt1_ick_data = { - .parent = "wkup_l4_ick", - .bit_shift = 0, - .reg = 0xc10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt1_ick = { - .name = "gpt1_ick", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &gpt1_ick_data, -}; - -static struct ti_clk_gate mcspi3_fck_data = { - .parent = "core_48m_fck", - .bit_shift = 20, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mcspi3_fck = { - .name = "mcspi3_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi3_fck_data, -}; - -static struct ti_clk_gate gpt2_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 3, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static const char *gpt2_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt2_mux_fck_data = { - .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt2_mux_fck_parents, -}; - -static struct ti_clk_composite gpt2_fck_data = { - .mux = &gpt2_mux_fck_data, - .gate = &gpt2_gate_fck_data, -}; - -static struct ti_clk gpt2_fck = { - .name = "gpt2_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt2_fck_data, -}; - -static struct ti_clk_gate gpt10_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 11, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt10_ick = { - .name = "gpt10_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &gpt10_ick_data, -}; - -static struct ti_clk_gate uart2_fck_data = { - .parent = "core_48m_fck", - .bit_shift = 14, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk uart2_fck = { - .name = "uart2_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &uart2_fck_data, -}; - -static struct ti_clk_fixed_factor sr_l4_ick_data = { - .parent = "l4_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk sr_l4_ick = { - .name = "sr_l4_ick", - .type = TI_CLK_FIXED_FACTOR, - .data = &sr_l4_ick_data, -}; - -static struct ti_clk_fixed_factor omap_96m_d8_fck_data = { - .parent = "omap_96m_fck", - .div = 8, - .mult = 1, -}; - -static struct ti_clk omap_96m_d8_fck = { - .name = "omap_96m_d8_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &omap_96m_d8_fck_data, -}; - -static struct ti_clk_divider dpll4_m5_ck_data = { - .parent = "dpll4_ck", - .max_div = 63, - .reg = 0xf40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll4_m5_ck = { - .name = "dpll4_m5_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll4_m5_ck_data, -}; - -static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = { - .parent = "dpll4_m5_ck", - .div = 1, - .mult = 2, - .flags = CLKF_SET_RATE_PARENT, -}; - -static struct ti_clk dpll4_m5x2_mul_ck = { - .name = "dpll4_m5x2_mul_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll4_m5x2_mul_ck_data, -}; - -static struct ti_clk_gate dpll4_m5x2_ck_data = { - .parent = "dpll4_m5x2_mul_ck", - .bit_shift = 0x1e, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m5x2_ck = { - .name = "dpll4_m5x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m5x2_ck_data, -}; - -static struct ti_clk_gate cam_mclk_data = { - .parent = "dpll4_m5x2_ck", - .bit_shift = 0, - .reg = 0xf00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_RATE_PARENT, -}; - -static struct ti_clk cam_mclk = { - .name = "cam_mclk", - .type = TI_CLK_GATE, - .data = &cam_mclk_data, -}; - -static struct ti_clk_gate mcbsp3_gate_fck_data = { - .parent = "mcbsp_clks", - .bit_shift = 1, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static const char *mcbsp3_mux_fck_parents[] = { - "per_96m_fck", - "mcbsp_clks", -}; - -static struct ti_clk_mux mcbsp3_mux_fck_data = { - .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents), - .reg = 0x2d8, - .module = TI_CLKM_SCRM, - .parents = mcbsp3_mux_fck_parents, -}; - -static struct ti_clk_composite mcbsp3_fck_data = { - .mux = &mcbsp3_mux_fck_data, - .gate = &mcbsp3_gate_fck_data, -}; - -static struct ti_clk mcbsp3_fck = { - .name = "mcbsp3_fck", - .type = TI_CLK_COMPOSITE, - .data = &mcbsp3_fck_data, -}; - -static struct ti_clk_gate csi2_96m_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 1, - .reg = 0xf00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk csi2_96m_fck = { - .name = "csi2_96m_fck", - .clkdm_name = "cam_clkdm", - .type = TI_CLK_GATE, - .data = &csi2_96m_fck_data, -}; - -static struct ti_clk_gate gpt9_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 10, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static const char *gpt9_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt9_mux_fck_data = { - .bit_shift = 7, - .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt9_mux_fck_parents, -}; - -static struct ti_clk_composite gpt9_fck_data = { - .mux = &gpt9_mux_fck_data, - .gate = &gpt9_gate_fck_data, -}; - -static struct ti_clk gpt9_fck = { - .name = "gpt9_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt9_fck_data, -}; - -static struct ti_clk_divider dpll3_m3_ck_data = { - .parent = "dpll3_ck", - .bit_shift = 16, - .max_div = 31, - .reg = 0x1140, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll3_m3_ck = { - .name = "dpll3_m3_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll3_m3_ck_data, -}; - -static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = { - .parent = "dpll3_m3_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll3_m3x2_mul_ck = { - .name = "dpll3_m3x2_mul_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll3_m3x2_mul_ck_data, -}; - -static struct ti_clk_gate sr2_fck_data = { - .parent = "sys_ck", - .bit_shift = 7, - .reg = 0xc00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk sr2_fck = { - .name = "sr2_fck", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &sr2_fck_data, -}; - -static struct ti_clk_fixed pclk_ck_data = { - .frequency = 27000000, -}; - -static struct ti_clk pclk_ck = { - .name = "pclk_ck", - .type = TI_CLK_FIXED, - .data = &pclk_ck_data, -}; - -static struct ti_clk_gate wdt2_ick_data = { - .parent = "wkup_l4_ick", - .bit_shift = 5, - .reg = 0xc10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk wdt2_ick = { - .name = "wdt2_ick", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &wdt2_ick_data, -}; - -static struct ti_clk_fixed_factor core_l3_ick_data = { - .parent = "l3_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk core_l3_ick = { - .name = "core_l3_ick", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_l3_ick_data, -}; - -static struct ti_clk_gate mcspi4_fck_data = { - .parent = "core_48m_fck", - .bit_shift = 21, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mcspi4_fck = { - .name = "mcspi4_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi4_fck_data, -}; - -static struct ti_clk_fixed_factor per_48m_fck_data = { - .parent = "omap_48m_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk per_48m_fck = { - .name = "per_48m_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &per_48m_fck_data, -}; - -static struct ti_clk_gate uart4_fck_data = { - .parent = "per_48m_fck", - .bit_shift = 18, - .reg = 0x1000, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk uart4_fck = { - .name = "uart4_fck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &uart4_fck_data, -}; - -static struct ti_clk_fixed_factor omap_96m_d10_fck_data = { - .parent = "omap_96m_fck", - .div = 10, - .mult = 1, -}; - -static struct ti_clk omap_96m_d10_fck = { - .name = "omap_96m_d10_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &omap_96m_d10_fck_data, -}; - -static struct ti_clk_gate usim_gate_fck_data = { - .parent = "omap_96m_fck", - .bit_shift = 9, - .reg = 0xc00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_fixed_factor per_l4_ick_data = { - .parent = "l4_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk per_l4_ick = { - .name = "per_l4_ick", - .type = TI_CLK_FIXED_FACTOR, - .data = &per_l4_ick_data, -}; - -static struct ti_clk_gate gpt5_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 6, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt5_ick = { - .name = "gpt5_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt5_ick_data, -}; - -static struct ti_clk_gate mcspi2_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 19, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcspi2_ick = { - .name = "mcspi2_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi2_ick_data, -}; - -static struct ti_clk_fixed_factor ssi_l4_ick_data = { - .parent = "l4_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk ssi_l4_ick = { - .name = "ssi_l4_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_FIXED_FACTOR, - .data = &ssi_l4_ick_data, -}; - -static struct ti_clk_gate ssi_ick_3430es1_data = { - .parent = "ssi_l4_ick", - .bit_shift = 0, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, -}; - -static struct ti_clk ssi_ick_3430es1 = { - .name = "ssi_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &ssi_ick_3430es1_data, -}; - -static struct ti_clk_gate i2c2_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 16, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk i2c2_fck = { - .name = "i2c2_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &i2c2_fck_data, -}; - -static struct ti_clk_divider dpll1_fck_data = { - .parent = "core_ck", - .bit_shift = 19, - .max_div = 7, - .reg = 0x940, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll1_fck = { - .name = "dpll1_fck", - .type = TI_CLK_DIVIDER, - .data = &dpll1_fck_data, -}; - -static const char *dpll1_ck_parents[] = { - "sys_ck", - "dpll1_fck", -}; - -static struct ti_clk_dpll dpll1_ck_data = { - .num_parents = ARRAY_SIZE(dpll1_ck_parents), - .control_reg = 0x904, - .idlest_reg = 0x924, - .mult_div1_reg = 0x940, - .autoidle_reg = 0x934, - .module = TI_CLKM_CM, - .parents = dpll1_ck_parents, - .freqsel_mask = 0xf0, - .modes = 0xa0, - .div1_mask = 0x7f, - .idlest_mask = 0x1, - .auto_recal_bit = 0x3, - .max_divider = 0x80, - .min_divider = 0x1, - .recal_en_bit = 0x7, - .max_multiplier = 0x7ff, - .enable_mask = 0x7, - .mult_mask = 0x7ff00, - .recal_st_bit = 0x7, - .autoidle_mask = 0x7, -}; - -static struct ti_clk dpll1_ck = { - .name = "dpll1_ck", - .clkdm_name = "dpll1_clkdm", - .type = TI_CLK_DPLL, - .data = &dpll1_ck_data, -}; - -static struct ti_clk_fixed secure_32k_fck_data = { - .frequency = 32768, -}; - -static struct ti_clk secure_32k_fck = { - .name = "secure_32k_fck", - .type = TI_CLK_FIXED, - .data = &secure_32k_fck_data, -}; - -static struct ti_clk_gate gpio5_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 16, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpio5_ick = { - .name = "gpio5_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio5_ick_data, -}; - -static struct ti_clk_divider dpll4_m4_ck_data = { - .parent = "dpll4_ck", - .max_div = 32, - .reg = 0xe40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll4_m4_ck = { - .name = "dpll4_m4_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll4_m4_ck_data, -}; - -static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = { - .parent = "dpll4_m4_ck", - .div = 1, - .mult = 2, - .flags = CLKF_SET_RATE_PARENT, -}; - -static struct ti_clk dpll4_m4x2_mul_ck = { - .name = "dpll4_m4x2_mul_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll4_m4x2_mul_ck_data, -}; - -static struct ti_clk_gate dpll4_m4x2_ck_data = { - .parent = "dpll4_m4x2_mul_ck", - .bit_shift = 0x1d, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m4x2_ck = { - .name = "dpll4_m4x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m4x2_ck_data, -}; - -static struct ti_clk_gate dss1_alwon_fck_3430es2_data = { - .parent = "dpll4_m4x2_ck", - .bit_shift = 0, - .reg = 0xe00, - .module = TI_CLKM_CM, - .flags = CLKF_DSS | CLKF_SET_RATE_PARENT, -}; - -static struct ti_clk dss1_alwon_fck_3430es2 = { - .name = "dss1_alwon_fck", - .clkdm_name = "dss_clkdm", - .type = TI_CLK_GATE, - .data = &dss1_alwon_fck_3430es2_data, -}; - -static struct ti_clk_gate uart3_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 11, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk uart3_ick = { - .name = "uart3_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &uart3_ick_data, -}; - -static struct ti_clk_divider dpll4_m3_ck_data = { - .parent = "dpll4_ck", - .bit_shift = 8, - .max_div = 32, - .reg = 0xe40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll4_m3_ck = { - .name = "dpll4_m3_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll4_m3_ck_data, -}; - -static struct ti_clk_gate mcbsp3_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 1, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcbsp3_ick = { - .name = "mcbsp3_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &mcbsp3_ick_data, -}; - -static struct ti_clk_gate gpio3_dbck_data = { - .parent = "per_32k_alwon_fck", - .bit_shift = 14, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk gpio3_dbck = { - .name = "gpio3_dbck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio3_dbck_data, -}; - -static struct ti_clk_gate fac_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 8, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk fac_ick = { - .name = "fac_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &fac_ick_data, -}; - -static struct ti_clk_gate clkout2_src_gate_ck_data = { - .parent = "core_ck", - .bit_shift = 7, - .reg = 0xd70, - .module = TI_CLKM_CM, - .flags = CLKF_NO_WAIT, -}; - -static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = { - .parent = "dpll4_m3_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll4_m3x2_mul_ck = { - .name = "dpll4_m3x2_mul_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll4_m3x2_mul_ck_data, -}; - -static struct ti_clk_gate dpll4_m3x2_ck_data = { - .parent = "dpll4_m3x2_mul_ck", - .bit_shift = 0x1c, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m3x2_ck = { - .name = "dpll4_m3x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m3x2_ck_data, -}; - -static const char *omap_54m_fck_parents[] = { - "dpll4_m3x2_ck", - "sys_altclk", -}; - -static struct ti_clk_mux omap_54m_fck_data = { - .bit_shift = 5, - .num_parents = ARRAY_SIZE(omap_54m_fck_parents), - .reg = 0xd40, - .module = TI_CLKM_CM, - .parents = omap_54m_fck_parents, -}; - -static struct ti_clk omap_54m_fck = { - .name = "omap_54m_fck", - .type = TI_CLK_MUX, - .data = &omap_54m_fck_data, -}; - -static const char *clkout2_src_mux_ck_parents[] = { - "core_ck", - "sys_ck", - "cm_96m_fck", - "omap_54m_fck", -}; - -static struct ti_clk_mux clkout2_src_mux_ck_data = { - .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents), - .reg = 0xd70, - .module = TI_CLKM_CM, - .parents = clkout2_src_mux_ck_parents, -}; - -static struct ti_clk_composite clkout2_src_ck_data = { - .mux = &clkout2_src_mux_ck_data, - .gate = &clkout2_src_gate_ck_data, -}; - -static struct ti_clk clkout2_src_ck = { - .name = "clkout2_src_ck", - .type = TI_CLK_COMPOSITE, - .data = &clkout2_src_ck_data, -}; - -static struct ti_clk_gate i2c1_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 15, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk i2c1_fck = { - .name = "i2c1_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &i2c1_fck_data, -}; - -static struct ti_clk_gate wdt3_fck_data = { - .parent = "per_32k_alwon_fck", - .bit_shift = 12, - .reg = 0x1000, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk wdt3_fck = { - .name = "wdt3_fck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &wdt3_fck_data, -}; - -static struct ti_clk_gate gpt7_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 8, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static const char *gpt7_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt7_mux_fck_data = { - .bit_shift = 5, - .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt7_mux_fck_parents, -}; - -static struct ti_clk_composite gpt7_fck_data = { - .mux = &gpt7_mux_fck_data, - .gate = &gpt7_gate_fck_data, -}; - -static struct ti_clk gpt7_fck = { - .name = "gpt7_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt7_fck_data, -}; - -static struct ti_clk_gate usb_l4_gate_ick_data = { - .parent = "l4_ick", - .bit_shift = 5, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_INTERFACE, -}; - -static struct ti_clk_divider usb_l4_div_ick_data = { - .parent = "l4_ick", - .bit_shift = 4, - .max_div = 1, - .reg = 0xa40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk_composite usb_l4_ick_data = { - .gate = &usb_l4_gate_ick_data, - .divider = &usb_l4_div_ick_data, -}; - -static struct ti_clk usb_l4_ick = { - .name = "usb_l4_ick", - .type = TI_CLK_COMPOSITE, - .data = &usb_l4_ick_data, -}; - -static struct ti_clk_gate uart4_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 18, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk uart4_ick = { - .name = "uart4_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &uart4_ick_data, -}; - -static struct ti_clk_fixed dummy_ck_data = { - .frequency = 0, -}; - -static struct ti_clk dummy_ck = { - .name = "dummy_ck", - .type = TI_CLK_FIXED, - .data = &dummy_ck_data, -}; - -static const char *gpt3_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt3_mux_fck_data = { - .bit_shift = 1, - .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt3_mux_fck_parents, -}; - -static struct ti_clk_gate gpt9_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 10, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt9_ick = { - .name = "gpt9_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt9_ick_data, -}; - -static struct ti_clk_gate gpt10_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 11, - .reg = 0xa00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_gate dss_ick_3430es1_data = { - .parent = "l4_ick", - .bit_shift = 0, - .reg = 0xe10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, -}; - -static struct ti_clk dss_ick_3430es1 = { - .name = "dss_ick", - .clkdm_name = "dss_clkdm", - .type = TI_CLK_GATE, - .data = &dss_ick_3430es1_data, -}; - -static struct ti_clk_gate gpt11_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 12, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt11_ick = { - .name = "gpt11_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &gpt11_ick_data, -}; - -static struct ti_clk_divider dpll2_fck_data = { - .parent = "core_ck", - .bit_shift = 19, - .max_div = 7, - .reg = 0x40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll2_fck = { - .name = "dpll2_fck", - .type = TI_CLK_DIVIDER, - .data = &dpll2_fck_data, -}; - -static struct ti_clk_gate uart1_fck_data = { - .parent = "core_48m_fck", - .bit_shift = 13, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk uart1_fck = { - .name = "uart1_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &uart1_fck_data, -}; - -static struct ti_clk_gate hsotgusb_ick_3430es1_data = { - .parent = "core_l3_ick", - .bit_shift = 4, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, -}; - -static struct ti_clk hsotgusb_ick_3430es1 = { - .name = "hsotgusb_ick_3430es1", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &hsotgusb_ick_3430es1_data, -}; - -static struct ti_clk_gate gpio2_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 13, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpio2_ick = { - .name = "gpio2_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio2_ick_data, -}; - -static struct ti_clk_gate mmchs1_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 24, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mmchs1_ick = { - .name = "mmchs1_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mmchs1_ick_data, -}; - -static struct ti_clk_gate modem_fck_data = { - .parent = "sys_ck", - .bit_shift = 31, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk modem_fck = { - .name = "modem_fck", - .clkdm_name = "d2d_clkdm", - .type = TI_CLK_GATE, - .data = &modem_fck_data, -}; - -static struct ti_clk_gate mcbsp4_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 2, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcbsp4_ick = { - .name = "mcbsp4_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &mcbsp4_ick_data, -}; - -static struct ti_clk_gate gpio1_ick_data = { - .parent = "wkup_l4_ick", - .bit_shift = 3, - .reg = 0xc10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpio1_ick = { - .name = "gpio1_ick", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &gpio1_ick_data, -}; - -static const char *gpt6_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt6_mux_fck_data = { - .bit_shift = 4, - .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt6_mux_fck_parents, -}; - -static struct ti_clk_fixed_factor dpll1_x2_ck_data = { - .parent = "dpll1_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll1_x2_ck = { - .name = "dpll1_x2_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll1_x2_ck_data, -}; - -static struct ti_clk_divider dpll1_x2m2_ck_data = { - .parent = "dpll1_x2_ck", - .max_div = 31, - .reg = 0x944, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll1_x2m2_ck = { - .name = "dpll1_x2m2_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll1_x2m2_ck_data, -}; - -static struct ti_clk_fixed_factor mpu_ck_data = { - .parent = "dpll1_x2m2_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk mpu_ck = { - .name = "mpu_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &mpu_ck_data, -}; - -static struct ti_clk_divider arm_fck_data = { - .parent = "mpu_ck", - .max_div = 2, - .reg = 0x924, - .module = TI_CLKM_CM, -}; - -static struct ti_clk arm_fck = { - .name = "arm_fck", - .type = TI_CLK_DIVIDER, - .data = &arm_fck_data, -}; - -static struct ti_clk_fixed_factor core_d3_ck_data = { - .parent = "core_ck", - .div = 3, - .mult = 1, -}; - -static struct ti_clk core_d3_ck = { - .name = "core_d3_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_d3_ck_data, -}; - -static struct ti_clk_gate gpt11_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 12, - .reg = 0xa00, - .module = TI_CLKM_CM, -}; - -static const char *gpt11_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt11_mux_fck_data = { - .bit_shift = 7, - .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents), - .reg = 0xa40, - .module = TI_CLKM_CM, - .parents = gpt11_mux_fck_parents, -}; - -static struct ti_clk_composite gpt11_fck_data = { - .mux = &gpt11_mux_fck_data, - .gate = &gpt11_gate_fck_data, -}; - -static struct ti_clk gpt11_fck = { - .name = "gpt11_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt11_fck_data, -}; - -static struct ti_clk_fixed_factor core_d6_ck_data = { - .parent = "core_ck", - .div = 6, - .mult = 1, -}; - -static struct ti_clk core_d6_ck = { - .name = "core_d6_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_d6_ck_data, -}; - -static struct ti_clk_gate uart4_fck_am35xx_data = { - .parent = "core_48m_fck", - .bit_shift = 23, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk uart4_fck_am35xx = { - .name = "uart4_fck_am35xx", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &uart4_fck_am35xx_data, -}; - -static struct ti_clk_gate dpll3_m3x2_ck_data = { - .parent = "dpll3_m3x2_mul_ck", - .bit_shift = 0xc, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll3_m3x2_ck = { - .name = "dpll3_m3x2_ck", - .type = TI_CLK_GATE, - .data = &dpll3_m3x2_ck_data, -}; - -static struct ti_clk_fixed_factor emu_core_alwon_ck_data = { - .parent = "dpll3_m3x2_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk emu_core_alwon_ck = { - .name = "emu_core_alwon_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &emu_core_alwon_ck_data, -}; - -static struct ti_clk_divider dpll4_m6_ck_data = { - .parent = "dpll4_ck", - .bit_shift = 24, - .max_div = 63, - .reg = 0x1140, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll4_m6_ck = { - .name = "dpll4_m6_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll4_m6_ck_data, -}; - -static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = { - .parent = "dpll4_m6_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll4_m6x2_mul_ck = { - .name = "dpll4_m6x2_mul_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll4_m6x2_mul_ck_data, -}; - -static struct ti_clk_gate dpll4_m6x2_ck_data = { - .parent = "dpll4_m6x2_mul_ck", - .bit_shift = 0x1f, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m6x2_ck = { - .name = "dpll4_m6x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m6x2_ck_data, -}; - -static struct ti_clk_fixed_factor emu_per_alwon_ck_data = { - .parent = "dpll4_m6x2_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk emu_per_alwon_ck = { - .name = "emu_per_alwon_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &emu_per_alwon_ck_data, -}; - -static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = { - .parent = "mpu_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk emu_mpu_alwon_ck = { - .name = "emu_mpu_alwon_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &emu_mpu_alwon_ck_data, -}; - -static const char *emu_src_mux_ck_parents[] = { - "sys_ck", - "emu_core_alwon_ck", - "emu_per_alwon_ck", - "emu_mpu_alwon_ck", -}; - -static struct ti_clk_mux emu_src_mux_ck_data = { - .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents), - .reg = 0x1140, - .module = TI_CLKM_CM, - .parents = emu_src_mux_ck_parents, -}; - -static struct ti_clk emu_src_mux_ck = { - .name = "emu_src_mux_ck", - .type = TI_CLK_MUX, - .data = &emu_src_mux_ck_data, -}; - -static struct ti_clk_gate emu_src_ck_data = { - .parent = "emu_src_mux_ck", - .flags = CLKF_CLKDM, -}; - -static struct ti_clk emu_src_ck = { - .name = "emu_src_ck", - .clkdm_name = "emu_clkdm", - .type = TI_CLK_GATE, - .data = &emu_src_ck_data, -}; - -static struct ti_clk_divider atclk_fck_data = { - .parent = "emu_src_ck", - .bit_shift = 4, - .max_div = 3, - .reg = 0x1140, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk atclk_fck = { - .name = "atclk_fck", - .type = TI_CLK_DIVIDER, - .data = &atclk_fck_data, -}; - -static struct ti_clk_gate ipss_ick_data = { - .parent = "core_l3_ick", - .bit_shift = 4, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_AM35XX | CLKF_INTERFACE, -}; - -static struct ti_clk ipss_ick = { - .name = "ipss_ick", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &ipss_ick_data, -}; - -static struct ti_clk_gate emac_ick_data = { - .parent = "ipss_ick", - .bit_shift = 1, - .reg = 0x59c, - .module = TI_CLKM_SCRM, - .flags = CLKF_AM35XX, -}; - -static struct ti_clk emac_ick = { - .name = "emac_ick", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &emac_ick_data, -}; - -static struct ti_clk_gate vpfe_ick_data = { - .parent = "ipss_ick", - .bit_shift = 2, - .reg = 0x59c, - .module = TI_CLKM_SCRM, - .flags = CLKF_AM35XX, -}; - -static struct ti_clk vpfe_ick = { - .name = "vpfe_ick", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &vpfe_ick_data, -}; - -static const char *dpll2_ck_parents[] = { - "sys_ck", - "dpll2_fck", -}; - -static struct ti_clk_dpll dpll2_ck_data = { - .num_parents = ARRAY_SIZE(dpll2_ck_parents), - .control_reg = 0x4, - .idlest_reg = 0x24, - .mult_div1_reg = 0x40, - .autoidle_reg = 0x34, - .module = TI_CLKM_CM, - .parents = dpll2_ck_parents, - .freqsel_mask = 0xf0, - .modes = 0xa2, - .div1_mask = 0x7f, - .idlest_mask = 0x1, - .auto_recal_bit = 0x3, - .max_divider = 0x80, - .min_divider = 0x1, - .recal_en_bit = 0x8, - .max_multiplier = 0x7ff, - .enable_mask = 0x7, - .mult_mask = 0x7ff00, - .recal_st_bit = 0x8, - .autoidle_mask = 0x7, -}; - -static struct ti_clk dpll2_ck = { - .name = "dpll2_ck", - .clkdm_name = "dpll2_clkdm", - .type = TI_CLK_DPLL, - .data = &dpll2_ck_data, -}; - -static struct ti_clk_divider dpll2_m2_ck_data = { - .parent = "dpll2_ck", - .max_div = 31, - .reg = 0x44, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk dpll2_m2_ck = { - .name = "dpll2_m2_ck", - .type = TI_CLK_DIVIDER, - .data = &dpll2_m2_ck_data, -}; - -static const char *mcbsp4_mux_fck_parents[] = { - "per_96m_fck", - "mcbsp_clks", -}; - -static struct ti_clk_mux mcbsp4_mux_fck_data = { - .bit_shift = 2, - .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents), - .reg = 0x2d8, - .module = TI_CLKM_SCRM, - .parents = mcbsp4_mux_fck_parents, -}; - -static const char *mcbsp1_mux_fck_parents[] = { - "core_96m_fck", - "mcbsp_clks", -}; - -static struct ti_clk_mux mcbsp1_mux_fck_data = { - .bit_shift = 2, - .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents), - .reg = 0x274, - .module = TI_CLKM_SCRM, - .parents = mcbsp1_mux_fck_parents, -}; - -static struct ti_clk_gate gpt8_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 9, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_gate gpt8_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 9, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt8_ick = { - .name = "gpt8_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt8_ick_data, -}; - -static const char *gpt10_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt10_mux_fck_data = { - .bit_shift = 6, - .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents), - .reg = 0xa40, - .module = TI_CLKM_CM, - .parents = gpt10_mux_fck_parents, -}; - -static struct ti_clk_gate mmchs3_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 30, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mmchs3_ick = { - .name = "mmchs3_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mmchs3_ick_data, -}; - -static struct ti_clk_gate gpio3_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 14, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpio3_ick = { - .name = "gpio3_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio3_ick_data, -}; - -static const char *traceclk_src_fck_parents[] = { - "sys_ck", - "emu_core_alwon_ck", - "emu_per_alwon_ck", - "emu_mpu_alwon_ck", -}; - -static struct ti_clk_mux traceclk_src_fck_data = { - .bit_shift = 2, - .num_parents = ARRAY_SIZE(traceclk_src_fck_parents), - .reg = 0x1140, - .module = TI_CLKM_CM, - .parents = traceclk_src_fck_parents, -}; - -static struct ti_clk traceclk_src_fck = { - .name = "traceclk_src_fck", - .type = TI_CLK_MUX, - .data = &traceclk_src_fck_data, -}; - -static struct ti_clk_divider traceclk_fck_data = { - .parent = "traceclk_src_fck", - .bit_shift = 11, - .max_div = 7, - .reg = 0x1140, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk traceclk_fck = { - .name = "traceclk_fck", - .type = TI_CLK_DIVIDER, - .data = &traceclk_fck_data, -}; - -static struct ti_clk_gate mcbsp5_gate_fck_data = { - .parent = "mcbsp_clks", - .bit_shift = 10, - .reg = 0xa00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_gate sad2d_ick_data = { - .parent = "l3_ick", - .bit_shift = 3, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk sad2d_ick = { - .name = "sad2d_ick", - .clkdm_name = "d2d_clkdm", - .type = TI_CLK_GATE, - .data = &sad2d_ick_data, -}; - -static const char *gpt1_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt1_mux_fck_data = { - .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents), - .reg = 0xc40, - .module = TI_CLKM_CM, - .parents = gpt1_mux_fck_parents, -}; - -static struct ti_clk_gate hecc_ck_data = { - .parent = "sys_ck", - .bit_shift = 3, - .reg = 0x59c, - .module = TI_CLKM_SCRM, - .flags = CLKF_AM35XX, -}; - -static struct ti_clk hecc_ck = { - .name = "hecc_ck", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &hecc_ck_data, -}; - -static struct ti_clk_gate gpt1_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 0, - .reg = 0xc00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_composite gpt1_fck_data = { - .mux = &gpt1_mux_fck_data, - .gate = &gpt1_gate_fck_data, -}; - -static struct ti_clk gpt1_fck = { - .name = "gpt1_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt1_fck_data, -}; - -static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = { - .parent = "dpll4_m2x2_mul_ck", - .bit_shift = 0x1b, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m2x2_ck_omap36xx = { - .name = "dpll4_m2x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m2x2_ck_omap36xx_data, - .patch = &dpll4_m2x2_ck, -}; - -static struct ti_clk_divider gfx_l3_fck_data = { - .parent = "l3_ick", - .max_div = 7, - .reg = 0xb40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk gfx_l3_fck = { - .name = "gfx_l3_fck", - .type = TI_CLK_DIVIDER, - .data = &gfx_l3_fck_data, -}; - -static struct ti_clk_gate gfx_cg1_ck_data = { - .parent = "gfx_l3_fck", - .bit_shift = 1, - .reg = 0xb00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk gfx_cg1_ck = { - .name = "gfx_cg1_ck", - .clkdm_name = "gfx_3430es1_clkdm", - .type = TI_CLK_GATE, - .data = &gfx_cg1_ck_data, -}; - -static struct ti_clk_gate mailboxes_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 7, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mailboxes_ick = { - .name = "mailboxes_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mailboxes_ick_data, -}; - -static struct ti_clk_gate sha11_ick_data = { - .parent = "security_l4_ick2", - .bit_shift = 1, - .reg = 0xa14, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk sha11_ick = { - .name = "sha11_ick", - .type = TI_CLK_GATE, - .data = &sha11_ick_data, -}; - -static struct ti_clk_gate hsotgusb_ick_am35xx_data = { - .parent = "ipss_ick", - .bit_shift = 0, - .reg = 0x59c, - .module = TI_CLKM_SCRM, - .flags = CLKF_AM35XX, -}; - -static struct ti_clk hsotgusb_ick_am35xx = { - .name = "hsotgusb_ick_am35xx", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &hsotgusb_ick_am35xx_data, -}; - -static struct ti_clk_gate mmchs3_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 30, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mmchs3_fck = { - .name = "mmchs3_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mmchs3_fck_data, -}; - -static struct ti_clk_divider pclk_fck_data = { - .parent = "emu_src_ck", - .bit_shift = 8, - .max_div = 7, - .reg = 0x1140, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk pclk_fck = { - .name = "pclk_fck", - .type = TI_CLK_DIVIDER, - .data = &pclk_fck_data, -}; - -static const char *dpll4_ck_omap36xx_parents[] = { - "sys_ck", - "sys_ck", -}; - -static struct ti_clk_dpll dpll4_ck_omap36xx_data = { - .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents), - .control_reg = 0xd00, - .idlest_reg = 0xd20, - .mult_div1_reg = 0xd44, - .autoidle_reg = 0xd30, - .module = TI_CLKM_CM, - .parents = dpll4_ck_omap36xx_parents, - .modes = 0x82, - .div1_mask = 0x7f, - .idlest_mask = 0x2, - .auto_recal_bit = 0x13, - .max_divider = 0x80, - .min_divider = 0x1, - .recal_en_bit = 0x6, - .max_multiplier = 0xfff, - .enable_mask = 0x70000, - .mult_mask = 0xfff00, - .recal_st_bit = 0x6, - .autoidle_mask = 0x38, - .sddiv_mask = 0xff000000, - .dco_mask = 0xe00000, - .flags = CLKF_PER | CLKF_J_TYPE, -}; - -static struct ti_clk dpll4_ck_omap36xx = { - .name = "dpll4_ck", - .type = TI_CLK_DPLL, - .data = &dpll4_ck_omap36xx_data, - .patch = &dpll4_ck, -}; - -static struct ti_clk_gate uart3_fck_data = { - .parent = "per_48m_fck", - .bit_shift = 11, - .reg = 0x1000, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk uart3_fck = { - .name = "uart3_fck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &uart3_fck_data, -}; - -static struct ti_clk_fixed_factor wkup_32k_fck_data = { - .parent = "omap_32k_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk wkup_32k_fck = { - .name = "wkup_32k_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &wkup_32k_fck_data, -}; - -static struct ti_clk_gate sys_clkout1_data = { - .parent = "osc_sys_ck", - .bit_shift = 7, - .reg = 0xd70, - .module = TI_CLKM_PRM, -}; - -static struct ti_clk sys_clkout1 = { - .name = "sys_clkout1", - .type = TI_CLK_GATE, - .data = &sys_clkout1_data, -}; - -static struct ti_clk_fixed_factor gpmc_fck_data = { - .parent = "core_l3_ick", - .div = 1, - .mult = 1, -}; - -static struct ti_clk gpmc_fck = { - .name = "gpmc_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &gpmc_fck_data, -}; - -static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = { - .parent = "dpll5_m2_ck", - .div = 20, - .mult = 1, -}; - -static struct ti_clk dpll5_m2_d20_ck = { - .name = "dpll5_m2_d20_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll5_m2_d20_ck_data, -}; - -static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = { - .parent = "dpll4_m5x2_mul_ck", - .bit_shift = 0x1e, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m5x2_ck_omap36xx = { - .name = "dpll4_m5x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m5x2_ck_omap36xx_data, - .patch = &dpll4_m5x2_ck, -}; - -static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = { - .parent = "corex2_fck", - .bit_shift = 0, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_NO_WAIT, -}; - -static struct ti_clk_gate uart1_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 13, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk uart1_ick = { - .name = "uart1_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &uart1_ick_data, -}; - -static struct ti_clk_gate iva2_ck_data = { - .parent = "dpll2_m2_ck", - .bit_shift = 0, - .reg = 0x0, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk iva2_ck = { - .name = "iva2_ck", - .clkdm_name = "iva2_clkdm", - .type = TI_CLK_GATE, - .data = &iva2_ck_data, -}; - -static struct ti_clk_gate pka_ick_data = { - .parent = "security_l3_ick", - .bit_shift = 4, - .reg = 0xa14, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk pka_ick = { - .name = "pka_ick", - .type = TI_CLK_GATE, - .data = &pka_ick_data, -}; - -static struct ti_clk_gate gpt12_ick_data = { - .parent = "wkup_l4_ick", - .bit_shift = 1, - .reg = 0xc10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt12_ick = { - .name = "gpt12_ick", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &gpt12_ick_data, -}; - -static const char *mcbsp5_mux_fck_parents[] = { - "core_96m_fck", - "mcbsp_clks", -}; - -static struct ti_clk_mux mcbsp5_mux_fck_data = { - .bit_shift = 4, - .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents), - .reg = 0x2d8, - .module = TI_CLKM_SCRM, - .parents = mcbsp5_mux_fck_parents, -}; - -static struct ti_clk_composite mcbsp5_fck_data = { - .mux = &mcbsp5_mux_fck_data, - .gate = &mcbsp5_gate_fck_data, -}; - -static struct ti_clk mcbsp5_fck = { - .name = "mcbsp5_fck", - .type = TI_CLK_COMPOSITE, - .data = &mcbsp5_fck_data, -}; - -static struct ti_clk_gate usbhost_48m_fck_data = { - .parent = "omap_48m_fck", - .bit_shift = 0, - .reg = 0x1400, - .module = TI_CLKM_CM, - .flags = CLKF_DSS, -}; - -static struct ti_clk usbhost_48m_fck = { - .name = "usbhost_48m_fck", - .clkdm_name = "usbhost_clkdm", - .type = TI_CLK_GATE, - .data = &usbhost_48m_fck_data, -}; - -static struct ti_clk_gate des1_ick_data = { - .parent = "security_l4_ick2", - .bit_shift = 0, - .reg = 0xa14, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk des1_ick = { - .name = "des1_ick", - .type = TI_CLK_GATE, - .data = &des1_ick_data, -}; - -static struct ti_clk_gate sgx_gate_fck_data = { - .parent = "core_ck", - .bit_shift = 1, - .reg = 0xb00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_fixed_factor core_d4_ck_data = { - .parent = "core_ck", - .div = 4, - .mult = 1, -}; - -static struct ti_clk core_d4_ck = { - .name = "core_d4_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_d4_ck_data, -}; - -static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = { - .parent = "dpll4_m2x2_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk omap_192m_alwon_fck = { - .name = "omap_192m_alwon_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &omap_192m_alwon_fck_data, -}; - -static struct ti_clk_fixed_factor core_d2_ck_data = { - .parent = "core_ck", - .div = 2, - .mult = 1, -}; - -static struct ti_clk core_d2_ck = { - .name = "core_d2_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_d2_ck_data, -}; - -static struct ti_clk_fixed_factor corex2_d3_fck_data = { - .parent = "corex2_fck", - .div = 3, - .mult = 1, -}; - -static struct ti_clk corex2_d3_fck = { - .name = "corex2_d3_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &corex2_d3_fck_data, -}; - -static struct ti_clk_fixed_factor corex2_d5_fck_data = { - .parent = "corex2_fck", - .div = 5, - .mult = 1, -}; - -static struct ti_clk corex2_d5_fck = { - .name = "corex2_d5_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &corex2_d5_fck_data, -}; - -static const char *sgx_mux_fck_parents[] = { - "core_d3_ck", - "core_d4_ck", - "core_d6_ck", - "cm_96m_fck", - "omap_192m_alwon_fck", - "core_d2_ck", - "corex2_d3_fck", - "corex2_d5_fck", -}; - -static struct ti_clk_mux sgx_mux_fck_data = { - .num_parents = ARRAY_SIZE(sgx_mux_fck_parents), - .reg = 0xb40, - .module = TI_CLKM_CM, - .parents = sgx_mux_fck_parents, -}; - -static struct ti_clk_composite sgx_fck_data = { - .mux = &sgx_mux_fck_data, - .gate = &sgx_gate_fck_data, -}; - -static struct ti_clk sgx_fck = { - .name = "sgx_fck", - .type = TI_CLK_COMPOSITE, - .data = &sgx_fck_data, -}; - -static struct ti_clk_gate mcspi1_fck_data = { - .parent = "core_48m_fck", - .bit_shift = 18, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mcspi1_fck = { - .name = "mcspi1_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi1_fck_data, -}; - -static struct ti_clk_gate mmchs2_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 25, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mmchs2_fck = { - .name = "mmchs2_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mmchs2_fck_data, -}; - -static struct ti_clk_gate mcspi2_fck_data = { - .parent = "core_48m_fck", - .bit_shift = 19, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mcspi2_fck = { - .name = "mcspi2_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi2_fck_data, -}; - -static struct ti_clk_gate vpfe_fck_data = { - .parent = "pclk_ck", - .bit_shift = 10, - .reg = 0x59c, - .module = TI_CLKM_SCRM, -}; - -static struct ti_clk vpfe_fck = { - .name = "vpfe_fck", - .type = TI_CLK_GATE, - .data = &vpfe_fck_data, -}; - -static struct ti_clk_gate gpt4_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 5, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_gate mcbsp1_gate_fck_data = { - .parent = "mcbsp_clks", - .bit_shift = 9, - .reg = 0xa00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_gate gpt5_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 6, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static const char *gpt5_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt5_mux_fck_data = { - .bit_shift = 3, - .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt5_mux_fck_parents, -}; - -static struct ti_clk_composite gpt5_fck_data = { - .mux = &gpt5_mux_fck_data, - .gate = &gpt5_gate_fck_data, -}; - -static struct ti_clk gpt5_fck = { - .name = "gpt5_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt5_fck_data, -}; - -static struct ti_clk_gate ts_fck_data = { - .parent = "omap_32k_fck", - .bit_shift = 1, - .reg = 0xa08, - .module = TI_CLKM_CM, -}; - -static struct ti_clk ts_fck = { - .name = "ts_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &ts_fck_data, -}; - -static struct ti_clk_fixed_factor wdt1_fck_data = { - .parent = "secure_32k_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk wdt1_fck = { - .name = "wdt1_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &wdt1_fck_data, -}; - -static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = { - .parent = "dpll4_m6x2_mul_ck", - .bit_shift = 0x1f, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m6x2_ck_omap36xx = { - .name = "dpll4_m6x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m6x2_ck_omap36xx_data, - .patch = &dpll4_m6x2_ck, -}; - -static const char *gpt4_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt4_mux_fck_data = { - .bit_shift = 2, - .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt4_mux_fck_parents, -}; - -static struct ti_clk_gate usbhost_ick_data = { - .parent = "l4_ick", - .bit_shift = 0, - .reg = 0x1410, - .module = TI_CLKM_CM, - .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk usbhost_ick = { - .name = "usbhost_ick", - .clkdm_name = "usbhost_clkdm", - .type = TI_CLK_GATE, - .data = &usbhost_ick_data, -}; - -static struct ti_clk_gate mcbsp2_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 0, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcbsp2_ick = { - .name = "mcbsp2_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &mcbsp2_ick_data, -}; - -static struct ti_clk_gate omapctrl_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 6, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk omapctrl_ick = { - .name = "omapctrl_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &omapctrl_ick_data, -}; - -static struct ti_clk_fixed_factor omap_96m_d4_fck_data = { - .parent = "omap_96m_fck", - .div = 4, - .mult = 1, -}; - -static struct ti_clk omap_96m_d4_fck = { - .name = "omap_96m_d4_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &omap_96m_d4_fck_data, -}; - -static struct ti_clk_gate gpt6_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 7, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt6_ick = { - .name = "gpt6_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt6_ick_data, -}; - -static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = { - .parent = "dpll3_m3x2_mul_ck", - .bit_shift = 0xc, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll3_m3x2_ck_omap36xx = { - .name = "dpll3_m3x2_ck", - .type = TI_CLK_GATE, - .data = &dpll3_m3x2_ck_omap36xx_data, - .patch = &dpll3_m3x2_ck, -}; - -static struct ti_clk_gate i2c3_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 17, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk i2c3_ick = { - .name = "i2c3_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &i2c3_ick_data, -}; - -static struct ti_clk_gate gpio6_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 17, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpio6_ick = { - .name = "gpio6_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio6_ick_data, -}; - -static struct ti_clk_gate mspro_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 23, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mspro_ick = { - .name = "mspro_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mspro_ick_data, -}; - -static struct ti_clk_composite mcbsp1_fck_data = { - .mux = &mcbsp1_mux_fck_data, - .gate = &mcbsp1_gate_fck_data, -}; - -static struct ti_clk mcbsp1_fck = { - .name = "mcbsp1_fck", - .type = TI_CLK_COMPOSITE, - .data = &mcbsp1_fck_data, -}; - -static struct ti_clk_gate gpt3_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 4, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_fixed rmii_ck_data = { - .frequency = 50000000, -}; - -static struct ti_clk rmii_ck = { - .name = "rmii_ck", - .type = TI_CLK_FIXED, - .data = &rmii_ck_data, -}; - -static struct ti_clk_gate gpt6_gate_fck_data = { - .parent = "sys_ck", - .bit_shift = 7, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_composite gpt6_fck_data = { - .mux = &gpt6_mux_fck_data, - .gate = &gpt6_gate_fck_data, -}; - -static struct ti_clk gpt6_fck = { - .name = "gpt6_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt6_fck_data, -}; - -static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = { - .parent = "dpll5_m2_ck", - .div = 4, - .mult = 1, -}; - -static struct ti_clk dpll5_m2_d4_ck = { - .name = "dpll5_m2_d4_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll5_m2_d4_ck_data, -}; - -static struct ti_clk_fixed_factor sys_d2_ck_data = { - .parent = "sys_ck", - .div = 2, - .mult = 1, -}; - -static struct ti_clk sys_d2_ck = { - .name = "sys_d2_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &sys_d2_ck_data, -}; - -static struct ti_clk_fixed_factor omap_96m_d2_fck_data = { - .parent = "omap_96m_fck", - .div = 2, - .mult = 1, -}; - -static struct ti_clk omap_96m_d2_fck = { - .name = "omap_96m_d2_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &omap_96m_d2_fck_data, -}; - -static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = { - .parent = "dpll5_m2_ck", - .div = 8, - .mult = 1, -}; - -static struct ti_clk dpll5_m2_d8_ck = { - .name = "dpll5_m2_d8_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll5_m2_d8_ck_data, -}; - -static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = { - .parent = "dpll5_m2_ck", - .div = 16, - .mult = 1, -}; - -static struct ti_clk dpll5_m2_d16_ck = { - .name = "dpll5_m2_d16_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll5_m2_d16_ck_data, -}; - -static const char *usim_mux_fck_parents[] = { - "sys_ck", - "sys_d2_ck", - "omap_96m_d2_fck", - "omap_96m_d4_fck", - "omap_96m_d8_fck", - "omap_96m_d10_fck", - "dpll5_m2_d4_ck", - "dpll5_m2_d8_ck", - "dpll5_m2_d16_ck", - "dpll5_m2_d20_ck", -}; - -static struct ti_clk_mux usim_mux_fck_data = { - .bit_shift = 3, - .num_parents = ARRAY_SIZE(usim_mux_fck_parents), - .reg = 0xc40, - .module = TI_CLKM_CM, - .parents = usim_mux_fck_parents, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk_composite usim_fck_data = { - .mux = &usim_mux_fck_data, - .gate = &usim_gate_fck_data, -}; - -static struct ti_clk usim_fck = { - .name = "usim_fck", - .type = TI_CLK_COMPOSITE, - .data = &usim_fck_data, -}; - -static int ssi_ssr_div_fck_3430es2_divs[] = { - 0, - 1, - 2, - 3, - 4, - 0, - 6, - 0, - 8, -}; - -static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = { - .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs), - .parent = "corex2_fck", - .bit_shift = 8, - .dividers = ssi_ssr_div_fck_3430es2_divs, - .reg = 0xa40, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_composite ssi_ssr_fck_3430es2_data = { - .gate = &ssi_ssr_gate_fck_3430es2_data, - .divider = &ssi_ssr_div_fck_3430es2_data, -}; - -static struct ti_clk ssi_ssr_fck_3430es2 = { - .name = "ssi_ssr_fck", - .type = TI_CLK_COMPOSITE, - .data = &ssi_ssr_fck_3430es2_data, -}; - -static struct ti_clk_gate dss1_alwon_fck_3430es1_data = { - .parent = "dpll4_m4x2_ck", - .bit_shift = 0, - .reg = 0xe00, - .module = TI_CLKM_CM, - .flags = CLKF_SET_RATE_PARENT, -}; - -static struct ti_clk dss1_alwon_fck_3430es1 = { - .name = "dss1_alwon_fck", - .clkdm_name = "dss_clkdm", - .type = TI_CLK_GATE, - .data = &dss1_alwon_fck_3430es1_data, -}; - -static struct ti_clk_gate gpt3_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 4, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt3_ick = { - .name = "gpt3_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt3_ick_data, -}; - -static struct ti_clk_fixed_factor omap_12m_fck_data = { - .parent = "omap_48m_fck", - .div = 4, - .mult = 1, -}; - -static struct ti_clk omap_12m_fck = { - .name = "omap_12m_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &omap_12m_fck_data, -}; - -static struct ti_clk_fixed_factor core_12m_fck_data = { - .parent = "omap_12m_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk core_12m_fck = { - .name = "core_12m_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &core_12m_fck_data, -}; - -static struct ti_clk_gate hdq_fck_data = { - .parent = "core_12m_fck", - .bit_shift = 22, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk hdq_fck = { - .name = "hdq_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &hdq_fck_data, -}; - -static struct ti_clk_gate usbtll_fck_data = { - .parent = "dpll5_m2_ck", - .bit_shift = 2, - .reg = 0xa08, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk usbtll_fck = { - .name = "usbtll_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &usbtll_fck_data, -}; - -static struct ti_clk_gate hsotgusb_fck_am35xx_data = { - .parent = "sys_ck", - .bit_shift = 8, - .reg = 0x59c, - .module = TI_CLKM_SCRM, -}; - -static struct ti_clk hsotgusb_fck_am35xx = { - .name = "hsotgusb_fck_am35xx", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &hsotgusb_fck_am35xx_data, -}; - -static struct ti_clk_gate hsotgusb_ick_3430es2_data = { - .parent = "core_l3_ick", - .bit_shift = 4, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk hsotgusb_ick_3430es2 = { - .name = "hsotgusb_ick_3430es2", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &hsotgusb_ick_3430es2_data, -}; - -static struct ti_clk_gate gfx_l3_ck_data = { - .parent = "l3_ick", - .bit_shift = 0, - .reg = 0xb10, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk gfx_l3_ck = { - .name = "gfx_l3_ck", - .clkdm_name = "gfx_3430es1_clkdm", - .type = TI_CLK_GATE, - .data = &gfx_l3_ck_data, -}; - -static struct ti_clk_fixed_factor gfx_l3_ick_data = { - .parent = "gfx_l3_ck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk gfx_l3_ick = { - .name = "gfx_l3_ick", - .type = TI_CLK_FIXED_FACTOR, - .data = &gfx_l3_ick_data, -}; - -static struct ti_clk_gate mcbsp1_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 9, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcbsp1_ick = { - .name = "mcbsp1_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcbsp1_ick_data, -}; - -static struct ti_clk_fixed_factor gpt12_fck_data = { - .parent = "secure_32k_fck", - .div = 1, - .mult = 1, -}; - -static struct ti_clk gpt12_fck = { - .name = "gpt12_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &gpt12_fck_data, -}; - -static struct ti_clk_gate gfx_cg2_ck_data = { - .parent = "gfx_l3_fck", - .bit_shift = 2, - .reg = 0xb00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk gfx_cg2_ck = { - .name = "gfx_cg2_ck", - .clkdm_name = "gfx_3430es1_clkdm", - .type = TI_CLK_GATE, - .data = &gfx_cg2_ck_data, -}; - -static struct ti_clk_gate i2c2_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 16, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk i2c2_ick = { - .name = "i2c2_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &i2c2_ick_data, -}; - -static struct ti_clk_gate gpio4_dbck_data = { - .parent = "per_32k_alwon_fck", - .bit_shift = 15, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk gpio4_dbck = { - .name = "gpio4_dbck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio4_dbck_data, -}; - -static struct ti_clk_gate i2c3_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 17, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk i2c3_fck = { - .name = "i2c3_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &i2c3_fck_data, -}; - -static struct ti_clk_composite gpt3_fck_data = { - .mux = &gpt3_mux_fck_data, - .gate = &gpt3_gate_fck_data, -}; - -static struct ti_clk gpt3_fck = { - .name = "gpt3_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt3_fck_data, -}; - -static struct ti_clk_gate i2c1_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 15, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk i2c1_ick = { - .name = "i2c1_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &i2c1_ick_data, -}; - -static struct ti_clk_gate omap_32ksync_ick_data = { - .parent = "wkup_l4_ick", - .bit_shift = 2, - .reg = 0xc10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk omap_32ksync_ick = { - .name = "omap_32ksync_ick", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &omap_32ksync_ick_data, -}; - -static struct ti_clk_gate aes2_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 28, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk aes2_ick = { - .name = "aes2_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &aes2_ick_data, -}; - -static const char *gpt8_mux_fck_parents[] = { - "omap_32k_fck", - "sys_ck", -}; - -static struct ti_clk_mux gpt8_mux_fck_data = { - .bit_shift = 6, - .num_parents = ARRAY_SIZE(gpt8_mux_fck_parents), - .reg = 0x1040, - .module = TI_CLKM_CM, - .parents = gpt8_mux_fck_parents, -}; - -static struct ti_clk_composite gpt8_fck_data = { - .mux = &gpt8_mux_fck_data, - .gate = &gpt8_gate_fck_data, -}; - -static struct ti_clk gpt8_fck = { - .name = "gpt8_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt8_fck_data, -}; - -static struct ti_clk_gate mcbsp4_gate_fck_data = { - .parent = "mcbsp_clks", - .bit_shift = 2, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk_composite mcbsp4_fck_data = { - .mux = &mcbsp4_mux_fck_data, - .gate = &mcbsp4_gate_fck_data, -}; - -static struct ti_clk mcbsp4_fck = { - .name = "mcbsp4_fck", - .type = TI_CLK_COMPOSITE, - .data = &mcbsp4_fck_data, -}; - -static struct ti_clk_gate gpio2_dbck_data = { - .parent = "per_32k_alwon_fck", - .bit_shift = 13, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk gpio2_dbck = { - .name = "gpio2_dbck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio2_dbck_data, -}; - -static struct ti_clk_gate usbtll_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 2, - .reg = 0xa18, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk usbtll_ick = { - .name = "usbtll_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &usbtll_ick_data, -}; - -static struct ti_clk_gate mcspi4_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 21, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcspi4_ick = { - .name = "mcspi4_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi4_ick_data, -}; - -static struct ti_clk_gate dss_96m_fck_data = { - .parent = "omap_96m_fck", - .bit_shift = 2, - .reg = 0xe00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk dss_96m_fck = { - .name = "dss_96m_fck", - .clkdm_name = "dss_clkdm", - .type = TI_CLK_GATE, - .data = &dss_96m_fck_data, -}; - -static struct ti_clk_divider rm_ick_data = { - .parent = "l4_ick", - .bit_shift = 1, - .max_div = 3, - .reg = 0xc40, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk rm_ick = { - .name = "rm_ick", - .type = TI_CLK_DIVIDER, - .data = &rm_ick_data, -}; - -static struct ti_clk_gate hdq_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 22, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk hdq_ick = { - .name = "hdq_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &hdq_ick_data, -}; - -static struct ti_clk_fixed_factor dpll3_x2_ck_data = { - .parent = "dpll3_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll3_x2_ck = { - .name = "dpll3_x2_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll3_x2_ck_data, -}; - -static struct ti_clk_gate mad2d_ick_data = { - .parent = "l3_ick", - .bit_shift = 3, - .reg = 0xa18, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mad2d_ick = { - .name = "mad2d_ick", - .clkdm_name = "d2d_clkdm", - .type = TI_CLK_GATE, - .data = &mad2d_ick_data, -}; - -static struct ti_clk_gate fshostusb_fck_data = { - .parent = "core_48m_fck", - .bit_shift = 5, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk fshostusb_fck = { - .name = "fshostusb_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &fshostusb_fck_data, -}; - -static struct ti_clk_gate sr1_fck_data = { - .parent = "sys_ck", - .bit_shift = 6, - .reg = 0xc00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk sr1_fck = { - .name = "sr1_fck", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &sr1_fck_data, -}; - -static struct ti_clk_gate des2_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 26, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk des2_ick = { - .name = "des2_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &des2_ick_data, -}; - -static struct ti_clk_gate sdrc_ick_data = { - .parent = "core_l3_ick", - .bit_shift = 1, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk sdrc_ick = { - .name = "sdrc_ick", - .clkdm_name = "core_l3_clkdm", - .type = TI_CLK_GATE, - .data = &sdrc_ick_data, -}; - -static struct ti_clk_composite gpt4_fck_data = { - .mux = &gpt4_mux_fck_data, - .gate = &gpt4_gate_fck_data, -}; - -static struct ti_clk gpt4_fck = { - .name = "gpt4_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt4_fck_data, -}; - -static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = { - .parent = "dpll4_m3x2_mul_ck", - .bit_shift = 0x1c, - .reg = 0xd00, - .module = TI_CLKM_CM, - .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, -}; - -static struct ti_clk dpll4_m3x2_ck_omap36xx = { - .name = "dpll4_m3x2_ck", - .type = TI_CLK_GATE, - .data = &dpll4_m3x2_ck_omap36xx_data, - .patch = &dpll4_m3x2_ck, -}; - -static struct ti_clk_gate cpefuse_fck_data = { - .parent = "sys_ck", - .bit_shift = 0, - .reg = 0xa08, - .module = TI_CLKM_CM, -}; - -static struct ti_clk cpefuse_fck = { - .name = "cpefuse_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &cpefuse_fck_data, -}; - -static struct ti_clk_gate mcspi3_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 20, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcspi3_ick = { - .name = "mcspi3_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi3_ick_data, -}; - -static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = { - .parent = "ssi_ssr_fck", - .div = 2, - .mult = 1, -}; - -static struct ti_clk ssi_sst_fck_3430es2 = { - .name = "ssi_sst_fck", - .type = TI_CLK_FIXED_FACTOR, - .data = &ssi_sst_fck_3430es2_data, -}; - -static struct ti_clk_gate gpio1_dbck_data = { - .parent = "wkup_32k_fck", - .bit_shift = 3, - .reg = 0xc00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk gpio1_dbck = { - .name = "gpio1_dbck", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &gpio1_dbck_data, -}; - -static struct ti_clk_gate gpt4_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 5, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt4_ick = { - .name = "gpt4_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt4_ick_data, -}; - -static struct ti_clk_gate gpt2_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 3, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt2_ick = { - .name = "gpt2_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt2_ick_data, -}; - -static struct ti_clk_gate mmchs1_fck_data = { - .parent = "core_96m_fck", - .bit_shift = 24, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk mmchs1_fck = { - .name = "mmchs1_fck", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mmchs1_fck_data, -}; - -static struct ti_clk_fixed dummy_apb_pclk_data = { - .frequency = 0x0, -}; - -static struct ti_clk dummy_apb_pclk = { - .name = "dummy_apb_pclk", - .type = TI_CLK_FIXED, - .data = &dummy_apb_pclk_data, -}; - -static struct ti_clk_gate gpio6_dbck_data = { - .parent = "per_32k_alwon_fck", - .bit_shift = 17, - .reg = 0x1000, - .module = TI_CLKM_CM, -}; - -static struct ti_clk gpio6_dbck = { - .name = "gpio6_dbck", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio6_dbck_data, -}; - -static struct ti_clk_gate uart2_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 14, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk uart2_ick = { - .name = "uart2_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &uart2_ick_data, -}; - -static struct ti_clk_fixed_factor dpll4_x2_ck_data = { - .parent = "dpll4_ck", - .div = 1, - .mult = 2, -}; - -static struct ti_clk dpll4_x2_ck = { - .name = "dpll4_x2_ck", - .type = TI_CLK_FIXED_FACTOR, - .data = &dpll4_x2_ck_data, -}; - -static struct ti_clk_gate gpt7_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 8, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpt7_ick = { - .name = "gpt7_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpt7_ick_data, -}; - -static struct ti_clk_gate dss_tv_fck_data = { - .parent = "omap_54m_fck", - .bit_shift = 2, - .reg = 0xe00, - .module = TI_CLKM_CM, -}; - -static struct ti_clk dss_tv_fck = { - .name = "dss_tv_fck", - .clkdm_name = "dss_clkdm", - .type = TI_CLK_GATE, - .data = &dss_tv_fck_data, -}; - -static struct ti_clk_gate mcbsp5_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 10, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcbsp5_ick = { - .name = "mcbsp5_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcbsp5_ick_data, -}; - -static struct ti_clk_gate mcspi1_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 18, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk mcspi1_ick = { - .name = "mcspi1_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &mcspi1_ick_data, -}; - -static struct ti_clk_gate d2d_26m_fck_data = { - .parent = "sys_ck", - .bit_shift = 3, - .reg = 0xa00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk d2d_26m_fck = { - .name = "d2d_26m_fck", - .clkdm_name = "d2d_clkdm", - .type = TI_CLK_GATE, - .data = &d2d_26m_fck_data, -}; - -static struct ti_clk_gate wdt3_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 12, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk wdt3_ick = { - .name = "wdt3_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &wdt3_ick_data, -}; - -static struct ti_clk_divider pclkx2_fck_data = { - .parent = "emu_src_ck", - .bit_shift = 6, - .max_div = 3, - .reg = 0x1140, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_STARTS_AT_ONE, -}; - -static struct ti_clk pclkx2_fck = { - .name = "pclkx2_fck", - .type = TI_CLK_DIVIDER, - .data = &pclkx2_fck_data, -}; - -static struct ti_clk_gate sha12_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 27, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk sha12_ick = { - .name = "sha12_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &sha12_ick_data, -}; - -static struct ti_clk_gate emac_fck_data = { - .parent = "rmii_ck", - .bit_shift = 9, - .reg = 0x59c, - .module = TI_CLKM_SCRM, -}; - -static struct ti_clk emac_fck = { - .name = "emac_fck", - .type = TI_CLK_GATE, - .data = &emac_fck_data, -}; - -static struct ti_clk_composite gpt10_fck_data = { - .mux = &gpt10_mux_fck_data, - .gate = &gpt10_gate_fck_data, -}; - -static struct ti_clk gpt10_fck = { - .name = "gpt10_fck", - .type = TI_CLK_COMPOSITE, - .data = &gpt10_fck_data, -}; - -static struct ti_clk_gate wdt2_fck_data = { - .parent = "wkup_32k_fck", - .bit_shift = 5, - .reg = 0xc00, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk wdt2_fck = { - .name = "wdt2_fck", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &wdt2_fck_data, -}; - -static struct ti_clk_gate cam_ick_data = { - .parent = "l4_ick", - .bit_shift = 0, - .reg = 0xf10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, -}; - -static struct ti_clk cam_ick = { - .name = "cam_ick", - .clkdm_name = "cam_clkdm", - .type = TI_CLK_GATE, - .data = &cam_ick_data, -}; - -static struct ti_clk_gate ssi_ick_3430es2_data = { - .parent = "ssi_l4_ick", - .bit_shift = 0, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk ssi_ick_3430es2 = { - .name = "ssi_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &ssi_ick_3430es2_data, -}; - -static struct ti_clk_gate gpio4_ick_data = { - .parent = "per_l4_ick", - .bit_shift = 15, - .reg = 0x1010, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk gpio4_ick = { - .name = "gpio4_ick", - .clkdm_name = "per_clkdm", - .type = TI_CLK_GATE, - .data = &gpio4_ick_data, -}; - -static struct ti_clk_gate wdt1_ick_data = { - .parent = "wkup_l4_ick", - .bit_shift = 4, - .reg = 0xc10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk wdt1_ick = { - .name = "wdt1_ick", - .clkdm_name = "wkup_clkdm", - .type = TI_CLK_GATE, - .data = &wdt1_ick_data, -}; - -static struct ti_clk_gate rng_ick_data = { - .parent = "security_l4_ick2", - .bit_shift = 2, - .reg = 0xa14, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk rng_ick = { - .name = "rng_ick", - .type = TI_CLK_GATE, - .data = &rng_ick_data, -}; - -static struct ti_clk_gate icr_ick_data = { - .parent = "core_l4_ick", - .bit_shift = 29, - .reg = 0xa10, - .module = TI_CLKM_CM, - .flags = CLKF_OMAP3 | CLKF_INTERFACE, -}; - -static struct ti_clk icr_ick = { - .name = "icr_ick", - .clkdm_name = "core_l4_clkdm", - .type = TI_CLK_GATE, - .data = &icr_ick_data, -}; - -static struct ti_clk_gate sgx_ick_data = { - .parent = "l3_ick", - .bit_shift = 0, - .reg = 0xb10, - .module = TI_CLKM_CM, - .flags = CLKF_WAIT, -}; - -static struct ti_clk sgx_ick = { - .name = "sgx_ick", - .clkdm_name = "sgx_clkdm", - .type = TI_CLK_GATE, - .data = &sgx_ick_data, -}; - -static struct ti_clk_divider sys_clkout2_data = { - .parent = "clkout2_src_ck", - .bit_shift = 3, - .max_div = 64, - .reg = 0xd70, - .module = TI_CLKM_CM, - .flags = CLKF_INDEX_POWER_OF_TWO, -}; - -static struct ti_clk sys_clkout2 = { - .name = "sys_clkout2", - .type = TI_CLK_DIVIDER, - .data = &sys_clkout2_data, -}; - -static struct ti_clk_alias omap34xx_omap36xx_clks[] = { - CLK(NULL, "security_l4_ick2", &security_l4_ick2), - CLK(NULL, "aes1_ick", &aes1_ick), - CLK("omap_rng", "ick", &rng_ick), - CLK("omap3-rom-rng", "ick", &rng_ick), - CLK(NULL, "sha11_ick", &sha11_ick), - CLK(NULL, "des1_ick", &des1_ick), - CLK(NULL, "cam_mclk", &cam_mclk), - CLK(NULL, "cam_ick", &cam_ick), - CLK(NULL, "csi2_96m_fck", &csi2_96m_fck), - CLK(NULL, "security_l3_ick", &security_l3_ick), - CLK(NULL, "pka_ick", &pka_ick), - CLK(NULL, "icr_ick", &icr_ick), - CLK(NULL, "des2_ick", &des2_ick), - CLK(NULL, "mspro_ick", &mspro_ick), - CLK(NULL, "mailboxes_ick", &mailboxes_ick), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), - CLK(NULL, "sr1_fck", &sr1_fck), - CLK(NULL, "sr2_fck", &sr2_fck), - CLK(NULL, "sr_l4_ick", &sr_l4_ick), - CLK(NULL, "dpll2_fck", &dpll2_fck), - CLK(NULL, "dpll2_ck", &dpll2_ck), - CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck), - CLK(NULL, "iva2_ck", &iva2_ck), - CLK(NULL, "modem_fck", &modem_fck), - CLK(NULL, "sad2d_ick", &sad2d_ick), - CLK(NULL, "mad2d_ick", &mad2d_ick), - CLK(NULL, "mspro_fck", &mspro_fck), - { NULL }, -}; - -static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = { - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2), - CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2), - CLK(NULL, "ssi_ick", &ssi_ick_3430es2), - CLK(NULL, "sys_d2_ck", &sys_d2_ck), - CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck), - CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck), - CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck), - CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck), - CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck), - CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck), - CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck), - CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck), - CLK(NULL, "usim_fck", &usim_fck), - CLK(NULL, "usim_ick", &usim_ick), - { NULL }, -}; - -static struct ti_clk_alias omap3xxx_clks[] = { - CLK(NULL, "apb_pclk", &dummy_apb_pclk), - CLK(NULL, "omap_32k_fck", &omap_32k_fck), - CLK(NULL, "virt_12m_ck", &virt_12m_ck), - CLK(NULL, "virt_13m_ck", &virt_13m_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), - CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck), - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck), - CLK(NULL, "osc_sys_ck", &osc_sys_ck), - CLK("twl", "fck", &osc_sys_ck), - CLK(NULL, "sys_ck", &sys_ck), - CLK(NULL, "timer_sys_ck", &sys_ck), - CLK(NULL, "dpll4_ck", &dpll4_ck), - CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck), - CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck), - CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck), - CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck), - CLK(NULL, "dpll3_ck", &dpll3_ck), - CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck), - CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck), - CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck), - CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck), - CLK(NULL, "sys_altclk", &sys_altclk), - CLK(NULL, "sys_clkout1", &sys_clkout1), - CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck), - CLK(NULL, "core_ck", &core_ck), - CLK(NULL, "dpll1_fck", &dpll1_fck), - CLK(NULL, "dpll1_ck", &dpll1_ck), - CLK(NULL, "cpufreq_ck", &dpll1_ck), - CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck), - CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck), - CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck), - CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck), - CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck), - CLK(NULL, "cm_96m_fck", &cm_96m_fck), - CLK(NULL, "omap_96m_fck", &omap_96m_fck), - CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck), - CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck), - CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck), - CLK(NULL, "omap_54m_fck", &omap_54m_fck), - CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck), - CLK(NULL, "omap_48m_fck", &omap_48m_fck), - CLK(NULL, "omap_12m_fck", &omap_12m_fck), - CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck), - CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck), - CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck), - CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck), - CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck), - CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck), - CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck), - CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck), - CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck), - CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck), - CLK(NULL, "clkout2_src_ck", &clkout2_src_ck), - CLK(NULL, "sys_clkout2", &sys_clkout2), - CLK(NULL, "corex2_fck", &corex2_fck), - CLK(NULL, "mpu_ck", &mpu_ck), - CLK(NULL, "arm_fck", &arm_fck), - CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck), - CLK(NULL, "l3_ick", &l3_ick), - CLK(NULL, "l4_ick", &l4_ick), - CLK(NULL, "rm_ick", &rm_ick), - CLK(NULL, "timer_32k_ck", &omap_32k_fck), - CLK(NULL, "gpt10_fck", &gpt10_fck), - CLK(NULL, "gpt11_fck", &gpt11_fck), - CLK(NULL, "core_96m_fck", &core_96m_fck), - CLK(NULL, "mmchs2_fck", &mmchs2_fck), - CLK(NULL, "mmchs1_fck", &mmchs1_fck), - CLK(NULL, "i2c3_fck", &i2c3_fck), - CLK(NULL, "i2c2_fck", &i2c2_fck), - CLK(NULL, "i2c1_fck", &i2c1_fck), - CLK(NULL, "core_48m_fck", &core_48m_fck), - CLK(NULL, "mcspi4_fck", &mcspi4_fck), - CLK(NULL, "mcspi3_fck", &mcspi3_fck), - CLK(NULL, "mcspi2_fck", &mcspi2_fck), - CLK(NULL, "mcspi1_fck", &mcspi1_fck), - CLK(NULL, "uart2_fck", &uart2_fck), - CLK(NULL, "uart1_fck", &uart1_fck), - CLK(NULL, "core_12m_fck", &core_12m_fck), - CLK("omap_hdq.0", "fck", &hdq_fck), - CLK(NULL, "hdq_fck", &hdq_fck), - CLK(NULL, "core_l3_ick", &core_l3_ick), - CLK(NULL, "sdrc_ick", &sdrc_ick), - CLK(NULL, "gpmc_fck", &gpmc_fck), - CLK(NULL, "core_l4_ick", &core_l4_ick), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick), - CLK(NULL, "mmchs2_ick", &mmchs2_ick), - CLK(NULL, "mmchs1_ick", &mmchs1_ick), - CLK("omap_hdq.0", "ick", &hdq_ick), - CLK(NULL, "hdq_ick", &hdq_ick), - CLK("omap2_mcspi.4", "ick", &mcspi4_ick), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick), - CLK(NULL, "mcspi4_ick", &mcspi4_ick), - CLK(NULL, "mcspi3_ick", &mcspi3_ick), - CLK(NULL, "mcspi2_ick", &mcspi2_ick), - CLK(NULL, "mcspi1_ick", &mcspi1_ick), - CLK("omap_i2c.3", "ick", &i2c3_ick), - CLK("omap_i2c.2", "ick", &i2c2_ick), - CLK("omap_i2c.1", "ick", &i2c1_ick), - CLK(NULL, "i2c3_ick", &i2c3_ick), - CLK(NULL, "i2c2_ick", &i2c2_ick), - CLK(NULL, "i2c1_ick", &i2c1_ick), - CLK(NULL, "uart2_ick", &uart2_ick), - CLK(NULL, "uart1_ick", &uart1_ick), - CLK(NULL, "gpt11_ick", &gpt11_ick), - CLK(NULL, "gpt10_ick", &gpt10_ick), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "omapctrl_ick", &omapctrl_ick), - CLK(NULL, "dss_tv_fck", &dss_tv_fck), - CLK(NULL, "dss_96m_fck", &dss_96m_fck), - CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck), - CLK(NULL, "init_60m_fclk", &dummy_ck), - CLK(NULL, "gpt1_fck", &gpt1_fck), - CLK(NULL, "aes2_ick", &aes2_ick), - CLK(NULL, "wkup_32k_fck", &wkup_32k_fck), - CLK(NULL, "gpio1_dbck", &gpio1_dbck), - CLK(NULL, "sha12_ick", &sha12_ick), - CLK(NULL, "wdt2_fck", &wdt2_fck), - CLK(NULL, "wkup_l4_ick", &wkup_l4_ick), - CLK("omap_wdt", "ick", &wdt2_ick), - CLK(NULL, "wdt2_ick", &wdt2_ick), - CLK(NULL, "wdt1_ick", &wdt1_ick), - CLK(NULL, "gpio1_ick", &gpio1_ick), - CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick), - CLK(NULL, "gpt12_ick", &gpt12_ick), - CLK(NULL, "gpt1_ick", &gpt1_ick), - CLK(NULL, "per_96m_fck", &per_96m_fck), - CLK(NULL, "per_48m_fck", &per_48m_fck), - CLK(NULL, "uart3_fck", &uart3_fck), - CLK(NULL, "gpt2_fck", &gpt2_fck), - CLK(NULL, "gpt3_fck", &gpt3_fck), - CLK(NULL, "gpt4_fck", &gpt4_fck), - CLK(NULL, "gpt5_fck", &gpt5_fck), - CLK(NULL, "gpt6_fck", &gpt6_fck), - CLK(NULL, "gpt7_fck", &gpt7_fck), - CLK(NULL, "gpt8_fck", &gpt8_fck), - CLK(NULL, "gpt9_fck", &gpt9_fck), - CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck), - CLK(NULL, "gpio6_dbck", &gpio6_dbck), - CLK(NULL, "gpio5_dbck", &gpio5_dbck), - CLK(NULL, "gpio4_dbck", &gpio4_dbck), - CLK(NULL, "gpio3_dbck", &gpio3_dbck), - CLK(NULL, "gpio2_dbck", &gpio2_dbck), - CLK(NULL, "wdt3_fck", &wdt3_fck), - CLK(NULL, "per_l4_ick", &per_l4_ick), - CLK(NULL, "gpio6_ick", &gpio6_ick), - CLK(NULL, "gpio5_ick", &gpio5_ick), - CLK(NULL, "gpio4_ick", &gpio4_ick), - CLK(NULL, "gpio3_ick", &gpio3_ick), - CLK(NULL, "gpio2_ick", &gpio2_ick), - CLK(NULL, "wdt3_ick", &wdt3_ick), - CLK(NULL, "uart3_ick", &uart3_ick), - CLK(NULL, "uart4_ick", &uart4_ick), - CLK(NULL, "gpt9_ick", &gpt9_ick), - CLK(NULL, "gpt8_ick", &gpt8_ick), - CLK(NULL, "gpt7_ick", &gpt7_ick), - CLK(NULL, "gpt6_ick", &gpt6_ick), - CLK(NULL, "gpt5_ick", &gpt5_ick), - CLK(NULL, "gpt4_ick", &gpt4_ick), - CLK(NULL, "gpt3_ick", &gpt3_ick), - CLK(NULL, "gpt2_ick", &gpt2_ick), - CLK(NULL, "mcbsp_clks", &mcbsp_clks), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), - CLK(NULL, "mcbsp4_ick", &mcbsp4_ick), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), - CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck), - CLK("etb", "emu_src_ck", &emu_src_ck), - CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck), - CLK(NULL, "emu_src_ck", &emu_src_ck), - CLK(NULL, "pclk_fck", &pclk_fck), - CLK(NULL, "pclkx2_fck", &pclkx2_fck), - CLK(NULL, "atclk_fck", &atclk_fck), - CLK(NULL, "traceclk_src_fck", &traceclk_src_fck), - CLK(NULL, "traceclk_fck", &traceclk_fck), - CLK(NULL, "secure_32k_fck", &secure_32k_fck), - CLK(NULL, "gpt12_fck", &gpt12_fck), - CLK(NULL, "wdt1_fck", &wdt1_fck), - { NULL }, -}; - -static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = { - CLK(NULL, "dpll5_ck", &dpll5_ck), - CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck), - CLK(NULL, "core_d3_ck", &core_d3_ck), - CLK(NULL, "core_d4_ck", &core_d4_ck), - CLK(NULL, "core_d6_ck", &core_d6_ck), - CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck), - CLK(NULL, "core_d2_ck", &core_d2_ck), - CLK(NULL, "corex2_d3_fck", &corex2_d3_fck), - CLK(NULL, "corex2_d5_fck", &corex2_d5_fck), - CLK(NULL, "sgx_fck", &sgx_fck), - CLK(NULL, "sgx_ick", &sgx_ick), - CLK(NULL, "cpefuse_fck", &cpefuse_fck), - CLK(NULL, "ts_fck", &ts_fck), - CLK(NULL, "usbtll_fck", &usbtll_fck), - CLK(NULL, "usbtll_ick", &usbtll_ick), - CLK("omap_hsmmc.2", "ick", &mmchs3_ick), - CLK(NULL, "mmchs3_ick", &mmchs3_ick), - CLK(NULL, "mmchs3_fck", &mmchs3_fck), - CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2), - CLK("omapdss_dss", "ick", &dss_ick_3430es2), - CLK(NULL, "dss_ick", &dss_ick_3430es2), - CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), - CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), - CLK(NULL, "usbhost_ick", &usbhost_ick), - { NULL }, -}; - -static struct ti_clk_alias omap3430es1_clks[] = { - CLK(NULL, "gfx_l3_ck", &gfx_l3_ck), - CLK(NULL, "gfx_l3_fck", &gfx_l3_fck), - CLK(NULL, "gfx_l3_ick", &gfx_l3_ick), - CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck), - CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck), - CLK(NULL, "d2d_26m_fck", &d2d_26m_fck), - CLK(NULL, "fshostusb_fck", &fshostusb_fck), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1), - CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1), - CLK(NULL, "fac_ick", &fac_ick), - CLK(NULL, "ssi_ick", &ssi_ick_3430es1), - CLK(NULL, "usb_l4_ick", &usb_l4_ick), - CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1), - CLK("omapdss_dss", "ick", &dss_ick_3430es1), - CLK(NULL, "dss_ick", &dss_ick_3430es1), - { NULL }, -}; - -static struct ti_clk_alias omap36xx_clks[] = { - CLK(NULL, "uart4_fck", &uart4_fck), - { NULL }, -}; - -static struct ti_clk_alias am35xx_clks[] = { - CLK(NULL, "ipss_ick", &ipss_ick), - CLK(NULL, "rmii_ck", &rmii_ck), - CLK(NULL, "pclk_ck", &pclk_ck), - CLK(NULL, "emac_ick", &emac_ick), - CLK(NULL, "emac_fck", &emac_fck), - CLK("davinci_emac.0", NULL, &emac_ick), - CLK("davinci_mdio.0", NULL, &emac_fck), - CLK("vpfe-capture", "master", &vpfe_ick), - CLK("vpfe-capture", "slave", &vpfe_fck), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx), - CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx), - CLK(NULL, "hecc_ck", &hecc_ck), - CLK(NULL, "uart4_ick", &uart4_ick_am35xx), - CLK(NULL, "uart4_fck", &uart4_fck_am35xx), - { NULL }, -}; - -static struct ti_clk *omap36xx_clk_patches[] = { - &dpll4_m3x2_ck_omap36xx, - &dpll3_m3x2_ck_omap36xx, - &dpll4_m6x2_ck_omap36xx, - &dpll4_m2x2_ck_omap36xx, - &dpll4_m5x2_ck_omap36xx, - &dpll4_ck_omap36xx, - NULL, -}; - -static const char *enable_init_clks[] = { - "sdrc_ick", - "gpmc_fck", - "omapctrl_ick", -}; - -static void __init omap3_clk_legacy_common_init(void) -{ - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(osc_sys_ck.clk) / 1000000), - (clk_get_rate(osc_sys_ck.clk) / 100000) % 10, - (clk_get_rate(core_ck.clk) / 1000000), - (clk_get_rate(arm_fck.clk) / 1000000)); -} - -int __init omap3430es1_clk_legacy_init(void) -{ - int r; - - r = ti_clk_register_legacy_clks(omap3430es1_clks); - r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks); - r |= ti_clk_register_legacy_clks(omap3xxx_clks); - - omap3_clk_legacy_common_init(); - - return r; -} - -int __init omap3430_clk_legacy_init(void) -{ - int r; - - r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks); - r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks); - r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks); - r |= ti_clk_register_legacy_clks(omap3xxx_clks); - - omap3_clk_legacy_common_init(); - omap3_clk_lock_dpll5(); - - return r; -} - -int __init omap36xx_clk_legacy_init(void) -{ - int r; - - ti_clk_patch_legacy_clks(omap36xx_clk_patches); - r = ti_clk_register_legacy_clks(omap36xx_clks); - r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks); - r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks); - r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks); - r |= ti_clk_register_legacy_clks(omap3xxx_clks); - - omap3_clk_legacy_common_init(); - omap3_clk_lock_dpll5(); - - return r; -} - -int __init am35xx_clk_legacy_init(void) -{ - int r; - - r = ti_clk_register_legacy_clks(am35xx_clks); - r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks); - r |= ti_clk_register_legacy_clks(omap3xxx_clks); - - omap3_clk_legacy_common_init(); - omap3_clk_lock_dpll5(); - - return r; -} diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 302c9e64e5fa..f4d6802a8544 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -336,141 +336,6 @@ void ti_dt_clk_init_retry_clks(void) } } -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) -void __init ti_clk_patch_legacy_clks(struct ti_clk **patch) -{ - while (*patch) { - memcpy((*patch)->patch, *patch, sizeof(**patch)); - patch++; - } -} - -struct clk __init *ti_clk_register_clk(struct ti_clk *setup) -{ - struct clk *clk; - struct ti_clk_fixed *fixed; - struct ti_clk_fixed_factor *fixed_factor; - struct clk_hw *clk_hw; - int ret; - - if (setup->clk) - return setup->clk; - - switch (setup->type) { - case TI_CLK_FIXED: - fixed = setup->data; - - clk = clk_register_fixed_rate(NULL, setup->name, NULL, 0, - fixed->frequency); - if (!IS_ERR(clk)) { - ret = ti_clk_add_alias(NULL, clk, setup->name); - if (ret) { - clk_unregister(clk); - clk = ERR_PTR(ret); - } - } - break; - case TI_CLK_MUX: - clk = ti_clk_register_mux(setup); - break; - case TI_CLK_DIVIDER: - clk = ti_clk_register_divider(setup); - break; - case TI_CLK_COMPOSITE: - clk = ti_clk_register_composite(setup); - break; - case TI_CLK_FIXED_FACTOR: - fixed_factor = setup->data; - - clk = clk_register_fixed_factor(NULL, setup->name, - fixed_factor->parent, - 0, fixed_factor->mult, - fixed_factor->div); - if (!IS_ERR(clk)) { - ret = ti_clk_add_alias(NULL, clk, setup->name); - if (ret) { - clk_unregister(clk); - clk = ERR_PTR(ret); - } - } - break; - case TI_CLK_GATE: - clk = ti_clk_register_gate(setup); - break; - case TI_CLK_DPLL: - clk = ti_clk_register_dpll(setup); - break; - default: - pr_err("bad type for %s!\n", setup->name); - clk = ERR_PTR(-EINVAL); - } - - if (!IS_ERR(clk)) { - setup->clk = clk; - if (setup->clkdm_name) { - clk_hw = __clk_get_hw(clk); - if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) { - pr_warn("can't setup clkdm for basic clk %s\n", - setup->name); - } else { - to_clk_hw_omap(clk_hw)->clkdm_name = - setup->clkdm_name; - omap2_init_clk_clkdm(clk_hw); - } - } - } - - return clk; -} - -int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks) -{ - struct clk *clk; - bool retry; - struct ti_clk_alias *retry_clk; - struct ti_clk_alias *tmp; - - while (clks->clk) { - clk = ti_clk_register_clk(clks->clk); - if (IS_ERR(clk)) { - if (PTR_ERR(clk) == -EAGAIN) { - list_add(&clks->link, &retry_list); - } else { - pr_err("register for %s failed: %ld\n", - clks->clk->name, PTR_ERR(clk)); - return PTR_ERR(clk); - } - } - clks++; - } - - retry = true; - - while (!list_empty(&retry_list) && retry) { - retry = false; - list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) { - pr_debug("retry-init: %s\n", retry_clk->clk->name); - clk = ti_clk_register_clk(retry_clk->clk); - if (IS_ERR(clk)) { - if (PTR_ERR(clk) == -EAGAIN) { - continue; - } else { - pr_err("register for %s failed: %ld\n", - retry_clk->clk->name, - PTR_ERR(clk)); - return PTR_ERR(clk); - } - } else { - retry = true; - list_del(&retry_clk->link); - } - } - } - - return 0; -} -#endif - static const struct of_device_id simple_clk_match_table[] __initconst = { { .compatible = "fixed-clock" }, { .compatible = "fixed-factor-clock" }, diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 883e39e5d3ec..d9b43bfc2532 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -92,17 +92,6 @@ struct ti_clk { struct clk *clk; }; -struct ti_clk_alias { - struct ti_clk *clk; - struct clk_lookup lk; - struct list_head link; -}; - -struct ti_clk_fixed { - u32 frequency; - u16 flags; -}; - struct ti_clk_mux { u8 bit_shift; int num_parents; @@ -123,13 +112,6 @@ struct ti_clk_divider { u16 flags; }; -struct ti_clk_fixed_factor { - const char *parent; - u16 div; - u16 mult; - u16 flags; -}; - struct ti_clk_gate { const char *parent; u8 bit_shift; @@ -138,44 +120,6 @@ struct ti_clk_gate { u16 flags; }; -struct ti_clk_composite { - struct ti_clk_divider *divider; - struct ti_clk_mux *mux; - struct ti_clk_gate *gate; - u16 flags; -}; - -struct ti_clk_clkdm_gate { - const char *parent; - u16 flags; -}; - -struct ti_clk_dpll { - int num_parents; - u16 control_reg; - u16 idlest_reg; - u16 autoidle_reg; - u16 mult_div1_reg; - u8 module; - const char **parents; - u16 flags; - u8 modes; - u32 mult_mask; - u32 div1_mask; - u32 enable_mask; - u32 autoidle_mask; - u32 freqsel_mask; - u32 idlest_mask; - u32 dco_mask; - u32 sddiv_mask; - u16 max_multiplier; - u16 max_divider; - u8 min_divider; - u8 auto_recal_bit; - u8 recal_en_bit; - u8 recal_st_bit; -}; - /* Composite clock component types */ enum { CLK_COMPONENT_TYPE_GATE = 0, @@ -245,29 +189,17 @@ extern const struct omap_clkctrl_data dm816_clkctrl_data[]; typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); -struct clk *ti_clk_register_gate(struct ti_clk *setup); -struct clk *ti_clk_register_interface(struct ti_clk *setup); -struct clk *ti_clk_register_mux(struct ti_clk *setup); -struct clk *ti_clk_register_divider(struct ti_clk *setup); -struct clk *ti_clk_register_composite(struct ti_clk *setup); -struct clk *ti_clk_register_dpll(struct ti_clk *setup); struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, const char *con); int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); void ti_clk_add_aliases(void); -struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup); -struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup); struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, u8 flags, u8 *width, const struct clk_div_table **table); -void ti_clk_patch_legacy_clks(struct ti_clk **patch); -struct clk *ti_clk_register_clk(struct ti_clk *setup); -int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); - int ti_clk_get_reg_addr(struct device_node *node, int index, struct clk_omap_reg *reg); void ti_dt_clocks_register(struct ti_dt_clk *oclks); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index 3eaba2d16ce4..030e8b2c1050 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -116,51 +116,6 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) #define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw) -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) -struct clk *ti_clk_register_composite(struct ti_clk *setup) -{ - struct ti_clk_composite *comp; - struct clk_hw *gate; - struct clk_hw *mux; - struct clk_hw *div; - int num_parents = 1; - const char * const *parent_names = NULL; - struct clk *clk; - int ret; - - comp = setup->data; - - div = ti_clk_build_component_div(comp->divider); - gate = ti_clk_build_component_gate(comp->gate); - mux = ti_clk_build_component_mux(comp->mux); - - if (div) - parent_names = &comp->divider->parent; - - if (gate) - parent_names = &comp->gate->parent; - - if (mux) { - num_parents = comp->mux->num_parents; - parent_names = comp->mux->parents; - } - - clk = clk_register_composite(NULL, setup->name, - parent_names, num_parents, mux, - &ti_clk_mux_ops, div, - &ti_composite_divider_ops, gate, - &ti_composite_gate_ops, 0); - - ret = ti_clk_add_alias(NULL, clk, setup->name); - if (ret) { - clk_unregister(clk); - return ERR_PTR(ret); - } - - return clk; -} -#endif - static void __init _register_composite(void *user, struct device_node *node) { diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index d246598c5016..7d33ca9042cb 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -203,96 +203,6 @@ cleanup: kfree(clk_hw); } -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) -void _get_reg(u8 module, u16 offset, struct clk_omap_reg *reg) -{ - reg->index = module; - reg->offset = offset; -} - -struct clk *ti_clk_register_dpll(struct ti_clk *setup) -{ - struct clk_hw_omap *clk_hw; - struct clk_init_data init = { NULL }; - struct dpll_data *dd; - struct clk *clk; - struct ti_clk_dpll *dpll; - const struct clk_ops *ops = &omap3_dpll_ck_ops; - struct clk *clk_ref; - struct clk *clk_bypass; - - dpll = setup->data; - - if (dpll->num_parents < 2) - return ERR_PTR(-EINVAL); - - clk_ref = clk_get_sys(NULL, dpll->parents[0]); - clk_bypass = clk_get_sys(NULL, dpll->parents[1]); - - if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass)) - return ERR_PTR(-EAGAIN); - - dd = kzalloc(sizeof(*dd), GFP_KERNEL); - clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); - if (!dd || !clk_hw) { - clk = ERR_PTR(-ENOMEM); - goto cleanup; - } - - clk_hw->dpll_data = dd; - clk_hw->ops = &clkhwops_omap3_dpll; - clk_hw->hw.init = &init; - - init.name = setup->name; - init.ops = ops; - - init.num_parents = dpll->num_parents; - init.parent_names = dpll->parents; - - _get_reg(dpll->module, dpll->control_reg, &dd->control_reg); - _get_reg(dpll->module, dpll->idlest_reg, &dd->idlest_reg); - _get_reg(dpll->module, dpll->mult_div1_reg, &dd->mult_div1_reg); - _get_reg(dpll->module, dpll->autoidle_reg, &dd->autoidle_reg); - - dd->modes = dpll->modes; - dd->div1_mask = dpll->div1_mask; - dd->idlest_mask = dpll->idlest_mask; - dd->mult_mask = dpll->mult_mask; - dd->autoidle_mask = dpll->autoidle_mask; - dd->enable_mask = dpll->enable_mask; - dd->sddiv_mask = dpll->sddiv_mask; - dd->dco_mask = dpll->dco_mask; - dd->max_divider = dpll->max_divider; - dd->min_divider = dpll->min_divider; - dd->max_multiplier = dpll->max_multiplier; - dd->auto_recal_bit = dpll->auto_recal_bit; - dd->recal_en_bit = dpll->recal_en_bit; - dd->recal_st_bit = dpll->recal_st_bit; - - dd->clk_ref = __clk_get_hw(clk_ref); - dd->clk_bypass = __clk_get_hw(clk_bypass); - - if (dpll->flags & CLKF_CORE) - ops = &omap3_dpll_core_ck_ops; - - if (dpll->flags & CLKF_PER) - ops = &omap3_dpll_per_ck_ops; - - if (dpll->flags & CLKF_J_TYPE) - dd->flags |= DPLL_J_TYPE; - - clk = ti_clk_register(NULL, &clk_hw->hw, setup->name); - - if (!IS_ERR(clk)) - return clk; - -cleanup: - kfree(dd); - kfree(clk_hw); - return clk; -} -#endif - #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ defined(CONFIG_SOC_AM43XX) diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index 7151ec3a1b07..935b2de5fb88 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -128,53 +128,6 @@ static struct clk *_register_gate(struct device *dev, const char *name, return clk; } -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) -struct clk *ti_clk_register_gate(struct ti_clk *setup) -{ - const struct clk_ops *ops = &omap_gate_clk_ops; - const struct clk_hw_omap_ops *hw_ops = NULL; - struct clk_omap_reg reg; - u32 flags = 0; - u8 clk_gate_flags = 0; - struct ti_clk_gate *gate; - - gate = setup->data; - - if (gate->flags & CLKF_INTERFACE) - return ti_clk_register_interface(setup); - - if (gate->flags & CLKF_SET_RATE_PARENT) - flags |= CLK_SET_RATE_PARENT; - - if (gate->flags & CLKF_SET_BIT_TO_DISABLE) - clk_gate_flags |= INVERT_ENABLE; - - if (gate->flags & CLKF_HSDIV) { - ops = &omap_gate_clk_hsdiv_restore_ops; - hw_ops = &clkhwops_wait; - } - - if (gate->flags & CLKF_DSS) - hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait; - - if (gate->flags & CLKF_WAIT) - hw_ops = &clkhwops_wait; - - if (gate->flags & CLKF_CLKDM) - ops = &omap_gate_clkdm_clk_ops; - - if (gate->flags & CLKF_AM35XX) - hw_ops = &clkhwops_am35xx_ipss_module_wait; - - reg.index = gate->module; - reg.offset = gate->reg; - reg.ptr = NULL; - - return _register_gate(NULL, setup->name, gate->parent, flags, - ®, gate->bit_shift, - clk_gate_flags, ops, hw_ops); -} - struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup) { struct clk_hw_omap *gate; @@ -204,7 +157,6 @@ struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup) return &gate->hw; } -#endif static void __init _of_ti_gate_clk_setup(struct device_node *node, const struct clk_ops *ops, diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c index 62cf50c1e1e3..41ae7021670e 100644 --- a/drivers/clk/ti/interface.c +++ b/drivers/clk/ti/interface.c @@ -67,38 +67,6 @@ static struct clk *_register_interface(struct device *dev, const char *name, return clk; } -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) -struct clk *ti_clk_register_interface(struct ti_clk *setup) -{ - const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait; - struct clk_omap_reg reg; - struct ti_clk_gate *gate; - - gate = setup->data; - reg.index = gate->module; - reg.offset = gate->reg; - reg.ptr = NULL; - - if (gate->flags & CLKF_NO_WAIT) - ops = &clkhwops_iclk; - - if (gate->flags & CLKF_HSOTGUSB) - ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait; - - if (gate->flags & CLKF_DSS) - ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait; - - if (gate->flags & CLKF_SSI) - ops = &clkhwops_omap3430es2_iclk_ssi_wait; - - if (gate->flags & CLKF_AM35XX) - ops = &clkhwops_am35xx_ipss_wait; - - return _register_interface(NULL, setup->name, gate->parent, - ®, gate->bit_shift, ops); -} -#endif - static void __init _of_ti_interface_clk_setup(struct device_node *node, const struct clk_hw_omap_ops *ops) { |
