diff options
27 files changed, 45 insertions, 3770 deletions
diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt index e1d01df8e3c1..909c9935360d 100644 --- a/Documentation/devicetree/bindings/ata/ahci-st.txt +++ b/Documentation/devicetree/bindings/ata/ahci-st.txt @@ -18,21 +18,6 @@ Optional properties: Example: - /* Example for stih416 */ - sata0: sata@fe380000 { - compatible = "st,ahci"; - reg = <0xfe380000 0x1000>; - interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - resets = <&powerdown STIH416_SATA0_POWERDOWN>, - <&softreset STIH416_SATA0_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ahci_clk"; - }; - /* Example for stih407 family silicon */ sata0: sata@9b20000 { compatible = "st,ahci"; diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt index 1cfd21d1dfa1..92527138bc93 100644 --- a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt +++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt @@ -16,15 +16,14 @@ Please refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "st,<chip>-powerdown" - ex: "st,stih415-powerdown", "st,stih416-powerdown" +- compatible: Should be "st,stih407-powerdown" - #reset-cells: 1, see below example: powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; #reset-cells = <1>; - compatible = "st,stih415-powerdown"; }; @@ -37,11 +36,10 @@ index specifying which channel to use, as described in reset.txt example: - usb1: usb@fe200000 { - resets = <&powerdown STIH41X_USB1_POWERDOWN>; + st_dwc3: dwc3@8f94000 { + resets = <&powerdown STIH407_USB3_POWERDOWN>, }; Macro definitions for the supported reset channels can be found in: -include/dt-bindings/reset/stih415-resets.h -include/dt-bindings/reset/stih416-resets.h +include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt index 891a2fd85ed6..a21658f18fe6 100644 --- a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt +++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt @@ -15,15 +15,14 @@ Please refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "st,<chip>-softreset" example: - "st,stih415-softreset" or "st,stih416-softreset"; +- compatible: Should be st,stih407-softreset"; - #reset-cells: 1, see below example: softreset: softreset-controller { #reset-cells = <1>; - compatible = "st,stih415-softreset"; + compatible = "st,stih407-softreset"; }; @@ -42,5 +41,4 @@ example: Macro definitions for the supported reset channels can be found in: -include/dt-bindings/reset/stih415-resets.h -include/dt-bindings/reset/stih416-resets.h +include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/thermal/st-thermal.txt b/Documentation/devicetree/bindings/thermal/st-thermal.txt index 3b9251b4a145..a2f939137e35 100644 --- a/Documentation/devicetree/bindings/thermal/st-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/st-thermal.txt @@ -3,17 +3,8 @@ Binding for Thermal Sensor driver for STMicroelectronics STi series of SoCs. Required parameters: ------------------- -compatible : st,<SoC>-<module>-thermal; should be one of: - "st,stih415-sas-thermal", - "st,stih415-mpe-thermal", - "st,stih416-sas-thermal" - "st,stih416-mpe-thermal" - "st,stid127-thermal" or - "st,stih407-thermal" - according to the SoC type (stih415, stih416, stid127, stih407) - and module type (sas or mpe). On stid127 & stih407 there is only - one die/module, so there is no module type in the compatible - string. +compatible : Should be "st,stih407-thermal" + clock-names : Should be "thermal". See: Documentation/devicetree/bindings/resource-names.txt clocks : Phandle of the clock used by the thermal sensor. @@ -25,18 +16,17 @@ Optional parameters: reg : For non-sysconf based sensors, this should be the physical base address and length of the sensor's registers. interrupts : Standard way to define interrupt number. - Interrupt is mandatory to be defined when compatible is - "stih416-mpe-thermal". NB: For thermal sensor's for which no interrupt has been defined, a polling delay of 1000ms will be used to read the temperature from device. Example: - temp1@fdfe8000 { - compatible = "st,stih416-mpe-thermal"; - reg = <0xfdfe8000 0x10>; - clock-names = "thermal"; - clocks = <&clk_m_mpethsens>; - interrupts = <GIC_SPI 23 IRQ_TYPE_NONE>; + temp0@91a0000 { + compatible = "st,stih407-thermal"; + reg = <0x91a0000 0x28>; + clock-names = "thermal"; + clocks = <&CLK_SYSIN>; + interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; + st,passive_cooling_temp = <110>; }; diff --git a/MAINTAINERS b/MAINTAINERS index c44795306342..474281a54dbe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1779,9 +1779,7 @@ F: drivers/media/rc/st_rc.c F: drivers/media/platform/sti/c8sectpfe/ F: drivers/mmc/host/sdhci-st.c F: drivers/phy/phy-miphy28lp.c -F: drivers/phy/phy-miphy365x.c F: drivers/phy/phy-stih407-usb.c -F: drivers/phy/phy-stih41x-usb.c F: drivers/pinctrl/pinctrl-st.c F: drivers/remoteproc/st_remoteproc.c F: drivers/reset/sti/ diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index befcd2619902..376db94a695f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -712,11 +712,6 @@ dtb-$(CONFIG_ARCH_STI) += \ stih407-b2120.dtb \ stih410-b2120.dtb \ stih410-b2260.dtb \ - stih415-b2000.dtb \ - stih415-b2020.dtb \ - stih416-b2000.dtb \ - stih416-b2020.dtb \ - stih416-b2020e.dtb \ stih418-b2199.dtb dtb-$(CONFIG_ARCH_STM32)+= \ stm32f429-disco.dtb \ diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 91096a49efa9..d29960b6c47b 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -900,7 +900,7 @@ }; sti_uni_player0: sti-uni-player@8d80000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_0>; @@ -910,17 +910,13 @@ reg = <0x8d80000 0x158>; interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; dmas = <&fdma0 2 0 1>; - dai-name = "Uni Player #0 (HDMI)"; dma-names = "tx"; - st,uniperiph-id = <0>; - st,version = <5>; - st,mode = "HDMI"; status = "disabled"; }; sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-pcm-out"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_1>; @@ -930,17 +926,13 @@ reg = <0x8d81000 0x158>; interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; dmas = <&fdma0 3 0 1>; - dai-name = "Uni Player #1 (PIO)"; dma-names = "tx"; - st,uniperiph-id = <1>; - st,version = <5>; - st,mode = "PCM"; status = "disabled"; }; sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-dac"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_2>; @@ -950,17 +942,13 @@ reg = <0x8d82000 0x158>; interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; dmas = <&fdma0 4 0 1>; - dai-name = "Uni Player #1 (DAC)"; dma-names = "tx"; - st,uniperiph-id = <2>; - st,version = <5>; - st,mode = "PCM"; status = "disabled"; }; sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-spdif"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; @@ -971,38 +959,30 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>; dmas = <&fdma0 7 0 1>; dma-names = "tx"; - dai-name = "Uni Player #1 (PIO)"; - st,uniperiph-id = <3>; - st,version = <5>; - st,mode = "SPDIF"; status = "disabled"; }; sti_uni_reader0: sti-uni-reader@8d83000 { - compatible = "st,sti-uni-reader"; + compatible = "st,stih407-uni-reader-pcm_in"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d83000 0x158>; interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; dmas = <&fdma0 5 0 1>; dma-names = "rx"; - dai-name = "Uni Reader #0 (PCM IN)"; - st,version = <3>; status = "disabled"; }; sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,sti-uni-reader"; + compatible = "st,stih407-uni-reader-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d84000 0x158>; interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>; dmas = <&fdma0 6 0 1>; dma-names = "rx"; - dai-name = "Uni Reader #1 (HDMI RX)"; - st,version = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 291ffacbd2e0..fa149837df14 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -102,7 +102,7 @@ <&clk_s_d2_quadfs 0>; }; - sti-hdmi@8d04000 { + sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index ef2ff2f518f6..511a1098741e 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -174,12 +174,6 @@ status = "okay"; }; - sti-display-subsystem { - sti_hdmi: sti-hdmi@8d04000 { - status = "okay"; - }; - }; - miphy28lp_phy: miphy28lp@9b22000 { phy_port1: port@9b2a000 { diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 8598effd6c01..07c8ef9d77f6 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -208,7 +208,8 @@ "clk-clust-hades", "clk-hwpe-hades", "clk-fc-hades"; - clock-critical = <CLK_ICN_CPU>, + clock-critical = <CLK_PROC_STFE>, + <CLK_ICN_CPU>, <CLK_TX_ICN_DMU>, <CLK_EXT2F_A9>, <CLK_ICN_LMI>, diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index a3ef7341c051..281a12424cf6 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -193,7 +193,7 @@ <&clk_s_d2_quadfs 0>; }; - sti-hdmi@8d04000 { + sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts deleted file mode 100644 index bdfbd3765db2..000000000000 --- a/arch/arm/boot/dts/stih415-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH415 B2000 Board"; - compatible = "st,stih415-b2000", "st,stih415"; -}; diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts deleted file mode 100644 index 71903a87bd31..000000000000 --- a/arch/arm/boot/dts/stih415-b2020.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH415 B2020 Board"; - compatible = "st,stih415-b2020", "st,stih415"; -}; diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi deleted file mode 100644 index 3ee34514bc4b..000000000000 --- a/arch/arm/boot/dts/stih415-clock.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <dt-bindings/clock/stih415-clks.h> - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator input to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG1 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - ""; /* clk-s-stac-sys */ - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE41 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-apb-pm", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-disp", - ""; /* Unused */ - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-icn-dmu-0", - "clk-m-icn-dmu-1", - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-eram", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-fdma-12", - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-lmi", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-icn-gpu", - "clk-m-icn-vdp-0"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-icn-vdp-1", - "clk-m-icn-vdp-2", - "clk-m-icn-vdp-3", - "clk-m-prv-t1-bus", - "clk-m-icn-vdp-4", - "clk-m-icn-reg-10", - "", /* Unused */ - ""; /* clk-m-icn-st231 */ - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp-0", - "clk-m-icn-bdisp-1"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "", /* clk-m-icn-hqvdp0 */ - "", /* clk-m-icn-hqvdp1 */ - "clk-m-icn-compo", - "", /* clk-m-icn-vdpaux */ - "clk-m-icn-ts", - "clk-m-icn-reg-lp-10", - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = ""; /* Unused */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde00d8 { - reg = <0xfdde00d8 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde00d8 { - #clock-cells = <0>; - compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde00d8 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi deleted file mode 100644 index bd028ce98b61..000000000000 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include <dt-bindings/interrupt-controller/arm-gic.h> -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - gpio6 = &pio6; - gpio7 = &pio7; - gpio8 = &pio8; - gpio9 = &pio9; - gpio10 = &pio10; - gpio11 = &pio11; - gpio12 = &pio12; - gpio13 = &pio13; - gpio14 = &pio14; - gpio15 = &pio15; - gpio16 = &pio16; - gpio17 = &pio17; - gpio18 = &pio18; - gpio19 = &pio100; - gpio20 = &pio101; - gpio21 = &pio102; - gpio22 = &pio103; - gpio23 = &pio104; - gpio24 = &pio105; - gpio25 = &pio106; - gpio26 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x5000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - sbc_serial1 { - pinctrl_sbc_serial1:sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; - }; - }; - - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x8000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x8000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0{ - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; - - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - - - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - }; - - pin-controller-left { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-left-pinctrl"; - st,syscfg = <&syscfg_left>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-right { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-right-pinctrl"; - st,syscfg = <&syscfg_right>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi deleted file mode 100644 index 12427e651e5e..000000000000 --- a/arch/arm/boot/dts/stih415.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih415-clock.dtsi" -#include "stih415-pinctrl.dtsi" -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/stih415-resets.h> -/ { - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <1 1 1>; - cache-unified; - cache-level = <2>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih415-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih415-softreset"; - }; - - syscfg_sbc: sbc-syscfg@fe600000{ - compatible = "st,stih415-sbc-syscfg", "syscon"; - reg = <0xfe600000 0xb4>; - }; - - syscfg_front: front-syscfg@fee10000{ - compatible = "st,stih415-front-syscfg", "syscon"; - reg = <0xfee10000 0x194>; - }; - - syscfg_rear: rear-syscfg@fe830000{ - compatible = "st,stih415-rear-syscfg", "syscon"; - reg = <0xfe830000 0x190>; - }; - - /* MPE syscfgs */ - syscfg_left: left-syscfg@fd690000{ - compatible = "st,stih415-left-syscfg", "syscon"; - reg = <0xfd690000 0x78>; - }; - - syscfg_right: right-syscfg@fd320000{ - compatible = "st,stih415-right-syscfg", "syscon"; - reg = <0xfd320000 0x180>; - }; - - syscfg_system: system-syscfg@fdde0000 { - compatible = "st,stih415-system-syscfg", "syscon"; - reg = <0xfdde0000 0x15c>; - }; - - syscfg_lpm: lpm-syscfg@fe4b5100{ - compatible = "st,stih415-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x08>; - }; - - serial2: serial@fed32000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - }; - - /* SBC comms block ASCs in SASG1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 147 0>, <0 148 0>, <0 149 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - resets = <&softreset STIH415_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_rear 0x148>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 150 0>, <0 151 0>, <0 152 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_sbc 0x74>; - - resets = <&softreset STIH415_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - clocks = <&clk_sysin>; - rx-mode = "infrared"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH415_IRB_SOFTRESET>; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, - <&softreset STIH415_KEYSCAN_SOFTRESET>; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = <GIC_SPI 145 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts deleted file mode 100644 index 488e80a5d69d..000000000000 --- a/arch/arm/boot/dts/stih416-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH416 B2000"; - compatible = "st,stih416-b2000", "st,stih416"; -}; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts deleted file mode 100644 index 200a81844765..000000000000 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH416 B2020"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts deleted file mode 100644 index de320cd067de..000000000000 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Lee Jones <lee.jones@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -#include <dt-bindings/gpio/gpio.h> -/ { - model = "STiH416 B2020 REV-E"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - ethernet1: dwmac@fef08000 { - snps,reset-gpio = <&pio0 7>; - }; - - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - status = "okay"; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi deleted file mode 100644 index 5b4fb838cddb..000000000000 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ /dev/null @@ -1,756 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics R&D Limited - * <stlinux-devel@stlinux.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <dt-bindings/clock/stih416-clks.h> - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG2 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc-0", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - "clk-s-stac-sys", - "clk-s-card-mmc-1"; - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE42 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-fdma-12", - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-lmi", - "clk-m-vid-dmu-0"; - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-vid-dmu-1", - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-tx-icn-dmu-0", - "clk-m-tx-icn-dmu-1", - "clk-m-tx-icn-ts", - "clk-m-icn-vdp-0", - "clk-m-icn-vdp-1"; - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-vp8", - "", /* Unused */ - "clk-m-icn-reg-11", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-alt", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-rx-icn-dmu-0", - "clk-m-rx-icn-dmu-1"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-rx-icn-ts", - "clk-m-rx-icn-vdp-0", - "", /* Unused */ - "clk-m-prv-t1-bus", - "clk-m-icn-reg-12", - "clk-m-icn-reg-10", - "", /* Unused */ - "clk-m-icn-st231"; - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "clk-m-icn-reg-13", - "clk-m-tx-icn-gpu", - "clk-m-rx-icn-gpu", - "", /* Unused */ - "", /* Unused */ - "", /* clk-m-apb-pm-12 */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* clk-m-gpu-alt */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp", - "clk-m-icn-compo"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-icn-vdp-2", - "", /* Unused */ - "clk-m-icn-reg-14", - "clk-m-mdtp", - "clk-m-jpegdec", - "", /* Unused */ - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - ""; /* clk-m-apb-pm-11 */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde08b0 { - reg = <0xfdde08b0 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde08ac { - #clock-cells = <0>; - compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde08ac 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Frequency synthesizers on the SASG2 - */ - clockgen_b0: clockgen-b0@fee108b4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee108b4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-usb48", - "clk-s-dss", - "clk-s-stfe-frc-2", - "clk-s-thsens-scard"; - }; - - clockgen_b1: clockgen-b1@fe8308c4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfe8308c4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-pcm-0", - "clk-s-pcm-1", - "clk-s-pcm-2", - "clk-s-pcm-3"; - }; - - clockgen_c: clockgen-c@fe8307d0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs432", "st,quadfs"; - reg = <0xfe8307d0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-c-fs0-ch0", - "clk-s-c-vcc-sd", - "clk-s-c-fs0-ch2"; - }; - - clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; - reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ - - clocks = <&clk_sysin>, - <&clockgen_c 0>; - }; - - /* - * Add a dummy clock for the HDMI PHY for the VCC input mux - */ - clk_s_tmds_fromphy: clk-s-tmds-fromphy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_c_vcc: clockgen-c-vcc@fe8308ac { - #clock-cells = <1>; - compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; - reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ - - clocks = <&clk_s_vcc_hd>, - <&clockgen_c 1>, - <&clk_s_tmds_fromphy>, - <&clockgen_c 2>; - - clock-output-names = "clk-s-pix-hdmi", - "clk-s-pix-dvo", - "clk-s-out-dvo", - "clk-s-pix-hd", - "clk-s-hddac", - "clk-s-denc", - "clk-s-sddac", - "clk-s-pix-main", - "clk-s-pix-aux", - "clk-s-stfe-frc-0", - "clk-s-ref-mcru", - "clk-s-slave-mcru", - "clk-s-tmds-hdmi", - "clk-s-hdmi-reject-pll", - "clk-s-thsens"; - }; - - clockgen_d: clockgen-d@fee107e0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee107e0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-ccsc", - "clk-s-stfe-frc-1", - "clk-s-tsout-1", - "clk-s-mchi"; - }; - - /* - * Frequency synthesizers on the MPE42 - */ - clockgen_e: clockgen-e@fd3208bc { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-E", "st,quadfs"; - reg = <0xfd3208bc 0xb0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-pix-mdtp-0", - "clk-m-pix-mdtp-1", - "clk-m-pix-mdtp-2", - "clk-m-mpelpc"; - }; - - clockgen_f: clockgen-f@fd320878 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-F", "st,quadfs"; - reg = <0xfd320878 0xf0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-main-vidfs", - "clk-m-hva-fs", - "clk-m-fvdp-vcpu", - "clk-m-fvdp-proc-fs"; - }; - - clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; - reg = <0xfd320910 0x4>; /* SYSCFG8580 */ - - clocks = <&clk_m_a1_div2 0>, - <&clockgen_f 3>; - }; - - clk_m_hva: clk-m-hva@fd690868 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; - reg = <0xfd690868 0x4>; /* SYSCFG9538 */ - - clocks = <&clockgen_f 1>, - <&clk_m_a1_div0 3>; - }; - - clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 7>, - <&clockgen_f 0>; - }; - - clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 8>, - <&clockgen_f 1>; - }; - - /* - * Add a dummy clock for the HDMIRx external signal clock - */ - clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_f_vcc: clockgen-f-vcc@fd32086c { - #clock-cells = <1>; - compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; - reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ - - clocks = <&clk_m_f_vcc_hd>, - <&clk_m_f_vcc_sd>, - <&clockgen_f 0>, - <&clk_m_pix_hdmirx_sas>; - - clock-output-names = "clk-m-pix-main-pipe", - "clk-m-pix-aux-pipe", - "clk-m-pix-main-cru", - "clk-m-pix-aux-cru", - "clk-m-xfer-be-compo", - "clk-m-xfer-pip-compo", - "clk-m-xfer-aux-compo", - "clk-m-vsens", - "clk-m-pix-hdmirx-0", - "clk-m-pix-hdmirx-1"; - }; - - /* - * DDR PLL - */ - clockgen-ddr@0xfdde07d8 { - reg = <0xfdde07d8 0x110>; - - clockgen_ddr_pll: clockgen-ddr-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-ddr0", - "clockgen-ddr1"; - }; - }; - - /* - * GPU PLL - */ - clockgen-gpu@fd68ff00 { - reg = <0xfd68ff00 0x910>; - - clockgen_gpu_pll: clockgen-gpu-pll { - #clock-cells = <1>; - compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-gpu-pll"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi deleted file mode 100644 index 9c97f7e651a0..000000000000 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ /dev/null @@ -1,692 +0,0 @@ - -/* - * Copyright (C) 2013 STMicroelectronics Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include <dt-bindings/interrupt-controller/arm-gic.h> -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio40; - gpio6 = &pio5; - gpio7 = &pio6; - gpio8 = &pio7; - gpio9 = &pio8; - gpio10 = &pio9; - gpio11 = &pio10; - gpio12 = &pio11; - gpio13 = &pio12; - gpio14 = &pio30; - gpio15 = &pio31; - gpio16 = &pio13; - gpio17 = &pio14; - gpio18 = &pio15; - gpio19 = &pio16; - gpio20 = &pio17; - gpio21 = &pio18; - gpio22 = &pio100; - gpio23 = &pio101; - gpio24 = &pio102; - gpio25 = &pio103; - gpio26 = &pio104; - gpio27 = &pio105; - gpio28 = &pio106; - gpio29 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x6000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - pio40: gpio@fe615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO40"; - st,retime-pin-mask = <0x7f>; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb3: usb3 { - st,pins { - oc-detect = <&pio40 0 ALT1 IN>; - pwr-enable = <&pio40 1 ALT1 OUT>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-out = <&pio4 4 ALT1 OUT>; - pwm-capturein = <&pio4 3 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x10000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - pio30: gpio@fee08000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@fee09000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO31"; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-out = <&pio9 7 ALT2 OUT>; - pwm-capturein = <&pio9 6 ALT2 IN>; - }; - }; - }; - - serial2-oe { - pinctrl_serial2_oe: serial2-1 { - st,pins { - output-enable = <&pio11 3 ALT2 OUT>; - }; - }; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb0: usb0 { - st,pins { - oc-detect = <&pio9 4 ALT1 IN>; - pwr-enable = <&pio9 5 ALT1 OUT>; - }; - }; - }; - - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio12 2 ALT1 OUT>; - spi-fsm-cs = <&pio12 3 ALT1 OUT>; - spi-fsm-mosi = <&pio12 4 ALT1 OUT>; - spi-fsm-miso = <&pio12 5 ALT1 IN>; - spi-fsm-hol = <&pio12 6 ALT1 OUT>; - spi-fsm-wp = <&pio12 7 ALT1 OUT>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x6000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - st,retime-pin-mask = <0xf>; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0 { - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - }; - }; - pinctrl_rgmii0: rgmii0 { - st,pins { - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - - mdio = <&pio15 4 ALT2 OUT BYPASS 0>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; - rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; - rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; - rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; - rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; - rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; - - clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - mmc1 { - pinctrl_mmc1: mmc1 { - st,pins { - mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>; - data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>; - data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>; - data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>; - cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>; - data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>; - data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>; - data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>; - data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>; - pwr = <&pio16 2 ALT3 OUT>; - nreset = <&pio13 6 ALT3 OUT>; - }; - }; - }; - - usb { - pinctrl_usb1: usb1 { - st,pins { - oc-detect = <&pio18 0 ALT1 IN>; - pwr-enable = <&pio18 1 ALT1 OUT>; - }; - }; - pinctrl_usb2: usb2 { - st,pins { - oc-detect = <&pio18 2 ALT1 IN>; - pwr-enable = <&pio18 3 ALT1 OUT>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan1_default: pwm0-1-default { - st,pins { - pwm-out = <&pio13 2 ALT2 OUT>; - pwm-capturein = <&pio13 1 ALT2 IN>; - }; - }; - pinctrl_pwm0_chan2_default: pwm0-2-default { - st,pins { - pwm-out = <&pio15 2 ALT4 OUT>; - }; - }; - pinctrl_pwm0_chan3_default: pwm0-3-default { - st,pins { - pwm-out = <&pio17 4 ALT1 OUT>; - }; - }; - }; - - }; - - pin-controller-fvdp-fe { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-fe-pinctrl"; - st,syscfg = <&syscfg_fvdp_fe>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-fvdp-lite { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-lite-pinctrl"; - st,syscfg = <&syscfg_fvdp_lite>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - st,retime-pin-mask = <0xf>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi deleted file mode 100644 index fe1f9cf770e4..000000000000 --- a/arch/arm/boot/dts/stih416.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright (C) 2012 STMicroelectronics Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih416-clock.dtsi" -#include "stih416-pinctrl.dtsi" - -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/stih416-resets.h> -#include <dt-bindings/interrupt-controller/irq-st.h> -/ { - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart { - compatible = "st,stih416-restart"; - st,syscfg = <&syscfg_sbc>; - status = "okay"; - }; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih416-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih416-softreset"; - }; - - syscfg_sbc:sbc-syscfg@fe600000{ - compatible = "st,stih416-sbc-syscfg", "syscon"; - reg = <0xfe600000 0x1000>; - }; - - syscfg_front:front-syscfg@fee10000{ - compatible = "st,stih416-front-syscfg", "syscon"; - reg = <0xfee10000 0x1000>; - }; - - syscfg_rear:rear-syscfg@fe830000{ - compatible = "st,stih416-rear-syscfg", "syscon"; - reg = <0xfe830000 0x1000>; - }; - - /* MPE */ - syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{ - compatible = "st,stih416-fvdp-fe-syscfg", "syscon"; - reg = <0xfddf0000 0x1000>; - }; - - syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{ - compatible = "st,stih416-fvdp-lite-syscfg", "syscon"; - reg = <0xfd6a0000 0x1000>; - }; - - syscfg_cpu:cpu-syscfg@fdde0000{ - compatible = "st,stih416-cpu-syscfg", "syscon"; - reg = <0xfdde0000 0x1000>; - }; - - syscfg_compo:compo-syscfg@fd320000{ - compatible = "st,stih416-compo-syscfg", "syscon"; - reg = <0xfd320000 0x1000>; - }; - - syscfg_transport:transport-syscfg@fd690000{ - compatible = "st,stih416-transport-syscfg", "syscon"; - reg = <0xfd690000 0x1000>; - }; - - syscfg_lpm:lpm-syscfg@fe4b5100{ - compatible = "st,stih416-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x8>; - }; - - irq-syscfg { - compatible = "st,stih416-irq-syscfg"; - st,syscfg = <&syscfg_cpu>; - st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, - <ST_IRQ_SYSCFG_PMU_1>; - st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, - <ST_IRQ_SYSCFG_DISABLED>; - }; - - serial2: serial@fed32000{ - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; - }; - - /* SBC_UART1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 133 0>, <0 134 0>, <0 135 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_rear 0x8bc>; - resets = <&softreset STIH416_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 136 0>, <0 137 0>, <0 138 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_sbc 0x7f0>; - - resets = <&softreset STIH416_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - rx-mode = "infrared"; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH416_IRB_SOFTRESET>; - }; - - /* FSM */ - spifsm: spifsm@fe902000 { - compatible = "st,spi-fsm"; - reg = <0xfe902000 0x1000>; - pinctrl-0 = <&pinctrl_fsm>; - - st,syscfg = <&syscfg_rear>; - st,boot-device-reg = <0x958>; - st,boot-device-spi = <0x1a>; - - status = "disabled"; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, - <&softreset STIH416_KEYSCAN_SOFTRESET>; - }; - - temp0 { - compatible = "st,stih416-sas-thermal"; - clock-names = "thermal"; - clocks = <&clockgen_c_vcc 14>; - - status = "okay"; - }; - - temp1@fdfe8000 { - compatible = "st,stih416-mpe-thermal"; - reg = <0xfdfe8000 0x10>; - clocks = <&clockgen_e 3>; - clock-names = "thermal"; - interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; - - status = "okay"; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - - mmc1: sdhci@fe81f000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81f000 0x1000>; - interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 8>; - }; - - miphy365x_phy: phy@fe382000 { - compatible = "st,miphy365x-phy"; - st,syscfg = <&syscfg_rear 0x824 0x828>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@fe382000 { - #phy-cells = <1>; - reg = <0xfe382000 0x100>, <0xfe394000 0x100>; - reg-names = "sata", "pcie"; - }; - - phy_port1: port@fe38a000 { - #phy-cells = <1>; - reg = <0xfe38a000 0x100>, <0xfe804000 0x100>; - reg-names = "sata", "pcie"; - }; - }; - - sata0: sata@fe380000 { - compatible = "st,sti-ahci"; - reg = <0xfe380000 0x1000>; - interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - resets = <&powerdown STIH416_SATA0_POWERDOWN>, - <&softreset STIH416_SATA0_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst"; - clock-names = "ahci_clk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - - status = "disabled"; - }; - - usb2_phy: phy@0 { - compatible = "st,stih416-usb-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_rear>; - clocks = <&clk_sysin>; - clock-names = "osc_phy"; - }; - - ehci0: usb@fe1ffe00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe1ffe00 0x100>; - interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci0: usb@fe1ffc00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe1ffc00 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - status = "okay"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci1: usb@fe203e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe203e00 0x100>; - interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci1: usb@fe203c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe203c00 0x100>; - interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci2: usb@fe303e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe303e00 0x100>; - interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci2: usb@fe303c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe303c00 0x100>; - interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci3: usb@fe343e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe343e00 0x100>; - interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci3: usb@fe343c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe343c00 0x100>; - interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfed10000 0x68>; - interrupts = <GIC_SPI 200 IRQ_TYPE_NONE>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default - &pinctrl_pwm0_chan1_default - &pinctrl_pwm0_chan2_default - &pinctrl_pwm0_chan3_default>; - - clock-names = "pwm", "capture"; - clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>; - - st,pwm-num-chan = <4>; - st,capture-num-chan = <2>; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfe510000 0x68>; - interrupts = <GIC_SPI 202 IRQ_TYPE_NONE>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - /* - * Shared with SBC_OBS_NOTRST. Don't - * enable unless you really know what - * you're doing. - * - * &pinctrl_pwm1_chan1_default - */ - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <3>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi deleted file mode 100644 index 9bfa0674b452..000000000000 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - - memory{ - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &serial2; - }; - - aliases { - ttyAS0 = &serial2; - ethernet0 = ðernet0; - ethernet1 = ðernet1; - }; - - soc { - serial2: serial@fed32000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - fp_led { - label = "Front Panel LED"; - gpios = <&pio105 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - ethernet0: dwmac@fe810000 { - status = "okay"; - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_mii0>; - - snps,reset-gpio = <&pio106 2>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - ethernet1: dwmac@fef08000 { - status = "disabled"; - phy-mode = "mii"; - st,tx-retime-src = "txclk"; - - snps,reset-gpio = <&pio4 7>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - keyscan: keyscan@fe4b0000 { - keypad,num-rows = <4>; - keypad,num-columns = <4>; - st,debounce-us = <5000>; - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) - MATRIX_KEY(0x00, 0x01, KEY_F9) - MATRIX_KEY(0x00, 0x02, KEY_F5) - MATRIX_KEY(0x00, 0x03, KEY_F1) - MATRIX_KEY(0x01, 0x00, KEY_F14) - MATRIX_KEY(0x01, 0x01, KEY_F10) - MATRIX_KEY(0x01, 0x02, KEY_F6) - MATRIX_KEY(0x01, 0x03, KEY_F2) - MATRIX_KEY(0x02, 0x00, KEY_F15) - MATRIX_KEY(0x02, 0x01, KEY_F11) - MATRIX_KEY(0x02, 0x02, KEY_F7) - MATRIX_KEY(0x02, 0x03, KEY_F3) - MATRIX_KEY(0x03, 0x00, KEY_F16) - MATRIX_KEY(0x03, 0x01, KEY_F12) - MATRIX_KEY(0x03, 0x02, KEY_F8) - MATRIX_KEY(0x03, 0x03, KEY_F4) >; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi deleted file mode 100644 index 322e0e95176c..000000000000 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x-b2020x.dtsi" -#include <dt-bindings/gpio/gpio.h> -/ { - memory{ - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial1; - }; - - aliases { - ttyAS0 = &sbc_serial1; - ethernet1 = ðernet1; - }; - soc { - sbc_serial1: serial@fe531000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio4 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - i2c@fed40000 { - status = "okay"; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - i2c@fe540000 { - status = "okay"; - }; - - i2c@fe541000 { - status = "okay"; - }; - - ethernet1: dwmac@fef08000 { - status = "okay"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - st,tx-retime-src = "clk_125"; - snps,reset-gpio = <&pio3 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-0 = <&pinctrl_rgmii1>; - }; - - mmc0: sdhci@fe81e000 { - bus-width = <8>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi deleted file mode 100644 index f797a0607382..000000000000 --- a/arch/arm/boot/dts/stih41x-b2020x.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Lee Jones <lee.jones@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - soc { - mmc0: sdhci@fe81e000 { - status = "okay"; - }; - - spifsm: spifsm@fe902000 { - #address-cells = <1>; - #size-cells = <1>; - - status = "okay"; - - partition@0 { - label = "SerialFlash1"; - reg = <0x00000000 0x00500000>; - }; - - partition@500000 { - label = "SerialFlash2"; - reg = <0x00500000 0x00b00000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi deleted file mode 100644 index 5cb0e63376b5..000000000000 --- a/arch/arm/boot/dts/stih41x.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - intc: interrupt-controller@fffe1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffe1000 0x1000>, - <0xfffe0100 0x100>; - }; - - scu@fffe0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffe0000 0x1000>; - }; - - timer@fffe0200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfffe0200 0x100>; - interrupts = <1 11 0x04>; - clocks = <&arm_periph_clk>; - }; -}; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index ed2b7a99ecff..313c1f8686d4 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -135,6 +135,10 @@ }; }; + sti_uni_player0: sti-uni-player@8d80000 { + status = "okay"; + }; + sti_uni_player2: sti-uni-player@8d82000 { status = "okay"; }; @@ -155,9 +159,22 @@ status = "okay"; simple-audio-card,dai-link@0 { + /* HDMI */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; + }; + simple-audio-card,dai-link@1 { /* DAC */ format = "i2s"; mclk-fs = <256>; + frame-inversion = <1>; cpu { sound-dai = <&sti_uni_player2>; }; @@ -166,7 +183,7 @@ sound-dai = <&sti_sasg_codec 1>; }; }; - simple-audio-card,dai-link@1 { + simple-audio-card,dai-link@2 { /* SPDIF */ format = "left_j"; mclk-fs = <128>; |
