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authorSeungwon Jeon <tgih.jun@samsung.com>2014-03-14 21:11:56 +0900
committerChris Ball <chris@printf.net>2014-04-20 16:59:28 -0400
commit79f7ae7c45a6ccf04e2908337461dee615f6afb0 (patch)
treed1fd1856fff504aeaa94782ff9e8ac47e36f0dcb /include/linux/mmc
parenta798c10faf62a505d24e5f6213fbaf904a39623f (diff)
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mmc: clarify DDR timing mode between SD-UHS and eMMC
This change distinguishes DDR timing mode of current mixed usage to clarify device type. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'include/linux/mmc')
-rw-r--r--include/linux/mmc/host.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index cb61ea4d6945..35354207e71f 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -58,7 +58,8 @@ struct mmc_ios {
#define MMC_TIMING_UHS_SDR50 5
#define MMC_TIMING_UHS_SDR104 6
#define MMC_TIMING_UHS_DDR50 7
-#define MMC_TIMING_MMC_HS200 8
+#define MMC_TIMING_MMC_DDR52 8
+#define MMC_TIMING_MMC_HS200 9
#define MMC_SDR_MODE 0
#define MMC_1_2V_DDR_MODE 1
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