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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-02-06 21:24:55 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:30:25 +0100 |
| commit | 0efe27617e67448dfe78e7cebde3a6f9eadf1223 (patch) | |
| tree | 858293ddf2a2e93da4186003ba7de016a073656f /include/asm-mips/mipsregs.h | |
| parent | d1e344e500cc693139a69d29122db18190916448 (diff) | |
| download | blackbird-obmc-linux-0efe27617e67448dfe78e7cebde3a6f9eadf1223.tar.gz blackbird-obmc-linux-0efe27617e67448dfe78e7cebde3a6f9eadf1223.zip | |
Provide functions to access cop0 config4-7 registers
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mipsregs.h')
| -rw-r--r-- | include/asm-mips/mipsregs.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 2197aa4ce456..006354ed2e29 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -790,10 +790,18 @@ do { \ #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) #define read_c0_config3() __read_32bit_c0_register($16, 3) +#define read_c0_config4() __read_32bit_c0_register($16, 4) +#define read_c0_config5() __read_32bit_c0_register($16, 5) +#define read_c0_config6() __read_32bit_c0_register($16, 6) +#define read_c0_config7() __read_32bit_c0_register($16, 7) #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) /* * The WatchLo register. There may be upto 8 of them. |
