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authorRhyland Klein <rklein@nvidia.com>2016-01-14 14:24:35 -0500
committerThierry Reding <treding@nvidia.com>2016-02-02 15:49:24 +0100
commit3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807 (patch)
treed3b7c9b1ec316b1bc5838f754c43f8b8a3250049 /firmware/e100
parent3eb61566a6efc5a56ebe1e6b86519bc5e0b39003 (diff)
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clk: tegra: Fix pllx dyn step calculation
The logic for calculating the input rate used when figuring out the proper dynamic steps for pllx was incorrect. It is supposed to be calculated using parent_rate / m but it was just using the parent rate directly, therefore using the wrong step values. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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