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| author | Lee Jones <lee.jones@linaro.org> | 2014-03-20 09:20:47 +0000 |
|---|---|---|
| committer | Brian Norris <computersforpeace@gmail.com> | 2014-03-20 04:17:17 -0700 |
| commit | fa5ba3af200db0b9c2922dc463ecdf122a93012b (patch) | |
| tree | 52c5e1eb116c33640f8d8c5393503713bb23128f /drivers/mtd | |
| parent | a63984c18a6186a323987817f01095d07503bda1 (diff) | |
| download | blackbird-obmc-linux-fa5ba3af200db0b9c2922dc463ecdf122a93012b.tar.gz blackbird-obmc-linux-fa5ba3af200db0b9c2922dc463ecdf122a93012b.zip | |
mtd: st_spi_fsm: Provide the erase one sector sequence
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for erasing a single sector.
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/devices/st_spi_fsm.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 6be267277756..06e6a5282044 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -389,6 +389,28 @@ static struct stfsm_seq stfsm_seq_read_jedec = { SEQ_CFG_STARTSEQ), }; +static struct stfsm_seq stfsm_seq_erase_sector = { + /* 'addr_cfg' configured during initialisation */ + .seq_opc = { + (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + + (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_SE)), + }, + .seq = { + STFSM_INST_CMD1, + STFSM_INST_CMD2, + STFSM_INST_ADD1, + STFSM_INST_ADD2, + STFSM_INST_STOP, + }, + .seq_cfg = (SEQ_CFG_PADS_1 | + SEQ_CFG_READNOTWRITE | + SEQ_CFG_CSDEASSERT | + SEQ_CFG_STARTSEQ), +}; + static inline int stfsm_is_idle(struct stfsm *fsm) { return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10; @@ -477,6 +499,19 @@ static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, } } +/* Configure 'addr_cfg' according to addressing mode */ +static void stfsm_prepare_erasesec_seq(struct stfsm *fsm, + struct stfsm_seq *seq) +{ + int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8; + + seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) | + ADR_CFG_PADS_1_ADD1 | + ADR_CFG_CYCLES_ADD2(16) | + ADR_CFG_PADS_1_ADD2 | + ADR_CFG_CSDEASSERT_ADD2); +} + /* Search for preferred configuration based on available flags */ static struct seq_rw_config * stfsm_search_seq_rw_configs(struct stfsm *fsm, |
