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authorMiquel Raynal <miquel.raynal@bootlin.com>2018-10-01 16:13:51 +0200
committerMarc Zyngier <marc.zyngier@arm.com>2018-10-02 12:00:08 +0100
commit61ce8d8d8a8168a714de80fc31b3d6ac160fc5b0 (patch)
treee9f9cd69b18879ae9929f18b200a7a5d59c9672a /drivers/irqchip/Makefile
parent4f4c867c91e644fc9d461c8c5cf2f09d6d5bcac2 (diff)
downloadblackbird-obmc-linux-61ce8d8d8a8168a714de80fc31b3d6ac160fc5b0.tar.gz
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irqchip/irq-mvebu-sei: Add new driver for Marvell SEI
This is a cascaded interrupt controller in the AP806 GIC that collapses SEIs (System Error Interrupt) coming from the AP and the CPs (through the ICU). The SEI handles up to 64 interrupts. The first 21 interrupts are wired from the AP. The next 43 interrupts are from the CPs and are triggered through MSI messages. To handle this complexity, the driver has to declare to the upper layer: one IRQ domain for the wired interrupts, one IRQ domain for the MSIs; and acts as a MSI controller ('parent') by declaring an MSI domain. Suggested-by: Haim Boot <hayim@marvell.com> Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/Makefile')
-rw-r--r--drivers/irqchip/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index fbd1ec8070ef..b822199445ff 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
+obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
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