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authorChristian König <christian.koenig@amd.com>2014-04-04 13:45:42 +0200
committerChristian König <christian.koenig@amd.com>2014-04-17 13:59:46 +0200
commit5fb9cc4d8b1639b9a7487c1ee7b2b0c52877327d (patch)
tree16b573a64725153bf6202164f383012c4da2d5f8 /drivers/gpu
parent6abc6d5c73b22ccf2e5688df6a2eb02ee8dfdf59 (diff)
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drm/radeon: apply more strict limits for PLL params v2
Letting post and refernce divider get to big is bad for signal stability. v2: increase the limit to 210 Signed-off-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 386cfa4c194d..2f42912031ac 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
}
post_div = post_div_best;
+ /* limit reference * post divider to a maximum */
+ ref_div_max = min(210 / post_div, ref_div_max);
+
/* get matching reference and feedback divider */
ref_div = max(den / post_div, 1u);
fb_div = nom;
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