diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2015-08-20 14:54:21 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2015-08-28 12:40:46 +1000 |
| commit | bd70563f015a5204c62a52a87a35c32377940187 (patch) | |
| tree | ae2382c2e4fdc3ba32dff11b4f993520c9b42e6a /drivers/gpu/drm/nouveau | |
| parent | 14d74acafb15fd3fac16eef89de7643cddd01775 (diff) | |
| download | blackbird-obmc-linux-bd70563f015a5204c62a52a87a35c32377940187.tar.gz blackbird-obmc-linux-bd70563f015a5204c62a52a87a35c32377940187.zip | |
drm/nouveau/dma: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
22 files changed, 162 insertions, 242 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 1b85ffe629aa..95a64d89547c 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -251,13 +251,13 @@ struct gf100_dma_v0 { __u8 pad03[5]; }; -struct gf110_dma_v0 { +struct gf119_dma_v0 { __u8 version; -#define GF110_DMA_V0_PAGE_LP 0x00 -#define GF110_DMA_V0_PAGE_SP 0x01 +#define GF119_DMA_V0_PAGE_LP 0x00 +#define GF119_DMA_V0_PAGE_SP 0x01 __u8 page; -#define GF110_DMA_V0_KIND_PITCH 0x00 -#define GF110_DMA_V0_KIND_VM 0xff +#define GF119_DMA_V0_KIND_PITCH 0x00 +#define GF119_DMA_V0_KIND_VM 0xff __u8 kind; __u8 pad03[5]; }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h index 7439a02bf7c9..114bfb737a81 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h @@ -2,7 +2,6 @@ #define __NVKM_DMA_H__ #include <core/engine.h> struct nvkm_client; -struct nvkm_gpuobj; struct nvkm_dmaobj { const struct nvkm_dmaobj_func *func; @@ -18,20 +17,16 @@ struct nvkm_dmaobj { u64 handle; /*XXX HANDLE MERGE */ }; -struct nvkm_dmaobj_func { - int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, int align, - struct nvkm_gpuobj **); -}; - struct nvkm_dma { + const struct nvkm_dma_func *func; struct nvkm_engine engine; }; struct nvkm_dmaobj * nvkm_dma_search(struct nvkm_dma *, struct nvkm_client *, u64 object); -extern struct nvkm_oclass *nv04_dmaeng_oclass; -extern struct nvkm_oclass *nv50_dmaeng_oclass; -extern struct nvkm_oclass *gf100_dmaeng_oclass; -extern struct nvkm_oclass *gf110_dmaeng_oclass; +int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **); +int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **); +int gf100_dma_new(struct nvkm_device *, int, struct nvkm_dma **); +int gf119_dma_new(struct nvkm_device *, int, struct nvkm_dma **); #endif diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 817ce09acb19..57b13602b2c5 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -2339,7 +2339,7 @@ nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kin union { struct nv50_dma_v0 nv50; struct gf100_dma_v0 gf100; - struct gf110_dma_v0 gf110; + struct gf119_dma_v0 gf119; }; } args = {}; struct nv50_fbdma *fbdma; @@ -2375,9 +2375,9 @@ nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kin args.gf100.kind = kind; size += sizeof(args.gf100); } else { - args.gf110.page = GF110_DMA_V0_PAGE_LP; - args.gf110.kind = kind; - size += sizeof(args.gf110); + args.gf119.page = GF119_DMA_V0_PAGE_LP; + args.gf119.kind = kind; + size += sizeof(args.gf119); } list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index e9ed83563028..fa4a1f00499c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -87,7 +87,7 @@ nv4_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv04_fifo_new, // .gr = nv04_gr_new, // .sw = nv04_sw_new, @@ -107,7 +107,7 @@ nv5_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv04_fifo_new, // .gr = nv04_gr_new, // .sw = nv04_sw_new, @@ -128,7 +128,7 @@ nv10_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .gr = nv10_gr_new, }; @@ -147,7 +147,7 @@ nv11_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, @@ -168,7 +168,7 @@ nv15_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, @@ -189,7 +189,7 @@ nv17_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, @@ -210,7 +210,7 @@ nv18_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, @@ -231,7 +231,7 @@ nv1a_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, @@ -252,7 +252,7 @@ nv1f_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, @@ -273,7 +273,7 @@ nv20_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv20_gr_new, // .sw = nv10_sw_new, @@ -294,7 +294,7 @@ nv25_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv25_gr_new, // .sw = nv10_sw_new, @@ -315,7 +315,7 @@ nv28_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv25_gr_new, // .sw = nv10_sw_new, @@ -336,7 +336,7 @@ nv2a_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv2a_gr_new, // .sw = nv10_sw_new, @@ -357,7 +357,7 @@ nv30_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv30_gr_new, // .sw = nv10_sw_new, @@ -378,7 +378,7 @@ nv31_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv30_gr_new, // .mpeg = nv31_mpeg_new, @@ -400,7 +400,7 @@ nv34_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv34_gr_new, // .mpeg = nv31_mpeg_new, @@ -422,7 +422,7 @@ nv35_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv35_gr_new, // .sw = nv10_sw_new, @@ -443,7 +443,7 @@ nv36_chipset = { .mmu = nv04_mmu_new, .timer = nv04_timer_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv35_gr_new, // .mpeg = nv31_mpeg_new, @@ -467,7 +467,7 @@ nv40_chipset = { .timer = nv40_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, @@ -492,7 +492,7 @@ nv41_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, @@ -517,7 +517,7 @@ nv42_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, @@ -542,7 +542,7 @@ nv43_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, @@ -567,7 +567,7 @@ nv44_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -592,7 +592,7 @@ nv45_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -617,7 +617,7 @@ nv46_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -642,7 +642,7 @@ nv47_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -667,7 +667,7 @@ nv49_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -692,7 +692,7 @@ nv4a_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -717,7 +717,7 @@ nv4b_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -742,7 +742,7 @@ nv4c_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -767,7 +767,7 @@ nv4e_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -795,7 +795,7 @@ nv50_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv50_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = nv50_fifo_new, // .gr = nv50_gr_new, // .mpeg = nv50_mpeg_new, @@ -820,7 +820,7 @@ nv63_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -845,7 +845,7 @@ nv67_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -870,7 +870,7 @@ nv68_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = nv04_disp_new, -// .dma = nv04_dma_new, + .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, @@ -900,7 +900,7 @@ nv84_chipset = { .bsp = g84_bsp_new, .cipher = g84_cipher_new, // .disp = g84_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -931,7 +931,7 @@ nv86_chipset = { .bsp = g84_bsp_new, .cipher = g84_cipher_new, // .disp = g84_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -962,7 +962,7 @@ nv92_chipset = { .bsp = g84_bsp_new, .cipher = g84_cipher_new, // .disp = g84_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -993,7 +993,7 @@ nv94_chipset = { .bsp = g84_bsp_new, .cipher = g84_cipher_new, // .disp = g94_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -1021,7 +1021,7 @@ nv96_chipset = { .mmu = nv50_mmu_new, .bar = g84_bar_new, .volt = nv40_volt_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .sw = nv50_sw_new, // .gr = nv50_gr_new, @@ -1052,7 +1052,7 @@ nv98_chipset = { .mmu = nv50_mmu_new, .bar = g84_bar_new, .volt = nv40_volt_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .sw = nv50_sw_new, // .gr = nv50_gr_new, @@ -1086,7 +1086,7 @@ nva0_chipset = { .bsp = g84_bsp_new, .cipher = g84_cipher_new, // .disp = gt200_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -1117,7 +1117,7 @@ nva3_chipset = { .volt = nv40_volt_new, .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -1150,7 +1150,7 @@ nva5_chipset = { .volt = nv40_volt_new, .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, @@ -1182,7 +1182,7 @@ nva8_chipset = { .volt = nv40_volt_new, .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, @@ -1212,7 +1212,7 @@ nvaa_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = g94_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, @@ -1243,7 +1243,7 @@ nvac_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, // .disp = g94_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, @@ -1276,7 +1276,7 @@ nvaf_chipset = { .volt = nv40_volt_new, .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, -// .dma = nv50_dma_new, + .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, @@ -1311,7 +1311,7 @@ nvc0_chipset = { .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, -// .dma = gf100_dma_new, + .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf100_gr_new, .mspdec = gf100_mspdec_new, @@ -1345,7 +1345,7 @@ nvc1_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, // .disp = gt215_disp_new, -// .dma = gf100_dma_new, + .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf108_gr_new, .mspdec = gf100_mspdec_new, @@ -1379,7 +1379,7 @@ nvc3_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, // .disp = gt215_disp_new, -// .dma = gf100_dma_new, + .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, @@ -1414,7 +1414,7 @@ nvc4_chipset = { .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, -// .dma = gf100_dma_new, + .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, @@ -1449,7 +1449,7 @@ nvc8_chipset = { .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, -// .dma = gf100_dma_new, + .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf110_gr_new, .mspdec = gf100_mspdec_new, @@ -1484,7 +1484,7 @@ nvce_chipset = { .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, -// .dma = gf100_dma_new, + .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, @@ -1518,7 +1518,7 @@ nvcf_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, // .disp = gt215_disp_new, -// .dma = gf100_dma_new, + .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, @@ -1550,7 +1550,7 @@ nvd7_chipset = { .timer = nv41_timer_new, .ce[0] = gf100_ce_new, // .disp = gf119_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gf100_fifo_new, // .gr = gf117_gr_new, .mspdec = gf100_mspdec_new, @@ -1584,7 +1584,7 @@ nvd9_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, // .disp = gf119_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gf100_fifo_new, // .gr = gf119_gr_new, .mspdec = gf100_mspdec_new, @@ -1620,7 +1620,7 @@ nve4_chipset = { .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gk104_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, @@ -1656,7 +1656,7 @@ nve6_chipset = { .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gk104_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, @@ -1692,7 +1692,7 @@ nve7_chipset = { .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gk104_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, @@ -1719,7 +1719,7 @@ nvea_chipset = { .timer = gk20a_timer_new, .volt = gk20a_volt_new, .ce[2] = gk104_ce_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk20a_fifo_new, // .gr = gk20a_gr_new, // .pm = gk104_pm_new, @@ -1752,7 +1752,7 @@ nvf0_chipset = { .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gk110_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk110_gr_new, .mspdec = gk104_mspdec_new, @@ -1788,7 +1788,7 @@ nvf1_chipset = { .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gk110_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk110b_gr_new, .mspdec = gk104_mspdec_new, @@ -1824,7 +1824,7 @@ nv106_chipset = { .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gk110_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, @@ -1859,7 +1859,7 @@ nv108_chipset = { .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gk110_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, @@ -1892,7 +1892,7 @@ nv117_chipset = { .ce[0] = gk104_ce_new, .ce[2] = gk104_ce_new, // .disp = gm107_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gm107_gr_new, // .sw = gf100_sw_new, @@ -1921,7 +1921,7 @@ nv124_chipset = { .ce[1] = gm204_ce_new, .ce[2] = gm204_ce_new, // .disp = gm204_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gm204_fifo_new, // .gr = gm204_gr_new, // .sw = gf100_sw_new, @@ -1950,7 +1950,7 @@ nv126_chipset = { .ce[1] = gm204_ce_new, .ce[2] = gm204_ce_new, // .disp = gm204_disp_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gm204_fifo_new, // .gr = gm206_gr_new, // .sw = gf100_sw_new, @@ -1971,7 +1971,7 @@ nv12b_chipset = { .mmu = gf100_mmu_new, .timer = gk20a_timer_new, .ce[2] = gm204_ce_new, -// .dma = gf119_dma_new, + .dma = gf119_dma_new, // .fifo = gm20b_fifo_new, // .gr = gm20b_gr_new, // .sw = gf100_sw_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index 336964a0cd92..3256b3b12e48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xc0: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; @@ -36,7 +35,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc4: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; @@ -44,7 +42,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc3: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; @@ -52,7 +49,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xce: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; @@ -60,7 +56,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xcf: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; @@ -68,7 +63,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc1: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; @@ -76,7 +70,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; break; case 0xc8: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; @@ -84,7 +77,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xd9: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; @@ -92,7 +84,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; case 0xd7: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index 3a9fa9428803..c02474168536 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xe4: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; @@ -36,7 +35,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe7: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; @@ -44,7 +42,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe6: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; @@ -52,14 +49,12 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xf0: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; @@ -67,7 +62,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0xf1: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; @@ -75,14 +69,12 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0x106: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; break; case 0x108: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index ec75f91e55cc..825e7cd07983 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device) #if 0 #endif - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; @@ -48,7 +47,6 @@ gm100_identify(struct nvkm_device *device) #endif #if 0 #endif - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass; @@ -63,7 +61,6 @@ gm100_identify(struct nvkm_device *device) #endif #if 0 #endif - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass; @@ -73,7 +70,6 @@ gm100_identify(struct nvkm_device *device) break; case 0x12b: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 1b2ebda82c1f..92c24618d101 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -28,14 +28,12 @@ nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x05: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index c5ecdddfbce3..17a694d60d7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -28,54 +28,46 @@ nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x16: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1a: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x11: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x17: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1f: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x18: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index 104ed4f093b5..6b59530743a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -28,28 +28,24 @@ nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x25: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x28: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x2a: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 5ea263c85043..232951b9854e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -28,21 +28,18 @@ nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x35: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x31: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; @@ -50,7 +47,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x36: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; @@ -58,7 +54,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x34: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 0d6da9716b7b..642000f8b2bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -37,7 +36,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -46,7 +44,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -55,7 +52,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -64,7 +60,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -73,7 +68,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -82,7 +76,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -91,7 +84,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -100,7 +92,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -109,7 +100,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -118,7 +108,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -127,7 +116,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -136,7 +124,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -145,7 +132,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -154,7 +140,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; @@ -163,7 +148,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 087edc8d412c..7e4ef30945e3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x50: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -37,7 +36,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; break; case 0x84: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -46,7 +44,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x86: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -55,7 +52,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x92: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -64,7 +60,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x94: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -73,7 +68,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x96: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -82,7 +76,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x98: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -90,7 +83,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa0: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -99,7 +91,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; break; case 0xaa: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -107,7 +98,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xac: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -115,7 +105,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa3: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -124,7 +113,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa5: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -132,7 +120,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa8: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; @@ -140,7 +127,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xaf: - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild index bb3a0528b6b5..c4a2ce9b0d71 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild @@ -2,10 +2,10 @@ nvkm-y += nvkm/engine/dma/base.o nvkm-y += nvkm/engine/dma/nv04.o nvkm-y += nvkm/engine/dma/nv50.o nvkm-y += nvkm/engine/dma/gf100.o -nvkm-y += nvkm/engine/dma/gf110.o +nvkm-y += nvkm/engine/dma/gf119.o nvkm-y += nvkm/engine/dma/user.o nvkm-y += nvkm/engine/dma/usernv04.o nvkm-y += nvkm/engine/dma/usernv50.o nvkm-y += nvkm/engine/dma/usergf100.o -nvkm-y += nvkm/engine/dma/usergf110.o +nvkm-y += nvkm/engine/dma/usergf119.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c index 1a377201949c..9769fc0d5351 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c @@ -52,14 +52,13 @@ nvkm_dma_oclass_new(struct nvkm_device *device, struct nvkm_object **pobject) { struct nvkm_dma *dma = nvkm_dma(oclass->engine); - struct nvkm_dma_impl *impl = (void *)dma->engine.subdev.object.oclass; struct nvkm_dmaobj *dmaobj = NULL; struct nvkm_client *client = oclass->client; struct rb_node **ptr = &client->dmaroot.rb_node; struct rb_node *parent = NULL; int ret; - ret = impl->class_new(dma, oclass, data, size, &dmaobj); + ret = dma->func->class_new(dma, oclass, data, size, &dmaobj); if (dmaobj) *pobject = &dmaobj->object; if (ret) @@ -130,26 +129,29 @@ nvkm_dma_oclass_fifo_get(struct nvkm_oclass *oclass, int index) return count; } +static void * +nvkm_dma_dtor(struct nvkm_engine *engine) +{ + return nvkm_dma(engine); +} + static const struct nvkm_engine_func nvkm_dma = { + .dtor = nvkm_dma_dtor, .base.sclass = nvkm_dma_oclass_base_get, .fifo.sclass = nvkm_dma_oclass_fifo_get, }; int -_nvkm_dma_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device, + int index, struct nvkm_dma **pdma) { - struct nvkm_dma *dmaeng; - int ret; + struct nvkm_dma *dma; - ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ", - "dmaobj", &dmaeng); - *pobject = nv_object(dmaeng); - if (ret) - return ret; + if (!(dma = *pdma = kzalloc(sizeof(*dma), GFP_KERNEL))) + return -ENOMEM; + dma->func = func; - dmaeng->engine.func = &nvkm_dma; - return 0; + return nvkm_engine_ctor(&nvkm_dma, device, index, + 0, true, &dma->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c index 81badf09eed8..efec5d322179 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c @@ -24,14 +24,13 @@ #include "priv.h" #include "user.h" -struct nvkm_oclass * -gf100_dmaeng_oclass = &(struct nvkm_dma_impl) { - .base.handle = NV_ENGINE(DMAOBJ, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_dma_ctor, - .dtor = _nvkm_dma_dtor, - .init = _nvkm_dma_init, - .fini = _nvkm_dma_fini, - }, +static const struct nvkm_dma_func +gf100_dma = { .class_new = gf100_dmaobj_new, -}.base; +}; + +int +gf100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +{ + return nvkm_dma_new_(&gf100_dma, device, index, pdma); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c index 79d869bf9a61..34c766039aed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c @@ -24,14 +24,13 @@ #include "priv.h" #include "user.h" -struct nvkm_oclass * -gf110_dmaeng_oclass = &(struct nvkm_dma_impl) { - .base.handle = NV_ENGINE(DMAOBJ, 0xd0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_dma_ctor, - .dtor = _nvkm_dma_dtor, - .init = _nvkm_dma_init, - .fini = _nvkm_dma_fini, - }, - .class_new = gf110_dmaobj_new, -}.base; +static const struct nvkm_dma_func +gf119_dma = { + .class_new = gf119_dmaobj_new, +}; + +int +gf119_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +{ + return nvkm_dma_new_(&gf119_dma, device, index, pdma); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c index c116995f8494..30747a0ce488 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c @@ -24,14 +24,13 @@ #include "priv.h" #include "user.h" -struct nvkm_oclass * -nv04_dmaeng_oclass = &(struct nvkm_dma_impl) { - .base.handle = NV_ENGINE(DMAOBJ, 0x04), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_dma_ctor, - .dtor = _nvkm_dma_dtor, - .init = _nvkm_dma_init, - .fini = _nvkm_dma_fini, - }, +static const struct nvkm_dma_func +nv04_dma = { .class_new = nv04_dmaobj_new, -}.base; +}; + +int +nv04_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +{ + return nvkm_dma_new_(&nv04_dma, device, index, pdma); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c index b8d87e7d6ed7..77aca7b71c83 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c @@ -24,14 +24,13 @@ #include "priv.h" #include "user.h" -struct nvkm_oclass * -nv50_dmaeng_oclass = &(struct nvkm_dma_impl) { - .base.handle = NV_ENGINE(DMAOBJ, 0x50), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_dma_ctor, - .dtor = _nvkm_dma_dtor, - .init = _nvkm_dma_init, - .fini = _nvkm_dma_fini, - }, +static const struct nvkm_dma_func +nv50_dma = { .class_new = nv50_dmaobj_new, -}.base; +}; + +int +nv50_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +{ + return nvkm_dma_new_(&nv50_dma, device, index, pdma); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h index fbff168e6cc8..deb37ee55c0b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h @@ -3,18 +3,15 @@ #define nvkm_dma(p) container_of((p), struct nvkm_dma, engine) #include <engine/dma.h> -int _nvkm_dma_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -#define _nvkm_dma_dtor _nvkm_engine_dtor -#define _nvkm_dma_init _nvkm_engine_init -#define _nvkm_dma_fini _nvkm_engine_fini - -struct nvkm_dma_impl { - struct nvkm_oclass base; - struct nvkm_oclass *sclass; - int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, +struct nvkm_dmaobj_func { + int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, int align, struct nvkm_gpuobj **); +}; + +int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *, + int index, struct nvkm_dma **); + +struct nvkm_dma_func { int (*class_new)(struct nvkm_dma *, const struct nvkm_oclass *, void *data, u32 size, struct nvkm_dmaobj **); }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h index f667505a892b..69a7f1034024 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h @@ -13,6 +13,6 @@ int nv50_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32, struct nvkm_dmaobj **); int gf100_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32, struct nvkm_dmaobj **); -int gf110_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32, +int gf119_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32, struct nvkm_dmaobj **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c index f6bbdffed4e7..0e1af8b4db84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#define gf110_dmaobj(p) container_of((p), struct gf110_dmaobj, base) +#define gf119_dmaobj(p) container_of((p), struct gf119_dmaobj, base) #include "user.h" #include <core/client.h> @@ -31,16 +31,16 @@ #include <nvif/class.h> #include <nvif/unpack.h> -struct gf110_dmaobj { +struct gf119_dmaobj { struct nvkm_dmaobj base; u32 flags0; }; static int -gf110_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, +gf119_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) { - struct gf110_dmaobj *dmaobj = gf110_dmaobj(base); + struct gf119_dmaobj *dmaobj = gf119_dmaobj(base); struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; int ret; @@ -60,19 +60,19 @@ gf110_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, } static const struct nvkm_dmaobj_func -gf110_dmaobj_func = { - .bind = gf110_dmaobj_bind, +gf119_dmaobj_func = { + .bind = gf119_dmaobj_bind, }; int -gf110_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, +gf119_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_dmaobj **pdmaobj) { union { - struct gf110_dma_v0 v0; + struct gf119_dma_v0 v0; } *args; struct nvkm_object *parent = oclass->parent; - struct gf110_dmaobj *dmaobj; + struct gf119_dmaobj *dmaobj; u32 kind, page; int ret; @@ -80,14 +80,14 @@ gf110_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, return -ENOMEM; *pdmaobj = &dmaobj->base; - ret = nvkm_dmaobj_ctor(&gf110_dmaobj_func, dma, oclass, + ret = nvkm_dmaobj_ctor(&gf119_dmaobj_func, dma, oclass, &data, &size, &dmaobj->base); if (ret) return ret; args = data; - nvif_ioctl(parent, "create gf110 dma size %d\n", size); + nvif_ioctl(parent, "create gf119 dma size %d\n", size); if (nvif_unpack(args->v0, 0, 0, false)) { nvif_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n", @@ -97,11 +97,11 @@ gf110_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, } else if (size == 0) { if (dmaobj->base.target != NV_MEM_TARGET_VM) { - kind = GF110_DMA_V0_KIND_PITCH; - page = GF110_DMA_V0_PAGE_SP; + kind = GF119_DMA_V0_KIND_PITCH; + page = GF119_DMA_V0_PAGE_SP; } else { - kind = GF110_DMA_V0_KIND_VM; - page = GF110_DMA_V0_PAGE_LP; + kind = GF119_DMA_V0_KIND_VM; + page = GF119_DMA_V0_PAGE_LP; } } else return ret; |
