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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2018-07-30 15:06:36 +0300 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2018-08-01 17:17:27 +0300 |
| commit | c358514ba8da9e235876db1628cedd19a35803c6 (patch) | |
| tree | ff1c9278719eaefbc99eb30ad0275d5ca0fb0eb3 /drivers/gpu/drm/i915/intel_workarounds.c | |
| parent | 21eb1850fa0bd0a9b729bf3708da78888433027f (diff) | |
| download | blackbird-obmc-linux-c358514ba8da9e235876db1628cedd19a35803c6.tar.gz blackbird-obmc-linux-c358514ba8da9e235876db1628cedd19a35803c6.zip | |
Revert "drm/i915/icl: WaEnableFloatBlendOptimization"
The register for 0xe420 is unable to hold any value, including
this bit. The documentation is also mixed between having a
register bit for toggle and having a state command setup
for it. Apparently the register toggle is deprecated.
Remove the register toggle as evidence shows it's futile.
The thing remaining is an apology and humble request for
Mesa folks to resurrect their state setup for this as they
were on right track from start.
This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.
Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
References: HSDES#1406393558
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180730120636.26958-1-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_workarounds.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_workarounds.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index f8bb32e974f6..4bcdeaf8d98f 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -508,9 +508,6 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv) WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); - /* WaEnableFloatBlendOptimization:icl */ - WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE); - return 0; } |
