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authorImre Deak <imre.deak@intel.com>2013-04-17 14:04:50 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-05-10 21:56:35 +0200
commit7d708ee40a6b9ca1112a322e554c887df105b025 (patch)
treece5a29a139c6e6c1c0c2d3e156ba3f8f48800baf /drivers/gpu/drm/i915/intel_drv.h
parentbc5ead8c09b51e85d110132495a9bfa58dc39dab (diff)
downloadblackbird-obmc-linux-7d708ee40a6b9ca1112a322e554c887df105b025.tar.gz
blackbird-obmc-linux-7d708ee40a6b9ca1112a322e554c887df105b025.zip
drm/i915: HSW: allow PCH clock gating for suspend
For the device to enter D3 we should enable PCH clock gating. v2: - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo) - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index be9ad392b0e8..6096871c4806 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -716,6 +716,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
extern void intel_init_clock_gating(struct drm_device *dev);
+extern void intel_suspend_hw(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_prepare_ddi(struct drm_device *dev);
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