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authorLukasz Majewski <l.majewski@samsung.com>2013-10-09 14:08:43 +0200
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-10-17 13:52:49 +0200
commit7ad65d592b0a7f70fe21af2e3d4d02c76333d5a0 (patch)
tree93e967897f077ed4d377c3d06d53fdaf4dbb72a9 /drivers/cpufreq/cpufreq_userspace.c
parentcf4671559fdc0550de38fc8f6cd0ea6369736f1f (diff)
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cpufreq: exynos4210: Use the common clock framework to set APLL clock rate
In the exynos4210_set_apll() function, the APLL frequency is set with direct register manipulation. Such approach is not allowed in the common clock framework. The frequency is changed, but the corresponding clock value is not updated. This causes wrong frequency read from cpufreq's cpuinfo_cur_freq sysfs attribute. Also direct manipulation with PLL's S parameter has been removed. It is already done at PLL35xx code. Tested at: - Exynos4210 - Trats board (linux 3.12-rc4) Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/cpufreq/cpufreq_userspace.c')
0 files changed, 0 insertions, 0 deletions
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