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authorSylwester Nawrocki <s.nawrocki@samsung.com>2017-07-21 13:19:50 +0200
committerStephen Boyd <sboyd@codeaurora.org>2017-07-31 13:16:03 -0700
commit5b30850bd6bda5188eedec60d364256617a87343 (patch)
treeff5010155c5662f5ef0e96102b60a1a5b9548e41 /drivers/clk/clkdev.c
parentd31fd43c0f9a41e2678a1e78c0f22f0384c6edd3 (diff)
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clk: samsung: exynos5420: The EPLL rate table corrections
This patch fixes values of the EPLL K coefficient and changes the EPLL output frequency values to match exactly what is possible to achieve with given M, P, S, K coefficients. This allows to avoid rounding errors and unexpected frequency being set with clk_set_rate(), due to recalc_rate returning different values than the PLL rate specified in the exynos5420_epll_24mhz_tbl table. E.g. this prevents a case where two consecutive clk_set_rate() calls with same argument result in different PLL output frequency. The PLL output frequencies have been calculated with formula: f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16 where fxtal = 24000000. Fixes: 9842452acd ("clk: samsung: exynos542x: Add EPLL rate table") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clkdev.c')
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