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| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-09-24 23:20:46 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2015-11-02 18:02:51 +0300 |
| commit | 01618bded680573163403666d0546be536b22ac0 (patch) | |
| tree | cb566bdc9514682771e020d6c6b1501f768fee4b /arch/xtensa/include/asm/cacheasm.h | |
| parent | 5029615e25dc5040beb065f36743c127a8e51497 (diff) | |
| download | blackbird-obmc-linux-01618bded680573163403666d0546be536b22ac0.tar.gz blackbird-obmc-linux-01618bded680573163403666d0546be536b22ac0.zip | |
xtensa: fix build for configs without cache options
- make cache-related assembly macros empty if core doesn't have
corresponding cache type;
- don't initialize cache attributes in instruction/data TLB entries if
there's no corresponding cache type.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include/asm/cacheasm.h')
| -rw-r--r-- | arch/xtensa/include/asm/cacheasm.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h index 60e18773ecb8..e0f9e1109c83 100644 --- a/arch/xtensa/include/asm/cacheasm.h +++ b/arch/xtensa/include/asm/cacheasm.h @@ -73,7 +73,9 @@ .macro ___unlock_dcache_all ar at +#if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#endif .endm @@ -90,30 +92,38 @@ .macro ___flush_invalidate_dcache_all ar at +#if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___flush_dcache_all ar at +#if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_dcache_all ar at +#if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_icache_all ar at +#if XCHAL_ICACHE_SIZE __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ XCHAL_ICACHE_LINEWIDTH +#endif .endm @@ -121,28 +131,36 @@ .macro ___flush_invalidate_dcache_range ar as at +#if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___flush_dcache_range ar as at +#if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_dcache_range ar as at +#if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_icache_range ar as at +#if XCHAL_ICACHE_SIZE __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH +#endif .endm @@ -150,27 +168,35 @@ .macro ___flush_invalidate_dcache_page ar as +#if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___flush_dcache_page ar as +#if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_dcache_page ar as +#if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_icache_page ar as +#if XCHAL_ICACHE_SIZE __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH +#endif .endm |
