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| author | James Hogan <james.hogan@imgtec.com> | 2015-12-16 23:49:33 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-01-24 03:15:51 +0100 |
| commit | 16d100db245ab34d975e080f39e4cc4ed09b3820 (patch) | |
| tree | d8353347f013c35a81276c22e068dc3ced73d8c5 /arch/mips/include/asm/mipsregs.h | |
| parent | 2db9d233860e638fecd4b6c519c880bee98ba5eb (diff) | |
| download | blackbird-obmc-linux-16d100db245ab34d975e080f39e4cc4ed09b3820.tar.gz blackbird-obmc-linux-16d100db245ab34d975e080f39e4cc4ed09b3820.zip | |
MIPS: Move Cause.ExcCode trap codes to mipsregs.h
Move the Cause.ExcCode trap code definitions from kvm_host.h to
mipsregs.h, since they describe architectural bits rather than KVM
specific constants, and change the prefix from T_ to EXCCODE_.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11891/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index af36d2be4d0d..eb89b877c6c9 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -404,6 +404,30 @@ #define CAUSEF_BD (_ULCAST_(1) << 31) /* + * Cause.ExcCode trap codes. + */ +#define EXCCODE_INT 0 /* Interrupt pending */ +#define EXCCODE_MOD 1 /* TLB modified fault */ +#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */ +#define EXCCODE_TLBS 3 /* TLB miss on a store */ +#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */ +#define EXCCODE_ADES 5 /* Address error on a store */ +#define EXCCODE_IBE 6 /* Bus error on an ifetch */ +#define EXCCODE_DBE 7 /* Bus error on a load or store */ +#define EXCCODE_SYS 8 /* System call */ +#define EXCCODE_BP 9 /* Breakpoint */ +#define EXCCODE_RI 10 /* Reserved instruction exception */ +#define EXCCODE_CPU 11 /* Coprocessor unusable */ +#define EXCCODE_OV 12 /* Arithmetic overflow */ +#define EXCCODE_TR 13 /* Trap instruction */ +#define EXCCODE_VCEI 14 /* Virtual coherency exception */ +#define EXCCODE_MSAFPE 14 /* MSA floating point exception */ +#define EXCCODE_FPE 15 /* Floating point exception */ +#define EXCCODE_MSADIS 21 /* MSA disabled exception */ +#define EXCCODE_WATCH 23 /* Watch address reference */ +#define EXCCODE_VCED 31 /* Virtual coherency data */ + +/* * Bits in the coprocessor 0 config register. */ /* Generic bits. */ |
