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authorManuel Lauss <manuel.lauss@googlemail.com>2009-10-07 20:15:15 +0200
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 12:52:53 +0100
commit788144656b8a862e724a1296e64ab6375eb541ed (patch)
tree96208eed56da25acdf9d923b9d9986e82dcd8944 /arch/mips/alchemy/xxs1500
parent93e9cd8485b31e5a33f1040bff4d15e65c0b2d19 (diff)
downloadblackbird-obmc-linux-788144656b8a862e724a1296e64ab6375eb541ed.tar.gz
blackbird-obmc-linux-788144656b8a862e724a1296e64ab6375eb541ed.zip
MIPS: Alchemy: Stop IRQ name sharing
Eliminate the sharing of IRQ names among the differenct Alchemy variants. IRQ numbers need no longer be hidden behind a CONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy code less reliant on a hardcoded subtype. This patch also renames the GPIO irq number constants. It's really an interrupt line, NOT a GPIO number! Code which relied on certain irq numbers to have the same name across all supported cpu subtypes is changed to determine current cpu subtype at runtime; in some places this isn't possible so a "compat" symbol is used. Run-tested on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/xxs1500')
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index eb31350d9772..21bef8dc0883 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -80,19 +80,19 @@ void __init board_setup(void)
static int __init xxs1500_init_irq(void)
{
- set_irq_type(AU1500_GPIO_204, IRQF_TRIGGER_HIGH);
- set_irq_type(AU1500_GPIO_201, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO_202, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO_203, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO_205, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO_207, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+ set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1000_GPIO_0, IRQF_TRIGGER_LOW);
- set_irq_type(AU1000_GPIO_1, IRQF_TRIGGER_LOW);
- set_irq_type(AU1000_GPIO_2, IRQF_TRIGGER_LOW);
- set_irq_type(AU1000_GPIO_3, IRQF_TRIGGER_LOW);
- set_irq_type(AU1000_GPIO_4, IRQF_TRIGGER_LOW); /* CF interrupt */
- set_irq_type(AU1000_GPIO_5, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
+ set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
+ set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
return 0;
}
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