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| author | Yi Li <yi.li@analog.com> | 2009-08-07 01:20:58 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-09-16 22:10:19 -0400 |
| commit | eb7bd9c461bbfbb195cb1e1346453222a4352df4 (patch) | |
| tree | 9c92f6ce5160b655213bbcff8175878771594121 /arch/blackfin/kernel/cplb-mpu/cacheinit.c | |
| parent | 8312440e05ea74feabc648ad8f36c823af4ddd8e (diff) | |
| download | blackbird-obmc-linux-eb7bd9c461bbfbb195cb1e1346453222a4352df4.tar.gz blackbird-obmc-linux-eb7bd9c461bbfbb195cb1e1346453222a4352df4.zip | |
Blackfin: cleanup sync handling when enabling/disabling cplbs
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper
sync procedures as laid out in the Blackfin programming manual. So rather
than audit/fix every call location, create helper functions that do the
right things in order to safely update these MMRs. Then convert all call
sites to use these new helper functions.
While we're fixing the code, drop the workaround for anomaly 05000125 as
that anomaly applies to old versions of silicon that we do not support.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/kernel/cplb-mpu/cacheinit.c')
| -rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cacheinit.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c index d5a86c3017f7..a082681faa8e 100644 --- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c @@ -30,13 +30,14 @@ void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) unsigned long ctrl; int i; - SSYNC(); for (i = 0; i < MAX_CPLBS; i++) { bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr); bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data); } ctrl = bfin_read_IMEM_CONTROL(); ctrl |= IMC | ENICPLB; + /* CSYNC to ensure load store ordering */ + CSYNC(); bfin_write_IMEM_CONTROL(ctrl); SSYNC(); } @@ -48,7 +49,6 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) unsigned long ctrl; int i; - SSYNC(); for (i = 0; i < MAX_CPLBS; i++) { bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); @@ -63,6 +63,8 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) * to port B */ ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); + /* CSYNC to ensure load store ordering */ + CSYNC(); bfin_write_DMEM_CONTROL(ctrl); SSYNC(); } |
