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authorWill Deacon <will.deacon@arm.com>2011-06-06 12:27:34 +0100
committerWill Deacon <will.deacon@arm.com>2011-07-07 19:20:53 +0100
commitf4daf06fc23b99df5ca5b3e892428b91e148cc52 (patch)
tree25d034cbf3109c03d33b404d1d910f64ee048629 /arch/arm
parent14abd038a7a209193c58ee7dde01ef4bf1523a91 (diff)
downloadblackbird-obmc-linux-f4daf06fc23b99df5ca5b3e892428b91e148cc52.tar.gz
blackbird-obmc-linux-f4daf06fc23b99df5ca5b3e892428b91e148cc52.zip
ARM: proc: add definition of cpu_reset for ARMv6 and ARMv7 cores
This patch adds simple definitions of cpu_reset for ARMv6 and ARMv7 cores, which disable the MMU via the SCTLR. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mm/proc-v6.S5
-rw-r--r--arch/arm/mm/proc-v7.S7
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5ec15431cf12..aedf3c5dbe4e 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -56,6 +56,11 @@ ENTRY(cpu_v6_proc_fin)
*/
.align 5
ENTRY(cpu_v6_reset)
+ mrc p15, 0, r1, c1, c0, 0 @ ctrl register
+ bic r1, r1, #0x1 @ ...............m
+ mcr p15, 0, r1, c1, c0, 0 @ disable MMU
+ mov r1, #0
+ mcr p15, 0, r1, c7, c5, 4 @ ISB
mov pc, r0
/*
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 593285419e75..54d1a63517c5 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -58,9 +58,16 @@ ENDPROC(cpu_v7_proc_fin)
* to what would be the reset vector.
*
* - loc - location to jump to for soft reset
+ *
+ * This code must be executed using a flat identity mapping with
+ * caches disabled.
*/
.align 5
ENTRY(cpu_v7_reset)
+ mrc p15, 0, r1, c1, c0, 0 @ ctrl register
+ bic r1, r1, #0x1 @ ...............m
+ mcr p15, 0, r1, c1, c0, 0 @ disable MMU
+ isb
mov pc, r0
ENDPROC(cpu_v7_reset)
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