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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-04-04 16:58:38 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-06-01 23:46:33 +0100 |
| commit | d8dc7fbd53eeb329a1dda5a19df7058b9c1c413e (patch) | |
| tree | 9350da1b44869917801c2445f1faad7aecf23986 /arch/arm/mm/Kconfig | |
| parent | c0b759d87eab301af0380f5459057656178e78cf (diff) | |
| download | blackbird-obmc-linux-d8dc7fbd53eeb329a1dda5a19df7058b9c1c413e.tar.gz blackbird-obmc-linux-d8dc7fbd53eeb329a1dda5a19df7058b9c1c413e.zip | |
ARM: re-implement physical address space switching
Re-implement the physical address space switching to be architecturally
compliant. This involves flushing the caches, disabling the MMU, and
only then updating the page tables. Once that is complete, the system
can be brought back up again.
Since we disable the MMU, we need to do the update in assembly code.
Luckily, the entries which need updating are fairly trivial, and are
all setup by the early assembly code. We can merely adjust each entry
by the delta required.
Not only does this fix the code to be architecturally compliant, but it
fixes a couple of bugs too:
1. The original code would only ever update the first L2 entry covering
a fraction of the kernel; the remainder were left untouched.
2. The L2 entries covering the DTB blob were likewise untouched.
This solution fixes up all entries.
Tested-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/Kconfig')
| -rw-r--r-- | arch/arm/mm/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index b4f92b9a13ac..4dc661e2d3a6 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -624,6 +624,10 @@ config ARM_LPAE If unsure, say N. +config ARM_PV_FIXUP + def_bool y + depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE + config ARCH_PHYS_ADDR_T_64BIT def_bool ARM_LPAE |
