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author | Rajendra Nayak <rnayak@ti.com> | 2009-12-08 18:47:16 -0700 |
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committer | paul <paul@twilight.(none)> | 2009-12-11 17:00:46 -0700 |
commit | a1391d276866845018920329bc2a3a82ab322af8 (patch) | |
tree | a16a46b6d0af3cb5e3dcd4f7de207f138d087011 /arch/arm/mach-omap2/clock.h | |
parent | d79b126724554122d9598834ef39fb0bb4fc132d (diff) | |
download | blackbird-obmc-linux-a1391d276866845018920329bc2a3a82ab322af8.tar.gz blackbird-obmc-linux-a1391d276866845018920329bc2a3a82ab322af8.zip |
ARM: OMAP4: PM: Move DPLL control apis to dpll.c
This patch moves all the dpll control api's to a
common file dpll.c. This is in preperation of omap4
support wherein most of these api's can be reused.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.h')
-rw-r--r-- | arch/arm/mach-omap2/clock.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 87c08056b303..4df7aa43ef44 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -36,6 +36,11 @@ #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP3XXX_EN_DPLL_LOCKED 0x7 +/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ +#define DPLL_LOW_POWER_STOP 0x1 +#define DPLL_LOW_POWER_BYPASS 0x5 +#define DPLL_LOCKED 0x7 + int omap2_clk_init(void); int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); @@ -44,6 +49,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); +unsigned long omap3_dpll_recalc(struct clk *clk); +unsigned long omap3_clkoutx2_recalc(struct clk *clk); +void omap3_dpll_allow_idle(struct clk *clk); +void omap3_dpll_deny_idle(struct clk *clk); +u32 omap3_dpll_autoidle_read(struct clk *clk); +int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); +int omap3_noncore_dpll_enable(struct clk *clk); +void omap3_noncore_dpll_disable(struct clk *clk); #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); |