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| author | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:16:29 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:16:29 +0000 |
| commit | dcf7ec5ee62a78123057a1e286c88ca739717409 (patch) | |
| tree | fa3f19434638a942ba66d236dde4d9aaadf8b370 /arch/arm/mach-exynos/platsmp.c | |
| parent | 15db3e823c3246e3bd31fe454f5c8927eb85caf2 (diff) | |
| parent | 142f2101a86ade2d6c9dfbedf82e1b5b31c8fce6 (diff) | |
| download | blackbird-obmc-linux-dcf7ec5ee62a78123057a1e286c88ca739717409.tar.gz blackbird-obmc-linux-dcf7ec5ee62a78123057a1e286c88ca739717409.zip | |
Merge branch 'samsung/driver' into next/drivers
Conflicts:
arch/arm/mach-mxs/include/mach/common.h
Pull in previous samsung conflict merges and do a trivial
merge of an mxs double-add conflict.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos/platsmp.c')
| -rw-r--r-- | arch/arm/mach-exynos/platsmp.c | 28 |
1 files changed, 1 insertions, 27 deletions
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 69ffb2fb3875..60bc45e3e709 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -32,7 +32,6 @@ #include <plat/cpu.h> -extern unsigned int gic_bank_offset; extern void exynos4_secondary_startup(void); #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ @@ -65,31 +64,6 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(boot_lock); -static void __cpuinit exynos4_gic_secondary_init(void) -{ - void __iomem *dist_base = S5P_VA_GIC_DIST + - (gic_bank_offset * smp_processor_id()); - void __iomem *cpu_base = S5P_VA_GIC_CPU + - (gic_bank_offset * smp_processor_id()); - int i; - - /* - * Deal with the banked PPI and SGI interrupts - disable all - * PPI interrupts, ensure all SGI interrupts are enabled. - */ - __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); - __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); - - /* - * Set priority on PPI and SGI interrupts - */ - for (i = 0; i < 32; i += 4) - __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); - - __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK); - __raw_writel(1, cpu_base + GIC_CPU_CTRL); -} - void __cpuinit platform_secondary_init(unsigned int cpu) { /* @@ -97,7 +71,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - exynos4_gic_secondary_init(); + gic_secondary_init(0); /* * let the primary processor know we're out of the |
