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| author | Takashi Iwai <tiwai@suse.de> | 2013-10-25 11:43:47 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2013-10-25 11:43:47 +0200 |
| commit | 6913a9dbf18f08e3577695032da15812bda92b66 (patch) | |
| tree | 05ca8620b11f2898022a7fd8a00f1f8566161428 /arch/arm/mach-at91/at91sam9g45_reset.S | |
| parent | 7342017f4a0f129d277f78b8761f2732661ba30a (diff) | |
| parent | 9645083ca5ef365b7b750cf219bb20b61bb925f8 (diff) | |
| download | blackbird-obmc-linux-6913a9dbf18f08e3577695032da15812bda92b66.tar.gz blackbird-obmc-linux-6913a9dbf18f08e3577695032da15812bda92b66.zip | |
Merge tag 'asoc-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
ASoC: Updates for v3.13
- Further work on the dmaengine helpers, including support for
configuring the parameters for DMA by reading the capabilities of the
DMA controller which removes some guesswork and magic numbers fromm
drivers.
- A refresh of the documentation.
- Conversions of many drivers to direct regmap API usage in order to
allow the ASoC level register I/O code to be removed, this will
hopefully be completed by v3.14.
- Support for using async register I/O in DAPM, reducing the time taken
to implement power transitions on systems that support it.
Diffstat (limited to 'arch/arm/mach-at91/at91sam9g45_reset.S')
| -rw-r--r-- | arch/arm/mach-at91/at91sam9g45_reset.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S index 721a1a34dd1d..c40c1e2ef80f 100644 --- a/arch/arm/mach-at91/at91sam9g45_reset.S +++ b/arch/arm/mach-at91/at91sam9g45_reset.S @@ -16,11 +16,17 @@ #include "at91_rstc.h" .arm +/* + * at91_ramc_base is an array void* + * init at NULL if only one DDR controler is present in or DT + */ .globl at91sam9g45_restart at91sam9g45_restart: ldr r5, =at91_ramc_base @ preload constants ldr r0, [r5] + ldr r5, [r5, #4] @ ddr1 + cmp r5, #0 ldr r4, =at91_rstc_base ldr r1, [r4] @@ -30,6 +36,8 @@ at91sam9g45_restart: .balign 32 @ align to cache line + strne r2, [r5, #AT91_DDRSDRC_RTR] @ disable DDR1 access + strne r3, [r5, #AT91_DDRSDRC_LPR] @ power down DDR1 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 str r4, [r1, #AT91_RSTC_CR] @ reset processor |
