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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2013-12-13 16:42:19 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-12-29 12:32:47 +0000
commite68f31f4520ea5d1ddbcaddb320ef0b4201eef3c (patch)
treeab66c89f6347e23dea8ded7334ca2ef691c099fd /arch/arm/include
parent017f161a55b48807a73fc9dff0b69f081bf43ee3 (diff)
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ARM: 7922/1: l2x0: add Marvell Tauros3 support
This adds support for the Marvell Tauros3 cache controller which is compatible with pl310 cache controller but broadcasts L1 cache operations to L2 cache. While updating the binding documentation, clean up the list of possible compatibles. Also reorder driver compatibles to allow non-ARM derivated to be compatible to ARM cache controller compatibles. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 3b2c40b5bfa2..6795ff743b3d 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -131,6 +131,7 @@ struct l2x0_regs {
unsigned long prefetch_ctrl;
unsigned long pwr_ctrl;
unsigned long ctrl;
+ unsigned long aux2_ctrl;
};
extern struct l2x0_regs l2x0_saved_regs;
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