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authorMatthew Leach <matthew.leach@arm.com>2014-03-14 10:18:21 +0000
committerDaniel Lezcano <daniel.lezcano@linaro.org>2014-04-22 11:44:26 +0200
commit3309a8e22d9ca4fa4dada687372b682bc6a12343 (patch)
tree84c2d0d62efaa78aadf85aff1daa5cd2087bf1fc /arch/arm/boot/dts/vexpress-v2p-ca5s.dts
parent10b1f231441d8f4422c27c6e9cffc0cb2c3d871d (diff)
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dts: ca5: add the global timer for the A5
The Cortex A5 contains a global timer: add the appropriate device tree node. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/vexpress-v2p-ca5s.dts')
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index c544a5504591..d2709b73316b 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -88,6 +88,14 @@
interrupts = <1 13 0x304>;
};
+ timer@2c000200 {
+ compatible = "arm,cortex-a5-global-timer",
+ "arm,cortex-a9-global-timer";
+ reg = <0x2c000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&oscclk0>;
+ };
+
watchdog@2c000620 {
compatible = "arm,cortex-a5-twd-wdt";
reg = <0x2c000620 0x20>;
@@ -120,7 +128,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- osc@0 {
+ oscclk0: osc@0 {
/* CPU and internal AXI reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
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