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authorMaurice Petallo <mauricex.r.petallo@intel.com>2014-07-08 19:11:01 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2014-07-10 14:58:29 +0200
commitf25c33724d1512a72554c0ad4cb70b43ba15374e (patch)
tree05aef5afbddc4d01c5facc90246293864f44e4dc /Documentation/fb/pxafb.txt
parentd61b59461b0cd0106f03e566d537b9072029e059 (diff)
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mmc: sdhci: add DDR50 1.8V mode support for BayTrail eMMC Controller
This is to enable DDR50 bus speed mode with 1.8V signaling capability for BayTrail ACPI and PCI mode eMMC Controller. Signed-off-by: Maurice Petallo <mauricex.r.petallo@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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