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authorLee Jones <lee.jones@linaro.org>2015-02-18 15:13:59 +0000
committerJason Cooper <jason@lakedaemon.net>2015-03-03 19:50:02 +0000
commitf1f5bc30f5726ff28fa1b263edcd805cced84a07 (patch)
tree9a7e9094e1d0adb52fc1ac07a37282303438a7e3 /Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
parent070884845baaeaa41a11eccc2fc2a4080de64946 (diff)
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irqchip: st: Add documentation for STi based syscfg IRQs
Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lkml.kernel.org/r/1424272444-16230-4-git-send-email-lee.jones@linaro.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
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+STMicroelectronics STi System Configuration Controlled IRQs
+-----------------------------------------------------------
+
+On STi based systems; External, CTI (Core Sight), PMU (Performance Management),
+and PL310 L2 Cache IRQs are controlled using System Configuration registers.
+This driver is used to unmask them prior to use.
+
+Required properties:
+- compatible : Should be set to one of:
+ "st,stih415-irq-syscfg"
+ "st,stih416-irq-syscfg"
+ "st,stih407-irq-syscfg"
+ "st,stid127-irq-syscfg"
+- st,syscfg : Phandle to Cortex-A9 IRQ system config registers
+- st,irq-device : Array of IRQs to enable - should be 2 in length
+- st,fiq-device : Array of FIQs to enable - should be 2 in length
+
+Optional properties:
+- st,invert-ext : External IRQs can be inverted at will. This property inverts
+ these IRQs using bitwise logic. A number of defines have been
+ provided for convenience:
+ ST_IRQ_SYSCFG_EXT_1_INV
+ ST_IRQ_SYSCFG_EXT_2_INV
+ ST_IRQ_SYSCFG_EXT_3_INV
+Example:
+
+irq-syscfg {
+ compatible = "st,stih416-irq-syscfg";
+ st,syscfg = <&syscfg_cpu>;
+ st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+ <ST_IRQ_SYSCFG_PMU_1>;
+ st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+ <ST_IRQ_SYSCFG_DISABLED>;
+ st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>;
+};
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