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| author | Gabriel Fernandez <gabriel.fernandez@st.com> | 2016-08-29 14:26:53 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-16 16:01:34 -0700 |
| commit | 7df404c9856deec4cea1538ef4786116e3fbf2e5 (patch) | |
| tree | ec7c584d5cc93ddd2d84ac42ffccf34b0347d3b0 /Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | |
| parent | f5644f10dcfbab90ffd27da1d8d51ffc13e1bc84 (diff) | |
| download | blackbird-obmc-linux-7df404c9856deec4cea1538ef4786116e3fbf2e5.tar.gz blackbird-obmc-linux-7df404c9856deec4cea1538ef4786116e3fbf2e5.zip | |
drivers: clk: st: Remove stih415-416 clock support
STiH415 and STiH416 platforms are no longer used.
these platforms will be deprecated for the next kernel.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index 844b3a0976bf..c9fd6748f85e 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -9,25 +9,12 @@ Base address is located to the parent node. See clock binding[2] Required properties: - compatible : shall be: - "st,clkgena-prediv-c65", "st,clkgena-prediv" - "st,clkgena-prediv-c32", "st,clkgena-prediv" - - "st,clkgena-plls-c65" - "st,plls-c32-a1x-0", "st,clkgen-plls-c32" - "st,plls-c32-a1x-1", "st,clkgen-plls-c32" - "st,stih415-plls-c32-a9", "st,clkgen-plls-c32" - "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32" - "st,stih416-plls-c32-a9", "st,clkgen-plls-c32" - "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih407-plls-c32-a0", "st,clkgen-plls-c32" "st,stih407-plls-c32-a9", "st,clkgen-plls-c32" "sst,plls-c32-cx_0", "st,clkgen-plls-c32" "sst,plls-c32-cx_1", "st,clkgen-plls-c32" "st,stih418-plls-c28-a9", "st,clkgen-plls-c32" - "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" - "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" - - #clock-cells : From common clock binding; shall be set to 1. - clocks : From common clock binding @@ -36,17 +23,16 @@ Required properties: Example: - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0xffff>; - clk_s_a0_pll: clk-s-a0-pll { + clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; + compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; + clock-output-names = "clockgen-a9-pll-odf"; }; }; |
