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authorKevin Cernekee <cernekee@gmail.com>2014-11-25 16:49:52 -0800
committerFlorian Fainelli <f.fainelli@gmail.com>2014-11-28 15:44:44 -0800
commitd1d6786846e1c40f780edb83569597a8a7769e95 (patch)
treed49b7b12ec58f2422d2b968ecede7ccf2de38dec /Documentation/devicetree/bindings/bus
parentf80835875d3d1a4764711a90f6cc2669f037f527 (diff)
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bus: brcmstb_gisb: Add register offset tables for older chips
This will select the appropriate register layout based on the DT "compatible" string. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'Documentation/devicetree/bindings/bus')
-rw-r--r--Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt6
1 files changed, 5 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
index e2d501d20c9a..1eceefb20f01 100644
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
@@ -2,7 +2,11 @@ Broadcom GISB bus Arbiter controller
Required properties:
-- compatible: should be "brcm,gisb-arb"
+- compatible:
+ "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips
+ "brcm,bcm7435-gisb-arb" for newer 40nm chips
+ "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
+ "brcm,bcm7038-gisb-arb" for 130nm chips
- reg: specifies the base physical address and size of the registers
- interrupt-parent: specifies the phandle to the parent interrupt controller
this arbiter gets interrupt line from
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