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authorHuacai Chen <chenhc@lemote.com>2016-03-03 09:45:10 +0800
committerRalf Baechle <ralf@linux-mips.org>2016-05-13 14:02:14 +0200
commit37fbe8faa94fa8cae889a3a793fd7b32508b26ab (patch)
tree5dbe1f3af3744da7ebbc49b5df7b24764ef66194 /.get_maintainer.ignore
parentb2edcfc814017eb278e29bfdc72844f0434dd8b1 (diff)
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MIPS: Loongson-3: Set cache flush handlers to cache_noop
Loongson-3 maintains cache coherency by hardware, this means: 1) It's icache is coherent with dcache. 2) It's dcaches don't alias (maybe depend on PAGE_SIZE). 3) It maintains cache coherency across cores (and for DMA). So we can skip most cache flush operations by setting relevant handlers to `cache_noop' in `r4k_cache_init'. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12752/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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