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<!-- IBM_PROLOG_BEGIN_TAG
This is an automatically generated prolog.
$Source: src/usr/hwpf/hwp/ei_bus_attributes.xml $
IBM CONFIDENTIAL
COPYRIGHT International Business Machines Corp. 2012
p1
Object Code Only (OCO) source materials
Licensed Internal Code Source Materials
IBM HostBoot Licensed Internal Code
The source code for this program is not published or other-
wise divested of its trade secrets, irrespective of what has
been deposited with the U.S. Copyright Office.
Origin: 30
IBM_PROLOG_END_TAG -->
<!--
XML file specifying HWPF attributes.
These are platInit attributes associated with chips.
-->
<attributes>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_EI_BUS_RX_MSB_LSB_SWAP</id>
<targetType>TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP</targetType>
<description>
PRBS scramble pattern per lane on DMI bus for p8 and centaur.
</description>
<valueType>uint8</valueType>
<platInit/>
</attribute>
<attribute>
<id>ATTR_EI_BUS_TX_MSB_LSB_SWAP</id>
<targetType>TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP</targetType>
<description>
PRBS scramble pattern per lane on DMI bus for p8 and centaur.
</description>
<valueType>uint8</valueType>
<platInit/>
</attribute>
</attributes>
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